target/nios2/cpu.c

   1 /*
   2  * QEMU Nios II CPU
   3  *
   4  * Copyright (c) 2012 Chris Wulff <crwulff@gmail.com>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qemu-common.h"
  23 #include "qapi/error.h"
  24 #include "cpu.h"
  25 #include "exec/log.h"
  26 #include "exec/gdbstub.h"
  27 #include "hw/qdev-properties.h"
  28
  29 static void nios2_cpu_set_pc(CPUState *cs, vaddr value)
  30 {
  31     Nios2CPU *cpu = NIOS2_CPU(cs);
  32     CPUNios2State *env = &cpu->env;
  33
  34     env->regs[R_PC] = value;
  35 }
  36
  37 static bool nios2_cpu_has_work(CPUState *cs)
  38 {
  39     return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
  40 }
  41
  42 /* CPUClass::reset() */
  43 static void nios2_cpu_reset(CPUState *cs)
  44 {
  45     Nios2CPU *cpu = NIOS2_CPU(cs);
  46     Nios2CPUClass *ncc = NIOS2_CPU_GET_CLASS(cpu);
  47     CPUNios2State *env = &cpu->env;
  48
  49     if (qemu_loglevel_mask(CPU_LOG_RESET)) {
  50         qemu_log("CPU Reset (CPU %d)\n", cs->cpu_index);
  51         log_cpu_state(cs, 0);
  52     }
  53
  54     ncc->parent_reset(cs);
  55
  56     memset(env->regs, 0, sizeof(uint32_t) * NUM_CORE_REGS);
  57     env->regs[R_PC] = cpu->reset_addr;
  58
  59 #if defined(CONFIG_USER_ONLY)
  60     /* Start in user mode with interrupts enabled. */
  61     env->regs[CR_STATUS] = CR_STATUS_U | CR_STATUS_PIE;
  62 #else
  63     env->regs[CR_STATUS] = 0;
  64 #endif
  65 }
  66
  67 static void nios2_cpu_initfn(Object *obj)
  68 {
  69     CPUState *cs = CPU(obj);
  70     Nios2CPU *cpu = NIOS2_CPU(obj);
  71     CPUNios2State *env = &cpu->env;
  72
  73     cs->env_ptr = env;
  74
  75 #if !defined(CONFIG_USER_ONLY)
  76     mmu_init(env);
  77 #endif
  78 }
  79
  80 static ObjectClass *nios2_cpu_class_by_name(const char *cpu_model)
  81 {
  82     return object_class_by_name(TYPE_NIOS2_CPU);
  83 }
  84
  85 static void nios2_cpu_realizefn(DeviceState *dev, Error **errp)
  86 {
  87     CPUState *cs = CPU(dev);
  88     Nios2CPUClass *ncc = NIOS2_CPU_GET_CLASS(dev);
  89     Error *local_err = NULL;
  90
  91     cpu_exec_realizefn(cs, &local_err);
  92     if (local_err != NULL) {
  93         error_propagate(errp, local_err);
  94         return;
  95     }
  96
  97     qemu_init_vcpu(cs);
  98     cpu_reset(cs);
  99
 100     ncc->parent_realize(dev, errp);
 101 }
 102
 103 static bool nios2_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 104 {
 105     Nios2CPU *cpu = NIOS2_CPU(cs);
 106     CPUNios2State *env = &cpu->env;
 107
 108     if ((interrupt_request & CPU_INTERRUPT_HARD) &&
 109         (env->regs[CR_STATUS] & CR_STATUS_PIE)) {
 110         cs->exception_index = EXCP_IRQ;
 111         nios2_cpu_do_interrupt(cs);
 112         return true;
 113     }
 114     return false;
 115 }
 116
 117
 118 static void nios2_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
 119 {
 120     /* NOTE: NiosII R2 is not supported yet. */
 121     info->mach = bfd_arch_nios2;
 122 #ifdef TARGET_WORDS_BIGENDIAN
 123     info->print_insn = print_insn_big_nios2;
 124 #else
 125     info->print_insn = print_insn_little_nios2;
 126 #endif
 127 }
 128
 129 static int nios2_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
 130 {
 131     Nios2CPU *cpu = NIOS2_CPU(cs);
 132     CPUClass *cc = CPU_GET_CLASS(cs);
 133     CPUNios2State *env = &cpu->env;
 134
 135     if (n > cc->gdb_num_core_regs) {
 136         return 0;
 137     }
 138
 139     if (n < 32) {          /* GP regs */
 140         return gdb_get_reg32(mem_buf, env->regs[n]);
 141     } else if (n == 32) {    /* PC */
 142         return gdb_get_reg32(mem_buf, env->regs[R_PC]);
 143     } else if (n < 49) {     /* Status regs */
 144         return gdb_get_reg32(mem_buf, env->regs[n - 1]);
 145     }
 146
 147     /* Invalid regs */
 148     return 0;
 149 }
 150
 151 static int nios2_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
 152 {
 153     Nios2CPU *cpu = NIOS2_CPU(cs);
 154     CPUClass *cc = CPU_GET_CLASS(cs);
 155     CPUNios2State *env = &cpu->env;
 156
 157     if (n > cc->gdb_num_core_regs) {
 158         return 0;
 159     }
 160
 161     if (n < 32) {            /* GP regs */
 162         env->regs[n] = ldl_p(mem_buf);
 163     } else if (n == 32) {    /* PC */
 164         env->regs[R_PC] = ldl_p(mem_buf);
 165     } else if (n < 49) {     /* Status regs */
 166         env->regs[n - 1] = ldl_p(mem_buf);
 167     }
 168
 169     return 4;
 170 }
 171
 172 static Property nios2_properties[] = {
 173     DEFINE_PROP_BOOL("mmu_present", Nios2CPU, mmu_present, true),
 174     /* ALTR,pid-num-bits */
 175     DEFINE_PROP_UINT32("mmu_pid_num_bits", Nios2CPU, pid_num_bits, 8),
 176     /* ALTR,tlb-num-ways */
 177     DEFINE_PROP_UINT32("mmu_tlb_num_ways", Nios2CPU, tlb_num_ways, 16),
 178     /* ALTR,tlb-num-entries */
 179     DEFINE_PROP_UINT32("mmu_pid_num_entries", Nios2CPU, tlb_num_entries, 256),
 180     DEFINE_PROP_END_OF_LIST(),
 181 };
 182
 183
 184 static void nios2_cpu_class_init(ObjectClass *oc, void *data)
 185 {
 186     DeviceClass *dc = DEVICE_CLASS(oc);
 187     CPUClass *cc = CPU_CLASS(oc);
 188     Nios2CPUClass *ncc = NIOS2_CPU_CLASS(oc);
 189
 190     device_class_set_parent_realize(dc, nios2_cpu_realizefn,
 191                                     &ncc->parent_realize);
 192     dc->props = nios2_properties;
 193     ncc->parent_reset = cc->reset;
 194     cc->reset = nios2_cpu_reset;
 195
 196     cc->class_by_name = nios2_cpu_class_by_name;
 197     cc->has_work = nios2_cpu_has_work;
 198     cc->do_interrupt = nios2_cpu_do_interrupt;
 199     cc->cpu_exec_interrupt = nios2_cpu_exec_interrupt;
 200     cc->dump_state = nios2_cpu_dump_state;
 201     cc->set_pc = nios2_cpu_set_pc;
 202     cc->disas_set_info = nios2_cpu_disas_set_info;
 203 #ifdef CONFIG_USER_ONLY
 204     cc->handle_mmu_fault = nios2_cpu_handle_mmu_fault;
 205 #else
 206     cc->do_unaligned_access = nios2_cpu_do_unaligned_access;
 207     cc->get_phys_page_debug = nios2_cpu_get_phys_page_debug;
 208 #endif
 209     cc->gdb_read_register = nios2_cpu_gdb_read_register;
 210     cc->gdb_write_register = nios2_cpu_gdb_write_register;
 211     cc->gdb_num_core_regs = 49;
 212     cc->tcg_initialize = nios2_tcg_init;
 213 }
 214
 215 static const TypeInfo nios2_cpu_type_info = {
 216     .name = TYPE_NIOS2_CPU,
 217     .parent = TYPE_CPU,
 218     .instance_size = sizeof(Nios2CPU),
 219     .instance_init = nios2_cpu_initfn,
 220     .class_size = sizeof(Nios2CPUClass),
 221     .class_init = nios2_cpu_class_init,
 222 };
 223
 224 static void nios2_cpu_register_types(void)
 225 {
 226     type_register_static(&nios2_cpu_type_info);
 227 }
 228
 229 type_init(nios2_cpu_register_types)