hw/scsi/esp-pci.c

   1 /*
   2  * QEMU ESP/NCR53C9x emulation
   3  *
   4  * Copyright (c) 2005-2006 Fabrice Bellard
   5  * Copyright (c) 2012 Herve Poussineau
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "hw/pci/pci.h"
  28 #include "hw/nvram/eeprom93xx.h"
  29 #include "hw/scsi/esp.h"
  30 #include "trace.h"
  31 #include "qapi/error.h"
  32 #include "qemu/log.h"
  33
  34 #define TYPE_AM53C974_DEVICE "am53c974"
  35
  36 #define PCI_ESP(obj) \
  37     OBJECT_CHECK(PCIESPState, (obj), TYPE_AM53C974_DEVICE)
  38
  39 #define DMA_CMD   0x0
  40 #define DMA_STC   0x1
  41 #define DMA_SPA   0x2
  42 #define DMA_WBC   0x3
  43 #define DMA_WAC   0x4
  44 #define DMA_STAT  0x5
  45 #define DMA_SMDLA 0x6
  46 #define DMA_WMAC  0x7
  47
  48 #define DMA_CMD_MASK   0x03
  49 #define DMA_CMD_DIAG   0x04
  50 #define DMA_CMD_MDL    0x10
  51 #define DMA_CMD_INTE_P 0x20
  52 #define DMA_CMD_INTE_D 0x40
  53 #define DMA_CMD_DIR    0x80
  54
  55 #define DMA_STAT_PWDN    0x01
  56 #define DMA_STAT_ERROR   0x02
  57 #define DMA_STAT_ABORT   0x04
  58 #define DMA_STAT_DONE    0x08
  59 #define DMA_STAT_SCSIINT 0x10
  60 #define DMA_STAT_BCMBLT  0x20
  61
  62 #define SBAC_STATUS 0x1000
  63
  64 typedef struct PCIESPState {
  65     /*< private >*/
  66     PCIDevice parent_obj;
  67     /*< public >*/
  68
  69     MemoryRegion io;
  70     uint32_t dma_regs[8];
  71     uint32_t sbac;
  72     ESPState esp;
  73 } PCIESPState;
  74
  75 static void esp_pci_handle_idle(PCIESPState *pci, uint32_t val)
  76 {
  77     trace_esp_pci_dma_idle(val);
  78     esp_dma_enable(&pci->esp, 0, 0);
  79 }
  80
  81 static void esp_pci_handle_blast(PCIESPState *pci, uint32_t val)
  82 {
  83     trace_esp_pci_dma_blast(val);
  84     qemu_log_mask(LOG_UNIMP, "am53c974: cmd BLAST not implemented\n");
  85 }
  86
  87 static void esp_pci_handle_abort(PCIESPState *pci, uint32_t val)
  88 {
  89     trace_esp_pci_dma_abort(val);
  90     if (pci->esp.current_req) {
  91         scsi_req_cancel(pci->esp.current_req);
  92     }
  93 }
  94
  95 static void esp_pci_handle_start(PCIESPState *pci, uint32_t val)
  96 {
  97     trace_esp_pci_dma_start(val);
  98
  99     pci->dma_regs[DMA_WBC] = pci->dma_regs[DMA_STC];
 100     pci->dma_regs[DMA_WAC] = pci->dma_regs[DMA_SPA];
 101     pci->dma_regs[DMA_WMAC] = pci->dma_regs[DMA_SMDLA];
 102
 103     pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_BCMBLT | DMA_STAT_SCSIINT
 104                                | DMA_STAT_DONE | DMA_STAT_ABORT
 105                                | DMA_STAT_ERROR | DMA_STAT_PWDN);
 106
 107     esp_dma_enable(&pci->esp, 0, 1);
 108 }
 109
 110 static void esp_pci_dma_write(PCIESPState *pci, uint32_t saddr, uint32_t val)
 111 {
 112     trace_esp_pci_dma_write(saddr, pci->dma_regs[saddr], val);
 113     switch (saddr) {
 114     case DMA_CMD:
 115         pci->dma_regs[saddr] = val;
 116         switch (val & DMA_CMD_MASK) {
 117         case 0x0: /* IDLE */
 118             esp_pci_handle_idle(pci, val);
 119             break;
 120         case 0x1: /* BLAST */
 121             esp_pci_handle_blast(pci, val);
 122             break;
 123         case 0x2: /* ABORT */
 124             esp_pci_handle_abort(pci, val);
 125             break;
 126         case 0x3: /* START */
 127             esp_pci_handle_start(pci, val);
 128             break;
 129         default: /* can't happen */
 130             abort();
 131         }
 132         break;
 133     case DMA_STC:
 134     case DMA_SPA:
 135     case DMA_SMDLA:
 136         pci->dma_regs[saddr] = val;
 137         break;
 138     case DMA_STAT:
 139         if (!(pci->sbac & SBAC_STATUS)) {
 140             /* clear some bits on write */
 141             uint32_t mask = DMA_STAT_ERROR | DMA_STAT_ABORT | DMA_STAT_DONE;
 142             pci->dma_regs[DMA_STAT] &= ~(val & mask);
 143         }
 144         break;
 145     default:
 146         trace_esp_pci_error_invalid_write_dma(val, saddr);
 147         return;
 148     }
 149 }
 150
 151 static uint32_t esp_pci_dma_read(PCIESPState *pci, uint32_t saddr)
 152 {
 153     uint32_t val;
 154
 155     val = pci->dma_regs[saddr];
 156     if (saddr == DMA_STAT) {
 157         if (pci->esp.rregs[ESP_RSTAT] & STAT_INT) {
 158             val |= DMA_STAT_SCSIINT;
 159         }
 160         if (pci->sbac & SBAC_STATUS) {
 161             pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_ERROR | DMA_STAT_ABORT |
 162                                          DMA_STAT_DONE);
 163         }
 164     }
 165
 166     trace_esp_pci_dma_read(saddr, val);
 167     return val;
 168 }
 169
 170 static void esp_pci_io_write(void *opaque, hwaddr addr,
 171                              uint64_t val, unsigned int size)
 172 {
 173     PCIESPState *pci = opaque;
 174
 175     if (size < 4 || addr & 3) {
 176         /* need to upgrade request: we only support 4-bytes accesses */
 177         uint32_t current = 0, mask;
 178         int shift;
 179
 180         if (addr < 0x40) {
 181             current = pci->esp.wregs[addr >> 2];
 182         } else if (addr < 0x60) {
 183             current = pci->dma_regs[(addr - 0x40) >> 2];
 184         } else if (addr < 0x74) {
 185             current = pci->sbac;
 186         }
 187
 188         shift = (4 - size) * 8;
 189         mask = (~(uint32_t)0 << shift) >> shift;
 190
 191         shift = ((4 - (addr & 3)) & 3) * 8;
 192         val <<= shift;
 193         val |= current & ~(mask << shift);
 194         addr &= ~3;
 195         size = 4;
 196     }
 197
 198     if (addr < 0x40) {
 199         /* SCSI core reg */
 200         esp_reg_write(&pci->esp, addr >> 2, val);
 201     } else if (addr < 0x60) {
 202         /* PCI DMA CCB */
 203         esp_pci_dma_write(pci, (addr - 0x40) >> 2, val);
 204     } else if (addr == 0x70) {
 205         /* DMA SCSI Bus and control */
 206         trace_esp_pci_sbac_write(pci->sbac, val);
 207         pci->sbac = val;
 208     } else {
 209         trace_esp_pci_error_invalid_write((int)addr);
 210     }
 211 }
 212
 213 static uint64_t esp_pci_io_read(void *opaque, hwaddr addr,
 214                                 unsigned int size)
 215 {
 216     PCIESPState *pci = opaque;
 217     uint32_t ret;
 218
 219     if (addr < 0x40) {
 220         /* SCSI core reg */
 221         ret = esp_reg_read(&pci->esp, addr >> 2);
 222     } else if (addr < 0x60) {
 223         /* PCI DMA CCB */
 224         ret = esp_pci_dma_read(pci, (addr - 0x40) >> 2);
 225     } else if (addr == 0x70) {
 226         /* DMA SCSI Bus and control */
 227         trace_esp_pci_sbac_read(pci->sbac);
 228         ret = pci->sbac;
 229     } else {
 230         /* Invalid region */
 231         trace_esp_pci_error_invalid_read((int)addr);
 232         ret = 0;
 233     }
 234
 235     /* give only requested data */
 236     ret >>= (addr & 3) * 8;
 237     ret &= ~(~(uint64_t)0 << (8 * size));
 238
 239     return ret;
 240 }
 241
 242 static void esp_pci_dma_memory_rw(PCIESPState *pci, uint8_t *buf, int len,
 243                                   DMADirection dir)
 244 {
 245     dma_addr_t addr;
 246     DMADirection expected_dir;
 247
 248     if (pci->dma_regs[DMA_CMD] & DMA_CMD_DIR) {
 249         expected_dir = DMA_DIRECTION_FROM_DEVICE;
 250     } else {
 251         expected_dir = DMA_DIRECTION_TO_DEVICE;
 252     }
 253
 254     if (dir != expected_dir) {
 255         trace_esp_pci_error_invalid_dma_direction();
 256         return;
 257     }
 258
 259     if (pci->dma_regs[DMA_STAT] & DMA_CMD_MDL) {
 260         qemu_log_mask(LOG_UNIMP, "am53c974: MDL transfer not implemented\n");
 261     }
 262
 263     addr = pci->dma_regs[DMA_SPA];
 264     if (pci->dma_regs[DMA_WBC] < len) {
 265         len = pci->dma_regs[DMA_WBC];
 266     }
 267
 268     pci_dma_rw(PCI_DEVICE(pci), addr, buf, len, dir);
 269
 270     /* update status registers */
 271     pci->dma_regs[DMA_WBC] -= len;
 272     pci->dma_regs[DMA_WAC] += len;
 273     if (pci->dma_regs[DMA_WBC] == 0) {
 274         pci->dma_regs[DMA_STAT] |= DMA_STAT_DONE;
 275     }
 276 }
 277
 278 static void esp_pci_dma_memory_read(void *opaque, uint8_t *buf, int len)
 279 {
 280     PCIESPState *pci = opaque;
 281     esp_pci_dma_memory_rw(pci, buf, len, DMA_DIRECTION_TO_DEVICE);
 282 }
 283
 284 static void esp_pci_dma_memory_write(void *opaque, uint8_t *buf, int len)
 285 {
 286     PCIESPState *pci = opaque;
 287     esp_pci_dma_memory_rw(pci, buf, len, DMA_DIRECTION_FROM_DEVICE);
 288 }
 289
 290 static const MemoryRegionOps esp_pci_io_ops = {
 291     .read = esp_pci_io_read,
 292     .write = esp_pci_io_write,
 293     .endianness = DEVICE_LITTLE_ENDIAN,
 294     .impl = {
 295         .min_access_size = 1,
 296         .max_access_size = 4,
 297     },
 298 };
 299
 300 static void esp_pci_hard_reset(DeviceState *dev)
 301 {
 302     PCIESPState *pci = PCI_ESP(dev);
 303     esp_hard_reset(&pci->esp);
 304     pci->dma_regs[DMA_CMD] &= ~(DMA_CMD_DIR | DMA_CMD_INTE_D | DMA_CMD_INTE_P
 305                               | DMA_CMD_MDL | DMA_CMD_DIAG | DMA_CMD_MASK);
 306     pci->dma_regs[DMA_WBC] &= ~0xffff;
 307     pci->dma_regs[DMA_WAC] = 0xffffffff;
 308     pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_BCMBLT | DMA_STAT_SCSIINT
 309                                | DMA_STAT_DONE | DMA_STAT_ABORT
 310                                | DMA_STAT_ERROR);
 311     pci->dma_regs[DMA_WMAC] = 0xfffffffd;
 312 }
 313
 314 static const VMStateDescription vmstate_esp_pci_scsi = {
 315     .name = "pciespscsi",
 316     .version_id = 0,
 317     .minimum_version_id = 0,
 318     .fields = (VMStateField[]) {
 319         VMSTATE_PCI_DEVICE(parent_obj, PCIESPState),
 320         VMSTATE_BUFFER_UNSAFE(dma_regs, PCIESPState, 0, 8 * sizeof(uint32_t)),
 321         VMSTATE_STRUCT(esp, PCIESPState, 0, vmstate_esp, ESPState),
 322         VMSTATE_END_OF_LIST()
 323     }
 324 };
 325
 326 static void esp_pci_command_complete(SCSIRequest *req, uint32_t status,
 327                                      size_t resid)
 328 {
 329     ESPState *s = req->hba_private;
 330     PCIESPState *pci = container_of(s, PCIESPState, esp);
 331
 332     esp_command_complete(req, status, resid);
 333     pci->dma_regs[DMA_WBC] = 0;
 334     pci->dma_regs[DMA_STAT] |= DMA_STAT_DONE;
 335 }
 336
 337 static const struct SCSIBusInfo esp_pci_scsi_info = {
 338     .tcq = false,
 339     .max_target = ESP_MAX_DEVS,
 340     .max_lun = 7,
 341
 342     .transfer_data = esp_transfer_data,
 343     .complete = esp_pci_command_complete,
 344     .cancel = esp_request_cancelled,
 345 };
 346
 347 static void esp_pci_scsi_realize(PCIDevice *dev, Error **errp)
 348 {
 349     PCIESPState *pci = PCI_ESP(dev);
 350     DeviceState *d = DEVICE(dev);
 351     ESPState *s = &pci->esp;
 352     uint8_t *pci_conf;
 353
 354     pci_conf = dev->config;
 355
 356     /* Interrupt pin A */
 357     pci_conf[PCI_INTERRUPT_PIN] = 0x01;
 358
 359     s->dma_memory_read = esp_pci_dma_memory_read;
 360     s->dma_memory_write = esp_pci_dma_memory_write;
 361     s->dma_opaque = pci;
 362     s->chip_id = TCHI_AM53C974;
 363     memory_region_init_io(&pci->io, OBJECT(pci), &esp_pci_io_ops, pci,
 364                           "esp-io", 0x80);
 365
 366     pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->io);
 367     s->irq = pci_allocate_irq(dev);
 368
 369     scsi_bus_new(&s->bus, sizeof(s->bus), d, &esp_pci_scsi_info, NULL);
 370 }
 371
 372 static void esp_pci_scsi_uninit(PCIDevice *d)
 373 {
 374     PCIESPState *pci = PCI_ESP(d);
 375
 376     qemu_free_irq(pci->esp.irq);
 377 }
 378
 379 static void esp_pci_class_init(ObjectClass *klass, void *data)
 380 {
 381     DeviceClass *dc = DEVICE_CLASS(klass);
 382     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 383
 384     k->realize = esp_pci_scsi_realize;
 385     k->exit = esp_pci_scsi_uninit;
 386     k->vendor_id = PCI_VENDOR_ID_AMD;
 387     k->device_id = PCI_DEVICE_ID_AMD_SCSI;
 388     k->revision = 0x10;
 389     k->class_id = PCI_CLASS_STORAGE_SCSI;
 390     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 391     dc->desc = "AMD Am53c974 PCscsi-PCI SCSI adapter";
 392     dc->reset = esp_pci_hard_reset;
 393     dc->vmsd = &vmstate_esp_pci_scsi;
 394 }
 395
 396 static const TypeInfo esp_pci_info = {
 397     .name = TYPE_AM53C974_DEVICE,
 398     .parent = TYPE_PCI_DEVICE,
 399     .instance_size = sizeof(PCIESPState),
 400     .class_init = esp_pci_class_init,
 401     .interfaces = (InterfaceInfo[]) {
 402         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 403         { },
 404     },
 405 };
 406
 407 typedef struct {
 408     PCIESPState pci;
 409     eeprom_t *eeprom;
 410 } DC390State;
 411
 412 #define TYPE_DC390_DEVICE "dc390"
 413 #define DC390(obj) \
 414     OBJECT_CHECK(DC390State, obj, TYPE_DC390_DEVICE)
 415
 416 #define EE_ADAPT_SCSI_ID 64
 417 #define EE_MODE2         65
 418 #define EE_DELAY         66
 419 #define EE_TAG_CMD_NUM   67
 420 #define EE_ADAPT_OPTIONS 68
 421 #define EE_BOOT_SCSI_ID  69
 422 #define EE_BOOT_SCSI_LUN 70
 423 #define EE_CHKSUM1       126
 424 #define EE_CHKSUM2       127
 425
 426 #define EE_ADAPT_OPTION_F6_F8_AT_BOOT   0x01
 427 #define EE_ADAPT_OPTION_BOOT_FROM_CDROM 0x02
 428 #define EE_ADAPT_OPTION_INT13           0x04
 429 #define EE_ADAPT_OPTION_SCAM_SUPPORT    0x08
 430
 431
 432 static uint32_t dc390_read_config(PCIDevice *dev, uint32_t addr, int l)
 433 {
 434     DC390State *pci = DC390(dev);
 435     uint32_t val;
 436
 437     val = pci_default_read_config(dev, addr, l);
 438
 439     if (addr == 0x00 && l == 1) {
 440         /* First byte of address space is AND-ed with EEPROM DO line */
 441         if (!eeprom93xx_read(pci->eeprom)) {
 442             val &= ~0xff;
 443         }
 444     }
 445
 446     return val;
 447 }
 448
 449 static void dc390_write_config(PCIDevice *dev,
 450                                uint32_t addr, uint32_t val, int l)
 451 {
 452     DC390State *pci = DC390(dev);
 453     if (addr == 0x80) {
 454         /* EEPROM write */
 455         int eesk = val & 0x80 ? 1 : 0;
 456         int eedi = val & 0x40 ? 1 : 0;
 457         eeprom93xx_write(pci->eeprom, 1, eesk, eedi);
 458     } else if (addr == 0xc0) {
 459         /* EEPROM CS low */
 460         eeprom93xx_write(pci->eeprom, 0, 0, 0);
 461     } else {
 462         pci_default_write_config(dev, addr, val, l);
 463     }
 464 }
 465
 466 static void dc390_scsi_realize(PCIDevice *dev, Error **errp)
 467 {
 468     DC390State *pci = DC390(dev);
 469     Error *err = NULL;
 470     uint8_t *contents;
 471     uint16_t chksum = 0;
 472     int i;
 473
 474     /* init base class */
 475     esp_pci_scsi_realize(dev, &err);
 476     if (err) {
 477         error_propagate(errp, err);
 478         return;
 479     }
 480
 481     /* EEPROM */
 482     pci->eeprom = eeprom93xx_new(DEVICE(dev), 64);
 483
 484     /* set default eeprom values */
 485     contents = (uint8_t *)eeprom93xx_data(pci->eeprom);
 486
 487     for (i = 0; i < 16; i++) {
 488         contents[i * 2] = 0x57;
 489         contents[i * 2 + 1] = 0x00;
 490     }
 491     contents[EE_ADAPT_SCSI_ID] = 7;
 492     contents[EE_MODE2] = 0x0f;
 493     contents[EE_TAG_CMD_NUM] = 0x04;
 494     contents[EE_ADAPT_OPTIONS] = EE_ADAPT_OPTION_F6_F8_AT_BOOT
 495                                | EE_ADAPT_OPTION_BOOT_FROM_CDROM
 496                                | EE_ADAPT_OPTION_INT13;
 497
 498     /* update eeprom checksum */
 499     for (i = 0; i < EE_CHKSUM1; i += 2) {
 500         chksum += contents[i] + (((uint16_t)contents[i + 1]) << 8);
 501     }
 502     chksum = 0x1234 - chksum;
 503     contents[EE_CHKSUM1] = chksum & 0xff;
 504     contents[EE_CHKSUM2] = chksum >> 8;
 505 }
 506
 507 static void dc390_class_init(ObjectClass *klass, void *data)
 508 {
 509     DeviceClass *dc = DEVICE_CLASS(klass);
 510     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 511
 512     k->realize = dc390_scsi_realize;
 513     k->config_read = dc390_read_config;
 514     k->config_write = dc390_write_config;
 515     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 516     dc->desc = "Tekram DC-390 SCSI adapter";
 517 }
 518
 519 static const TypeInfo dc390_info = {
 520     .name = "dc390",
 521     .parent = TYPE_AM53C974_DEVICE,
 522     .instance_size = sizeof(DC390State),
 523     .class_init = dc390_class_init,
 524 };
 525
 526 static void esp_pci_register_types(void)
 527 {
 528     type_register_static(&esp_pci_info);
 529     type_register_static(&dc390_info);
 530 }
 531
 532 type_init(esp_pci_register_types)