1 /* Support for generating ACPI tables and passing them to Guests
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
7 * Author: Michael S. Tsirkin <mst@redhat.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "qapi/qmp/qnum.h"
26 #include "acpi-build.h"
27 #include "qemu-common.h"
28 #include "qemu/bitmap.h"
29 #include "qemu/error-report.h"
30 #include "hw/pci/pci.h"
32 #include "target/i386/cpu.h"
33 #include "hw/misc/pvpanic.h"
34 #include "hw/timer/hpet.h"
35 #include "hw/acpi/acpi-defs.h"
36 #include "hw/acpi/acpi.h"
37 #include "hw/acpi/cpu.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/acpi/bios-linker-loader.h"
40 #include "hw/loader.h"
41 #include "hw/isa/isa.h"
42 #include "hw/block/fdc.h"
43 #include "hw/acpi/memory_hotplug.h"
44 #include "sysemu/tpm.h"
45 #include "hw/acpi/tpm.h"
46 #include "hw/acpi/vmgenid.h"
47 #include "sysemu/tpm_backend.h"
48 #include "hw/timer/mc146818rtc_regs.h"
49 #include "sysemu/numa.h"
51 /* Supported chipsets: */
52 #include "hw/acpi/piix4.h"
53 #include "hw/acpi/pcihp.h"
54 #include "hw/i386/ich9.h"
55 #include "hw/pci/pci_bus.h"
56 #include "hw/pci-host/q35.h"
57 #include "hw/i386/x86-iommu.h"
59 #include "hw/acpi/aml-build.h"
61 #include "qom/qom-qobject.h"
62 #include "hw/i386/amd_iommu.h"
63 #include "hw/i386/intel_iommu.h"
65 #include "hw/acpi/ipmi.h"
67 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
68 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
69 * a little bit, there should be plenty of free space since the DSDT
70 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
72 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
73 #define ACPI_BUILD_ALIGN_SIZE 0x1000
75 #define ACPI_BUILD_TABLE_SIZE 0x20000
77 /* #define DEBUG_ACPI_BUILD */
78 #ifdef DEBUG_ACPI_BUILD
79 #define ACPI_BUILD_DPRINTF(fmt, ...) \
80 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
82 #define ACPI_BUILD_DPRINTF(fmt, ...)
85 /* Default IOAPIC ID */
86 #define ACPI_BUILD_IOAPIC_ID 0x0
88 typedef struct AcpiMcfgInfo
{
93 typedef struct AcpiPmInfo
{
100 uint8_t acpi_enable_cmd
;
101 uint8_t acpi_disable_cmd
;
103 uint32_t gpe0_blk_len
;
105 uint16_t cpu_hp_io_base
;
106 uint16_t pcihp_io_base
;
107 uint16_t pcihp_io_len
;
110 typedef struct AcpiMiscInfo
{
113 TPMVersion tpm_version
;
114 const unsigned char *dsdt_code
;
116 uint16_t pvpanic_port
;
117 uint16_t applesmc_io_base
;
120 typedef struct AcpiBuildPciBusHotplugState
{
121 GArray
*device_table
;
122 GArray
*notify_table
;
123 struct AcpiBuildPciBusHotplugState
*parent
;
124 bool pcihp_bridge_en
;
125 } AcpiBuildPciBusHotplugState
;
127 static void acpi_get_pm_info(AcpiPmInfo
*pm
)
129 Object
*piix
= piix4_pm_find();
130 Object
*lpc
= ich9_lpc_find();
134 pm
->force_rev1_fadt
= false;
135 pm
->cpu_hp_io_base
= 0;
136 pm
->pcihp_io_base
= 0;
137 pm
->pcihp_io_len
= 0;
139 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */
140 pm
->force_rev1_fadt
= true;
142 pm
->cpu_hp_io_base
= PIIX4_CPU_HOTPLUG_IO_BASE
;
144 object_property_get_uint(obj
, ACPI_PCIHP_IO_BASE_PROP
, NULL
);
146 object_property_get_uint(obj
, ACPI_PCIHP_IO_LEN_PROP
, NULL
);
150 pm
->cpu_hp_io_base
= ICH9_CPU_HOTPLUG_IO_BASE
;
154 /* Fill in optional s3/s4 related properties */
155 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S3_DISABLED
, NULL
);
157 pm
->s3_disabled
= qnum_get_uint(qobject_to_qnum(o
));
159 pm
->s3_disabled
= false;
162 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S4_DISABLED
, NULL
);
164 pm
->s4_disabled
= qnum_get_uint(qobject_to_qnum(o
));
166 pm
->s4_disabled
= false;
169 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S4_VAL
, NULL
);
171 pm
->s4_val
= qnum_get_uint(qobject_to_qnum(o
));
177 /* Fill in mandatory properties */
178 pm
->sci_int
= object_property_get_uint(obj
, ACPI_PM_PROP_SCI_INT
, NULL
);
180 pm
->acpi_enable_cmd
= object_property_get_uint(obj
,
181 ACPI_PM_PROP_ACPI_ENABLE_CMD
,
183 pm
->acpi_disable_cmd
=
184 object_property_get_uint(obj
,
185 ACPI_PM_PROP_ACPI_DISABLE_CMD
,
187 pm
->io_base
= object_property_get_uint(obj
, ACPI_PM_PROP_PM_IO_BASE
,
189 pm
->gpe0_blk
= object_property_get_uint(obj
, ACPI_PM_PROP_GPE0_BLK
,
191 pm
->gpe0_blk_len
= object_property_get_uint(obj
, ACPI_PM_PROP_GPE0_BLK_LEN
,
193 pm
->pcihp_bridge_en
=
194 object_property_get_bool(obj
, "acpi-pci-hotplug-with-bridge-support",
198 static void acpi_get_misc_info(AcpiMiscInfo
*info
)
200 Object
*piix
= piix4_pm_find();
201 Object
*lpc
= ich9_lpc_find();
202 assert(!!piix
!= !!lpc
);
205 info
->is_piix4
= true;
208 info
->is_piix4
= false;
211 info
->has_hpet
= hpet_find();
212 info
->tpm_version
= tpm_get_version(tpm_find());
213 info
->pvpanic_port
= pvpanic_port();
214 info
->applesmc_io_base
= applesmc_port();
218 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
219 * On i386 arch we only have two pci hosts, so we can look only for them.
221 static Object
*acpi_get_i386_pci_host(void)
225 host
= OBJECT_CHECK(PCIHostState
,
226 object_resolve_path("/machine/i440fx", NULL
),
227 TYPE_PCI_HOST_BRIDGE
);
229 host
= OBJECT_CHECK(PCIHostState
,
230 object_resolve_path("/machine/q35", NULL
),
231 TYPE_PCI_HOST_BRIDGE
);
237 static void acpi_get_pci_holes(Range
*hole
, Range
*hole64
)
241 pci_host
= acpi_get_i386_pci_host();
244 range_set_bounds1(hole
,
245 object_property_get_uint(pci_host
,
246 PCI_HOST_PROP_PCI_HOLE_START
,
248 object_property_get_uint(pci_host
,
249 PCI_HOST_PROP_PCI_HOLE_END
,
251 range_set_bounds1(hole64
,
252 object_property_get_uint(pci_host
,
253 PCI_HOST_PROP_PCI_HOLE64_START
,
255 object_property_get_uint(pci_host
,
256 PCI_HOST_PROP_PCI_HOLE64_END
,
260 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
262 static void acpi_align_size(GArray
*blob
, unsigned align
)
264 /* Align size to multiple of given size. This reduces the chance
265 * we need to change size in the future (breaking cross version migration).
267 g_array_set_size(blob
, ROUND_UP(acpi_data_len(blob
), align
));
272 build_facs(GArray
*table_data
, BIOSLinker
*linker
)
274 AcpiFacsDescriptorRev1
*facs
= acpi_data_push(table_data
, sizeof *facs
);
275 memcpy(&facs
->signature
, "FACS", 4);
276 facs
->length
= cpu_to_le32(sizeof(*facs
));
279 /* Load chipset information in FADT */
280 static void fadt_setup(AcpiFadtDescriptorRev3
*fadt
, AcpiPmInfo
*pm
)
284 fadt
->sci_int
= cpu_to_le16(pm
->sci_int
);
285 fadt
->smi_cmd
= cpu_to_le32(ACPI_PORT_SMI_CMD
);
286 fadt
->acpi_enable
= pm
->acpi_enable_cmd
;
287 fadt
->acpi_disable
= pm
->acpi_disable_cmd
;
288 /* EVT, CNT, TMR offset matches hw/acpi/core.c */
289 fadt
->pm1a_evt_blk
= cpu_to_le32(pm
->io_base
);
290 fadt
->pm1a_cnt_blk
= cpu_to_le32(pm
->io_base
+ 0x04);
291 fadt
->pm_tmr_blk
= cpu_to_le32(pm
->io_base
+ 0x08);
292 fadt
->gpe0_blk
= cpu_to_le32(pm
->gpe0_blk
);
293 /* EVT, CNT, TMR length matches hw/acpi/core.c */
294 fadt
->pm1_evt_len
= 4;
295 fadt
->pm1_cnt_len
= 2;
296 fadt
->pm_tmr_len
= 4;
297 fadt
->gpe0_blk_len
= pm
->gpe0_blk_len
;
298 fadt
->plvl2_lat
= cpu_to_le16(0xfff); /* C2 state not supported */
299 fadt
->plvl3_lat
= cpu_to_le16(0xfff); /* C3 state not supported */
300 fadt
->flags
= cpu_to_le32((1 << ACPI_FADT_F_WBINVD
) |
301 (1 << ACPI_FADT_F_PROC_C1
) |
302 (1 << ACPI_FADT_F_SLP_BUTTON
) |
303 (1 << ACPI_FADT_F_RTC_S4
));
304 fadt
->flags
|= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK
);
305 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs
306 * For more than 8 CPUs, "Clustered Logical" mode has to be used
309 fadt
->flags
|= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL
);
311 fadt
->century
= RTC_CENTURY
;
312 if (pm
->force_rev1_fadt
) {
316 fadt
->flags
|= cpu_to_le32(1 << ACPI_FADT_F_RESET_REG_SUP
);
317 fadt
->reset_value
= 0xf;
318 fadt
->reset_register
.space_id
= AML_SYSTEM_IO
;
319 fadt
->reset_register
.bit_width
= 8;
320 fadt
->reset_register
.address
= cpu_to_le64(ICH9_RST_CNT_IOPORT
);
321 /* The above need not be conditional on machine type because the reset port
322 * happens to be the same on PIIX (pc) and ICH9 (q35). */
323 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT
!= RCR_IOPORT
);
325 fadt
->xpm1a_event_block
.space_id
= AML_SYSTEM_IO
;
326 fadt
->xpm1a_event_block
.bit_width
= fadt
->pm1_evt_len
* 8;
327 fadt
->xpm1a_event_block
.address
= cpu_to_le64(pm
->io_base
);
329 fadt
->xpm1a_control_block
.space_id
= AML_SYSTEM_IO
;
330 fadt
->xpm1a_control_block
.bit_width
= fadt
->pm1_cnt_len
* 8;
331 fadt
->xpm1a_control_block
.address
= cpu_to_le64(pm
->io_base
+ 0x4);
333 fadt
->xpm_timer_block
.space_id
= AML_SYSTEM_IO
;
334 fadt
->xpm_timer_block
.bit_width
= fadt
->pm_tmr_len
* 8;
335 fadt
->xpm_timer_block
.address
= cpu_to_le64(pm
->io_base
+ 0x8);
337 fadt
->xgpe0_block
.space_id
= AML_SYSTEM_IO
;
338 fadt
->xgpe0_block
.bit_width
= pm
->gpe0_blk_len
* 8;
339 fadt
->xgpe0_block
.address
= cpu_to_le64(pm
->gpe0_blk
);
345 build_fadt(GArray
*table_data
, BIOSLinker
*linker
, AcpiPmInfo
*pm
,
346 unsigned facs_tbl_offset
, unsigned dsdt_tbl_offset
,
347 const char *oem_id
, const char *oem_table_id
)
349 AcpiFadtDescriptorRev3
*fadt
= acpi_data_push(table_data
, sizeof(*fadt
));
350 unsigned fw_ctrl_offset
= (char *)&fadt
->firmware_ctrl
- table_data
->data
;
351 unsigned dsdt_entry_offset
= (char *)&fadt
->dsdt
- table_data
->data
;
352 unsigned xdsdt_entry_offset
= (char *)&fadt
->x_dsdt
- table_data
->data
;
353 int fadt_size
= sizeof(*fadt
);
356 /* FACS address to be filled by Guest linker */
357 bios_linker_loader_add_pointer(linker
,
358 ACPI_BUILD_TABLE_FILE
, fw_ctrl_offset
, sizeof(fadt
->firmware_ctrl
),
359 ACPI_BUILD_TABLE_FILE
, facs_tbl_offset
);
361 /* DSDT address to be filled by Guest linker */
362 fadt_setup(fadt
, pm
);
363 bios_linker_loader_add_pointer(linker
,
364 ACPI_BUILD_TABLE_FILE
, dsdt_entry_offset
, sizeof(fadt
->dsdt
),
365 ACPI_BUILD_TABLE_FILE
, dsdt_tbl_offset
);
366 if (pm
->force_rev1_fadt
) {
368 fadt_size
= offsetof(typeof(*fadt
), reset_register
);
370 bios_linker_loader_add_pointer(linker
,
371 ACPI_BUILD_TABLE_FILE
, xdsdt_entry_offset
, sizeof(fadt
->x_dsdt
),
372 ACPI_BUILD_TABLE_FILE
, dsdt_tbl_offset
);
375 build_header(linker
, table_data
,
376 (void *)fadt
, "FACP", fadt_size
, rev
, oem_id
, oem_table_id
);
379 void pc_madt_cpu_entry(AcpiDeviceIf
*adev
, int uid
,
380 const CPUArchIdList
*apic_ids
, GArray
*entry
)
382 uint32_t apic_id
= apic_ids
->cpus
[uid
].arch_id
;
384 /* ACPI spec says that LAPIC entry for non present
385 * CPU may be omitted from MADT or it must be marked
386 * as disabled. However omitting non present CPU from
387 * MADT breaks hotplug on linux. So possible CPUs
388 * should be put in MADT but kept disabled.
391 AcpiMadtProcessorApic
*apic
= acpi_data_push(entry
, sizeof *apic
);
393 apic
->type
= ACPI_APIC_PROCESSOR
;
394 apic
->length
= sizeof(*apic
);
395 apic
->processor_id
= uid
;
396 apic
->local_apic_id
= apic_id
;
397 if (apic_ids
->cpus
[uid
].cpu
!= NULL
) {
398 apic
->flags
= cpu_to_le32(1);
400 apic
->flags
= cpu_to_le32(0);
403 AcpiMadtProcessorX2Apic
*apic
= acpi_data_push(entry
, sizeof *apic
);
405 apic
->type
= ACPI_APIC_LOCAL_X2APIC
;
406 apic
->length
= sizeof(*apic
);
407 apic
->uid
= cpu_to_le32(uid
);
408 apic
->x2apic_id
= cpu_to_le32(apic_id
);
409 if (apic_ids
->cpus
[uid
].cpu
!= NULL
) {
410 apic
->flags
= cpu_to_le32(1);
412 apic
->flags
= cpu_to_le32(0);
418 build_madt(GArray
*table_data
, BIOSLinker
*linker
, PCMachineState
*pcms
)
420 MachineClass
*mc
= MACHINE_GET_CLASS(pcms
);
421 const CPUArchIdList
*apic_ids
= mc
->possible_cpu_arch_ids(MACHINE(pcms
));
422 int madt_start
= table_data
->len
;
423 AcpiDeviceIfClass
*adevc
= ACPI_DEVICE_IF_GET_CLASS(pcms
->acpi_dev
);
424 AcpiDeviceIf
*adev
= ACPI_DEVICE_IF(pcms
->acpi_dev
);
425 bool x2apic_mode
= false;
427 AcpiMultipleApicTable
*madt
;
428 AcpiMadtIoApic
*io_apic
;
429 AcpiMadtIntsrcovr
*intsrcovr
;
432 madt
= acpi_data_push(table_data
, sizeof *madt
);
433 madt
->local_apic_address
= cpu_to_le32(APIC_DEFAULT_ADDRESS
);
434 madt
->flags
= cpu_to_le32(1);
436 for (i
= 0; i
< apic_ids
->len
; i
++) {
437 adevc
->madt_cpu(adev
, i
, apic_ids
, table_data
);
438 if (apic_ids
->cpus
[i
].arch_id
> 254) {
443 io_apic
= acpi_data_push(table_data
, sizeof *io_apic
);
444 io_apic
->type
= ACPI_APIC_IO
;
445 io_apic
->length
= sizeof(*io_apic
);
446 io_apic
->io_apic_id
= ACPI_BUILD_IOAPIC_ID
;
447 io_apic
->address
= cpu_to_le32(IO_APIC_DEFAULT_ADDRESS
);
448 io_apic
->interrupt
= cpu_to_le32(0);
450 if (pcms
->apic_xrupt_override
) {
451 intsrcovr
= acpi_data_push(table_data
, sizeof *intsrcovr
);
452 intsrcovr
->type
= ACPI_APIC_XRUPT_OVERRIDE
;
453 intsrcovr
->length
= sizeof(*intsrcovr
);
454 intsrcovr
->source
= 0;
455 intsrcovr
->gsi
= cpu_to_le32(2);
456 intsrcovr
->flags
= cpu_to_le16(0); /* conforms to bus specifications */
458 for (i
= 1; i
< 16; i
++) {
459 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
460 if (!(ACPI_BUILD_PCI_IRQS
& (1 << i
))) {
461 /* No need for a INT source override structure. */
464 intsrcovr
= acpi_data_push(table_data
, sizeof *intsrcovr
);
465 intsrcovr
->type
= ACPI_APIC_XRUPT_OVERRIDE
;
466 intsrcovr
->length
= sizeof(*intsrcovr
);
467 intsrcovr
->source
= i
;
468 intsrcovr
->gsi
= cpu_to_le32(i
);
469 intsrcovr
->flags
= cpu_to_le16(0xd); /* active high, level triggered */
473 AcpiMadtLocalX2ApicNmi
*local_nmi
;
475 local_nmi
= acpi_data_push(table_data
, sizeof *local_nmi
);
476 local_nmi
->type
= ACPI_APIC_LOCAL_X2APIC_NMI
;
477 local_nmi
->length
= sizeof(*local_nmi
);
478 local_nmi
->uid
= 0xFFFFFFFF; /* all processors */
479 local_nmi
->flags
= cpu_to_le16(0);
480 local_nmi
->lint
= 1; /* ACPI_LINT1 */
482 AcpiMadtLocalNmi
*local_nmi
;
484 local_nmi
= acpi_data_push(table_data
, sizeof *local_nmi
);
485 local_nmi
->type
= ACPI_APIC_LOCAL_NMI
;
486 local_nmi
->length
= sizeof(*local_nmi
);
487 local_nmi
->processor_id
= 0xff; /* all processors */
488 local_nmi
->flags
= cpu_to_le16(0);
489 local_nmi
->lint
= 1; /* ACPI_LINT1 */
492 build_header(linker
, table_data
,
493 (void *)(table_data
->data
+ madt_start
), "APIC",
494 table_data
->len
- madt_start
, 1, NULL
, NULL
);
497 static void build_append_pcihp_notify_entry(Aml
*method
, int slot
)
500 int32_t devfn
= PCI_DEVFN(slot
, 0);
502 if_ctx
= aml_if(aml_and(aml_arg(0), aml_int(0x1U
<< slot
), NULL
));
503 aml_append(if_ctx
, aml_notify(aml_name("S%.02X", devfn
), aml_arg(1)));
504 aml_append(method
, if_ctx
);
507 static void build_append_pci_bus_devices(Aml
*parent_scope
, PCIBus
*bus
,
508 bool pcihp_bridge_en
)
510 Aml
*dev
, *notify_method
, *method
;
515 bsel
= object_property_get_qobject(OBJECT(bus
), ACPI_PCIHP_PROP_BSEL
, NULL
);
517 uint64_t bsel_val
= qnum_get_uint(qobject_to_qnum(bsel
));
519 aml_append(parent_scope
, aml_name_decl("BSEL", aml_int(bsel_val
)));
520 notify_method
= aml_method("DVNT", 2, AML_NOTSERIALIZED
);
523 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); i
+= PCI_FUNC_MAX
) {
526 PCIDevice
*pdev
= bus
->devices
[i
];
527 int slot
= PCI_SLOT(i
);
528 bool hotplug_enabled_dev
;
532 if (bsel
) { /* add hotplug slots for non present devices */
533 dev
= aml_device("S%.02X", PCI_DEVFN(slot
, 0));
534 aml_append(dev
, aml_name_decl("_SUN", aml_int(slot
)));
535 aml_append(dev
, aml_name_decl("_ADR", aml_int(slot
<< 16)));
536 method
= aml_method("_EJ0", 1, AML_NOTSERIALIZED
);
538 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
540 aml_append(dev
, method
);
541 aml_append(parent_scope
, dev
);
543 build_append_pcihp_notify_entry(notify_method
, slot
);
548 pc
= PCI_DEVICE_GET_CLASS(pdev
);
549 dc
= DEVICE_GET_CLASS(pdev
);
551 /* When hotplug for bridges is enabled, bridges are
552 * described in ACPI separately (see build_pci_bus_end).
553 * In this case they aren't themselves hot-pluggable.
554 * Hotplugged bridges *are* hot-pluggable.
556 bridge_in_acpi
= pc
->is_bridge
&& pcihp_bridge_en
&&
557 !DEVICE(pdev
)->hotplugged
;
559 hotplug_enabled_dev
= bsel
&& dc
->hotpluggable
&& !bridge_in_acpi
;
561 if (pc
->class_id
== PCI_CLASS_BRIDGE_ISA
) {
565 /* start to compose PCI slot descriptor */
566 dev
= aml_device("S%.02X", PCI_DEVFN(slot
, 0));
567 aml_append(dev
, aml_name_decl("_ADR", aml_int(slot
<< 16)));
569 if (pc
->class_id
== PCI_CLASS_DISPLAY_VGA
) {
570 /* add VGA specific AML methods */
573 if (object_dynamic_cast(OBJECT(pdev
), "qxl-vga")) {
579 method
= aml_method("_S1D", 0, AML_NOTSERIALIZED
);
580 aml_append(method
, aml_return(aml_int(0)));
581 aml_append(dev
, method
);
583 method
= aml_method("_S2D", 0, AML_NOTSERIALIZED
);
584 aml_append(method
, aml_return(aml_int(0)));
585 aml_append(dev
, method
);
587 method
= aml_method("_S3D", 0, AML_NOTSERIALIZED
);
588 aml_append(method
, aml_return(aml_int(s3d
)));
589 aml_append(dev
, method
);
590 } else if (hotplug_enabled_dev
) {
591 /* add _SUN/_EJ0 to make slot hotpluggable */
592 aml_append(dev
, aml_name_decl("_SUN", aml_int(slot
)));
594 method
= aml_method("_EJ0", 1, AML_NOTSERIALIZED
);
596 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
598 aml_append(dev
, method
);
601 build_append_pcihp_notify_entry(notify_method
, slot
);
603 } else if (bridge_in_acpi
) {
605 * device is coldplugged bridge,
606 * add child device descriptions into its scope
608 PCIBus
*sec_bus
= pci_bridge_get_sec_bus(PCI_BRIDGE(pdev
));
610 build_append_pci_bus_devices(dev
, sec_bus
, pcihp_bridge_en
);
612 /* slot descriptor has been composed, add it into parent context */
613 aml_append(parent_scope
, dev
);
617 aml_append(parent_scope
, notify_method
);
620 /* Append PCNT method to notify about events on local and child buses.
621 * Add unconditionally for root since DSDT expects it.
623 method
= aml_method("PCNT", 0, AML_NOTSERIALIZED
);
625 /* If bus supports hotplug select it and notify about local events */
627 uint64_t bsel_val
= qnum_get_uint(qobject_to_qnum(bsel
));
629 aml_append(method
, aml_store(aml_int(bsel_val
), aml_name("BNUM")));
631 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
634 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
638 /* Notify about child bus events in any case */
639 if (pcihp_bridge_en
) {
640 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
641 int32_t devfn
= sec
->parent_dev
->devfn
;
643 if (pci_bus_is_root(sec
) || pci_bus_is_express(sec
)) {
647 aml_append(method
, aml_name("^S%.02X.PCNT", devfn
));
650 aml_append(parent_scope
, method
);
651 qobject_decref(bsel
);
656 * @link_name: link name for PCI route entry
658 * build AML package containing a PCI route entry for @link_name
660 static Aml
*build_prt_entry(const char *link_name
)
662 Aml
*a_zero
= aml_int(0);
663 Aml
*pkg
= aml_package(4);
664 aml_append(pkg
, a_zero
);
665 aml_append(pkg
, a_zero
);
666 aml_append(pkg
, aml_name("%s", link_name
));
667 aml_append(pkg
, a_zero
);
672 * initialize_route - Initialize the interrupt routing rule
673 * through a specific LINK:
674 * if (lnk_idx == idx)
675 * route using link 'link_name'
677 static Aml
*initialize_route(Aml
*route
, const char *link_name
,
678 Aml
*lnk_idx
, int idx
)
680 Aml
*if_ctx
= aml_if(aml_equal(lnk_idx
, aml_int(idx
)));
681 Aml
*pkg
= build_prt_entry(link_name
);
683 aml_append(if_ctx
, aml_store(pkg
, route
));
689 * build_prt - Define interrupt rounting rules
691 * Returns an array of 128 routes, one for each device,
692 * based on device location.
693 * The main goal is to equaly distribute the interrupts
694 * over the 4 existing ACPI links (works only for i440fx).
695 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
698 static Aml
*build_prt(bool is_pci0_prt
)
700 Aml
*method
, *while_ctx
, *pin
, *res
;
702 method
= aml_method("_PRT", 0, AML_NOTSERIALIZED
);
705 aml_append(method
, aml_store(aml_package(128), res
));
706 aml_append(method
, aml_store(aml_int(0), pin
));
708 /* while (pin < 128) */
709 while_ctx
= aml_while(aml_lless(pin
, aml_int(128)));
711 Aml
*slot
= aml_local(2);
712 Aml
*lnk_idx
= aml_local(3);
713 Aml
*route
= aml_local(4);
715 /* slot = pin >> 2 */
716 aml_append(while_ctx
,
717 aml_store(aml_shiftright(pin
, aml_int(2), NULL
), slot
));
718 /* lnk_idx = (slot + pin) & 3 */
719 aml_append(while_ctx
,
720 aml_store(aml_and(aml_add(pin
, slot
, NULL
), aml_int(3), NULL
),
723 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
724 aml_append(while_ctx
, initialize_route(route
, "LNKD", lnk_idx
, 0));
726 Aml
*if_device_1
, *if_pin_4
, *else_pin_4
;
728 /* device 1 is the power-management device, needs SCI */
729 if_device_1
= aml_if(aml_equal(lnk_idx
, aml_int(1)));
731 if_pin_4
= aml_if(aml_equal(pin
, aml_int(4)));
734 aml_store(build_prt_entry("LNKS"), route
));
736 aml_append(if_device_1
, if_pin_4
);
737 else_pin_4
= aml_else();
739 aml_append(else_pin_4
,
740 aml_store(build_prt_entry("LNKA"), route
));
742 aml_append(if_device_1
, else_pin_4
);
744 aml_append(while_ctx
, if_device_1
);
746 aml_append(while_ctx
, initialize_route(route
, "LNKA", lnk_idx
, 1));
748 aml_append(while_ctx
, initialize_route(route
, "LNKB", lnk_idx
, 2));
749 aml_append(while_ctx
, initialize_route(route
, "LNKC", lnk_idx
, 3));
751 /* route[0] = 0x[slot]FFFF */
752 aml_append(while_ctx
,
753 aml_store(aml_or(aml_shiftleft(slot
, aml_int(16)), aml_int(0xFFFF),
755 aml_index(route
, aml_int(0))));
756 /* route[1] = pin & 3 */
757 aml_append(while_ctx
,
758 aml_store(aml_and(pin
, aml_int(3), NULL
),
759 aml_index(route
, aml_int(1))));
760 /* res[pin] = route */
761 aml_append(while_ctx
, aml_store(route
, aml_index(res
, pin
)));
763 aml_append(while_ctx
, aml_increment(pin
));
765 aml_append(method
, while_ctx
);
767 aml_append(method
, aml_return(res
));
772 typedef struct CrsRangeEntry
{
777 static void crs_range_insert(GPtrArray
*ranges
, uint64_t base
, uint64_t limit
)
779 CrsRangeEntry
*entry
;
781 entry
= g_malloc(sizeof(*entry
));
783 entry
->limit
= limit
;
785 g_ptr_array_add(ranges
, entry
);
788 static void crs_range_free(gpointer data
)
790 CrsRangeEntry
*entry
= (CrsRangeEntry
*)data
;
794 typedef struct CrsRangeSet
{
795 GPtrArray
*io_ranges
;
796 GPtrArray
*mem_ranges
;
797 GPtrArray
*mem_64bit_ranges
;
800 static void crs_range_set_init(CrsRangeSet
*range_set
)
802 range_set
->io_ranges
= g_ptr_array_new_with_free_func(crs_range_free
);
803 range_set
->mem_ranges
= g_ptr_array_new_with_free_func(crs_range_free
);
804 range_set
->mem_64bit_ranges
=
805 g_ptr_array_new_with_free_func(crs_range_free
);
808 static void crs_range_set_free(CrsRangeSet
*range_set
)
810 g_ptr_array_free(range_set
->io_ranges
, true);
811 g_ptr_array_free(range_set
->mem_ranges
, true);
812 g_ptr_array_free(range_set
->mem_64bit_ranges
, true);
815 static gint
crs_range_compare(gconstpointer a
, gconstpointer b
)
817 CrsRangeEntry
*entry_a
= *(CrsRangeEntry
**)a
;
818 CrsRangeEntry
*entry_b
= *(CrsRangeEntry
**)b
;
820 return (int64_t)entry_a
->base
- (int64_t)entry_b
->base
;
824 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
825 * interval, computes the 'free' ranges from the same interval.
826 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
827 * will return { [base - a1], [a2 - b1], [b2 - limit] }.
829 static void crs_replace_with_free_ranges(GPtrArray
*ranges
,
830 uint64_t start
, uint64_t end
)
832 GPtrArray
*free_ranges
= g_ptr_array_new();
833 uint64_t free_base
= start
;
836 g_ptr_array_sort(ranges
, crs_range_compare
);
837 for (i
= 0; i
< ranges
->len
; i
++) {
838 CrsRangeEntry
*used
= g_ptr_array_index(ranges
, i
);
840 if (free_base
< used
->base
) {
841 crs_range_insert(free_ranges
, free_base
, used
->base
- 1);
844 free_base
= used
->limit
+ 1;
847 if (free_base
< end
) {
848 crs_range_insert(free_ranges
, free_base
, end
);
851 g_ptr_array_set_size(ranges
, 0);
852 for (i
= 0; i
< free_ranges
->len
; i
++) {
853 g_ptr_array_add(ranges
, g_ptr_array_index(free_ranges
, i
));
856 g_ptr_array_free(free_ranges
, true);
860 * crs_range_merge - merges adjacent ranges in the given array.
861 * Array elements are deleted and replaced with the merged ranges.
863 static void crs_range_merge(GPtrArray
*range
)
865 GPtrArray
*tmp
= g_ptr_array_new_with_free_func(crs_range_free
);
866 CrsRangeEntry
*entry
;
867 uint64_t range_base
, range_limit
;
874 g_ptr_array_sort(range
, crs_range_compare
);
876 entry
= g_ptr_array_index(range
, 0);
877 range_base
= entry
->base
;
878 range_limit
= entry
->limit
;
879 for (i
= 1; i
< range
->len
; i
++) {
880 entry
= g_ptr_array_index(range
, i
);
881 if (entry
->base
- 1 == range_limit
) {
882 range_limit
= entry
->limit
;
884 crs_range_insert(tmp
, range_base
, range_limit
);
885 range_base
= entry
->base
;
886 range_limit
= entry
->limit
;
889 crs_range_insert(tmp
, range_base
, range_limit
);
891 g_ptr_array_set_size(range
, 0);
892 for (i
= 0; i
< tmp
->len
; i
++) {
893 entry
= g_ptr_array_index(tmp
, i
);
894 crs_range_insert(range
, entry
->base
, entry
->limit
);
896 g_ptr_array_free(tmp
, true);
899 static Aml
*build_crs(PCIHostState
*host
, CrsRangeSet
*range_set
)
901 Aml
*crs
= aml_resource_template();
902 CrsRangeSet temp_range_set
;
903 CrsRangeEntry
*entry
;
904 uint8_t max_bus
= pci_bus_num(host
->bus
);
909 crs_range_set_init(&temp_range_set
);
910 for (devfn
= 0; devfn
< ARRAY_SIZE(host
->bus
->devices
); devfn
++) {
911 uint64_t range_base
, range_limit
;
912 PCIDevice
*dev
= host
->bus
->devices
[devfn
];
918 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
919 PCIIORegion
*r
= &dev
->io_regions
[i
];
921 range_base
= r
->addr
;
922 range_limit
= r
->addr
+ r
->size
- 1;
925 * Work-around for old bioses
926 * that do not support multiple root buses
928 if (!range_base
|| range_base
> range_limit
) {
932 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
933 crs_range_insert(temp_range_set
.io_ranges
,
934 range_base
, range_limit
);
935 } else { /* "memory" */
936 crs_range_insert(temp_range_set
.mem_ranges
,
937 range_base
, range_limit
);
941 type
= dev
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
942 if (type
== PCI_HEADER_TYPE_BRIDGE
) {
943 uint8_t subordinate
= dev
->config
[PCI_SUBORDINATE_BUS
];
944 if (subordinate
> max_bus
) {
945 max_bus
= subordinate
;
948 range_base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
949 range_limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
952 * Work-around for old bioses
953 * that do not support multiple root buses
955 if (range_base
&& range_base
<= range_limit
) {
956 crs_range_insert(temp_range_set
.io_ranges
,
957 range_base
, range_limit
);
961 pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
963 pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
966 * Work-around for old bioses
967 * that do not support multiple root buses
969 if (range_base
&& range_base
<= range_limit
) {
970 uint64_t length
= range_limit
- range_base
+ 1;
971 if (range_limit
<= UINT32_MAX
&& length
<= UINT32_MAX
) {
972 crs_range_insert(temp_range_set
.mem_ranges
,
973 range_base
, range_limit
);
975 crs_range_insert(temp_range_set
.mem_64bit_ranges
,
976 range_base
, range_limit
);
981 pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
983 pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
986 * Work-around for old bioses
987 * that do not support multiple root buses
989 if (range_base
&& range_base
<= range_limit
) {
990 uint64_t length
= range_limit
- range_base
+ 1;
991 if (range_limit
<= UINT32_MAX
&& length
<= UINT32_MAX
) {
992 crs_range_insert(temp_range_set
.mem_ranges
,
993 range_base
, range_limit
);
995 crs_range_insert(temp_range_set
.mem_64bit_ranges
,
996 range_base
, range_limit
);
1002 crs_range_merge(temp_range_set
.io_ranges
);
1003 for (i
= 0; i
< temp_range_set
.io_ranges
->len
; i
++) {
1004 entry
= g_ptr_array_index(temp_range_set
.io_ranges
, i
);
1006 aml_word_io(AML_MIN_FIXED
, AML_MAX_FIXED
,
1007 AML_POS_DECODE
, AML_ENTIRE_RANGE
,
1008 0, entry
->base
, entry
->limit
, 0,
1009 entry
->limit
- entry
->base
+ 1));
1010 crs_range_insert(range_set
->io_ranges
, entry
->base
, entry
->limit
);
1013 crs_range_merge(temp_range_set
.mem_ranges
);
1014 for (i
= 0; i
< temp_range_set
.mem_ranges
->len
; i
++) {
1015 entry
= g_ptr_array_index(temp_range_set
.mem_ranges
, i
);
1017 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
,
1018 AML_MAX_FIXED
, AML_NON_CACHEABLE
,
1020 0, entry
->base
, entry
->limit
, 0,
1021 entry
->limit
- entry
->base
+ 1));
1022 crs_range_insert(range_set
->mem_ranges
, entry
->base
, entry
->limit
);
1025 crs_range_merge(temp_range_set
.mem_64bit_ranges
);
1026 for (i
= 0; i
< temp_range_set
.mem_64bit_ranges
->len
; i
++) {
1027 entry
= g_ptr_array_index(temp_range_set
.mem_64bit_ranges
, i
);
1029 aml_qword_memory(AML_POS_DECODE
, AML_MIN_FIXED
,
1030 AML_MAX_FIXED
, AML_NON_CACHEABLE
,
1032 0, entry
->base
, entry
->limit
, 0,
1033 entry
->limit
- entry
->base
+ 1));
1034 crs_range_insert(range_set
->mem_64bit_ranges
,
1035 entry
->base
, entry
->limit
);
1038 crs_range_set_free(&temp_range_set
);
1041 aml_word_bus_number(AML_MIN_FIXED
, AML_MAX_FIXED
, AML_POS_DECODE
,
1043 pci_bus_num(host
->bus
),
1046 max_bus
- pci_bus_num(host
->bus
) + 1));
1051 static void build_hpet_aml(Aml
*table
)
1057 Aml
*scope
= aml_scope("_SB");
1058 Aml
*dev
= aml_device("HPET");
1059 Aml
*zero
= aml_int(0);
1060 Aml
*id
= aml_local(0);
1061 Aml
*period
= aml_local(1);
1063 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0103")));
1064 aml_append(dev
, aml_name_decl("_UID", zero
));
1067 aml_operation_region("HPTM", AML_SYSTEM_MEMORY
, aml_int(HPET_BASE
),
1069 field
= aml_field("HPTM", AML_DWORD_ACC
, AML_LOCK
, AML_PRESERVE
);
1070 aml_append(field
, aml_named_field("VEND", 32));
1071 aml_append(field
, aml_named_field("PRD", 32));
1072 aml_append(dev
, field
);
1074 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1075 aml_append(method
, aml_store(aml_name("VEND"), id
));
1076 aml_append(method
, aml_store(aml_name("PRD"), period
));
1077 aml_append(method
, aml_shiftright(id
, aml_int(16), id
));
1078 if_ctx
= aml_if(aml_lor(aml_equal(id
, zero
),
1079 aml_equal(id
, aml_int(0xffff))));
1081 aml_append(if_ctx
, aml_return(zero
));
1083 aml_append(method
, if_ctx
);
1085 if_ctx
= aml_if(aml_lor(aml_equal(period
, zero
),
1086 aml_lgreater(period
, aml_int(100000000))));
1088 aml_append(if_ctx
, aml_return(zero
));
1090 aml_append(method
, if_ctx
);
1092 aml_append(method
, aml_return(aml_int(0x0F)));
1093 aml_append(dev
, method
);
1095 crs
= aml_resource_template();
1096 aml_append(crs
, aml_memory32_fixed(HPET_BASE
, HPET_LEN
, AML_READ_ONLY
));
1097 aml_append(dev
, aml_name_decl("_CRS", crs
));
1099 aml_append(scope
, dev
);
1100 aml_append(table
, scope
);
1103 static Aml
*build_fdinfo_aml(int idx
, FloppyDriveType type
)
1106 uint8_t maxc
, maxh
, maxs
;
1108 isa_fdc_get_drive_max_chs(type
, &maxc
, &maxh
, &maxs
);
1110 dev
= aml_device("FLP%c", 'A' + idx
);
1112 aml_append(dev
, aml_name_decl("_ADR", aml_int(idx
)));
1114 fdi
= aml_package(16);
1115 aml_append(fdi
, aml_int(idx
)); /* Drive Number */
1117 aml_int(cmos_get_fd_drive_type(type
))); /* Device Type */
1119 * the values below are the limits of the drive, and are thus independent
1120 * of the inserted media
1122 aml_append(fdi
, aml_int(maxc
)); /* Maximum Cylinder Number */
1123 aml_append(fdi
, aml_int(maxs
)); /* Maximum Sector Number */
1124 aml_append(fdi
, aml_int(maxh
)); /* Maximum Head Number */
1126 * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of
1127 * the drive type, so shall we
1129 aml_append(fdi
, aml_int(0xAF)); /* disk_specify_1 */
1130 aml_append(fdi
, aml_int(0x02)); /* disk_specify_2 */
1131 aml_append(fdi
, aml_int(0x25)); /* disk_motor_wait */
1132 aml_append(fdi
, aml_int(0x02)); /* disk_sector_siz */
1133 aml_append(fdi
, aml_int(0x12)); /* disk_eot */
1134 aml_append(fdi
, aml_int(0x1B)); /* disk_rw_gap */
1135 aml_append(fdi
, aml_int(0xFF)); /* disk_dtl */
1136 aml_append(fdi
, aml_int(0x6C)); /* disk_formt_gap */
1137 aml_append(fdi
, aml_int(0xF6)); /* disk_fill */
1138 aml_append(fdi
, aml_int(0x0F)); /* disk_head_sttl */
1139 aml_append(fdi
, aml_int(0x08)); /* disk_motor_strt */
1141 aml_append(dev
, aml_name_decl("_FDI", fdi
));
1145 static Aml
*build_fdc_device_aml(ISADevice
*fdc
)
1151 #define ACPI_FDE_MAX_FD 4
1152 uint32_t fde_buf
[5] = {
1153 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */
1154 cpu_to_le32(2) /* tape presence (2 == never present) */
1157 dev
= aml_device("FDC0");
1158 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0700")));
1160 crs
= aml_resource_template();
1161 aml_append(crs
, aml_io(AML_DECODE16
, 0x03F2, 0x03F2, 0x00, 0x04));
1162 aml_append(crs
, aml_io(AML_DECODE16
, 0x03F7, 0x03F7, 0x00, 0x01));
1163 aml_append(crs
, aml_irq_no_flags(6));
1165 aml_dma(AML_COMPATIBILITY
, AML_NOTBUSMASTER
, AML_TRANSFER8
, 2));
1166 aml_append(dev
, aml_name_decl("_CRS", crs
));
1168 for (i
= 0; i
< MIN(MAX_FD
, ACPI_FDE_MAX_FD
); i
++) {
1169 FloppyDriveType type
= isa_fdc_get_drive_type(fdc
, i
);
1171 if (type
< FLOPPY_DRIVE_TYPE_NONE
) {
1172 fde_buf
[i
] = cpu_to_le32(1); /* drive present */
1173 aml_append(dev
, build_fdinfo_aml(i
, type
));
1176 aml_append(dev
, aml_name_decl("_FDE",
1177 aml_buffer(sizeof(fde_buf
), (uint8_t *)fde_buf
)));
1182 static Aml
*build_rtc_device_aml(void)
1187 dev
= aml_device("RTC");
1188 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
1189 crs
= aml_resource_template();
1190 aml_append(crs
, aml_io(AML_DECODE16
, 0x0070, 0x0070, 0x10, 0x02));
1191 aml_append(crs
, aml_irq_no_flags(8));
1192 aml_append(crs
, aml_io(AML_DECODE16
, 0x0072, 0x0072, 0x02, 0x06));
1193 aml_append(dev
, aml_name_decl("_CRS", crs
));
1198 static Aml
*build_kbd_device_aml(void)
1204 dev
= aml_device("KBD");
1205 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0303")));
1207 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1208 aml_append(method
, aml_return(aml_int(0x0f)));
1209 aml_append(dev
, method
);
1211 crs
= aml_resource_template();
1212 aml_append(crs
, aml_io(AML_DECODE16
, 0x0060, 0x0060, 0x01, 0x01));
1213 aml_append(crs
, aml_io(AML_DECODE16
, 0x0064, 0x0064, 0x01, 0x01));
1214 aml_append(crs
, aml_irq_no_flags(1));
1215 aml_append(dev
, aml_name_decl("_CRS", crs
));
1220 static Aml
*build_mouse_device_aml(void)
1226 dev
= aml_device("MOU");
1227 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
1229 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1230 aml_append(method
, aml_return(aml_int(0x0f)));
1231 aml_append(dev
, method
);
1233 crs
= aml_resource_template();
1234 aml_append(crs
, aml_irq_no_flags(12));
1235 aml_append(dev
, aml_name_decl("_CRS", crs
));
1240 static Aml
*build_lpt_device_aml(void)
1247 Aml
*zero
= aml_int(0);
1248 Aml
*is_present
= aml_local(0);
1250 dev
= aml_device("LPT");
1251 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0400")));
1253 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1254 aml_append(method
, aml_store(aml_name("LPEN"), is_present
));
1255 if_ctx
= aml_if(aml_equal(is_present
, zero
));
1257 aml_append(if_ctx
, aml_return(aml_int(0x00)));
1259 aml_append(method
, if_ctx
);
1260 else_ctx
= aml_else();
1262 aml_append(else_ctx
, aml_return(aml_int(0x0f)));
1264 aml_append(method
, else_ctx
);
1265 aml_append(dev
, method
);
1267 crs
= aml_resource_template();
1268 aml_append(crs
, aml_io(AML_DECODE16
, 0x0378, 0x0378, 0x08, 0x08));
1269 aml_append(crs
, aml_irq_no_flags(7));
1270 aml_append(dev
, aml_name_decl("_CRS", crs
));
1275 static Aml
*build_com_device_aml(uint8_t uid
)
1282 Aml
*zero
= aml_int(0);
1283 Aml
*is_present
= aml_local(0);
1284 const char *enabled_field
= "CAEN";
1286 uint16_t io_port
= 0x03F8;
1288 assert(uid
== 1 || uid
== 2);
1290 enabled_field
= "CBEN";
1295 dev
= aml_device("COM%d", uid
);
1296 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0501")));
1297 aml_append(dev
, aml_name_decl("_UID", aml_int(uid
)));
1299 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1300 aml_append(method
, aml_store(aml_name("%s", enabled_field
), is_present
));
1301 if_ctx
= aml_if(aml_equal(is_present
, zero
));
1303 aml_append(if_ctx
, aml_return(aml_int(0x00)));
1305 aml_append(method
, if_ctx
);
1306 else_ctx
= aml_else();
1308 aml_append(else_ctx
, aml_return(aml_int(0x0f)));
1310 aml_append(method
, else_ctx
);
1311 aml_append(dev
, method
);
1313 crs
= aml_resource_template();
1314 aml_append(crs
, aml_io(AML_DECODE16
, io_port
, io_port
, 0x00, 0x08));
1315 aml_append(crs
, aml_irq_no_flags(irq
));
1316 aml_append(dev
, aml_name_decl("_CRS", crs
));
1321 static void build_isa_devices_aml(Aml
*table
)
1323 ISADevice
*fdc
= pc_find_fdc0();
1326 Aml
*scope
= aml_scope("_SB.PCI0.ISA");
1327 Object
*obj
= object_resolve_path_type("", TYPE_ISA_BUS
, &ambiguous
);
1329 aml_append(scope
, build_rtc_device_aml());
1330 aml_append(scope
, build_kbd_device_aml());
1331 aml_append(scope
, build_mouse_device_aml());
1333 aml_append(scope
, build_fdc_device_aml(fdc
));
1335 aml_append(scope
, build_lpt_device_aml());
1336 aml_append(scope
, build_com_device_aml(1));
1337 aml_append(scope
, build_com_device_aml(2));
1340 error_report("Multiple ISA busses, unable to define IPMI ACPI data");
1342 error_report("No ISA bus, unable to define IPMI ACPI data");
1344 build_acpi_ipmi_devices(scope
, BUS(obj
));
1347 aml_append(table
, scope
);
1350 static void build_dbg_aml(Aml
*table
)
1355 Aml
*scope
= aml_scope("\\");
1356 Aml
*buf
= aml_local(0);
1357 Aml
*len
= aml_local(1);
1358 Aml
*idx
= aml_local(2);
1361 aml_operation_region("DBG", AML_SYSTEM_IO
, aml_int(0x0402), 0x01));
1362 field
= aml_field("DBG", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1363 aml_append(field
, aml_named_field("DBGB", 8));
1364 aml_append(scope
, field
);
1366 method
= aml_method("DBUG", 1, AML_NOTSERIALIZED
);
1368 aml_append(method
, aml_to_hexstring(aml_arg(0), buf
));
1369 aml_append(method
, aml_to_buffer(buf
, buf
));
1370 aml_append(method
, aml_subtract(aml_sizeof(buf
), aml_int(1), len
));
1371 aml_append(method
, aml_store(aml_int(0), idx
));
1373 while_ctx
= aml_while(aml_lless(idx
, len
));
1374 aml_append(while_ctx
,
1375 aml_store(aml_derefof(aml_index(buf
, idx
)), aml_name("DBGB")));
1376 aml_append(while_ctx
, aml_increment(idx
));
1377 aml_append(method
, while_ctx
);
1379 aml_append(method
, aml_store(aml_int(0x0A), aml_name("DBGB")));
1380 aml_append(scope
, method
);
1382 aml_append(table
, scope
);
1385 static Aml
*build_link_dev(const char *name
, uint8_t uid
, Aml
*reg
)
1390 uint32_t irqs
[] = {5, 10, 11};
1392 dev
= aml_device("%s", name
);
1393 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1394 aml_append(dev
, aml_name_decl("_UID", aml_int(uid
)));
1396 crs
= aml_resource_template();
1397 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
, AML_ACTIVE_HIGH
,
1398 AML_SHARED
, irqs
, ARRAY_SIZE(irqs
)));
1399 aml_append(dev
, aml_name_decl("_PRS", crs
));
1401 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1402 aml_append(method
, aml_return(aml_call1("IQST", reg
)));
1403 aml_append(dev
, method
);
1405 method
= aml_method("_DIS", 0, AML_NOTSERIALIZED
);
1406 aml_append(method
, aml_or(reg
, aml_int(0x80), reg
));
1407 aml_append(dev
, method
);
1409 method
= aml_method("_CRS", 0, AML_NOTSERIALIZED
);
1410 aml_append(method
, aml_return(aml_call1("IQCR", reg
)));
1411 aml_append(dev
, method
);
1413 method
= aml_method("_SRS", 1, AML_NOTSERIALIZED
);
1414 aml_append(method
, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
1415 aml_append(method
, aml_store(aml_name("PRRI"), reg
));
1416 aml_append(dev
, method
);
1421 static Aml
*build_gsi_link_dev(const char *name
, uint8_t uid
, uint8_t gsi
)
1428 dev
= aml_device("%s", name
);
1429 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1430 aml_append(dev
, aml_name_decl("_UID", aml_int(uid
)));
1432 crs
= aml_resource_template();
1434 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
, AML_ACTIVE_HIGH
,
1435 AML_SHARED
, &irqs
, 1));
1436 aml_append(dev
, aml_name_decl("_PRS", crs
));
1438 aml_append(dev
, aml_name_decl("_CRS", crs
));
1441 * _DIS can be no-op because the interrupt cannot be disabled.
1443 method
= aml_method("_DIS", 0, AML_NOTSERIALIZED
);
1444 aml_append(dev
, method
);
1446 method
= aml_method("_SRS", 1, AML_NOTSERIALIZED
);
1447 aml_append(dev
, method
);
1452 /* _CRS method - get current settings */
1453 static Aml
*build_iqcr_method(bool is_piix4
)
1457 Aml
*method
= aml_method("IQCR", 1, AML_SERIALIZED
);
1458 Aml
*crs
= aml_resource_template();
1461 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
,
1462 AML_ACTIVE_HIGH
, AML_SHARED
, &irqs
, 1));
1463 aml_append(method
, aml_name_decl("PRR0", crs
));
1466 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
1469 if_ctx
= aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
1470 aml_append(if_ctx
, aml_store(aml_arg(0), aml_name("PRRI")));
1471 aml_append(method
, if_ctx
);
1474 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL
),
1478 aml_append(method
, aml_return(aml_name("PRR0")));
1482 /* _STA method - get status */
1483 static Aml
*build_irq_status_method(void)
1486 Aml
*method
= aml_method("IQST", 1, AML_NOTSERIALIZED
);
1488 if_ctx
= aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL
));
1489 aml_append(if_ctx
, aml_return(aml_int(0x09)));
1490 aml_append(method
, if_ctx
);
1491 aml_append(method
, aml_return(aml_int(0x0B)));
1495 static void build_piix4_pci0_int(Aml
*table
)
1502 Aml
*sb_scope
= aml_scope("_SB");
1503 Aml
*pci0_scope
= aml_scope("PCI0");
1505 aml_append(pci0_scope
, build_prt(true));
1506 aml_append(sb_scope
, pci0_scope
);
1508 field
= aml_field("PCI0.ISA.P40C", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1509 aml_append(field
, aml_named_field("PRQ0", 8));
1510 aml_append(field
, aml_named_field("PRQ1", 8));
1511 aml_append(field
, aml_named_field("PRQ2", 8));
1512 aml_append(field
, aml_named_field("PRQ3", 8));
1513 aml_append(sb_scope
, field
);
1515 aml_append(sb_scope
, build_irq_status_method());
1516 aml_append(sb_scope
, build_iqcr_method(true));
1518 aml_append(sb_scope
, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1519 aml_append(sb_scope
, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1520 aml_append(sb_scope
, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1521 aml_append(sb_scope
, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1523 dev
= aml_device("LNKS");
1525 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1526 aml_append(dev
, aml_name_decl("_UID", aml_int(4)));
1528 crs
= aml_resource_template();
1530 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
,
1531 AML_ACTIVE_HIGH
, AML_SHARED
,
1533 aml_append(dev
, aml_name_decl("_PRS", crs
));
1535 /* The SCI cannot be disabled and is always attached to GSI 9,
1536 * so these are no-ops. We only need this link to override the
1537 * polarity to active high and match the content of the MADT.
1539 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1540 aml_append(method
, aml_return(aml_int(0x0b)));
1541 aml_append(dev
, method
);
1543 method
= aml_method("_DIS", 0, AML_NOTSERIALIZED
);
1544 aml_append(dev
, method
);
1546 method
= aml_method("_CRS", 0, AML_NOTSERIALIZED
);
1547 aml_append(method
, aml_return(aml_name("_PRS")));
1548 aml_append(dev
, method
);
1550 method
= aml_method("_SRS", 1, AML_NOTSERIALIZED
);
1551 aml_append(dev
, method
);
1553 aml_append(sb_scope
, dev
);
1555 aml_append(table
, sb_scope
);
1558 static void append_q35_prt_entry(Aml
*ctx
, uint32_t nr
, const char *name
)
1563 char base
= name
[3] < 'E' ? 'A' : 'E';
1564 char *s
= g_strdup(name
);
1565 Aml
*a_nr
= aml_int((nr
<< 16) | 0xffff);
1567 assert(strlen(s
) == 4);
1569 head
= name
[3] - base
;
1570 for (i
= 0; i
< 4; i
++) {
1574 s
[3] = base
+ head
+ i
;
1575 pkg
= aml_package(4);
1576 aml_append(pkg
, a_nr
);
1577 aml_append(pkg
, aml_int(i
));
1578 aml_append(pkg
, aml_name("%s", s
));
1579 aml_append(pkg
, aml_int(0));
1580 aml_append(ctx
, pkg
);
1585 static Aml
*build_q35_routing_table(const char *str
)
1589 char *name
= g_strdup_printf("%s ", str
);
1591 pkg
= aml_package(128);
1592 for (i
= 0; i
< 0x18; i
++) {
1593 name
[3] = 'E' + (i
& 0x3);
1594 append_q35_prt_entry(pkg
, i
, name
);
1598 append_q35_prt_entry(pkg
, 0x18, name
);
1600 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1601 for (i
= 0x0019; i
< 0x1e; i
++) {
1603 append_q35_prt_entry(pkg
, i
, name
);
1606 /* PCIe->PCI bridge. use PIRQ[E-H] */
1608 append_q35_prt_entry(pkg
, 0x1e, name
);
1610 append_q35_prt_entry(pkg
, 0x1f, name
);
1616 static void build_q35_pci0_int(Aml
*table
)
1620 Aml
*sb_scope
= aml_scope("_SB");
1621 Aml
*pci0_scope
= aml_scope("PCI0");
1623 /* Zero => PIC mode, One => APIC Mode */
1624 aml_append(table
, aml_name_decl("PICF", aml_int(0)));
1625 method
= aml_method("_PIC", 1, AML_NOTSERIALIZED
);
1627 aml_append(method
, aml_store(aml_arg(0), aml_name("PICF")));
1629 aml_append(table
, method
);
1631 aml_append(pci0_scope
,
1632 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1633 aml_append(pci0_scope
,
1634 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1636 method
= aml_method("_PRT", 0, AML_NOTSERIALIZED
);
1641 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1643 /* Note: we provide the same info as the PCI routing
1644 table of the Bochs BIOS */
1645 if_ctx
= aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1646 aml_append(if_ctx
, aml_return(aml_name("PRTP")));
1647 aml_append(method
, if_ctx
);
1648 else_ctx
= aml_else();
1649 aml_append(else_ctx
, aml_return(aml_name("PRTA")));
1650 aml_append(method
, else_ctx
);
1652 aml_append(pci0_scope
, method
);
1653 aml_append(sb_scope
, pci0_scope
);
1655 field
= aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1656 aml_append(field
, aml_named_field("PRQA", 8));
1657 aml_append(field
, aml_named_field("PRQB", 8));
1658 aml_append(field
, aml_named_field("PRQC", 8));
1659 aml_append(field
, aml_named_field("PRQD", 8));
1660 aml_append(field
, aml_reserved_field(0x20));
1661 aml_append(field
, aml_named_field("PRQE", 8));
1662 aml_append(field
, aml_named_field("PRQF", 8));
1663 aml_append(field
, aml_named_field("PRQG", 8));
1664 aml_append(field
, aml_named_field("PRQH", 8));
1665 aml_append(sb_scope
, field
);
1667 aml_append(sb_scope
, build_irq_status_method());
1668 aml_append(sb_scope
, build_iqcr_method(false));
1670 aml_append(sb_scope
, build_link_dev("LNKA", 0, aml_name("PRQA")));
1671 aml_append(sb_scope
, build_link_dev("LNKB", 1, aml_name("PRQB")));
1672 aml_append(sb_scope
, build_link_dev("LNKC", 2, aml_name("PRQC")));
1673 aml_append(sb_scope
, build_link_dev("LNKD", 3, aml_name("PRQD")));
1674 aml_append(sb_scope
, build_link_dev("LNKE", 4, aml_name("PRQE")));
1675 aml_append(sb_scope
, build_link_dev("LNKF", 5, aml_name("PRQF")));
1676 aml_append(sb_scope
, build_link_dev("LNKG", 6, aml_name("PRQG")));
1677 aml_append(sb_scope
, build_link_dev("LNKH", 7, aml_name("PRQH")));
1679 aml_append(sb_scope
, build_gsi_link_dev("GSIA", 0x10, 0x10));
1680 aml_append(sb_scope
, build_gsi_link_dev("GSIB", 0x11, 0x11));
1681 aml_append(sb_scope
, build_gsi_link_dev("GSIC", 0x12, 0x12));
1682 aml_append(sb_scope
, build_gsi_link_dev("GSID", 0x13, 0x13));
1683 aml_append(sb_scope
, build_gsi_link_dev("GSIE", 0x14, 0x14));
1684 aml_append(sb_scope
, build_gsi_link_dev("GSIF", 0x15, 0x15));
1685 aml_append(sb_scope
, build_gsi_link_dev("GSIG", 0x16, 0x16));
1686 aml_append(sb_scope
, build_gsi_link_dev("GSIH", 0x17, 0x17));
1688 aml_append(table
, sb_scope
);
1691 static void build_q35_isa_bridge(Aml
*table
)
1697 scope
= aml_scope("_SB.PCI0");
1698 dev
= aml_device("ISA");
1699 aml_append(dev
, aml_name_decl("_ADR", aml_int(0x001F0000)));
1701 /* ICH9 PCI to ISA irq remapping */
1702 aml_append(dev
, aml_operation_region("PIRQ", AML_PCI_CONFIG
,
1703 aml_int(0x60), 0x0C));
1705 aml_append(dev
, aml_operation_region("LPCD", AML_PCI_CONFIG
,
1706 aml_int(0x80), 0x02));
1707 field
= aml_field("LPCD", AML_ANY_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1708 aml_append(field
, aml_named_field("COMA", 3));
1709 aml_append(field
, aml_reserved_field(1));
1710 aml_append(field
, aml_named_field("COMB", 3));
1711 aml_append(field
, aml_reserved_field(1));
1712 aml_append(field
, aml_named_field("LPTD", 2));
1713 aml_append(dev
, field
);
1715 aml_append(dev
, aml_operation_region("LPCE", AML_PCI_CONFIG
,
1716 aml_int(0x82), 0x02));
1718 field
= aml_field("LPCE", AML_ANY_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1719 aml_append(field
, aml_named_field("CAEN", 1));
1720 aml_append(field
, aml_named_field("CBEN", 1));
1721 aml_append(field
, aml_named_field("LPEN", 1));
1722 aml_append(dev
, field
);
1724 aml_append(scope
, dev
);
1725 aml_append(table
, scope
);
1728 static void build_piix4_pm(Aml
*table
)
1733 scope
= aml_scope("_SB.PCI0");
1734 dev
= aml_device("PX13");
1735 aml_append(dev
, aml_name_decl("_ADR", aml_int(0x00010003)));
1737 aml_append(dev
, aml_operation_region("P13C", AML_PCI_CONFIG
,
1738 aml_int(0x00), 0xff));
1739 aml_append(scope
, dev
);
1740 aml_append(table
, scope
);
1743 static void build_piix4_isa_bridge(Aml
*table
)
1749 scope
= aml_scope("_SB.PCI0");
1750 dev
= aml_device("ISA");
1751 aml_append(dev
, aml_name_decl("_ADR", aml_int(0x00010000)));
1753 /* PIIX PCI to ISA irq remapping */
1754 aml_append(dev
, aml_operation_region("P40C", AML_PCI_CONFIG
,
1755 aml_int(0x60), 0x04));
1757 field
= aml_field("^PX13.P13C", AML_ANY_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1758 /* Offset(0x5f),, 7, */
1759 aml_append(field
, aml_reserved_field(0x2f8));
1760 aml_append(field
, aml_reserved_field(7));
1761 aml_append(field
, aml_named_field("LPEN", 1));
1762 /* Offset(0x67),, 3, */
1763 aml_append(field
, aml_reserved_field(0x38));
1764 aml_append(field
, aml_reserved_field(3));
1765 aml_append(field
, aml_named_field("CAEN", 1));
1766 aml_append(field
, aml_reserved_field(3));
1767 aml_append(field
, aml_named_field("CBEN", 1));
1768 aml_append(dev
, field
);
1770 aml_append(scope
, dev
);
1771 aml_append(table
, scope
);
1774 static void build_piix4_pci_hotplug(Aml
*table
)
1780 scope
= aml_scope("_SB.PCI0");
1783 aml_operation_region("PCST", AML_SYSTEM_IO
, aml_int(0xae00), 0x08));
1784 field
= aml_field("PCST", AML_DWORD_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1785 aml_append(field
, aml_named_field("PCIU", 32));
1786 aml_append(field
, aml_named_field("PCID", 32));
1787 aml_append(scope
, field
);
1790 aml_operation_region("SEJ", AML_SYSTEM_IO
, aml_int(0xae08), 0x04));
1791 field
= aml_field("SEJ", AML_DWORD_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1792 aml_append(field
, aml_named_field("B0EJ", 32));
1793 aml_append(scope
, field
);
1796 aml_operation_region("BNMR", AML_SYSTEM_IO
, aml_int(0xae10), 0x04));
1797 field
= aml_field("BNMR", AML_DWORD_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1798 aml_append(field
, aml_named_field("BNUM", 32));
1799 aml_append(scope
, field
);
1801 aml_append(scope
, aml_mutex("BLCK", 0));
1803 method
= aml_method("PCEJ", 2, AML_NOTSERIALIZED
);
1804 aml_append(method
, aml_acquire(aml_name("BLCK"), 0xFFFF));
1805 aml_append(method
, aml_store(aml_arg(0), aml_name("BNUM")));
1807 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1808 aml_append(method
, aml_release(aml_name("BLCK")));
1809 aml_append(method
, aml_return(aml_int(0)));
1810 aml_append(scope
, method
);
1812 aml_append(table
, scope
);
1815 static Aml
*build_q35_osc_method(void)
1821 Aml
*a_cwd1
= aml_name("CDW1");
1822 Aml
*a_ctrl
= aml_local(0);
1824 method
= aml_method("_OSC", 4, AML_NOTSERIALIZED
);
1825 aml_append(method
, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1827 if_ctx
= aml_if(aml_equal(
1828 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1829 aml_append(if_ctx
, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1830 aml_append(if_ctx
, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1832 aml_append(if_ctx
, aml_store(aml_name("CDW3"), a_ctrl
));
1835 * Always allow native PME, AER (no dependencies)
1836 * Allow SHPC (PCI bridges can have SHPC controller)
1838 aml_append(if_ctx
, aml_and(a_ctrl
, aml_int(0x1F), a_ctrl
));
1840 if_ctx2
= aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1841 /* Unknown revision */
1842 aml_append(if_ctx2
, aml_or(a_cwd1
, aml_int(0x08), a_cwd1
));
1843 aml_append(if_ctx
, if_ctx2
);
1845 if_ctx2
= aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl
)));
1846 /* Capabilities bits were masked */
1847 aml_append(if_ctx2
, aml_or(a_cwd1
, aml_int(0x10), a_cwd1
));
1848 aml_append(if_ctx
, if_ctx2
);
1850 /* Update DWORD3 in the buffer */
1851 aml_append(if_ctx
, aml_store(a_ctrl
, aml_name("CDW3")));
1852 aml_append(method
, if_ctx
);
1854 else_ctx
= aml_else();
1855 /* Unrecognized UUID */
1856 aml_append(else_ctx
, aml_or(a_cwd1
, aml_int(4), a_cwd1
));
1857 aml_append(method
, else_ctx
);
1859 aml_append(method
, aml_return(aml_arg(3)));
1864 build_dsdt(GArray
*table_data
, BIOSLinker
*linker
,
1865 AcpiPmInfo
*pm
, AcpiMiscInfo
*misc
,
1866 Range
*pci_hole
, Range
*pci_hole64
, MachineState
*machine
)
1868 CrsRangeEntry
*entry
;
1869 Aml
*dsdt
, *sb_scope
, *scope
, *dev
, *method
, *field
, *pkg
, *crs
;
1870 CrsRangeSet crs_range_set
;
1871 PCMachineState
*pcms
= PC_MACHINE(machine
);
1872 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(machine
);
1873 uint32_t nr_mem
= machine
->ram_slots
;
1874 int root_bus_limit
= 0xFF;
1878 dsdt
= init_aml_allocator();
1880 /* Reserve space for header */
1881 acpi_data_push(dsdt
->buf
, sizeof(AcpiTableHeader
));
1883 build_dbg_aml(dsdt
);
1884 if (misc
->is_piix4
) {
1885 sb_scope
= aml_scope("_SB");
1886 dev
= aml_device("PCI0");
1887 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1888 aml_append(dev
, aml_name_decl("_ADR", aml_int(0)));
1889 aml_append(dev
, aml_name_decl("_UID", aml_int(1)));
1890 aml_append(sb_scope
, dev
);
1891 aml_append(dsdt
, sb_scope
);
1893 build_hpet_aml(dsdt
);
1894 build_piix4_pm(dsdt
);
1895 build_piix4_isa_bridge(dsdt
);
1896 build_isa_devices_aml(dsdt
);
1897 build_piix4_pci_hotplug(dsdt
);
1898 build_piix4_pci0_int(dsdt
);
1900 sb_scope
= aml_scope("_SB");
1901 dev
= aml_device("PCI0");
1902 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1903 aml_append(dev
, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1904 aml_append(dev
, aml_name_decl("_ADR", aml_int(0)));
1905 aml_append(dev
, aml_name_decl("_UID", aml_int(1)));
1906 aml_append(dev
, build_q35_osc_method());
1907 aml_append(sb_scope
, dev
);
1908 aml_append(dsdt
, sb_scope
);
1910 build_hpet_aml(dsdt
);
1911 build_q35_isa_bridge(dsdt
);
1912 build_isa_devices_aml(dsdt
);
1913 build_q35_pci0_int(dsdt
);
1916 if (pcmc
->legacy_cpu_hotplug
) {
1917 build_legacy_cpu_hotplug_aml(dsdt
, machine
, pm
->cpu_hp_io_base
);
1919 CPUHotplugFeatures opts
= {
1920 .apci_1_compatible
= true, .has_legacy_cphp
= true
1922 build_cpus_aml(dsdt
, machine
, opts
, pm
->cpu_hp_io_base
,
1923 "\\_SB.PCI0", "\\_GPE._E02");
1925 build_memory_hotplug_aml(dsdt
, nr_mem
, "\\_SB.PCI0", "\\_GPE._E03");
1927 scope
= aml_scope("_GPE");
1929 aml_append(scope
, aml_name_decl("_HID", aml_string("ACPI0006")));
1931 if (misc
->is_piix4
) {
1932 method
= aml_method("_E01", 0, AML_NOTSERIALIZED
);
1934 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1935 aml_append(method
, aml_call0("\\_SB.PCI0.PCNT"));
1936 aml_append(method
, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1937 aml_append(scope
, method
);
1940 if (pcms
->acpi_nvdimm_state
.is_enabled
) {
1941 method
= aml_method("_E04", 0, AML_NOTSERIALIZED
);
1942 aml_append(method
, aml_notify(aml_name("\\_SB.NVDR"),
1944 aml_append(scope
, method
);
1947 aml_append(dsdt
, scope
);
1949 crs_range_set_init(&crs_range_set
);
1950 bus
= PC_MACHINE(machine
)->bus
;
1952 QLIST_FOREACH(bus
, &bus
->child
, sibling
) {
1953 uint8_t bus_num
= pci_bus_num(bus
);
1954 uint8_t numa_node
= pci_bus_numa_node(bus
);
1956 /* look only for expander root buses */
1957 if (!pci_bus_is_root(bus
)) {
1961 if (bus_num
< root_bus_limit
) {
1962 root_bus_limit
= bus_num
- 1;
1965 scope
= aml_scope("\\_SB");
1966 dev
= aml_device("PC%.02X", bus_num
);
1967 aml_append(dev
, aml_name_decl("_UID", aml_int(bus_num
)));
1968 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1969 aml_append(dev
, aml_name_decl("_BBN", aml_int(bus_num
)));
1970 if (pci_bus_is_express(bus
)) {
1971 aml_append(dev
, build_q35_osc_method());
1974 if (numa_node
!= NUMA_NODE_UNASSIGNED
) {
1975 aml_append(dev
, aml_name_decl("_PXM", aml_int(numa_node
)));
1978 aml_append(dev
, build_prt(false));
1979 crs
= build_crs(PCI_HOST_BRIDGE(BUS(bus
)->parent
), &crs_range_set
);
1980 aml_append(dev
, aml_name_decl("_CRS", crs
));
1981 aml_append(scope
, dev
);
1982 aml_append(dsdt
, scope
);
1986 scope
= aml_scope("\\_SB.PCI0");
1987 /* build PCI0._CRS */
1988 crs
= aml_resource_template();
1990 aml_word_bus_number(AML_MIN_FIXED
, AML_MAX_FIXED
, AML_POS_DECODE
,
1991 0x0000, 0x0, root_bus_limit
,
1992 0x0000, root_bus_limit
+ 1));
1993 aml_append(crs
, aml_io(AML_DECODE16
, 0x0CF8, 0x0CF8, 0x01, 0x08));
1996 aml_word_io(AML_MIN_FIXED
, AML_MAX_FIXED
,
1997 AML_POS_DECODE
, AML_ENTIRE_RANGE
,
1998 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
2000 crs_replace_with_free_ranges(crs_range_set
.io_ranges
, 0x0D00, 0xFFFF);
2001 for (i
= 0; i
< crs_range_set
.io_ranges
->len
; i
++) {
2002 entry
= g_ptr_array_index(crs_range_set
.io_ranges
, i
);
2004 aml_word_io(AML_MIN_FIXED
, AML_MAX_FIXED
,
2005 AML_POS_DECODE
, AML_ENTIRE_RANGE
,
2006 0x0000, entry
->base
, entry
->limit
,
2007 0x0000, entry
->limit
- entry
->base
+ 1));
2011 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
, AML_MAX_FIXED
,
2012 AML_CACHEABLE
, AML_READ_WRITE
,
2013 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
2015 crs_replace_with_free_ranges(crs_range_set
.mem_ranges
,
2016 range_lob(pci_hole
),
2017 range_upb(pci_hole
));
2018 for (i
= 0; i
< crs_range_set
.mem_ranges
->len
; i
++) {
2019 entry
= g_ptr_array_index(crs_range_set
.mem_ranges
, i
);
2021 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
, AML_MAX_FIXED
,
2022 AML_NON_CACHEABLE
, AML_READ_WRITE
,
2023 0, entry
->base
, entry
->limit
,
2024 0, entry
->limit
- entry
->base
+ 1));
2027 if (!range_is_empty(pci_hole64
)) {
2028 crs_replace_with_free_ranges(crs_range_set
.mem_64bit_ranges
,
2029 range_lob(pci_hole64
),
2030 range_upb(pci_hole64
));
2031 for (i
= 0; i
< crs_range_set
.mem_64bit_ranges
->len
; i
++) {
2032 entry
= g_ptr_array_index(crs_range_set
.mem_64bit_ranges
, i
);
2034 aml_qword_memory(AML_POS_DECODE
, AML_MIN_FIXED
,
2036 AML_CACHEABLE
, AML_READ_WRITE
,
2037 0, entry
->base
, entry
->limit
,
2038 0, entry
->limit
- entry
->base
+ 1));
2042 if (TPM_IS_TIS(tpm_find())) {
2043 aml_append(crs
, aml_memory32_fixed(TPM_TIS_ADDR_BASE
,
2044 TPM_TIS_ADDR_SIZE
, AML_READ_WRITE
));
2046 aml_append(scope
, aml_name_decl("_CRS", crs
));
2048 /* reserve GPE0 block resources */
2049 dev
= aml_device("GPE0");
2050 aml_append(dev
, aml_name_decl("_HID", aml_string("PNP0A06")));
2051 aml_append(dev
, aml_name_decl("_UID", aml_string("GPE0 resources")));
2052 /* device present, functioning, decoding, not shown in UI */
2053 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
2054 crs
= aml_resource_template();
2056 aml_io(AML_DECODE16
, pm
->gpe0_blk
, pm
->gpe0_blk
, 1, pm
->gpe0_blk_len
)
2058 aml_append(dev
, aml_name_decl("_CRS", crs
));
2059 aml_append(scope
, dev
);
2061 crs_range_set_free(&crs_range_set
);
2063 /* reserve PCIHP resources */
2064 if (pm
->pcihp_io_len
) {
2065 dev
= aml_device("PHPR");
2066 aml_append(dev
, aml_name_decl("_HID", aml_string("PNP0A06")));
2068 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
2069 /* device present, functioning, decoding, not shown in UI */
2070 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
2071 crs
= aml_resource_template();
2073 aml_io(AML_DECODE16
, pm
->pcihp_io_base
, pm
->pcihp_io_base
, 1,
2076 aml_append(dev
, aml_name_decl("_CRS", crs
));
2077 aml_append(scope
, dev
);
2079 aml_append(dsdt
, scope
);
2081 /* create S3_ / S4_ / S5_ packages if necessary */
2082 scope
= aml_scope("\\");
2083 if (!pm
->s3_disabled
) {
2084 pkg
= aml_package(4);
2085 aml_append(pkg
, aml_int(1)); /* PM1a_CNT.SLP_TYP */
2086 aml_append(pkg
, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2087 aml_append(pkg
, aml_int(0)); /* reserved */
2088 aml_append(pkg
, aml_int(0)); /* reserved */
2089 aml_append(scope
, aml_name_decl("_S3", pkg
));
2092 if (!pm
->s4_disabled
) {
2093 pkg
= aml_package(4);
2094 aml_append(pkg
, aml_int(pm
->s4_val
)); /* PM1a_CNT.SLP_TYP */
2095 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2096 aml_append(pkg
, aml_int(pm
->s4_val
));
2097 aml_append(pkg
, aml_int(0)); /* reserved */
2098 aml_append(pkg
, aml_int(0)); /* reserved */
2099 aml_append(scope
, aml_name_decl("_S4", pkg
));
2102 pkg
= aml_package(4);
2103 aml_append(pkg
, aml_int(0)); /* PM1a_CNT.SLP_TYP */
2104 aml_append(pkg
, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
2105 aml_append(pkg
, aml_int(0)); /* reserved */
2106 aml_append(pkg
, aml_int(0)); /* reserved */
2107 aml_append(scope
, aml_name_decl("_S5", pkg
));
2108 aml_append(dsdt
, scope
);
2110 /* create fw_cfg node, unconditionally */
2112 /* when using port i/o, the 8-bit data register *always* overlaps
2113 * with half of the 16-bit control register. Hence, the total size
2114 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the
2115 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */
2116 uint8_t io_size
= object_property_get_bool(OBJECT(pcms
->fw_cfg
),
2117 "dma_enabled", NULL
) ?
2118 ROUND_UP(FW_CFG_CTL_SIZE
, 4) + sizeof(dma_addr_t
) :
2121 scope
= aml_scope("\\_SB.PCI0");
2122 dev
= aml_device("FWCF");
2124 aml_append(dev
, aml_name_decl("_HID", aml_string("QEMU0002")));
2126 /* device present, functioning, decoding, not shown in UI */
2127 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
2129 crs
= aml_resource_template();
2131 aml_io(AML_DECODE16
, FW_CFG_IO_BASE
, FW_CFG_IO_BASE
, 0x01, io_size
)
2133 aml_append(dev
, aml_name_decl("_CRS", crs
));
2135 aml_append(scope
, dev
);
2136 aml_append(dsdt
, scope
);
2139 if (misc
->applesmc_io_base
) {
2140 scope
= aml_scope("\\_SB.PCI0.ISA");
2141 dev
= aml_device("SMC");
2143 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("APP0001")));
2144 /* device present, functioning, decoding, not shown in UI */
2145 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
2147 crs
= aml_resource_template();
2149 aml_io(AML_DECODE16
, misc
->applesmc_io_base
, misc
->applesmc_io_base
,
2150 0x01, APPLESMC_MAX_DATA_LENGTH
)
2152 aml_append(crs
, aml_irq_no_flags(6));
2153 aml_append(dev
, aml_name_decl("_CRS", crs
));
2155 aml_append(scope
, dev
);
2156 aml_append(dsdt
, scope
);
2159 if (misc
->pvpanic_port
) {
2160 scope
= aml_scope("\\_SB.PCI0.ISA");
2162 dev
= aml_device("PEVT");
2163 aml_append(dev
, aml_name_decl("_HID", aml_string("QEMU0001")));
2165 crs
= aml_resource_template();
2167 aml_io(AML_DECODE16
, misc
->pvpanic_port
, misc
->pvpanic_port
, 1, 1)
2169 aml_append(dev
, aml_name_decl("_CRS", crs
));
2171 aml_append(dev
, aml_operation_region("PEOR", AML_SYSTEM_IO
,
2172 aml_int(misc
->pvpanic_port
), 1));
2173 field
= aml_field("PEOR", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
2174 aml_append(field
, aml_named_field("PEPT", 8));
2175 aml_append(dev
, field
);
2177 /* device present, functioning, decoding, shown in UI */
2178 aml_append(dev
, aml_name_decl("_STA", aml_int(0xF)));
2180 method
= aml_method("RDPT", 0, AML_NOTSERIALIZED
);
2181 aml_append(method
, aml_store(aml_name("PEPT"), aml_local(0)));
2182 aml_append(method
, aml_return(aml_local(0)));
2183 aml_append(dev
, method
);
2185 method
= aml_method("WRPT", 1, AML_NOTSERIALIZED
);
2186 aml_append(method
, aml_store(aml_arg(0), aml_name("PEPT")));
2187 aml_append(dev
, method
);
2189 aml_append(scope
, dev
);
2190 aml_append(dsdt
, scope
);
2193 sb_scope
= aml_scope("\\_SB");
2198 pci_host
= acpi_get_i386_pci_host();
2200 bus
= PCI_HOST_BRIDGE(pci_host
)->bus
;
2204 Aml
*scope
= aml_scope("PCI0");
2205 /* Scan all PCI buses. Generate tables to support hotplug. */
2206 build_append_pci_bus_devices(scope
, bus
, pm
->pcihp_bridge_en
);
2208 if (TPM_IS_TIS(tpm_find())) {
2209 dev
= aml_device("ISA.TPM");
2210 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C31")));
2211 aml_append(dev
, aml_name_decl("_STA", aml_int(0xF)));
2212 crs
= aml_resource_template();
2213 aml_append(crs
, aml_memory32_fixed(TPM_TIS_ADDR_BASE
,
2214 TPM_TIS_ADDR_SIZE
, AML_READ_WRITE
));
2216 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs,
2217 Rewrite to take IRQ from TPM device model and
2218 fix default IRQ value there to use some unused IRQ
2220 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */
2221 aml_append(dev
, aml_name_decl("_CRS", crs
));
2222 aml_append(scope
, dev
);
2225 aml_append(sb_scope
, scope
);
2229 if (TPM_IS_CRB(tpm_find())) {
2230 dev
= aml_device("TPM");
2231 aml_append(dev
, aml_name_decl("_HID", aml_string("MSFT0101")));
2232 crs
= aml_resource_template();
2233 aml_append(crs
, aml_memory32_fixed(TPM_CRB_ADDR_BASE
,
2234 TPM_CRB_ADDR_SIZE
, AML_READ_WRITE
));
2235 aml_append(dev
, aml_name_decl("_CRS", crs
));
2237 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
2238 aml_append(method
, aml_return(aml_int(0x0f)));
2239 aml_append(dev
, method
);
2241 aml_append(sb_scope
, dev
);
2244 aml_append(dsdt
, sb_scope
);
2246 /* copy AML table into ACPI tables blob and patch header there */
2247 g_array_append_vals(table_data
, dsdt
->buf
->data
, dsdt
->buf
->len
);
2248 build_header(linker
, table_data
,
2249 (void *)(table_data
->data
+ table_data
->len
- dsdt
->buf
->len
),
2250 "DSDT", dsdt
->buf
->len
, 1, NULL
, NULL
);
2251 free_aml_allocator();
2255 build_hpet(GArray
*table_data
, BIOSLinker
*linker
)
2259 hpet
= acpi_data_push(table_data
, sizeof(*hpet
));
2260 /* Note timer_block_id value must be kept in sync with value advertised by
2263 hpet
->timer_block_id
= cpu_to_le32(0x8086a201);
2264 hpet
->addr
.address
= cpu_to_le64(HPET_BASE
);
2265 build_header(linker
, table_data
,
2266 (void *)hpet
, "HPET", sizeof(*hpet
), 1, NULL
, NULL
);
2270 build_tpm_tcpa(GArray
*table_data
, BIOSLinker
*linker
, GArray
*tcpalog
)
2272 Acpi20Tcpa
*tcpa
= acpi_data_push(table_data
, sizeof *tcpa
);
2273 unsigned log_addr_size
= sizeof(tcpa
->log_area_start_address
);
2274 unsigned log_addr_offset
=
2275 (char *)&tcpa
->log_area_start_address
- table_data
->data
;
2277 tcpa
->platform_class
= cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT
);
2278 tcpa
->log_area_minimum_length
= cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE
);
2279 acpi_data_push(tcpalog
, le32_to_cpu(tcpa
->log_area_minimum_length
));
2281 bios_linker_loader_alloc(linker
, ACPI_BUILD_TPMLOG_FILE
, tcpalog
, 1,
2282 false /* high memory */);
2284 /* log area start address to be filled by Guest linker */
2285 bios_linker_loader_add_pointer(linker
,
2286 ACPI_BUILD_TABLE_FILE
, log_addr_offset
, log_addr_size
,
2287 ACPI_BUILD_TPMLOG_FILE
, 0);
2289 build_header(linker
, table_data
,
2290 (void *)tcpa
, "TCPA", sizeof(*tcpa
), 2, NULL
, NULL
);
2294 build_tpm2(GArray
*table_data
, BIOSLinker
*linker
, GArray
*tcpalog
)
2296 Acpi20TPM2
*tpm2_ptr
= acpi_data_push(table_data
, sizeof *tpm2_ptr
);
2297 unsigned log_addr_size
= sizeof(tpm2_ptr
->log_area_start_address
);
2298 unsigned log_addr_offset
=
2299 (char *)&tpm2_ptr
->log_area_start_address
- table_data
->data
;
2301 tpm2_ptr
->platform_class
= cpu_to_le16(TPM2_ACPI_CLASS_CLIENT
);
2302 if (TPM_IS_TIS(tpm_find())) {
2303 tpm2_ptr
->control_area_address
= cpu_to_le64(0);
2304 tpm2_ptr
->start_method
= cpu_to_le32(TPM2_START_METHOD_MMIO
);
2305 } else if (TPM_IS_CRB(tpm_find())) {
2306 tpm2_ptr
->control_area_address
= cpu_to_le64(TPM_CRB_ADDR_CTRL
);
2307 tpm2_ptr
->start_method
= cpu_to_le32(TPM2_START_METHOD_CRB
);
2309 g_warn_if_reached();
2312 tpm2_ptr
->log_area_minimum_length
=
2313 cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE
);
2315 /* log area start address to be filled by Guest linker */
2316 bios_linker_loader_add_pointer(linker
, ACPI_BUILD_TABLE_FILE
,
2317 log_addr_offset
, log_addr_size
,
2318 ACPI_BUILD_TPMLOG_FILE
, 0);
2319 build_header(linker
, table_data
,
2320 (void *)tpm2_ptr
, "TPM2", sizeof(*tpm2_ptr
), 4, NULL
, NULL
);
2323 #define HOLE_640K_START (640 * 1024)
2324 #define HOLE_640K_END (1024 * 1024)
2327 build_srat(GArray
*table_data
, BIOSLinker
*linker
, MachineState
*machine
)
2329 AcpiSystemResourceAffinityTable
*srat
;
2330 AcpiSratMemoryAffinity
*numamem
;
2333 int srat_start
, numa_start
, slots
;
2334 uint64_t mem_len
, mem_base
, next_base
;
2335 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2336 const CPUArchIdList
*apic_ids
= mc
->possible_cpu_arch_ids(machine
);
2337 PCMachineState
*pcms
= PC_MACHINE(machine
);
2338 ram_addr_t hotplugabble_address_space_size
=
2339 object_property_get_int(OBJECT(pcms
), PC_MACHINE_MEMHP_REGION_SIZE
,
2342 srat_start
= table_data
->len
;
2344 srat
= acpi_data_push(table_data
, sizeof *srat
);
2345 srat
->reserved1
= cpu_to_le32(1);
2347 for (i
= 0; i
< apic_ids
->len
; i
++) {
2348 int node_id
= apic_ids
->cpus
[i
].props
.node_id
;
2349 uint32_t apic_id
= apic_ids
->cpus
[i
].arch_id
;
2351 if (apic_id
< 255) {
2352 AcpiSratProcessorAffinity
*core
;
2354 core
= acpi_data_push(table_data
, sizeof *core
);
2355 core
->type
= ACPI_SRAT_PROCESSOR_APIC
;
2356 core
->length
= sizeof(*core
);
2357 core
->local_apic_id
= apic_id
;
2358 core
->proximity_lo
= node_id
;
2359 memset(core
->proximity_hi
, 0, 3);
2360 core
->local_sapic_eid
= 0;
2361 core
->flags
= cpu_to_le32(1);
2363 AcpiSratProcessorX2ApicAffinity
*core
;
2365 core
= acpi_data_push(table_data
, sizeof *core
);
2366 core
->type
= ACPI_SRAT_PROCESSOR_x2APIC
;
2367 core
->length
= sizeof(*core
);
2368 core
->x2apic_id
= cpu_to_le32(apic_id
);
2369 core
->proximity_domain
= cpu_to_le32(node_id
);
2370 core
->flags
= cpu_to_le32(1);
2375 /* the memory map is a bit tricky, it contains at least one hole
2376 * from 640k-1M and possibly another one from 3.5G-4G.
2379 numa_start
= table_data
->len
;
2381 for (i
= 1; i
< pcms
->numa_nodes
+ 1; ++i
) {
2382 mem_base
= next_base
;
2383 mem_len
= pcms
->node_mem
[i
- 1];
2384 next_base
= mem_base
+ mem_len
;
2386 /* Cut out the 640K hole */
2387 if (mem_base
<= HOLE_640K_START
&&
2388 next_base
> HOLE_640K_START
) {
2389 mem_len
-= next_base
- HOLE_640K_START
;
2391 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2392 build_srat_memory(numamem
, mem_base
, mem_len
, i
- 1,
2393 MEM_AFFINITY_ENABLED
);
2396 /* Check for the rare case: 640K < RAM < 1M */
2397 if (next_base
<= HOLE_640K_END
) {
2398 next_base
= HOLE_640K_END
;
2401 mem_base
= HOLE_640K_END
;
2402 mem_len
= next_base
- HOLE_640K_END
;
2405 /* Cut out the ACPI_PCI hole */
2406 if (mem_base
<= pcms
->below_4g_mem_size
&&
2407 next_base
> pcms
->below_4g_mem_size
) {
2408 mem_len
-= next_base
- pcms
->below_4g_mem_size
;
2410 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2411 build_srat_memory(numamem
, mem_base
, mem_len
, i
- 1,
2412 MEM_AFFINITY_ENABLED
);
2414 mem_base
= 1ULL << 32;
2415 mem_len
= next_base
- pcms
->below_4g_mem_size
;
2416 next_base
= mem_base
+ mem_len
;
2418 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2419 build_srat_memory(numamem
, mem_base
, mem_len
, i
- 1,
2420 MEM_AFFINITY_ENABLED
);
2422 slots
= (table_data
->len
- numa_start
) / sizeof *numamem
;
2423 for (; slots
< pcms
->numa_nodes
+ 2; slots
++) {
2424 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2425 build_srat_memory(numamem
, 0, 0, 0, MEM_AFFINITY_NOFLAGS
);
2429 * Entry is required for Windows to enable memory hotplug in OS
2430 * and for Linux to enable SWIOTLB when booted with less than
2431 * 4G of RAM. Windows works better if the entry sets proximity
2432 * to the highest NUMA node in the machine.
2433 * Memory devices may override proximity set by this entry,
2434 * providing _PXM method if necessary.
2436 if (hotplugabble_address_space_size
) {
2437 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2438 build_srat_memory(numamem
, pcms
->hotplug_memory
.base
,
2439 hotplugabble_address_space_size
, pcms
->numa_nodes
- 1,
2440 MEM_AFFINITY_HOTPLUGGABLE
| MEM_AFFINITY_ENABLED
);
2443 build_header(linker
, table_data
,
2444 (void *)(table_data
->data
+ srat_start
),
2446 table_data
->len
- srat_start
, 1, NULL
, NULL
);
2450 build_mcfg_q35(GArray
*table_data
, BIOSLinker
*linker
, AcpiMcfgInfo
*info
)
2452 AcpiTableMcfg
*mcfg
;
2454 int len
= sizeof(*mcfg
) + 1 * sizeof(mcfg
->allocation
[0]);
2456 mcfg
= acpi_data_push(table_data
, len
);
2457 mcfg
->allocation
[0].address
= cpu_to_le64(info
->mcfg_base
);
2458 /* Only a single allocation so no need to play with segments */
2459 mcfg
->allocation
[0].pci_segment
= cpu_to_le16(0);
2460 mcfg
->allocation
[0].start_bus_number
= 0;
2461 mcfg
->allocation
[0].end_bus_number
= PCIE_MMCFG_BUS(info
->mcfg_size
- 1);
2463 /* MCFG is used for ECAM which can be enabled or disabled by guest.
2464 * To avoid table size changes (which create migration issues),
2465 * always create the table even if there are no allocations,
2466 * but set the signature to a reserved value in this case.
2467 * ACPI spec requires OSPMs to ignore such tables.
2469 if (info
->mcfg_base
== PCIE_BASE_ADDR_UNMAPPED
) {
2470 /* Reserved signature: ignored by OSPM */
2475 build_header(linker
, table_data
, (void *)mcfg
, sig
, len
, 1, NULL
, NULL
);
2479 * VT-d spec 8.1 DMA Remapping Reporting Structure
2480 * (version Oct. 2014 or later)
2483 build_dmar_q35(GArray
*table_data
, BIOSLinker
*linker
)
2485 int dmar_start
= table_data
->len
;
2487 AcpiTableDmar
*dmar
;
2488 AcpiDmarHardwareUnit
*drhd
;
2489 AcpiDmarRootPortATS
*atsr
;
2490 uint8_t dmar_flags
= 0;
2491 X86IOMMUState
*iommu
= x86_iommu_get_default();
2492 AcpiDmarDeviceScope
*scope
= NULL
;
2493 /* Root complex IOAPIC use one path[0] only */
2494 size_t ioapic_scope_size
= sizeof(*scope
) + sizeof(scope
->path
[0]);
2495 IntelIOMMUState
*intel_iommu
= INTEL_IOMMU_DEVICE(iommu
);
2498 if (iommu
->intr_supported
) {
2499 dmar_flags
|= 0x1; /* Flags: 0x1: INT_REMAP */
2502 dmar
= acpi_data_push(table_data
, sizeof(*dmar
));
2503 dmar
->host_address_width
= intel_iommu
->aw_bits
- 1;
2504 dmar
->flags
= dmar_flags
;
2506 /* DMAR Remapping Hardware Unit Definition structure */
2507 drhd
= acpi_data_push(table_data
, sizeof(*drhd
) + ioapic_scope_size
);
2508 drhd
->type
= cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT
);
2509 drhd
->length
= cpu_to_le16(sizeof(*drhd
) + ioapic_scope_size
);
2510 drhd
->flags
= ACPI_DMAR_INCLUDE_PCI_ALL
;
2511 drhd
->pci_segment
= cpu_to_le16(0);
2512 drhd
->address
= cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR
);
2514 /* Scope definition for the root-complex IOAPIC. See VT-d spec
2515 * 8.3.1 (version Oct. 2014 or later). */
2516 scope
= &drhd
->scope
[0];
2517 scope
->entry_type
= 0x03; /* Type: 0x03 for IOAPIC */
2518 scope
->length
= ioapic_scope_size
;
2519 scope
->enumeration_id
= ACPI_BUILD_IOAPIC_ID
;
2520 scope
->bus
= Q35_PSEUDO_BUS_PLATFORM
;
2521 scope
->path
[0].device
= PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC
);
2522 scope
->path
[0].function
= PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC
);
2524 if (iommu
->dt_supported
) {
2525 atsr
= acpi_data_push(table_data
, sizeof(*atsr
));
2526 atsr
->type
= cpu_to_le16(ACPI_DMAR_TYPE_ATSR
);
2527 atsr
->length
= cpu_to_le16(sizeof(*atsr
));
2528 atsr
->flags
= ACPI_DMAR_ATSR_ALL_PORTS
;
2529 atsr
->pci_segment
= cpu_to_le16(0);
2532 build_header(linker
, table_data
, (void *)(table_data
->data
+ dmar_start
),
2533 "DMAR", table_data
->len
- dmar_start
, 1, NULL
, NULL
);
2536 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2
2537 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf
2540 build_amd_iommu(GArray
*table_data
, BIOSLinker
*linker
)
2542 int iommu_start
= table_data
->len
;
2543 AMDVIState
*s
= AMD_IOMMU_DEVICE(x86_iommu_get_default());
2546 acpi_data_push(table_data
, sizeof(AcpiTableHeader
));
2547 /* IVinfo - IO virtualization information common to all
2548 * IOMMU units in a system
2550 build_append_int_noprefix(table_data
, 40UL << 8/* PASize */, 4);
2552 build_append_int_noprefix(table_data
, 0, 8);
2554 /* IVHD definition - type 10h */
2555 build_append_int_noprefix(table_data
, 0x10, 1);
2556 /* virtualization flags */
2557 build_append_int_noprefix(table_data
,
2558 (1UL << 0) | /* HtTunEn */
2559 (1UL << 4) | /* iotblSup */
2560 (1UL << 6) | /* PrefSup */
2561 (1UL << 7), /* PPRSup */
2564 build_append_int_noprefix(table_data
, 0x24, 2);
2566 build_append_int_noprefix(table_data
, s
->devid
, 2);
2567 /* Capability offset */
2568 build_append_int_noprefix(table_data
, s
->capab_offset
, 2);
2569 /* IOMMU base address */
2570 build_append_int_noprefix(table_data
, s
->mmio
.addr
, 8);
2571 /* PCI Segment Group */
2572 build_append_int_noprefix(table_data
, 0, 2);
2574 build_append_int_noprefix(table_data
, 0, 2);
2575 /* IOMMU Feature Reporting */
2576 build_append_int_noprefix(table_data
,
2577 (48UL << 30) | /* HATS */
2578 (48UL << 28) | /* GATS */
2579 (1UL << 2), /* GTSup */
2582 * Type 1 device entry reporting all devices
2583 * These are 4-byte device entries currently reporting the range of
2584 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte)
2586 build_append_int_noprefix(table_data
, 0x0000001, 4);
2588 build_header(linker
, table_data
, (void *)(table_data
->data
+ iommu_start
),
2589 "IVRS", table_data
->len
- iommu_start
, 1, NULL
, NULL
);
2593 build_rsdp(GArray
*rsdp_table
, BIOSLinker
*linker
, unsigned rsdt_tbl_offset
)
2595 AcpiRsdpDescriptor
*rsdp
= acpi_data_push(rsdp_table
, sizeof *rsdp
);
2596 unsigned rsdt_pa_size
= sizeof(rsdp
->rsdt_physical_address
);
2597 unsigned rsdt_pa_offset
=
2598 (char *)&rsdp
->rsdt_physical_address
- rsdp_table
->data
;
2600 bios_linker_loader_alloc(linker
, ACPI_BUILD_RSDP_FILE
, rsdp_table
, 16,
2601 true /* fseg memory */);
2603 memcpy(&rsdp
->signature
, "RSD PTR ", 8);
2604 memcpy(rsdp
->oem_id
, ACPI_BUILD_APPNAME6
, 6);
2605 /* Address to be filled by Guest linker */
2606 bios_linker_loader_add_pointer(linker
,
2607 ACPI_BUILD_RSDP_FILE
, rsdt_pa_offset
, rsdt_pa_size
,
2608 ACPI_BUILD_TABLE_FILE
, rsdt_tbl_offset
);
2610 /* Checksum to be filled by Guest linker */
2611 bios_linker_loader_add_checksum(linker
, ACPI_BUILD_RSDP_FILE
,
2612 (char *)rsdp
- rsdp_table
->data
, sizeof *rsdp
,
2613 (char *)&rsdp
->checksum
- rsdp_table
->data
);
2619 struct AcpiBuildState
{
2620 /* Copy of table in RAM (for patching). */
2621 MemoryRegion
*table_mr
;
2622 /* Is table patched? */
2625 MemoryRegion
*rsdp_mr
;
2626 MemoryRegion
*linker_mr
;
2629 static bool acpi_get_mcfg(AcpiMcfgInfo
*mcfg
)
2634 pci_host
= acpi_get_i386_pci_host();
2637 o
= object_property_get_qobject(pci_host
, PCIE_HOST_MCFG_BASE
, NULL
);
2641 mcfg
->mcfg_base
= qnum_get_uint(qobject_to_qnum(o
));
2644 o
= object_property_get_qobject(pci_host
, PCIE_HOST_MCFG_SIZE
, NULL
);
2646 mcfg
->mcfg_size
= qnum_get_uint(qobject_to_qnum(o
));
2652 void acpi_build(AcpiBuildTables
*tables
, MachineState
*machine
)
2654 PCMachineState
*pcms
= PC_MACHINE(machine
);
2655 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
2656 GArray
*table_offsets
;
2657 unsigned facs
, dsdt
, rsdt
, fadt
;
2661 Range pci_hole
, pci_hole64
;
2664 GArray
*tables_blob
= tables
->table_data
;
2665 AcpiSlicOem slic_oem
= { .id
= NULL
, .table_id
= NULL
};
2666 Object
*vmgenid_dev
;
2668 acpi_get_pm_info(&pm
);
2669 acpi_get_misc_info(&misc
);
2670 acpi_get_pci_holes(&pci_hole
, &pci_hole64
);
2671 acpi_get_slic_oem(&slic_oem
);
2673 table_offsets
= g_array_new(false, true /* clear */,
2675 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2677 bios_linker_loader_alloc(tables
->linker
,
2678 ACPI_BUILD_TABLE_FILE
, tables_blob
,
2679 64 /* Ensure FACS is aligned */,
2680 false /* high memory */);
2683 * FACS is pointed to by FADT.
2684 * We place it first since it's the only table that has alignment
2687 facs
= tables_blob
->len
;
2688 build_facs(tables_blob
, tables
->linker
);
2690 /* DSDT is pointed to by FADT */
2691 dsdt
= tables_blob
->len
;
2692 build_dsdt(tables_blob
, tables
->linker
, &pm
, &misc
,
2693 &pci_hole
, &pci_hole64
, machine
);
2695 /* Count the size of the DSDT and SSDT, we will need it for legacy
2696 * sizing of ACPI tables.
2698 aml_len
+= tables_blob
->len
- dsdt
;
2700 /* ACPI tables pointed to by RSDT */
2701 fadt
= tables_blob
->len
;
2702 acpi_add_table(table_offsets
, tables_blob
);
2703 build_fadt(tables_blob
, tables
->linker
, &pm
, facs
, dsdt
,
2704 slic_oem
.id
, slic_oem
.table_id
);
2705 aml_len
+= tables_blob
->len
- fadt
;
2707 acpi_add_table(table_offsets
, tables_blob
);
2708 build_madt(tables_blob
, tables
->linker
, pcms
);
2710 vmgenid_dev
= find_vmgenid_dev();
2712 acpi_add_table(table_offsets
, tables_blob
);
2713 vmgenid_build_acpi(VMGENID(vmgenid_dev
), tables_blob
,
2714 tables
->vmgenid
, tables
->linker
);
2717 if (misc
.has_hpet
) {
2718 acpi_add_table(table_offsets
, tables_blob
);
2719 build_hpet(tables_blob
, tables
->linker
);
2721 if (misc
.tpm_version
!= TPM_VERSION_UNSPEC
) {
2722 acpi_add_table(table_offsets
, tables_blob
);
2723 build_tpm_tcpa(tables_blob
, tables
->linker
, tables
->tcpalog
);
2725 if (misc
.tpm_version
== TPM_VERSION_2_0
) {
2726 acpi_add_table(table_offsets
, tables_blob
);
2727 build_tpm2(tables_blob
, tables
->linker
, tables
->tcpalog
);
2730 if (pcms
->numa_nodes
) {
2731 acpi_add_table(table_offsets
, tables_blob
);
2732 build_srat(tables_blob
, tables
->linker
, machine
);
2733 if (have_numa_distance
) {
2734 acpi_add_table(table_offsets
, tables_blob
);
2735 build_slit(tables_blob
, tables
->linker
);
2738 if (acpi_get_mcfg(&mcfg
)) {
2739 acpi_add_table(table_offsets
, tables_blob
);
2740 build_mcfg_q35(tables_blob
, tables
->linker
, &mcfg
);
2742 if (x86_iommu_get_default()) {
2743 IommuType IOMMUType
= x86_iommu_get_type();
2744 if (IOMMUType
== TYPE_AMD
) {
2745 acpi_add_table(table_offsets
, tables_blob
);
2746 build_amd_iommu(tables_blob
, tables
->linker
);
2747 } else if (IOMMUType
== TYPE_INTEL
) {
2748 acpi_add_table(table_offsets
, tables_blob
);
2749 build_dmar_q35(tables_blob
, tables
->linker
);
2752 if (pcms
->acpi_nvdimm_state
.is_enabled
) {
2753 nvdimm_build_acpi(table_offsets
, tables_blob
, tables
->linker
,
2754 &pcms
->acpi_nvdimm_state
, machine
->ram_slots
);
2757 /* Add tables supplied by user (if any) */
2758 for (u
= acpi_table_first(); u
; u
= acpi_table_next(u
)) {
2759 unsigned len
= acpi_table_len(u
);
2761 acpi_add_table(table_offsets
, tables_blob
);
2762 g_array_append_vals(tables_blob
, u
, len
);
2765 /* RSDT is pointed to by RSDP */
2766 rsdt
= tables_blob
->len
;
2767 build_rsdt(tables_blob
, tables
->linker
, table_offsets
,
2768 slic_oem
.id
, slic_oem
.table_id
);
2770 /* RSDP is in FSEG memory, so allocate it separately */
2771 build_rsdp(tables
->rsdp
, tables
->linker
, rsdt
);
2773 /* We'll expose it all to Guest so we want to reduce
2774 * chance of size changes.
2776 * We used to align the tables to 4k, but of course this would
2777 * too simple to be enough. 4k turned out to be too small an
2778 * alignment very soon, and in fact it is almost impossible to
2779 * keep the table size stable for all (max_cpus, max_memory_slots)
2780 * combinations. So the table size is always 64k for pc-i440fx-2.1
2781 * and we give an error if the table grows beyond that limit.
2783 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2784 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2785 * than 2.0 and we can always pad the smaller tables with zeros. We can
2786 * then use the exact size of the 2.0 tables.
2788 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2790 if (pcmc
->legacy_acpi_table_size
) {
2791 /* Subtracting aml_len gives the size of fixed tables. Then add the
2792 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2794 int legacy_aml_len
=
2795 pcmc
->legacy_acpi_table_size
+
2796 ACPI_BUILD_LEGACY_CPU_AML_SIZE
* pcms
->apic_id_limit
;
2797 int legacy_table_size
=
2798 ROUND_UP(tables_blob
->len
- aml_len
+ legacy_aml_len
,
2799 ACPI_BUILD_ALIGN_SIZE
);
2800 if (tables_blob
->len
> legacy_table_size
) {
2801 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
2802 warn_report("ACPI table size %u exceeds %d bytes,"
2803 " migration may not work",
2804 tables_blob
->len
, legacy_table_size
);
2805 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2806 " or PCI bridges.");
2808 g_array_set_size(tables_blob
, legacy_table_size
);
2810 /* Make sure we have a buffer in case we need to resize the tables. */
2811 if (tables_blob
->len
> ACPI_BUILD_TABLE_SIZE
/ 2) {
2812 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
2813 warn_report("ACPI table size %u exceeds %d bytes,"
2814 " migration may not work",
2815 tables_blob
->len
, ACPI_BUILD_TABLE_SIZE
/ 2);
2816 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2817 " or PCI bridges.");
2819 acpi_align_size(tables_blob
, ACPI_BUILD_TABLE_SIZE
);
2822 acpi_align_size(tables
->linker
->cmd_blob
, ACPI_BUILD_ALIGN_SIZE
);
2824 /* Cleanup memory that's no longer used. */
2825 g_array_free(table_offsets
, true);
2828 static void acpi_ram_update(MemoryRegion
*mr
, GArray
*data
)
2830 uint32_t size
= acpi_data_len(data
);
2832 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2833 memory_region_ram_resize(mr
, size
, &error_abort
);
2835 memcpy(memory_region_get_ram_ptr(mr
), data
->data
, size
);
2836 memory_region_set_dirty(mr
, 0, size
);
2839 static void acpi_build_update(void *build_opaque
)
2841 AcpiBuildState
*build_state
= build_opaque
;
2842 AcpiBuildTables tables
;
2844 /* No state to update or already patched? Nothing to do. */
2845 if (!build_state
|| build_state
->patched
) {
2848 build_state
->patched
= 1;
2850 acpi_build_tables_init(&tables
);
2852 acpi_build(&tables
, MACHINE(qdev_get_machine()));
2854 acpi_ram_update(build_state
->table_mr
, tables
.table_data
);
2856 if (build_state
->rsdp
) {
2857 memcpy(build_state
->rsdp
, tables
.rsdp
->data
, acpi_data_len(tables
.rsdp
));
2859 acpi_ram_update(build_state
->rsdp_mr
, tables
.rsdp
);
2862 acpi_ram_update(build_state
->linker_mr
, tables
.linker
->cmd_blob
);
2863 acpi_build_tables_cleanup(&tables
, true);
2866 static void acpi_build_reset(void *build_opaque
)
2868 AcpiBuildState
*build_state
= build_opaque
;
2869 build_state
->patched
= 0;
2872 static MemoryRegion
*acpi_add_rom_blob(AcpiBuildState
*build_state
,
2873 GArray
*blob
, const char *name
,
2876 return rom_add_blob(name
, blob
->data
, acpi_data_len(blob
), max_size
, -1,
2877 name
, acpi_build_update
, build_state
, NULL
, true);
2880 static const VMStateDescription vmstate_acpi_build
= {
2881 .name
= "acpi_build",
2883 .minimum_version_id
= 1,
2884 .fields
= (VMStateField
[]) {
2885 VMSTATE_UINT8(patched
, AcpiBuildState
),
2886 VMSTATE_END_OF_LIST()
2890 void acpi_setup(void)
2892 PCMachineState
*pcms
= PC_MACHINE(qdev_get_machine());
2893 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
2894 AcpiBuildTables tables
;
2895 AcpiBuildState
*build_state
;
2896 Object
*vmgenid_dev
;
2898 if (!pcms
->fw_cfg
) {
2899 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2903 if (!pcms
->acpi_build_enabled
) {
2904 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2908 if (!acpi_enabled
) {
2909 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2913 build_state
= g_malloc0(sizeof *build_state
);
2915 acpi_build_tables_init(&tables
);
2916 acpi_build(&tables
, MACHINE(pcms
));
2918 /* Now expose it all to Guest */
2919 build_state
->table_mr
= acpi_add_rom_blob(build_state
, tables
.table_data
,
2920 ACPI_BUILD_TABLE_FILE
,
2921 ACPI_BUILD_TABLE_MAX_SIZE
);
2922 assert(build_state
->table_mr
!= NULL
);
2924 build_state
->linker_mr
=
2925 acpi_add_rom_blob(build_state
, tables
.linker
->cmd_blob
,
2926 "etc/table-loader", 0);
2928 fw_cfg_add_file(pcms
->fw_cfg
, ACPI_BUILD_TPMLOG_FILE
,
2929 tables
.tcpalog
->data
, acpi_data_len(tables
.tcpalog
));
2931 vmgenid_dev
= find_vmgenid_dev();
2933 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev
), pcms
->fw_cfg
,
2937 if (!pcmc
->rsdp_in_ram
) {
2939 * Keep for compatibility with old machine types.
2940 * Though RSDP is small, its contents isn't immutable, so
2941 * we'll update it along with the rest of tables on guest access.
2943 uint32_t rsdp_size
= acpi_data_len(tables
.rsdp
);
2945 build_state
->rsdp
= g_memdup(tables
.rsdp
->data
, rsdp_size
);
2946 fw_cfg_add_file_callback(pcms
->fw_cfg
, ACPI_BUILD_RSDP_FILE
,
2947 acpi_build_update
, NULL
, build_state
,
2948 build_state
->rsdp
, rsdp_size
, true);
2949 build_state
->rsdp_mr
= NULL
;
2951 build_state
->rsdp
= NULL
;
2952 build_state
->rsdp_mr
= acpi_add_rom_blob(build_state
, tables
.rsdp
,
2953 ACPI_BUILD_RSDP_FILE
, 0);
2956 qemu_register_reset(acpi_build_reset
, build_state
);
2957 acpi_build_reset(build_state
);
2958 vmstate_register(NULL
, 0, &vmstate_acpi_build
, build_state
);
2960 /* Cleanup tables but don't free the memory: we track it
2963 acpi_build_tables_cleanup(&tables
, false);