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Merge remote-tracking branch 'remotes/mcayland/tags/qemu-sparc-20190702' into staging
[qemu/ar7.git] / target / ppc / translate.c
blob4a5de280365b240b8959ef391af72f28afd7b950
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "internal.h"
24 #include "disas/disas.h"
25 #include "exec/exec-all.h"
26 #include "tcg-op.h"
27 #include "tcg-op-gvec.h"
28 #include "qemu/host-utils.h"
29 #include "exec/cpu_ldst.h"
30
31 #include "exec/helper-proto.h"
32 #include "exec/helper-gen.h"
33
34 #include "trace-tcg.h"
35 #include "exec/translator.h"
36 #include "exec/log.h"
37 #include "qemu/atomic128.h"
38
39
40 #define CPU_SINGLE_STEP 0x1
41 #define CPU_BRANCH_STEP 0x2
42 #define GDBSTUB_SINGLE_STEP 0x4
43
44 /* Include definitions for instructions classes and implementations flags */
45 /* #define PPC_DEBUG_DISAS */
46 /* #define DO_PPC_STATISTICS */
47
48 #ifdef PPC_DEBUG_DISAS
49 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
50 #else
51 # define LOG_DISAS(...) do { } while (0)
52 #endif
53 /*****************************************************************************/
54 /* Code translation helpers */
55
56 /* global register indexes */
57 static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */
58 + 10 * 4 + 22 * 5 /* SPE GPRh */
59 + 8 * 5 /* CRF */];
60 static TCGv cpu_gpr[32];
61 static TCGv cpu_gprh[32];
62 static TCGv_i32 cpu_crf[8];
63 static TCGv cpu_nip;
64 static TCGv cpu_msr;
65 static TCGv cpu_ctr;
66 static TCGv cpu_lr;
67 #if defined(TARGET_PPC64)
68 static TCGv cpu_cfar;
69 #endif
70 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32;
71 static TCGv cpu_reserve;
72 static TCGv cpu_reserve_val;
73 static TCGv cpu_fpscr;
74 static TCGv_i32 cpu_access_type;
75
76 #include "exec/gen-icount.h"
77
78 void ppc_translate_init(void)
79 {
80 int i;
81 char *p;
82 size_t cpu_reg_names_size;
83
84 p = cpu_reg_names;
85 cpu_reg_names_size = sizeof(cpu_reg_names);
86
87 for (i = 0; i < 8; i++) {
88 snprintf(p, cpu_reg_names_size, "crf%d", i);
89 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
90 offsetof(CPUPPCState, crf[i]), p);
91 p += 5;
92 cpu_reg_names_size -= 5;
93 }
94
95 for (i = 0; i < 32; i++) {
96 snprintf(p, cpu_reg_names_size, "r%d", i);
97 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
98 offsetof(CPUPPCState, gpr[i]), p);
99 p += (i < 10) ? 3 : 4;
100 cpu_reg_names_size -= (i < 10) ? 3 : 4;
101 snprintf(p, cpu_reg_names_size, "r%dH", i);
102 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
103 offsetof(CPUPPCState, gprh[i]), p);
104 p += (i < 10) ? 4 : 5;
105 cpu_reg_names_size -= (i < 10) ? 4 : 5;
106 }
107
108 cpu_nip = tcg_global_mem_new(cpu_env,
109 offsetof(CPUPPCState, nip), "nip");
110
111 cpu_msr = tcg_global_mem_new(cpu_env,
112 offsetof(CPUPPCState, msr), "msr");
113
114 cpu_ctr = tcg_global_mem_new(cpu_env,
115 offsetof(CPUPPCState, ctr), "ctr");
116
117 cpu_lr = tcg_global_mem_new(cpu_env,
118 offsetof(CPUPPCState, lr), "lr");
119
120 #if defined(TARGET_PPC64)
121 cpu_cfar = tcg_global_mem_new(cpu_env,
122 offsetof(CPUPPCState, cfar), "cfar");
123 #endif
124
125 cpu_xer = tcg_global_mem_new(cpu_env,
126 offsetof(CPUPPCState, xer), "xer");
127 cpu_so = tcg_global_mem_new(cpu_env,
128 offsetof(CPUPPCState, so), "SO");
129 cpu_ov = tcg_global_mem_new(cpu_env,
130 offsetof(CPUPPCState, ov), "OV");
131 cpu_ca = tcg_global_mem_new(cpu_env,
132 offsetof(CPUPPCState, ca), "CA");
133 cpu_ov32 = tcg_global_mem_new(cpu_env,
134 offsetof(CPUPPCState, ov32), "OV32");
135 cpu_ca32 = tcg_global_mem_new(cpu_env,
136 offsetof(CPUPPCState, ca32), "CA32");
137
138 cpu_reserve = tcg_global_mem_new(cpu_env,
139 offsetof(CPUPPCState, reserve_addr),
140 "reserve_addr");
141 cpu_reserve_val = tcg_global_mem_new(cpu_env,
142 offsetof(CPUPPCState, reserve_val),
143 "reserve_val");
144
145 cpu_fpscr = tcg_global_mem_new(cpu_env,
146 offsetof(CPUPPCState, fpscr), "fpscr");
147
148 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
149 offsetof(CPUPPCState, access_type),
150 "access_type");
151 }
152
153 /* internal defines */
154 struct DisasContext {
155 DisasContextBase base;
156 uint32_t opcode;
157 uint32_t exception;
158 /* Routine used to access memory */
159 bool pr, hv, dr, le_mode;
160 bool lazy_tlb_flush;
161 bool need_access_type;
162 int mem_idx;
163 int access_type;
164 /* Translation flags */
165 TCGMemOp default_tcg_memop_mask;
166 #if defined(TARGET_PPC64)
167 bool sf_mode;
168 bool has_cfar;
169 #endif
170 bool fpu_enabled;
171 bool altivec_enabled;
172 bool vsx_enabled;
173 bool spe_enabled;
174 bool tm_enabled;
175 bool gtse;
176 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
177 int singlestep_enabled;
178 uint32_t flags;
179 uint64_t insns_flags;
180 uint64_t insns_flags2;
181 };
182
183 /* Return true iff byteswap is needed in a scalar memop */
184 static inline bool need_byteswap(const DisasContext *ctx)
185 {
186 #if defined(TARGET_WORDS_BIGENDIAN)
187 return ctx->le_mode;
188 #else
189 return !ctx->le_mode;
190 #endif
191 }
192
193 /* True when active word size < size of target_long. */
194 #ifdef TARGET_PPC64
195 # define NARROW_MODE(C) (!(C)->sf_mode)
196 #else
197 # define NARROW_MODE(C) 0
198 #endif
199
200 struct opc_handler_t {
201 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
202 uint32_t inval1;
203 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
204 uint32_t inval2;
205 /* instruction type */
206 uint64_t type;
207 /* extended instruction type */
208 uint64_t type2;
209 /* handler */
210 void (*handler)(DisasContext *ctx);
211 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
212 const char *oname;
213 #endif
214 #if defined(DO_PPC_STATISTICS)
215 uint64_t count;
216 #endif
217 };
218
219 /* SPR load/store helpers */
220 static inline void gen_load_spr(TCGv t, int reg)
221 {
222 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
223 }
224
225 static inline void gen_store_spr(int reg, TCGv t)
226 {
227 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
228 }
229
230 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
231 {
232 if (ctx->need_access_type && ctx->access_type != access_type) {
233 tcg_gen_movi_i32(cpu_access_type, access_type);
234 ctx->access_type = access_type;
235 }
236 }
237
238 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
239 {
240 if (NARROW_MODE(ctx)) {
241 nip = (uint32_t)nip;
242 }
243 tcg_gen_movi_tl(cpu_nip, nip);
244 }
245
246 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
247 {
248 TCGv_i32 t0, t1;
249
250 /*
251 * These are all synchronous exceptions, we set the PC back to the
252 * faulting instruction
253 */
254 if (ctx->exception == POWERPC_EXCP_NONE) {
255 gen_update_nip(ctx, ctx->base.pc_next - 4);
256 }
257 t0 = tcg_const_i32(excp);
258 t1 = tcg_const_i32(error);
259 gen_helper_raise_exception_err(cpu_env, t0, t1);
260 tcg_temp_free_i32(t0);
261 tcg_temp_free_i32(t1);
262 ctx->exception = (excp);
263 }
264
265 static void gen_exception(DisasContext *ctx, uint32_t excp)
266 {
267 TCGv_i32 t0;
268
269 /*
270 * These are all synchronous exceptions, we set the PC back to the
271 * faulting instruction
272 */
273 if (ctx->exception == POWERPC_EXCP_NONE) {
274 gen_update_nip(ctx, ctx->base.pc_next - 4);
275 }
276 t0 = tcg_const_i32(excp);
277 gen_helper_raise_exception(cpu_env, t0);
278 tcg_temp_free_i32(t0);
279 ctx->exception = (excp);
280 }
281
282 static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
283 target_ulong nip)
284 {
285 TCGv_i32 t0;
286
287 gen_update_nip(ctx, nip);
288 t0 = tcg_const_i32(excp);
289 gen_helper_raise_exception(cpu_env, t0);
290 tcg_temp_free_i32(t0);
291 ctx->exception = (excp);
292 }
293
294 /*
295 * Tells the caller what is the appropriate exception to generate and prepares
296 * SPR registers for this exception.
297 *
298 * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or
299 * POWERPC_EXCP_DEBUG (on BookE).
300 */
301 static uint32_t gen_prep_dbgex(DisasContext *ctx)
302 {
303 if (ctx->flags & POWERPC_FLAG_DE) {
304 target_ulong dbsr = 0;
305 if (ctx->singlestep_enabled & CPU_SINGLE_STEP) {
306 dbsr = DBCR0_ICMP;
307 } else {
308 /* Must have been branch */
309 dbsr = DBCR0_BRT;
310 }
311 TCGv t0 = tcg_temp_new();
312 gen_load_spr(t0, SPR_BOOKE_DBSR);
313 tcg_gen_ori_tl(t0, t0, dbsr);
314 gen_store_spr(SPR_BOOKE_DBSR, t0);
315 tcg_temp_free(t0);
316 return POWERPC_EXCP_DEBUG;
317 } else {
318 return POWERPC_EXCP_TRACE;
319 }
320 }
321
322 static void gen_debug_exception(DisasContext *ctx)
323 {
324 TCGv_i32 t0;
325
326 /*
327 * These are all synchronous exceptions, we set the PC back to the
328 * faulting instruction
329 */
330 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
331 (ctx->exception != POWERPC_EXCP_SYNC)) {
332 gen_update_nip(ctx, ctx->base.pc_next);
333 }
334 t0 = tcg_const_i32(EXCP_DEBUG);
335 gen_helper_raise_exception(cpu_env, t0);
336 tcg_temp_free_i32(t0);
337 }
338
339 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
340 {
341 /* Will be converted to program check if needed */
342 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error);
343 }
344
345 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error)
346 {
347 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error);
348 }
349
350 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error)
351 {
352 /* Will be converted to program check if needed */
353 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error);
354 }
355
356 /* Stop translation */
357 static inline void gen_stop_exception(DisasContext *ctx)
358 {
359 gen_update_nip(ctx, ctx->base.pc_next);
360 ctx->exception = POWERPC_EXCP_STOP;
361 }
362
363 #ifndef CONFIG_USER_ONLY
364 /* No need to update nip here, as execution flow will change */
365 static inline void gen_sync_exception(DisasContext *ctx)
366 {
367 ctx->exception = POWERPC_EXCP_SYNC;
368 }
369 #endif
370
371 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
372 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
373
374 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
375 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
376
377 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
378 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
379
380 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
381 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
382
383 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \
384 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
385
386 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \
387 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2)
388
389 typedef struct opcode_t {
390 unsigned char opc1, opc2, opc3, opc4;
391 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
392 unsigned char pad[4];
393 #endif
394 opc_handler_t handler;
395 const char *oname;
396 } opcode_t;
397
398 /* Helpers for priv. check */
399 #define GEN_PRIV \
400 do { \
401 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
402 } while (0)
403
404 #if defined(CONFIG_USER_ONLY)
405 #define CHK_HV GEN_PRIV
406 #define CHK_SV GEN_PRIV
407 #define CHK_HVRM GEN_PRIV
408 #else
409 #define CHK_HV \
410 do { \
411 if (unlikely(ctx->pr || !ctx->hv)) { \
412 GEN_PRIV; \
413 } \
414 } while (0)
415 #define CHK_SV \
416 do { \
417 if (unlikely(ctx->pr)) { \
418 GEN_PRIV; \
419 } \
420 } while (0)
421 #define CHK_HVRM \
422 do { \
423 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
424 GEN_PRIV; \
425 } \
426 } while (0)
427 #endif
428
429 #define CHK_NONE
430
431 /*****************************************************************************/
432 /* PowerPC instructions table */
433
434 #if defined(DO_PPC_STATISTICS)
435 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
436 { \
437 .opc1 = op1, \
438 .opc2 = op2, \
439 .opc3 = op3, \
440 .opc4 = 0xff, \
441 .handler = { \
442 .inval1 = invl, \
443 .type = _typ, \
444 .type2 = _typ2, \
445 .handler = &gen_##name, \
446 .oname = stringify(name), \
447 }, \
448 .oname = stringify(name), \
449 }
450 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
451 { \
452 .opc1 = op1, \
453 .opc2 = op2, \
454 .opc3 = op3, \
455 .opc4 = 0xff, \
456 .handler = { \
457 .inval1 = invl1, \
458 .inval2 = invl2, \
459 .type = _typ, \
460 .type2 = _typ2, \
461 .handler = &gen_##name, \
462 .oname = stringify(name), \
463 }, \
464 .oname = stringify(name), \
465 }
466 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
467 { \
468 .opc1 = op1, \
469 .opc2 = op2, \
470 .opc3 = op3, \
471 .opc4 = 0xff, \
472 .handler = { \
473 .inval1 = invl, \
474 .type = _typ, \
475 .type2 = _typ2, \
476 .handler = &gen_##name, \
477 .oname = onam, \
478 }, \
479 .oname = onam, \
480 }
481 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
482 { \
483 .opc1 = op1, \
484 .opc2 = op2, \
485 .opc3 = op3, \
486 .opc4 = op4, \
487 .handler = { \
488 .inval1 = invl, \
489 .type = _typ, \
490 .type2 = _typ2, \
491 .handler = &gen_##name, \
492 .oname = stringify(name), \
493 }, \
494 .oname = stringify(name), \
495 }
496 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
497 { \
498 .opc1 = op1, \
499 .opc2 = op2, \
500 .opc3 = op3, \
501 .opc4 = op4, \
502 .handler = { \
503 .inval1 = invl, \
504 .type = _typ, \
505 .type2 = _typ2, \
506 .handler = &gen_##name, \
507 .oname = onam, \
508 }, \
509 .oname = onam, \
510 }
511 #else
512 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
513 { \
514 .opc1 = op1, \
515 .opc2 = op2, \
516 .opc3 = op3, \
517 .opc4 = 0xff, \
518 .handler = { \
519 .inval1 = invl, \
520 .type = _typ, \
521 .type2 = _typ2, \
522 .handler = &gen_##name, \
523 }, \
524 .oname = stringify(name), \
525 }
526 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
527 { \
528 .opc1 = op1, \
529 .opc2 = op2, \
530 .opc3 = op3, \
531 .opc4 = 0xff, \
532 .handler = { \
533 .inval1 = invl1, \
534 .inval2 = invl2, \
535 .type = _typ, \
536 .type2 = _typ2, \
537 .handler = &gen_##name, \
538 }, \
539 .oname = stringify(name), \
540 }
541 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
542 { \
543 .opc1 = op1, \
544 .opc2 = op2, \
545 .opc3 = op3, \
546 .opc4 = 0xff, \
547 .handler = { \
548 .inval1 = invl, \
549 .type = _typ, \
550 .type2 = _typ2, \
551 .handler = &gen_##name, \
552 }, \
553 .oname = onam, \
554 }
555 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
556 { \
557 .opc1 = op1, \
558 .opc2 = op2, \
559 .opc3 = op3, \
560 .opc4 = op4, \
561 .handler = { \
562 .inval1 = invl, \
563 .type = _typ, \
564 .type2 = _typ2, \
565 .handler = &gen_##name, \
566 }, \
567 .oname = stringify(name), \
568 }
569 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
570 { \
571 .opc1 = op1, \
572 .opc2 = op2, \
573 .opc3 = op3, \
574 .opc4 = op4, \
575 .handler = { \
576 .inval1 = invl, \
577 .type = _typ, \
578 .type2 = _typ2, \
579 .handler = &gen_##name, \
580 }, \
581 .oname = onam, \
582 }
583 #endif
584
585 /* Invalid instruction */
586 static void gen_invalid(DisasContext *ctx)
587 {
588 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
589 }
590
591 static opc_handler_t invalid_handler = {
592 .inval1 = 0xFFFFFFFF,
593 .inval2 = 0xFFFFFFFF,
594 .type = PPC_NONE,
595 .type2 = PPC_NONE,
596 .handler = gen_invalid,
597 };
598
599 /*** Integer comparison ***/
600
601 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
602 {
603 TCGv t0 = tcg_temp_new();
604 TCGv t1 = tcg_temp_new();
605 TCGv_i32 t = tcg_temp_new_i32();
606
607 tcg_gen_movi_tl(t0, CRF_EQ);
608 tcg_gen_movi_tl(t1, CRF_LT);
609 tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU),
610 t0, arg0, arg1, t1, t0);
611 tcg_gen_movi_tl(t1, CRF_GT);
612 tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU),
613 t0, arg0, arg1, t1, t0);
614
615 tcg_gen_trunc_tl_i32(t, t0);
616 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
617 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t);
618
619 tcg_temp_free(t0);
620 tcg_temp_free(t1);
621 tcg_temp_free_i32(t);
622 }
623
624 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
625 {
626 TCGv t0 = tcg_const_tl(arg1);
627 gen_op_cmp(arg0, t0, s, crf);
628 tcg_temp_free(t0);
629 }
630
631 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
632 {
633 TCGv t0, t1;
634 t0 = tcg_temp_new();
635 t1 = tcg_temp_new();
636 if (s) {
637 tcg_gen_ext32s_tl(t0, arg0);
638 tcg_gen_ext32s_tl(t1, arg1);
639 } else {
640 tcg_gen_ext32u_tl(t0, arg0);
641 tcg_gen_ext32u_tl(t1, arg1);
642 }
643 gen_op_cmp(t0, t1, s, crf);
644 tcg_temp_free(t1);
645 tcg_temp_free(t0);
646 }
647
648 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
649 {
650 TCGv t0 = tcg_const_tl(arg1);
651 gen_op_cmp32(arg0, t0, s, crf);
652 tcg_temp_free(t0);
653 }
654
655 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
656 {
657 if (NARROW_MODE(ctx)) {
658 gen_op_cmpi32(reg, 0, 1, 0);
659 } else {
660 gen_op_cmpi(reg, 0, 1, 0);
661 }
662 }
663
664 /* cmp */
665 static void gen_cmp(DisasContext *ctx)
666 {
667 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
668 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
669 1, crfD(ctx->opcode));
670 } else {
671 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
672 1, crfD(ctx->opcode));
673 }
674 }
675
676 /* cmpi */
677 static void gen_cmpi(DisasContext *ctx)
678 {
679 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
680 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
681 1, crfD(ctx->opcode));
682 } else {
683 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
684 1, crfD(ctx->opcode));
685 }
686 }
687
688 /* cmpl */
689 static void gen_cmpl(DisasContext *ctx)
690 {
691 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
692 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
693 0, crfD(ctx->opcode));
694 } else {
695 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
696 0, crfD(ctx->opcode));
697 }
698 }
699
700 /* cmpli */
701 static void gen_cmpli(DisasContext *ctx)
702 {
703 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
704 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
705 0, crfD(ctx->opcode));
706 } else {
707 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
708 0, crfD(ctx->opcode));
709 }
710 }
711
712 /* cmprb - range comparison: isupper, isaplha, islower*/
713 static void gen_cmprb(DisasContext *ctx)
714 {
715 TCGv_i32 src1 = tcg_temp_new_i32();
716 TCGv_i32 src2 = tcg_temp_new_i32();
717 TCGv_i32 src2lo = tcg_temp_new_i32();
718 TCGv_i32 src2hi = tcg_temp_new_i32();
719 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)];
720
721 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]);
722 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]);
723
724 tcg_gen_andi_i32(src1, src1, 0xFF);
725 tcg_gen_ext8u_i32(src2lo, src2);
726 tcg_gen_shri_i32(src2, src2, 8);
727 tcg_gen_ext8u_i32(src2hi, src2);
728
729 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
730 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
731 tcg_gen_and_i32(crf, src2lo, src2hi);
732
733 if (ctx->opcode & 0x00200000) {
734 tcg_gen_shri_i32(src2, src2, 8);
735 tcg_gen_ext8u_i32(src2lo, src2);
736 tcg_gen_shri_i32(src2, src2, 8);
737 tcg_gen_ext8u_i32(src2hi, src2);
738 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
739 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
740 tcg_gen_and_i32(src2lo, src2lo, src2hi);
741 tcg_gen_or_i32(crf, crf, src2lo);
742 }
743 tcg_gen_shli_i32(crf, crf, CRF_GT_BIT);
744 tcg_temp_free_i32(src1);
745 tcg_temp_free_i32(src2);
746 tcg_temp_free_i32(src2lo);
747 tcg_temp_free_i32(src2hi);
748 }
749
750 #if defined(TARGET_PPC64)
751 /* cmpeqb */
752 static void gen_cmpeqb(DisasContext *ctx)
753 {
754 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
755 cpu_gpr[rB(ctx->opcode)]);
756 }
757 #endif
758
759 /* isel (PowerPC 2.03 specification) */
760 static void gen_isel(DisasContext *ctx)
761 {
762 uint32_t bi = rC(ctx->opcode);
763 uint32_t mask = 0x08 >> (bi & 0x03);
764 TCGv t0 = tcg_temp_new();
765 TCGv zr;
766
767 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
768 tcg_gen_andi_tl(t0, t0, mask);
769
770 zr = tcg_const_tl(0);
771 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
772 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
773 cpu_gpr[rB(ctx->opcode)]);
774 tcg_temp_free(zr);
775 tcg_temp_free(t0);
776 }
777
778 /* cmpb: PowerPC 2.05 specification */
779 static void gen_cmpb(DisasContext *ctx)
780 {
781 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
782 cpu_gpr[rB(ctx->opcode)]);
783 }
784
785 /*** Integer arithmetic ***/
786
787 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
788 TCGv arg1, TCGv arg2, int sub)
789 {
790 TCGv t0 = tcg_temp_new();
791
792 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
793 tcg_gen_xor_tl(t0, arg1, arg2);
794 if (sub) {
795 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
796 } else {
797 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
798 }
799 tcg_temp_free(t0);
800 if (NARROW_MODE(ctx)) {
801 tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1);
802 if (is_isa300(ctx)) {
803 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
804 }
805 } else {
806 if (is_isa300(ctx)) {
807 tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1);
808 }
809 tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1);
810 }
811 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
812 }
813
814 static inline void gen_op_arith_compute_ca32(DisasContext *ctx,
815 TCGv res, TCGv arg0, TCGv arg1,
816 TCGv ca32, int sub)
817 {
818 TCGv t0;
819
820 if (!is_isa300(ctx)) {
821 return;
822 }
823
824 t0 = tcg_temp_new();
825 if (sub) {
826 tcg_gen_eqv_tl(t0, arg0, arg1);
827 } else {
828 tcg_gen_xor_tl(t0, arg0, arg1);
829 }
830 tcg_gen_xor_tl(t0, t0, res);
831 tcg_gen_extract_tl(ca32, t0, 32, 1);
832 tcg_temp_free(t0);
833 }
834
835 /* Common add function */
836 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
837 TCGv arg2, TCGv ca, TCGv ca32,
838 bool add_ca, bool compute_ca,
839 bool compute_ov, bool compute_rc0)
840 {
841 TCGv t0 = ret;
842
843 if (compute_ca || compute_ov) {
844 t0 = tcg_temp_new();
845 }
846
847 if (compute_ca) {
848 if (NARROW_MODE(ctx)) {
849 /*
850 * Caution: a non-obvious corner case of the spec is that
851 * we must produce the *entire* 64-bit addition, but
852 * produce the carry into bit 32.
853 */
854 TCGv t1 = tcg_temp_new();
855 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
856 tcg_gen_add_tl(t0, arg1, arg2);
857 if (add_ca) {
858 tcg_gen_add_tl(t0, t0, ca);
859 }
860 tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */
861 tcg_temp_free(t1);
862 tcg_gen_extract_tl(ca, ca, 32, 1);
863 if (is_isa300(ctx)) {
864 tcg_gen_mov_tl(ca32, ca);
865 }
866 } else {
867 TCGv zero = tcg_const_tl(0);
868 if (add_ca) {
869 tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero);
870 tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero);
871 } else {
872 tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero);
873 }
874 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0);
875 tcg_temp_free(zero);
876 }
877 } else {
878 tcg_gen_add_tl(t0, arg1, arg2);
879 if (add_ca) {
880 tcg_gen_add_tl(t0, t0, ca);
881 }
882 }
883
884 if (compute_ov) {
885 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
886 }
887 if (unlikely(compute_rc0)) {
888 gen_set_Rc0(ctx, t0);
889 }
890
891 if (t0 != ret) {
892 tcg_gen_mov_tl(ret, t0);
893 tcg_temp_free(t0);
894 }
895 }
896 /* Add functions with two operands */
897 #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \
898 static void glue(gen_, name)(DisasContext *ctx) \
899 { \
900 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
901 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
902 ca, glue(ca, 32), \
903 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
904 }
905 /* Add functions with one operand and one immediate */
906 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \
907 add_ca, compute_ca, compute_ov) \
908 static void glue(gen_, name)(DisasContext *ctx) \
909 { \
910 TCGv t0 = tcg_const_tl(const_val); \
911 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
912 cpu_gpr[rA(ctx->opcode)], t0, \
913 ca, glue(ca, 32), \
914 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
915 tcg_temp_free(t0); \
916 }
917
918 /* add add. addo addo. */
919 GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0)
920 GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1)
921 /* addc addc. addco addco. */
922 GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0)
923 GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1)
924 /* adde adde. addeo addeo. */
925 GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0)
926 GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1)
927 /* addme addme. addmeo addmeo. */
928 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0)
929 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1)
930 /* addex */
931 GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0);
932 /* addze addze. addzeo addzeo.*/
933 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0)
934 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1)
935 /* addi */
936 static void gen_addi(DisasContext *ctx)
937 {
938 target_long simm = SIMM(ctx->opcode);
939
940 if (rA(ctx->opcode) == 0) {
941 /* li case */
942 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
943 } else {
944 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
945 cpu_gpr[rA(ctx->opcode)], simm);
946 }
947 }
948 /* addic addic.*/
949 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
950 {
951 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
952 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
953 c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0);
954 tcg_temp_free(c);
955 }
956
957 static void gen_addic(DisasContext *ctx)
958 {
959 gen_op_addic(ctx, 0);
960 }
961
962 static void gen_addic_(DisasContext *ctx)
963 {
964 gen_op_addic(ctx, 1);
965 }
966
967 /* addis */
968 static void gen_addis(DisasContext *ctx)
969 {
970 target_long simm = SIMM(ctx->opcode);
971
972 if (rA(ctx->opcode) == 0) {
973 /* lis case */
974 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
975 } else {
976 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
977 cpu_gpr[rA(ctx->opcode)], simm << 16);
978 }
979 }
980
981 /* addpcis */
982 static void gen_addpcis(DisasContext *ctx)
983 {
984 target_long d = DX(ctx->opcode);
985
986 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16));
987 }
988
989 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
990 TCGv arg2, int sign, int compute_ov)
991 {
992 TCGv_i32 t0 = tcg_temp_new_i32();
993 TCGv_i32 t1 = tcg_temp_new_i32();
994 TCGv_i32 t2 = tcg_temp_new_i32();
995 TCGv_i32 t3 = tcg_temp_new_i32();
996
997 tcg_gen_trunc_tl_i32(t0, arg1);
998 tcg_gen_trunc_tl_i32(t1, arg2);
999 if (sign) {
1000 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1001 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1002 tcg_gen_and_i32(t2, t2, t3);
1003 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1004 tcg_gen_or_i32(t2, t2, t3);
1005 tcg_gen_movi_i32(t3, 0);
1006 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1007 tcg_gen_div_i32(t3, t0, t1);
1008 tcg_gen_extu_i32_tl(ret, t3);
1009 } else {
1010 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0);
1011 tcg_gen_movi_i32(t3, 0);
1012 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1013 tcg_gen_divu_i32(t3, t0, t1);
1014 tcg_gen_extu_i32_tl(ret, t3);
1015 }
1016 if (compute_ov) {
1017 tcg_gen_extu_i32_tl(cpu_ov, t2);
1018 if (is_isa300(ctx)) {
1019 tcg_gen_extu_i32_tl(cpu_ov32, t2);
1020 }
1021 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1022 }
1023 tcg_temp_free_i32(t0);
1024 tcg_temp_free_i32(t1);
1025 tcg_temp_free_i32(t2);
1026 tcg_temp_free_i32(t3);
1027
1028 if (unlikely(Rc(ctx->opcode) != 0)) {
1029 gen_set_Rc0(ctx, ret);
1030 }
1031 }
1032 /* Div functions */
1033 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1034 static void glue(gen_, name)(DisasContext *ctx) \
1035 { \
1036 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1037 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1038 sign, compute_ov); \
1039 }
1040 /* divwu divwu. divwuo divwuo. */
1041 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1042 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1043 /* divw divw. divwo divwo. */
1044 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1045 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1046
1047 /* div[wd]eu[o][.] */
1048 #define GEN_DIVE(name, hlpr, compute_ov) \
1049 static void gen_##name(DisasContext *ctx) \
1050 { \
1051 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1052 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1053 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1054 tcg_temp_free_i32(t0); \
1055 if (unlikely(Rc(ctx->opcode) != 0)) { \
1056 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1057 } \
1058 }
1059
1060 GEN_DIVE(divweu, divweu, 0);
1061 GEN_DIVE(divweuo, divweu, 1);
1062 GEN_DIVE(divwe, divwe, 0);
1063 GEN_DIVE(divweo, divwe, 1);
1064
1065 #if defined(TARGET_PPC64)
1066 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1067 TCGv arg2, int sign, int compute_ov)
1068 {
1069 TCGv_i64 t0 = tcg_temp_new_i64();
1070 TCGv_i64 t1 = tcg_temp_new_i64();
1071 TCGv_i64 t2 = tcg_temp_new_i64();
1072 TCGv_i64 t3 = tcg_temp_new_i64();
1073
1074 tcg_gen_mov_i64(t0, arg1);
1075 tcg_gen_mov_i64(t1, arg2);
1076 if (sign) {
1077 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1078 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1079 tcg_gen_and_i64(t2, t2, t3);
1080 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1081 tcg_gen_or_i64(t2, t2, t3);
1082 tcg_gen_movi_i64(t3, 0);
1083 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1084 tcg_gen_div_i64(ret, t0, t1);
1085 } else {
1086 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0);
1087 tcg_gen_movi_i64(t3, 0);
1088 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1089 tcg_gen_divu_i64(ret, t0, t1);
1090 }
1091 if (compute_ov) {
1092 tcg_gen_mov_tl(cpu_ov, t2);
1093 if (is_isa300(ctx)) {
1094 tcg_gen_mov_tl(cpu_ov32, t2);
1095 }
1096 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1097 }
1098 tcg_temp_free_i64(t0);
1099 tcg_temp_free_i64(t1);
1100 tcg_temp_free_i64(t2);
1101 tcg_temp_free_i64(t3);
1102
1103 if (unlikely(Rc(ctx->opcode) != 0)) {
1104 gen_set_Rc0(ctx, ret);
1105 }
1106 }
1107
1108 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1109 static void glue(gen_, name)(DisasContext *ctx) \
1110 { \
1111 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1112 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1113 sign, compute_ov); \
1114 }
1115 /* divdu divdu. divduo divduo. */
1116 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1117 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1118 /* divd divd. divdo divdo. */
1119 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1120 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1121
1122 GEN_DIVE(divdeu, divdeu, 0);
1123 GEN_DIVE(divdeuo, divdeu, 1);
1124 GEN_DIVE(divde, divde, 0);
1125 GEN_DIVE(divdeo, divde, 1);
1126 #endif
1127
1128 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
1129 TCGv arg2, int sign)
1130 {
1131 TCGv_i32 t0 = tcg_temp_new_i32();
1132 TCGv_i32 t1 = tcg_temp_new_i32();
1133
1134 tcg_gen_trunc_tl_i32(t0, arg1);
1135 tcg_gen_trunc_tl_i32(t1, arg2);
1136 if (sign) {
1137 TCGv_i32 t2 = tcg_temp_new_i32();
1138 TCGv_i32 t3 = tcg_temp_new_i32();
1139 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1140 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1141 tcg_gen_and_i32(t2, t2, t3);
1142 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1143 tcg_gen_or_i32(t2, t2, t3);
1144 tcg_gen_movi_i32(t3, 0);
1145 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1146 tcg_gen_rem_i32(t3, t0, t1);
1147 tcg_gen_ext_i32_tl(ret, t3);
1148 tcg_temp_free_i32(t2);
1149 tcg_temp_free_i32(t3);
1150 } else {
1151 TCGv_i32 t2 = tcg_const_i32(1);
1152 TCGv_i32 t3 = tcg_const_i32(0);
1153 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1);
1154 tcg_gen_remu_i32(t3, t0, t1);
1155 tcg_gen_extu_i32_tl(ret, t3);
1156 tcg_temp_free_i32(t2);
1157 tcg_temp_free_i32(t3);
1158 }
1159 tcg_temp_free_i32(t0);
1160 tcg_temp_free_i32(t1);
1161 }
1162
1163 #define GEN_INT_ARITH_MODW(name, opc3, sign) \
1164 static void glue(gen_, name)(DisasContext *ctx) \
1165 { \
1166 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \
1167 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1168 sign); \
1169 }
1170
1171 GEN_INT_ARITH_MODW(moduw, 0x08, 0);
1172 GEN_INT_ARITH_MODW(modsw, 0x18, 1);
1173
1174 #if defined(TARGET_PPC64)
1175 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
1176 TCGv arg2, int sign)
1177 {
1178 TCGv_i64 t0 = tcg_temp_new_i64();
1179 TCGv_i64 t1 = tcg_temp_new_i64();
1180
1181 tcg_gen_mov_i64(t0, arg1);
1182 tcg_gen_mov_i64(t1, arg2);
1183 if (sign) {
1184 TCGv_i64 t2 = tcg_temp_new_i64();
1185 TCGv_i64 t3 = tcg_temp_new_i64();
1186 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1187 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1188 tcg_gen_and_i64(t2, t2, t3);
1189 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1190 tcg_gen_or_i64(t2, t2, t3);
1191 tcg_gen_movi_i64(t3, 0);
1192 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1193 tcg_gen_rem_i64(ret, t0, t1);
1194 tcg_temp_free_i64(t2);
1195 tcg_temp_free_i64(t3);
1196 } else {
1197 TCGv_i64 t2 = tcg_const_i64(1);
1198 TCGv_i64 t3 = tcg_const_i64(0);
1199 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1);
1200 tcg_gen_remu_i64(ret, t0, t1);
1201 tcg_temp_free_i64(t2);
1202 tcg_temp_free_i64(t3);
1203 }
1204 tcg_temp_free_i64(t0);
1205 tcg_temp_free_i64(t1);
1206 }
1207
1208 #define GEN_INT_ARITH_MODD(name, opc3, sign) \
1209 static void glue(gen_, name)(DisasContext *ctx) \
1210 { \
1211 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \
1212 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1213 sign); \
1214 }
1215
1216 GEN_INT_ARITH_MODD(modud, 0x08, 0);
1217 GEN_INT_ARITH_MODD(modsd, 0x18, 1);
1218 #endif
1219
1220 /* mulhw mulhw. */
1221 static void gen_mulhw(DisasContext *ctx)
1222 {
1223 TCGv_i32 t0 = tcg_temp_new_i32();
1224 TCGv_i32 t1 = tcg_temp_new_i32();
1225
1226 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1227 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1228 tcg_gen_muls2_i32(t0, t1, t0, t1);
1229 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1230 tcg_temp_free_i32(t0);
1231 tcg_temp_free_i32(t1);
1232 if (unlikely(Rc(ctx->opcode) != 0)) {
1233 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1234 }
1235 }
1236
1237 /* mulhwu mulhwu. */
1238 static void gen_mulhwu(DisasContext *ctx)
1239 {
1240 TCGv_i32 t0 = tcg_temp_new_i32();
1241 TCGv_i32 t1 = tcg_temp_new_i32();
1242
1243 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1244 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1245 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1246 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1247 tcg_temp_free_i32(t0);
1248 tcg_temp_free_i32(t1);
1249 if (unlikely(Rc(ctx->opcode) != 0)) {
1250 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1251 }
1252 }
1253
1254 /* mullw mullw. */
1255 static void gen_mullw(DisasContext *ctx)
1256 {
1257 #if defined(TARGET_PPC64)
1258 TCGv_i64 t0, t1;
1259 t0 = tcg_temp_new_i64();
1260 t1 = tcg_temp_new_i64();
1261 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1262 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1263 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1264 tcg_temp_free(t0);
1265 tcg_temp_free(t1);
1266 #else
1267 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1268 cpu_gpr[rB(ctx->opcode)]);
1269 #endif
1270 if (unlikely(Rc(ctx->opcode) != 0)) {
1271 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1272 }
1273 }
1274
1275 /* mullwo mullwo. */
1276 static void gen_mullwo(DisasContext *ctx)
1277 {
1278 TCGv_i32 t0 = tcg_temp_new_i32();
1279 TCGv_i32 t1 = tcg_temp_new_i32();
1280
1281 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1282 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1283 tcg_gen_muls2_i32(t0, t1, t0, t1);
1284 #if defined(TARGET_PPC64)
1285 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1286 #else
1287 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1288 #endif
1289
1290 tcg_gen_sari_i32(t0, t0, 31);
1291 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1292 tcg_gen_extu_i32_tl(cpu_ov, t0);
1293 if (is_isa300(ctx)) {
1294 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
1295 }
1296 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1297
1298 tcg_temp_free_i32(t0);
1299 tcg_temp_free_i32(t1);
1300 if (unlikely(Rc(ctx->opcode) != 0)) {
1301 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1302 }
1303 }
1304
1305 /* mulli */
1306 static void gen_mulli(DisasContext *ctx)
1307 {
1308 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1309 SIMM(ctx->opcode));
1310 }
1311
1312 #if defined(TARGET_PPC64)
1313 /* mulhd mulhd. */
1314 static void gen_mulhd(DisasContext *ctx)
1315 {
1316 TCGv lo = tcg_temp_new();
1317 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1318 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1319 tcg_temp_free(lo);
1320 if (unlikely(Rc(ctx->opcode) != 0)) {
1321 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1322 }
1323 }
1324
1325 /* mulhdu mulhdu. */
1326 static void gen_mulhdu(DisasContext *ctx)
1327 {
1328 TCGv lo = tcg_temp_new();
1329 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1330 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1331 tcg_temp_free(lo);
1332 if (unlikely(Rc(ctx->opcode) != 0)) {
1333 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1334 }
1335 }
1336
1337 /* mulld mulld. */
1338 static void gen_mulld(DisasContext *ctx)
1339 {
1340 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1341 cpu_gpr[rB(ctx->opcode)]);
1342 if (unlikely(Rc(ctx->opcode) != 0)) {
1343 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1344 }
1345 }
1346
1347 /* mulldo mulldo. */
1348 static void gen_mulldo(DisasContext *ctx)
1349 {
1350 TCGv_i64 t0 = tcg_temp_new_i64();
1351 TCGv_i64 t1 = tcg_temp_new_i64();
1352
1353 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1354 cpu_gpr[rB(ctx->opcode)]);
1355 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1356
1357 tcg_gen_sari_i64(t0, t0, 63);
1358 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1359 if (is_isa300(ctx)) {
1360 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
1361 }
1362 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1363
1364 tcg_temp_free_i64(t0);
1365 tcg_temp_free_i64(t1);
1366
1367 if (unlikely(Rc(ctx->opcode) != 0)) {
1368 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1369 }
1370 }
1371 #endif
1372
1373 /* Common subf function */
1374 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1375 TCGv arg2, bool add_ca, bool compute_ca,
1376 bool compute_ov, bool compute_rc0)
1377 {
1378 TCGv t0 = ret;
1379
1380 if (compute_ca || compute_ov) {
1381 t0 = tcg_temp_new();
1382 }
1383
1384 if (compute_ca) {
1385 /* dest = ~arg1 + arg2 [+ ca]. */
1386 if (NARROW_MODE(ctx)) {
1387 /*
1388 * Caution: a non-obvious corner case of the spec is that
1389 * we must produce the *entire* 64-bit addition, but
1390 * produce the carry into bit 32.
1391 */
1392 TCGv inv1 = tcg_temp_new();
1393 TCGv t1 = tcg_temp_new();
1394 tcg_gen_not_tl(inv1, arg1);
1395 if (add_ca) {
1396 tcg_gen_add_tl(t0, arg2, cpu_ca);
1397 } else {
1398 tcg_gen_addi_tl(t0, arg2, 1);
1399 }
1400 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1401 tcg_gen_add_tl(t0, t0, inv1);
1402 tcg_temp_free(inv1);
1403 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1404 tcg_temp_free(t1);
1405 tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1);
1406 if (is_isa300(ctx)) {
1407 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
1408 }
1409 } else if (add_ca) {
1410 TCGv zero, inv1 = tcg_temp_new();
1411 tcg_gen_not_tl(inv1, arg1);
1412 zero = tcg_const_tl(0);
1413 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1414 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1415 gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0);
1416 tcg_temp_free(zero);
1417 tcg_temp_free(inv1);
1418 } else {
1419 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1420 tcg_gen_sub_tl(t0, arg2, arg1);
1421 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1);
1422 }
1423 } else if (add_ca) {
1424 /*
1425 * Since we're ignoring carry-out, we can simplify the
1426 * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1.
1427 */
1428 tcg_gen_sub_tl(t0, arg2, arg1);
1429 tcg_gen_add_tl(t0, t0, cpu_ca);
1430 tcg_gen_subi_tl(t0, t0, 1);
1431 } else {
1432 tcg_gen_sub_tl(t0, arg2, arg1);
1433 }
1434
1435 if (compute_ov) {
1436 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1437 }
1438 if (unlikely(compute_rc0)) {
1439 gen_set_Rc0(ctx, t0);
1440 }
1441
1442 if (t0 != ret) {
1443 tcg_gen_mov_tl(ret, t0);
1444 tcg_temp_free(t0);
1445 }
1446 }
1447 /* Sub functions with Two operands functions */
1448 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1449 static void glue(gen_, name)(DisasContext *ctx) \
1450 { \
1451 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1452 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1453 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1454 }
1455 /* Sub functions with one operand and one immediate */
1456 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1457 add_ca, compute_ca, compute_ov) \
1458 static void glue(gen_, name)(DisasContext *ctx) \
1459 { \
1460 TCGv t0 = tcg_const_tl(const_val); \
1461 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1462 cpu_gpr[rA(ctx->opcode)], t0, \
1463 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1464 tcg_temp_free(t0); \
1465 }
1466 /* subf subf. subfo subfo. */
1467 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1468 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1469 /* subfc subfc. subfco subfco. */
1470 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1471 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1472 /* subfe subfe. subfeo subfo. */
1473 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1474 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1475 /* subfme subfme. subfmeo subfmeo. */
1476 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1477 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1478 /* subfze subfze. subfzeo subfzeo.*/
1479 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1480 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1481
1482 /* subfic */
1483 static void gen_subfic(DisasContext *ctx)
1484 {
1485 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1486 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1487 c, 0, 1, 0, 0);
1488 tcg_temp_free(c);
1489 }
1490
1491 /* neg neg. nego nego. */
1492 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1493 {
1494 TCGv zero = tcg_const_tl(0);
1495 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1496 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1497 tcg_temp_free(zero);
1498 }
1499
1500 static void gen_neg(DisasContext *ctx)
1501 {
1502 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1503 if (unlikely(Rc(ctx->opcode))) {
1504 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1505 }
1506 }
1507
1508 static void gen_nego(DisasContext *ctx)
1509 {
1510 gen_op_arith_neg(ctx, 1);
1511 }
1512
1513 /*** Integer logical ***/
1514 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1515 static void glue(gen_, name)(DisasContext *ctx) \
1516 { \
1517 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1518 cpu_gpr[rB(ctx->opcode)]); \
1519 if (unlikely(Rc(ctx->opcode) != 0)) \
1520 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1521 }
1522
1523 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1524 static void glue(gen_, name)(DisasContext *ctx) \
1525 { \
1526 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1527 if (unlikely(Rc(ctx->opcode) != 0)) \
1528 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1529 }
1530
1531 /* and & and. */
1532 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1533 /* andc & andc. */
1534 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1535
1536 /* andi. */
1537 static void gen_andi_(DisasContext *ctx)
1538 {
1539 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
1540 UIMM(ctx->opcode));
1541 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1542 }
1543
1544 /* andis. */
1545 static void gen_andis_(DisasContext *ctx)
1546 {
1547 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
1548 UIMM(ctx->opcode) << 16);
1549 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1550 }
1551
1552 /* cntlzw */
1553 static void gen_cntlzw(DisasContext *ctx)
1554 {
1555 TCGv_i32 t = tcg_temp_new_i32();
1556
1557 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]);
1558 tcg_gen_clzi_i32(t, t, 32);
1559 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t);
1560 tcg_temp_free_i32(t);
1561
1562 if (unlikely(Rc(ctx->opcode) != 0)) {
1563 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1564 }
1565 }
1566
1567 /* cnttzw */
1568 static void gen_cnttzw(DisasContext *ctx)
1569 {
1570 TCGv_i32 t = tcg_temp_new_i32();
1571
1572 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]);
1573 tcg_gen_ctzi_i32(t, t, 32);
1574 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t);
1575 tcg_temp_free_i32(t);
1576
1577 if (unlikely(Rc(ctx->opcode) != 0)) {
1578 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1579 }
1580 }
1581
1582 /* eqv & eqv. */
1583 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1584 /* extsb & extsb. */
1585 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1586 /* extsh & extsh. */
1587 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1588 /* nand & nand. */
1589 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1590 /* nor & nor. */
1591 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1592
1593 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1594 static void gen_pause(DisasContext *ctx)
1595 {
1596 TCGv_i32 t0 = tcg_const_i32(0);
1597 tcg_gen_st_i32(t0, cpu_env,
1598 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
1599 tcg_temp_free_i32(t0);
1600
1601 /* Stop translation, this gives other CPUs a chance to run */
1602 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
1603 }
1604 #endif /* defined(TARGET_PPC64) */
1605
1606 /* or & or. */
1607 static void gen_or(DisasContext *ctx)
1608 {
1609 int rs, ra, rb;
1610
1611 rs = rS(ctx->opcode);
1612 ra = rA(ctx->opcode);
1613 rb = rB(ctx->opcode);
1614 /* Optimisation for mr. ri case */
1615 if (rs != ra || rs != rb) {
1616 if (rs != rb) {
1617 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1618 } else {
1619 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1620 }
1621 if (unlikely(Rc(ctx->opcode) != 0)) {
1622 gen_set_Rc0(ctx, cpu_gpr[ra]);
1623 }
1624 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1625 gen_set_Rc0(ctx, cpu_gpr[rs]);
1626 #if defined(TARGET_PPC64)
1627 } else if (rs != 0) { /* 0 is nop */
1628 int prio = 0;
1629
1630 switch (rs) {
1631 case 1:
1632 /* Set process priority to low */
1633 prio = 2;
1634 break;
1635 case 6:
1636 /* Set process priority to medium-low */
1637 prio = 3;
1638 break;
1639 case 2:
1640 /* Set process priority to normal */
1641 prio = 4;
1642 break;
1643 #if !defined(CONFIG_USER_ONLY)
1644 case 31:
1645 if (!ctx->pr) {
1646 /* Set process priority to very low */
1647 prio = 1;
1648 }
1649 break;
1650 case 5:
1651 if (!ctx->pr) {
1652 /* Set process priority to medium-hight */
1653 prio = 5;
1654 }
1655 break;
1656 case 3:
1657 if (!ctx->pr) {
1658 /* Set process priority to high */
1659 prio = 6;
1660 }
1661 break;
1662 case 7:
1663 if (ctx->hv && !ctx->pr) {
1664 /* Set process priority to very high */
1665 prio = 7;
1666 }
1667 break;
1668 #endif
1669 default:
1670 break;
1671 }
1672 if (prio) {
1673 TCGv t0 = tcg_temp_new();
1674 gen_load_spr(t0, SPR_PPR);
1675 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1676 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1677 gen_store_spr(SPR_PPR, t0);
1678 tcg_temp_free(t0);
1679 }
1680 #if !defined(CONFIG_USER_ONLY)
1681 /*
1682 * Pause out of TCG otherwise spin loops with smt_low eat too
1683 * much CPU and the kernel hangs. This applies to all
1684 * encodings other than no-op, e.g., miso(rs=26), yield(27),
1685 * mdoio(29), mdoom(30), and all currently undefined.
1686 */
1687 gen_pause(ctx);
1688 #endif
1689 #endif
1690 }
1691 }
1692 /* orc & orc. */
1693 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1694
1695 /* xor & xor. */
1696 static void gen_xor(DisasContext *ctx)
1697 {
1698 /* Optimisation for "set to zero" case */
1699 if (rS(ctx->opcode) != rB(ctx->opcode)) {
1700 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
1701 cpu_gpr[rB(ctx->opcode)]);
1702 } else {
1703 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1704 }
1705 if (unlikely(Rc(ctx->opcode) != 0)) {
1706 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1707 }
1708 }
1709
1710 /* ori */
1711 static void gen_ori(DisasContext *ctx)
1712 {
1713 target_ulong uimm = UIMM(ctx->opcode);
1714
1715 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1716 return;
1717 }
1718 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1719 }
1720
1721 /* oris */
1722 static void gen_oris(DisasContext *ctx)
1723 {
1724 target_ulong uimm = UIMM(ctx->opcode);
1725
1726 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1727 /* NOP */
1728 return;
1729 }
1730 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
1731 uimm << 16);
1732 }
1733
1734 /* xori */
1735 static void gen_xori(DisasContext *ctx)
1736 {
1737 target_ulong uimm = UIMM(ctx->opcode);
1738
1739 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1740 /* NOP */
1741 return;
1742 }
1743 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1744 }
1745
1746 /* xoris */
1747 static void gen_xoris(DisasContext *ctx)
1748 {
1749 target_ulong uimm = UIMM(ctx->opcode);
1750
1751 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1752 /* NOP */
1753 return;
1754 }
1755 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
1756 uimm << 16);
1757 }
1758
1759 /* popcntb : PowerPC 2.03 specification */
1760 static void gen_popcntb(DisasContext *ctx)
1761 {
1762 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1763 }
1764
1765 static void gen_popcntw(DisasContext *ctx)
1766 {
1767 #if defined(TARGET_PPC64)
1768 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1769 #else
1770 tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1771 #endif
1772 }
1773
1774 #if defined(TARGET_PPC64)
1775 /* popcntd: PowerPC 2.06 specification */
1776 static void gen_popcntd(DisasContext *ctx)
1777 {
1778 tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1779 }
1780 #endif
1781
1782 /* prtyw: PowerPC 2.05 specification */
1783 static void gen_prtyw(DisasContext *ctx)
1784 {
1785 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1786 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1787 TCGv t0 = tcg_temp_new();
1788 tcg_gen_shri_tl(t0, rs, 16);
1789 tcg_gen_xor_tl(ra, rs, t0);
1790 tcg_gen_shri_tl(t0, ra, 8);
1791 tcg_gen_xor_tl(ra, ra, t0);
1792 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1793 tcg_temp_free(t0);
1794 }
1795
1796 #if defined(TARGET_PPC64)
1797 /* prtyd: PowerPC 2.05 specification */
1798 static void gen_prtyd(DisasContext *ctx)
1799 {
1800 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1801 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1802 TCGv t0 = tcg_temp_new();
1803 tcg_gen_shri_tl(t0, rs, 32);
1804 tcg_gen_xor_tl(ra, rs, t0);
1805 tcg_gen_shri_tl(t0, ra, 16);
1806 tcg_gen_xor_tl(ra, ra, t0);
1807 tcg_gen_shri_tl(t0, ra, 8);
1808 tcg_gen_xor_tl(ra, ra, t0);
1809 tcg_gen_andi_tl(ra, ra, 1);
1810 tcg_temp_free(t0);
1811 }
1812 #endif
1813
1814 #if defined(TARGET_PPC64)
1815 /* bpermd */
1816 static void gen_bpermd(DisasContext *ctx)
1817 {
1818 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1819 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1820 }
1821 #endif
1822
1823 #if defined(TARGET_PPC64)
1824 /* extsw & extsw. */
1825 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1826
1827 /* cntlzd */
1828 static void gen_cntlzd(DisasContext *ctx)
1829 {
1830 tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64);
1831 if (unlikely(Rc(ctx->opcode) != 0)) {
1832 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1833 }
1834 }
1835
1836 /* cnttzd */
1837 static void gen_cnttzd(DisasContext *ctx)
1838 {
1839 tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64);
1840 if (unlikely(Rc(ctx->opcode) != 0)) {
1841 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1842 }
1843 }
1844
1845 /* darn */
1846 static void gen_darn(DisasContext *ctx)
1847 {
1848 int l = L(ctx->opcode);
1849
1850 if (l > 2) {
1851 tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1);
1852 } else {
1853 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
1854 gen_io_start();
1855 }
1856 if (l == 0) {
1857 gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]);
1858 } else {
1859 /* Return 64-bit random for both CRN and RRN */
1860 gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]);
1861 }
1862 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
1863 gen_io_end();
1864 gen_stop_exception(ctx);
1865 }
1866 }
1867 }
1868 #endif
1869
1870 /*** Integer rotate ***/
1871
1872 /* rlwimi & rlwimi. */
1873 static void gen_rlwimi(DisasContext *ctx)
1874 {
1875 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1876 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1877 uint32_t sh = SH(ctx->opcode);
1878 uint32_t mb = MB(ctx->opcode);
1879 uint32_t me = ME(ctx->opcode);
1880
1881 if (sh == (31 - me) && mb <= me) {
1882 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
1883 } else {
1884 target_ulong mask;
1885 TCGv t1;
1886
1887 #if defined(TARGET_PPC64)
1888 mb += 32;
1889 me += 32;
1890 #endif
1891 mask = MASK(mb, me);
1892
1893 t1 = tcg_temp_new();
1894 if (mask <= 0xffffffffu) {
1895 TCGv_i32 t0 = tcg_temp_new_i32();
1896 tcg_gen_trunc_tl_i32(t0, t_rs);
1897 tcg_gen_rotli_i32(t0, t0, sh);
1898 tcg_gen_extu_i32_tl(t1, t0);
1899 tcg_temp_free_i32(t0);
1900 } else {
1901 #if defined(TARGET_PPC64)
1902 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32);
1903 tcg_gen_rotli_i64(t1, t1, sh);
1904 #else
1905 g_assert_not_reached();
1906 #endif
1907 }
1908
1909 tcg_gen_andi_tl(t1, t1, mask);
1910 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1911 tcg_gen_or_tl(t_ra, t_ra, t1);
1912 tcg_temp_free(t1);
1913 }
1914 if (unlikely(Rc(ctx->opcode) != 0)) {
1915 gen_set_Rc0(ctx, t_ra);
1916 }
1917 }
1918
1919 /* rlwinm & rlwinm. */
1920 static void gen_rlwinm(DisasContext *ctx)
1921 {
1922 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1923 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1924 int sh = SH(ctx->opcode);
1925 int mb = MB(ctx->opcode);
1926 int me = ME(ctx->opcode);
1927 int len = me - mb + 1;
1928 int rsh = (32 - sh) & 31;
1929
1930 if (sh != 0 && len > 0 && me == (31 - sh)) {
1931 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
1932 } else if (me == 31 && rsh + len <= 32) {
1933 tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
1934 } else {
1935 target_ulong mask;
1936 #if defined(TARGET_PPC64)
1937 mb += 32;
1938 me += 32;
1939 #endif
1940 mask = MASK(mb, me);
1941 if (sh == 0) {
1942 tcg_gen_andi_tl(t_ra, t_rs, mask);
1943 } else if (mask <= 0xffffffffu) {
1944 TCGv_i32 t0 = tcg_temp_new_i32();
1945 tcg_gen_trunc_tl_i32(t0, t_rs);
1946 tcg_gen_rotli_i32(t0, t0, sh);
1947 tcg_gen_andi_i32(t0, t0, mask);
1948 tcg_gen_extu_i32_tl(t_ra, t0);
1949 tcg_temp_free_i32(t0);
1950 } else {
1951 #if defined(TARGET_PPC64)
1952 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1953 tcg_gen_rotli_i64(t_ra, t_ra, sh);
1954 tcg_gen_andi_i64(t_ra, t_ra, mask);
1955 #else
1956 g_assert_not_reached();
1957 #endif
1958 }
1959 }
1960 if (unlikely(Rc(ctx->opcode) != 0)) {
1961 gen_set_Rc0(ctx, t_ra);
1962 }
1963 }
1964
1965 /* rlwnm & rlwnm. */
1966 static void gen_rlwnm(DisasContext *ctx)
1967 {
1968 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1969 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1970 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
1971 uint32_t mb = MB(ctx->opcode);
1972 uint32_t me = ME(ctx->opcode);
1973 target_ulong mask;
1974
1975 #if defined(TARGET_PPC64)
1976 mb += 32;
1977 me += 32;
1978 #endif
1979 mask = MASK(mb, me);
1980
1981 if (mask <= 0xffffffffu) {
1982 TCGv_i32 t0 = tcg_temp_new_i32();
1983 TCGv_i32 t1 = tcg_temp_new_i32();
1984 tcg_gen_trunc_tl_i32(t0, t_rb);
1985 tcg_gen_trunc_tl_i32(t1, t_rs);
1986 tcg_gen_andi_i32(t0, t0, 0x1f);
1987 tcg_gen_rotl_i32(t1, t1, t0);
1988 tcg_gen_extu_i32_tl(t_ra, t1);
1989 tcg_temp_free_i32(t0);
1990 tcg_temp_free_i32(t1);
1991 } else {
1992 #if defined(TARGET_PPC64)
1993 TCGv_i64 t0 = tcg_temp_new_i64();
1994 tcg_gen_andi_i64(t0, t_rb, 0x1f);
1995 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1996 tcg_gen_rotl_i64(t_ra, t_ra, t0);
1997 tcg_temp_free_i64(t0);
1998 #else
1999 g_assert_not_reached();
2000 #endif
2001 }
2002
2003 tcg_gen_andi_tl(t_ra, t_ra, mask);
2004
2005 if (unlikely(Rc(ctx->opcode) != 0)) {
2006 gen_set_Rc0(ctx, t_ra);
2007 }
2008 }
2009
2010 #if defined(TARGET_PPC64)
2011 #define GEN_PPC64_R2(name, opc1, opc2) \
2012 static void glue(gen_, name##0)(DisasContext *ctx) \
2013 { \
2014 gen_##name(ctx, 0); \
2015 } \
2016 \
2017 static void glue(gen_, name##1)(DisasContext *ctx) \
2018 { \
2019 gen_##name(ctx, 1); \
2020 }
2021 #define GEN_PPC64_R4(name, opc1, opc2) \
2022 static void glue(gen_, name##0)(DisasContext *ctx) \
2023 { \
2024 gen_##name(ctx, 0, 0); \
2025 } \
2026 \
2027 static void glue(gen_, name##1)(DisasContext *ctx) \
2028 { \
2029 gen_##name(ctx, 0, 1); \
2030 } \
2031 \
2032 static void glue(gen_, name##2)(DisasContext *ctx) \
2033 { \
2034 gen_##name(ctx, 1, 0); \
2035 } \
2036 \
2037 static void glue(gen_, name##3)(DisasContext *ctx) \
2038 { \
2039 gen_##name(ctx, 1, 1); \
2040 }
2041
2042 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
2043 {
2044 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2045 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2046 int len = me - mb + 1;
2047 int rsh = (64 - sh) & 63;
2048
2049 if (sh != 0 && len > 0 && me == (63 - sh)) {
2050 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
2051 } else if (me == 63 && rsh + len <= 64) {
2052 tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
2053 } else {
2054 tcg_gen_rotli_tl(t_ra, t_rs, sh);
2055 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2056 }
2057 if (unlikely(Rc(ctx->opcode) != 0)) {
2058 gen_set_Rc0(ctx, t_ra);
2059 }
2060 }
2061
2062 /* rldicl - rldicl. */
2063 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
2064 {
2065 uint32_t sh, mb;
2066
2067 sh = SH(ctx->opcode) | (shn << 5);
2068 mb = MB(ctx->opcode) | (mbn << 5);
2069 gen_rldinm(ctx, mb, 63, sh);
2070 }
2071 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
2072
2073 /* rldicr - rldicr. */
2074 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
2075 {
2076 uint32_t sh, me;
2077
2078 sh = SH(ctx->opcode) | (shn << 5);
2079 me = MB(ctx->opcode) | (men << 5);
2080 gen_rldinm(ctx, 0, me, sh);
2081 }
2082 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
2083
2084 /* rldic - rldic. */
2085 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
2086 {
2087 uint32_t sh, mb;
2088
2089 sh = SH(ctx->opcode) | (shn << 5);
2090 mb = MB(ctx->opcode) | (mbn << 5);
2091 gen_rldinm(ctx, mb, 63 - sh, sh);
2092 }
2093 GEN_PPC64_R4(rldic, 0x1E, 0x04);
2094
2095 static void gen_rldnm(DisasContext *ctx, int mb, int me)
2096 {
2097 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2098 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2099 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
2100 TCGv t0;
2101
2102 t0 = tcg_temp_new();
2103 tcg_gen_andi_tl(t0, t_rb, 0x3f);
2104 tcg_gen_rotl_tl(t_ra, t_rs, t0);
2105 tcg_temp_free(t0);
2106
2107 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2108 if (unlikely(Rc(ctx->opcode) != 0)) {
2109 gen_set_Rc0(ctx, t_ra);
2110 }
2111 }
2112
2113 /* rldcl - rldcl. */
2114 static inline void gen_rldcl(DisasContext *ctx, int mbn)
2115 {
2116 uint32_t mb;
2117
2118 mb = MB(ctx->opcode) | (mbn << 5);
2119 gen_rldnm(ctx, mb, 63);
2120 }
2121 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
2122
2123 /* rldcr - rldcr. */
2124 static inline void gen_rldcr(DisasContext *ctx, int men)
2125 {
2126 uint32_t me;
2127
2128 me = MB(ctx->opcode) | (men << 5);
2129 gen_rldnm(ctx, 0, me);
2130 }
2131 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
2132
2133 /* rldimi - rldimi. */
2134 static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
2135 {
2136 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2137 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2138 uint32_t sh = SH(ctx->opcode) | (shn << 5);
2139 uint32_t mb = MB(ctx->opcode) | (mbn << 5);
2140 uint32_t me = 63 - sh;
2141
2142 if (mb <= me) {
2143 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
2144 } else {
2145 target_ulong mask = MASK(mb, me);
2146 TCGv t1 = tcg_temp_new();
2147
2148 tcg_gen_rotli_tl(t1, t_rs, sh);
2149 tcg_gen_andi_tl(t1, t1, mask);
2150 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
2151 tcg_gen_or_tl(t_ra, t_ra, t1);
2152 tcg_temp_free(t1);
2153 }
2154 if (unlikely(Rc(ctx->opcode) != 0)) {
2155 gen_set_Rc0(ctx, t_ra);
2156 }
2157 }
2158 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
2159 #endif
2160
2161 /*** Integer shift ***/
2162
2163 /* slw & slw. */
2164 static void gen_slw(DisasContext *ctx)
2165 {
2166 TCGv t0, t1;
2167
2168 t0 = tcg_temp_new();
2169 /* AND rS with a mask that is 0 when rB >= 0x20 */
2170 #if defined(TARGET_PPC64)
2171 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2172 tcg_gen_sari_tl(t0, t0, 0x3f);
2173 #else
2174 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2175 tcg_gen_sari_tl(t0, t0, 0x1f);
2176 #endif
2177 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2178 t1 = tcg_temp_new();
2179 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2180 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2181 tcg_temp_free(t1);
2182 tcg_temp_free(t0);
2183 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
2184 if (unlikely(Rc(ctx->opcode) != 0)) {
2185 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2186 }
2187 }
2188
2189 /* sraw & sraw. */
2190 static void gen_sraw(DisasContext *ctx)
2191 {
2192 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
2193 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2194 if (unlikely(Rc(ctx->opcode) != 0)) {
2195 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2196 }
2197 }
2198
2199 /* srawi & srawi. */
2200 static void gen_srawi(DisasContext *ctx)
2201 {
2202 int sh = SH(ctx->opcode);
2203 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2204 TCGv src = cpu_gpr[rS(ctx->opcode)];
2205 if (sh == 0) {
2206 tcg_gen_ext32s_tl(dst, src);
2207 tcg_gen_movi_tl(cpu_ca, 0);
2208 if (is_isa300(ctx)) {
2209 tcg_gen_movi_tl(cpu_ca32, 0);
2210 }
2211 } else {
2212 TCGv t0;
2213 tcg_gen_ext32s_tl(dst, src);
2214 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
2215 t0 = tcg_temp_new();
2216 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
2217 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2218 tcg_temp_free(t0);
2219 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2220 if (is_isa300(ctx)) {
2221 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
2222 }
2223 tcg_gen_sari_tl(dst, dst, sh);
2224 }
2225 if (unlikely(Rc(ctx->opcode) != 0)) {
2226 gen_set_Rc0(ctx, dst);
2227 }
2228 }
2229
2230 /* srw & srw. */
2231 static void gen_srw(DisasContext *ctx)
2232 {
2233 TCGv t0, t1;
2234
2235 t0 = tcg_temp_new();
2236 /* AND rS with a mask that is 0 when rB >= 0x20 */
2237 #if defined(TARGET_PPC64)
2238 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2239 tcg_gen_sari_tl(t0, t0, 0x3f);
2240 #else
2241 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2242 tcg_gen_sari_tl(t0, t0, 0x1f);
2243 #endif
2244 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2245 tcg_gen_ext32u_tl(t0, t0);
2246 t1 = tcg_temp_new();
2247 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2248 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2249 tcg_temp_free(t1);
2250 tcg_temp_free(t0);
2251 if (unlikely(Rc(ctx->opcode) != 0)) {
2252 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2253 }
2254 }
2255
2256 #if defined(TARGET_PPC64)
2257 /* sld & sld. */
2258 static void gen_sld(DisasContext *ctx)
2259 {
2260 TCGv t0, t1;
2261
2262 t0 = tcg_temp_new();
2263 /* AND rS with a mask that is 0 when rB >= 0x40 */
2264 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2265 tcg_gen_sari_tl(t0, t0, 0x3f);
2266 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2267 t1 = tcg_temp_new();
2268 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2269 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2270 tcg_temp_free(t1);
2271 tcg_temp_free(t0);
2272 if (unlikely(Rc(ctx->opcode) != 0)) {
2273 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2274 }
2275 }
2276
2277 /* srad & srad. */
2278 static void gen_srad(DisasContext *ctx)
2279 {
2280 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
2281 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2282 if (unlikely(Rc(ctx->opcode) != 0)) {
2283 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2284 }
2285 }
2286 /* sradi & sradi. */
2287 static inline void gen_sradi(DisasContext *ctx, int n)
2288 {
2289 int sh = SH(ctx->opcode) + (n << 5);
2290 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2291 TCGv src = cpu_gpr[rS(ctx->opcode)];
2292 if (sh == 0) {
2293 tcg_gen_mov_tl(dst, src);
2294 tcg_gen_movi_tl(cpu_ca, 0);
2295 if (is_isa300(ctx)) {
2296 tcg_gen_movi_tl(cpu_ca32, 0);
2297 }
2298 } else {
2299 TCGv t0;
2300 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2301 t0 = tcg_temp_new();
2302 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2303 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2304 tcg_temp_free(t0);
2305 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2306 if (is_isa300(ctx)) {
2307 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
2308 }
2309 tcg_gen_sari_tl(dst, src, sh);
2310 }
2311 if (unlikely(Rc(ctx->opcode) != 0)) {
2312 gen_set_Rc0(ctx, dst);
2313 }
2314 }
2315
2316 static void gen_sradi0(DisasContext *ctx)
2317 {
2318 gen_sradi(ctx, 0);
2319 }
2320
2321 static void gen_sradi1(DisasContext *ctx)
2322 {
2323 gen_sradi(ctx, 1);
2324 }
2325
2326 /* extswsli & extswsli. */
2327 static inline void gen_extswsli(DisasContext *ctx, int n)
2328 {
2329 int sh = SH(ctx->opcode) + (n << 5);
2330 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2331 TCGv src = cpu_gpr[rS(ctx->opcode)];
2332
2333 tcg_gen_ext32s_tl(dst, src);
2334 tcg_gen_shli_tl(dst, dst, sh);
2335 if (unlikely(Rc(ctx->opcode) != 0)) {
2336 gen_set_Rc0(ctx, dst);
2337 }
2338 }
2339
2340 static void gen_extswsli0(DisasContext *ctx)
2341 {
2342 gen_extswsli(ctx, 0);
2343 }
2344
2345 static void gen_extswsli1(DisasContext *ctx)
2346 {
2347 gen_extswsli(ctx, 1);
2348 }
2349
2350 /* srd & srd. */
2351 static void gen_srd(DisasContext *ctx)
2352 {
2353 TCGv t0, t1;
2354
2355 t0 = tcg_temp_new();
2356 /* AND rS with a mask that is 0 when rB >= 0x40 */
2357 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2358 tcg_gen_sari_tl(t0, t0, 0x3f);
2359 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2360 t1 = tcg_temp_new();
2361 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2362 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2363 tcg_temp_free(t1);
2364 tcg_temp_free(t0);
2365 if (unlikely(Rc(ctx->opcode) != 0)) {
2366 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2367 }
2368 }
2369 #endif
2370
2371 /*** Addressing modes ***/
2372 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2373 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2374 target_long maskl)
2375 {
2376 target_long simm = SIMM(ctx->opcode);
2377
2378 simm &= ~maskl;
2379 if (rA(ctx->opcode) == 0) {
2380 if (NARROW_MODE(ctx)) {
2381 simm = (uint32_t)simm;
2382 }
2383 tcg_gen_movi_tl(EA, simm);
2384 } else if (likely(simm != 0)) {
2385 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2386 if (NARROW_MODE(ctx)) {
2387 tcg_gen_ext32u_tl(EA, EA);
2388 }
2389 } else {
2390 if (NARROW_MODE(ctx)) {
2391 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2392 } else {
2393 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2394 }
2395 }
2396 }
2397
2398 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2399 {
2400 if (rA(ctx->opcode) == 0) {
2401 if (NARROW_MODE(ctx)) {
2402 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2403 } else {
2404 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2405 }
2406 } else {
2407 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2408 if (NARROW_MODE(ctx)) {
2409 tcg_gen_ext32u_tl(EA, EA);
2410 }
2411 }
2412 }
2413
2414 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2415 {
2416 if (rA(ctx->opcode) == 0) {
2417 tcg_gen_movi_tl(EA, 0);
2418 } else if (NARROW_MODE(ctx)) {
2419 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2420 } else {
2421 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2422 }
2423 }
2424
2425 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2426 target_long val)
2427 {
2428 tcg_gen_addi_tl(ret, arg1, val);
2429 if (NARROW_MODE(ctx)) {
2430 tcg_gen_ext32u_tl(ret, ret);
2431 }
2432 }
2433
2434 static inline void gen_align_no_le(DisasContext *ctx)
2435 {
2436 gen_exception_err(ctx, POWERPC_EXCP_ALIGN,
2437 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE);
2438 }
2439
2440 /*** Integer load ***/
2441 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask)
2442 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP))
2443
2444 #define GEN_QEMU_LOAD_TL(ldop, op) \
2445 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \
2446 TCGv val, \
2447 TCGv addr) \
2448 { \
2449 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \
2450 }
2451
2452 GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB))
2453 GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW))
2454 GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW))
2455 GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL))
2456 GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL))
2457
2458 GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW))
2459 GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL))
2460
2461 #define GEN_QEMU_LOAD_64(ldop, op) \
2462 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \
2463 TCGv_i64 val, \
2464 TCGv addr) \
2465 { \
2466 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \
2467 }
2468
2469 GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB))
2470 GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW))
2471 GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL))
2472 GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL))
2473 GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q))
2474
2475 #if defined(TARGET_PPC64)
2476 GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q))
2477 #endif
2478
2479 #define GEN_QEMU_STORE_TL(stop, op) \
2480 static void glue(gen_qemu_, stop)(DisasContext *ctx, \
2481 TCGv val, \
2482 TCGv addr) \
2483 { \
2484 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \
2485 }
2486
2487 GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB))
2488 GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW))
2489 GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL))
2490
2491 GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW))
2492 GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL))
2493
2494 #define GEN_QEMU_STORE_64(stop, op) \
2495 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \
2496 TCGv_i64 val, \
2497 TCGv addr) \
2498 { \
2499 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \
2500 }
2501
2502 GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB))
2503 GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW))
2504 GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL))
2505 GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q))
2506
2507 #if defined(TARGET_PPC64)
2508 GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q))
2509 #endif
2510
2511 #define GEN_LD(name, ldop, opc, type) \
2512 static void glue(gen_, name)(DisasContext *ctx) \
2513 { \
2514 TCGv EA; \
2515 gen_set_access_type(ctx, ACCESS_INT); \
2516 EA = tcg_temp_new(); \
2517 gen_addr_imm_index(ctx, EA, 0); \
2518 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2519 tcg_temp_free(EA); \
2520 }
2521
2522 #define GEN_LDU(name, ldop, opc, type) \
2523 static void glue(gen_, name##u)(DisasContext *ctx) \
2524 { \
2525 TCGv EA; \
2526 if (unlikely(rA(ctx->opcode) == 0 || \
2527 rA(ctx->opcode) == rD(ctx->opcode))) { \
2528 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2529 return; \
2530 } \
2531 gen_set_access_type(ctx, ACCESS_INT); \
2532 EA = tcg_temp_new(); \
2533 if (type == PPC_64B) \
2534 gen_addr_imm_index(ctx, EA, 0x03); \
2535 else \
2536 gen_addr_imm_index(ctx, EA, 0); \
2537 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2538 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2539 tcg_temp_free(EA); \
2540 }
2541
2542 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2543 static void glue(gen_, name##ux)(DisasContext *ctx) \
2544 { \
2545 TCGv EA; \
2546 if (unlikely(rA(ctx->opcode) == 0 || \
2547 rA(ctx->opcode) == rD(ctx->opcode))) { \
2548 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2549 return; \
2550 } \
2551 gen_set_access_type(ctx, ACCESS_INT); \
2552 EA = tcg_temp_new(); \
2553 gen_addr_reg_index(ctx, EA); \
2554 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2555 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2556 tcg_temp_free(EA); \
2557 }
2558
2559 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
2560 static void glue(gen_, name##x)(DisasContext *ctx) \
2561 { \
2562 TCGv EA; \
2563 chk; \
2564 gen_set_access_type(ctx, ACCESS_INT); \
2565 EA = tcg_temp_new(); \
2566 gen_addr_reg_index(ctx, EA); \
2567 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2568 tcg_temp_free(EA); \
2569 }
2570
2571 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2572 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2573
2574 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
2575 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2576
2577 #define GEN_LDS(name, ldop, op, type) \
2578 GEN_LD(name, ldop, op | 0x20, type); \
2579 GEN_LDU(name, ldop, op | 0x21, type); \
2580 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2581 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2582
2583 /* lbz lbzu lbzux lbzx */
2584 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2585 /* lha lhau lhaux lhax */
2586 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2587 /* lhz lhzu lhzux lhzx */
2588 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2589 /* lwz lwzu lwzux lwzx */
2590 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2591
2592 #define GEN_LDEPX(name, ldop, opc2, opc3) \
2593 static void glue(gen_, name##epx)(DisasContext *ctx) \
2594 { \
2595 TCGv EA; \
2596 CHK_SV; \
2597 gen_set_access_type(ctx, ACCESS_INT); \
2598 EA = tcg_temp_new(); \
2599 gen_addr_reg_index(ctx, EA); \
2600 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\
2601 tcg_temp_free(EA); \
2602 }
2603
2604 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02)
2605 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08)
2606 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00)
2607 #if defined(TARGET_PPC64)
2608 GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00)
2609 #endif
2610
2611 #if defined(TARGET_PPC64)
2612 /* lwaux */
2613 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2614 /* lwax */
2615 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2616 /* ldux */
2617 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B);
2618 /* ldx */
2619 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B);
2620
2621 /* CI load/store variants */
2622 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
2623 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
2624 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
2625 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
2626
2627 static void gen_ld(DisasContext *ctx)
2628 {
2629 TCGv EA;
2630 if (Rc(ctx->opcode)) {
2631 if (unlikely(rA(ctx->opcode) == 0 ||
2632 rA(ctx->opcode) == rD(ctx->opcode))) {
2633 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2634 return;
2635 }
2636 }
2637 gen_set_access_type(ctx, ACCESS_INT);
2638 EA = tcg_temp_new();
2639 gen_addr_imm_index(ctx, EA, 0x03);
2640 if (ctx->opcode & 0x02) {
2641 /* lwa (lwau is undefined) */
2642 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2643 } else {
2644 /* ld - ldu */
2645 gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2646 }
2647 if (Rc(ctx->opcode)) {
2648 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2649 }
2650 tcg_temp_free(EA);
2651 }
2652
2653 /* lq */
2654 static void gen_lq(DisasContext *ctx)
2655 {
2656 int ra, rd;
2657 TCGv EA, hi, lo;
2658
2659 /* lq is a legal user mode instruction starting in ISA 2.07 */
2660 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2661 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2662
2663 if (!legal_in_user_mode && ctx->pr) {
2664 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2665 return;
2666 }
2667
2668 if (!le_is_supported && ctx->le_mode) {
2669 gen_align_no_le(ctx);
2670 return;
2671 }
2672 ra = rA(ctx->opcode);
2673 rd = rD(ctx->opcode);
2674 if (unlikely((rd & 1) || rd == ra)) {
2675 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2676 return;
2677 }
2678
2679 gen_set_access_type(ctx, ACCESS_INT);
2680 EA = tcg_temp_new();
2681 gen_addr_imm_index(ctx, EA, 0x0F);
2682
2683 /* Note that the low part is always in RD+1, even in LE mode. */
2684 lo = cpu_gpr[rd + 1];
2685 hi = cpu_gpr[rd];
2686
2687 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
2688 if (HAVE_ATOMIC128) {
2689 TCGv_i32 oi = tcg_temp_new_i32();
2690 if (ctx->le_mode) {
2691 tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx));
2692 gen_helper_lq_le_parallel(lo, cpu_env, EA, oi);
2693 } else {
2694 tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx));
2695 gen_helper_lq_be_parallel(lo, cpu_env, EA, oi);
2696 }
2697 tcg_temp_free_i32(oi);
2698 tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh));
2699 } else {
2700 /* Restart with exclusive lock. */
2701 gen_helper_exit_atomic(cpu_env);
2702 ctx->base.is_jmp = DISAS_NORETURN;
2703 }
2704 } else if (ctx->le_mode) {
2705 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ);
2706 gen_addr_add(ctx, EA, EA, 8);
2707 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ);
2708 } else {
2709 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ);
2710 gen_addr_add(ctx, EA, EA, 8);
2711 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ);
2712 }
2713 tcg_temp_free(EA);
2714 }
2715 #endif
2716
2717 /*** Integer store ***/
2718 #define GEN_ST(name, stop, opc, type) \
2719 static void glue(gen_, name)(DisasContext *ctx) \
2720 { \
2721 TCGv EA; \
2722 gen_set_access_type(ctx, ACCESS_INT); \
2723 EA = tcg_temp_new(); \
2724 gen_addr_imm_index(ctx, EA, 0); \
2725 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2726 tcg_temp_free(EA); \
2727 }
2728
2729 #define GEN_STU(name, stop, opc, type) \
2730 static void glue(gen_, stop##u)(DisasContext *ctx) \
2731 { \
2732 TCGv EA; \
2733 if (unlikely(rA(ctx->opcode) == 0)) { \
2734 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2735 return; \
2736 } \
2737 gen_set_access_type(ctx, ACCESS_INT); \
2738 EA = tcg_temp_new(); \
2739 if (type == PPC_64B) \
2740 gen_addr_imm_index(ctx, EA, 0x03); \
2741 else \
2742 gen_addr_imm_index(ctx, EA, 0); \
2743 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2744 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2745 tcg_temp_free(EA); \
2746 }
2747
2748 #define GEN_STUX(name, stop, opc2, opc3, type) \
2749 static void glue(gen_, name##ux)(DisasContext *ctx) \
2750 { \
2751 TCGv EA; \
2752 if (unlikely(rA(ctx->opcode) == 0)) { \
2753 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2754 return; \
2755 } \
2756 gen_set_access_type(ctx, ACCESS_INT); \
2757 EA = tcg_temp_new(); \
2758 gen_addr_reg_index(ctx, EA); \
2759 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2760 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2761 tcg_temp_free(EA); \
2762 }
2763
2764 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
2765 static void glue(gen_, name##x)(DisasContext *ctx) \
2766 { \
2767 TCGv EA; \
2768 chk; \
2769 gen_set_access_type(ctx, ACCESS_INT); \
2770 EA = tcg_temp_new(); \
2771 gen_addr_reg_index(ctx, EA); \
2772 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2773 tcg_temp_free(EA); \
2774 }
2775 #define GEN_STX(name, stop, opc2, opc3, type) \
2776 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2777
2778 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
2779 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2780
2781 #define GEN_STS(name, stop, op, type) \
2782 GEN_ST(name, stop, op | 0x20, type); \
2783 GEN_STU(name, stop, op | 0x21, type); \
2784 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2785 GEN_STX(name, stop, 0x17, op | 0x00, type)
2786
2787 /* stb stbu stbux stbx */
2788 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2789 /* sth sthu sthux sthx */
2790 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2791 /* stw stwu stwux stwx */
2792 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2793
2794 #define GEN_STEPX(name, stop, opc2, opc3) \
2795 static void glue(gen_, name##epx)(DisasContext *ctx) \
2796 { \
2797 TCGv EA; \
2798 CHK_SV; \
2799 gen_set_access_type(ctx, ACCESS_INT); \
2800 EA = tcg_temp_new(); \
2801 gen_addr_reg_index(ctx, EA); \
2802 tcg_gen_qemu_st_tl( \
2803 cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \
2804 tcg_temp_free(EA); \
2805 }
2806
2807 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06)
2808 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C)
2809 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04)
2810 #if defined(TARGET_PPC64)
2811 GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04)
2812 #endif
2813
2814 #if defined(TARGET_PPC64)
2815 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B);
2816 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B);
2817 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
2818 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
2819 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
2820 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
2821
2822 static void gen_std(DisasContext *ctx)
2823 {
2824 int rs;
2825 TCGv EA;
2826
2827 rs = rS(ctx->opcode);
2828 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
2829 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2830 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2831 TCGv hi, lo;
2832
2833 if (!(ctx->insns_flags & PPC_64BX)) {
2834 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2835 }
2836
2837 if (!legal_in_user_mode && ctx->pr) {
2838 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2839 return;
2840 }
2841
2842 if (!le_is_supported && ctx->le_mode) {
2843 gen_align_no_le(ctx);
2844 return;
2845 }
2846
2847 if (unlikely(rs & 1)) {
2848 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2849 return;
2850 }
2851 gen_set_access_type(ctx, ACCESS_INT);
2852 EA = tcg_temp_new();
2853 gen_addr_imm_index(ctx, EA, 0x03);
2854
2855 /* Note that the low part is always in RS+1, even in LE mode. */
2856 lo = cpu_gpr[rs + 1];
2857 hi = cpu_gpr[rs];
2858
2859 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
2860 if (HAVE_ATOMIC128) {
2861 TCGv_i32 oi = tcg_temp_new_i32();
2862 if (ctx->le_mode) {
2863 tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx));
2864 gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi);
2865 } else {
2866 tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx));
2867 gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi);
2868 }
2869 tcg_temp_free_i32(oi);
2870 } else {
2871 /* Restart with exclusive lock. */
2872 gen_helper_exit_atomic(cpu_env);
2873 ctx->base.is_jmp = DISAS_NORETURN;
2874 }
2875 } else if (ctx->le_mode) {
2876 tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ);
2877 gen_addr_add(ctx, EA, EA, 8);
2878 tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_LEQ);
2879 } else {
2880 tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_BEQ);
2881 gen_addr_add(ctx, EA, EA, 8);
2882 tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_BEQ);
2883 }
2884 tcg_temp_free(EA);
2885 } else {
2886 /* std / stdu */
2887 if (Rc(ctx->opcode)) {
2888 if (unlikely(rA(ctx->opcode) == 0)) {
2889 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2890 return;
2891 }
2892 }
2893 gen_set_access_type(ctx, ACCESS_INT);
2894 EA = tcg_temp_new();
2895 gen_addr_imm_index(ctx, EA, 0x03);
2896 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
2897 if (Rc(ctx->opcode)) {
2898 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2899 }
2900 tcg_temp_free(EA);
2901 }
2902 }
2903 #endif
2904 /*** Integer load and store with byte reverse ***/
2905
2906 /* lhbrx */
2907 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2908
2909 /* lwbrx */
2910 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2911
2912 #if defined(TARGET_PPC64)
2913 /* ldbrx */
2914 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE);
2915 /* stdbrx */
2916 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE);
2917 #endif /* TARGET_PPC64 */
2918
2919 /* sthbrx */
2920 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2921 /* stwbrx */
2922 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2923
2924 /*** Integer load and store multiple ***/
2925
2926 /* lmw */
2927 static void gen_lmw(DisasContext *ctx)
2928 {
2929 TCGv t0;
2930 TCGv_i32 t1;
2931
2932 if (ctx->le_mode) {
2933 gen_align_no_le(ctx);
2934 return;
2935 }
2936 gen_set_access_type(ctx, ACCESS_INT);
2937 t0 = tcg_temp_new();
2938 t1 = tcg_const_i32(rD(ctx->opcode));
2939 gen_addr_imm_index(ctx, t0, 0);
2940 gen_helper_lmw(cpu_env, t0, t1);
2941 tcg_temp_free(t0);
2942 tcg_temp_free_i32(t1);
2943 }
2944
2945 /* stmw */
2946 static void gen_stmw(DisasContext *ctx)
2947 {
2948 TCGv t0;
2949 TCGv_i32 t1;
2950
2951 if (ctx->le_mode) {
2952 gen_align_no_le(ctx);
2953 return;
2954 }
2955 gen_set_access_type(ctx, ACCESS_INT);
2956 t0 = tcg_temp_new();
2957 t1 = tcg_const_i32(rS(ctx->opcode));
2958 gen_addr_imm_index(ctx, t0, 0);
2959 gen_helper_stmw(cpu_env, t0, t1);
2960 tcg_temp_free(t0);
2961 tcg_temp_free_i32(t1);
2962 }
2963
2964 /*** Integer load and store strings ***/
2965
2966 /* lswi */
2967 /*
2968 * PowerPC32 specification says we must generate an exception if rA is
2969 * in the range of registers to be loaded. In an other hand, IBM says
2970 * this is valid, but rA won't be loaded. For now, I'll follow the
2971 * spec...
2972 */
2973 static void gen_lswi(DisasContext *ctx)
2974 {
2975 TCGv t0;
2976 TCGv_i32 t1, t2;
2977 int nb = NB(ctx->opcode);
2978 int start = rD(ctx->opcode);
2979 int ra = rA(ctx->opcode);
2980 int nr;
2981
2982 if (ctx->le_mode) {
2983 gen_align_no_le(ctx);
2984 return;
2985 }
2986 if (nb == 0) {
2987 nb = 32;
2988 }
2989 nr = DIV_ROUND_UP(nb, 4);
2990 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
2991 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2992 return;
2993 }
2994 gen_set_access_type(ctx, ACCESS_INT);
2995 t0 = tcg_temp_new();
2996 gen_addr_register(ctx, t0);
2997 t1 = tcg_const_i32(nb);
2998 t2 = tcg_const_i32(start);
2999 gen_helper_lsw(cpu_env, t0, t1, t2);
3000 tcg_temp_free(t0);
3001 tcg_temp_free_i32(t1);
3002 tcg_temp_free_i32(t2);
3003 }
3004
3005 /* lswx */
3006 static void gen_lswx(DisasContext *ctx)
3007 {
3008 TCGv t0;
3009 TCGv_i32 t1, t2, t3;
3010
3011 if (ctx->le_mode) {
3012 gen_align_no_le(ctx);
3013 return;
3014 }
3015 gen_set_access_type(ctx, ACCESS_INT);
3016 t0 = tcg_temp_new();
3017 gen_addr_reg_index(ctx, t0);
3018 t1 = tcg_const_i32(rD(ctx->opcode));
3019 t2 = tcg_const_i32(rA(ctx->opcode));
3020 t3 = tcg_const_i32(rB(ctx->opcode));
3021 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3022 tcg_temp_free(t0);
3023 tcg_temp_free_i32(t1);
3024 tcg_temp_free_i32(t2);
3025 tcg_temp_free_i32(t3);
3026 }
3027
3028 /* stswi */
3029 static void gen_stswi(DisasContext *ctx)
3030 {
3031 TCGv t0;
3032 TCGv_i32 t1, t2;
3033 int nb = NB(ctx->opcode);
3034
3035 if (ctx->le_mode) {
3036 gen_align_no_le(ctx);
3037 return;
3038 }
3039 gen_set_access_type(ctx, ACCESS_INT);
3040 t0 = tcg_temp_new();
3041 gen_addr_register(ctx, t0);
3042 if (nb == 0) {
3043 nb = 32;
3044 }
3045 t1 = tcg_const_i32(nb);
3046 t2 = tcg_const_i32(rS(ctx->opcode));
3047 gen_helper_stsw(cpu_env, t0, t1, t2);
3048 tcg_temp_free(t0);
3049 tcg_temp_free_i32(t1);
3050 tcg_temp_free_i32(t2);
3051 }
3052
3053 /* stswx */
3054 static void gen_stswx(DisasContext *ctx)
3055 {
3056 TCGv t0;
3057 TCGv_i32 t1, t2;
3058
3059 if (ctx->le_mode) {
3060 gen_align_no_le(ctx);
3061 return;
3062 }
3063 gen_set_access_type(ctx, ACCESS_INT);
3064 t0 = tcg_temp_new();
3065 gen_addr_reg_index(ctx, t0);
3066 t1 = tcg_temp_new_i32();
3067 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3068 tcg_gen_andi_i32(t1, t1, 0x7F);
3069 t2 = tcg_const_i32(rS(ctx->opcode));
3070 gen_helper_stsw(cpu_env, t0, t1, t2);
3071 tcg_temp_free(t0);
3072 tcg_temp_free_i32(t1);
3073 tcg_temp_free_i32(t2);
3074 }
3075
3076 /*** Memory synchronisation ***/
3077 /* eieio */
3078 static void gen_eieio(DisasContext *ctx)
3079 {
3080 TCGBar bar = TCG_MO_LD_ST;
3081
3082 /*
3083 * POWER9 has a eieio instruction variant using bit 6 as a hint to
3084 * tell the CPU it is a store-forwarding barrier.
3085 */
3086 if (ctx->opcode & 0x2000000) {
3087 /*
3088 * ISA says that "Reserved fields in instructions are ignored
3089 * by the processor". So ignore the bit 6 on non-POWER9 CPU but
3090 * as this is not an instruction software should be using,
3091 * complain to the user.
3092 */
3093 if (!(ctx->insns_flags2 & PPC2_ISA300)) {
3094 qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @"
3095 TARGET_FMT_lx "\n", ctx->base.pc_next - 4);
3096 } else {
3097 bar = TCG_MO_ST_LD;
3098 }
3099 }
3100
3101 tcg_gen_mb(bar | TCG_BAR_SC);
3102 }
3103
3104 #if !defined(CONFIG_USER_ONLY)
3105 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global)
3106 {
3107 TCGv_i32 t;
3108 TCGLabel *l;
3109
3110 if (!ctx->lazy_tlb_flush) {
3111 return;
3112 }
3113 l = gen_new_label();
3114 t = tcg_temp_new_i32();
3115 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
3116 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
3117 if (global) {
3118 gen_helper_check_tlb_flush_global(cpu_env);
3119 } else {
3120 gen_helper_check_tlb_flush_local(cpu_env);
3121 }
3122 gen_set_label(l);
3123 tcg_temp_free_i32(t);
3124 }
3125 #else
3126 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { }
3127 #endif
3128
3129 /* isync */
3130 static void gen_isync(DisasContext *ctx)
3131 {
3132 /*
3133 * We need to check for a pending TLB flush. This can only happen in
3134 * kernel mode however so check MSR_PR
3135 */
3136 if (!ctx->pr) {
3137 gen_check_tlb_flush(ctx, false);
3138 }
3139 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
3140 gen_stop_exception(ctx);
3141 }
3142
3143 #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE))
3144
3145 static void gen_load_locked(DisasContext *ctx, TCGMemOp memop)
3146 {
3147 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3148 TCGv t0 = tcg_temp_new();
3149
3150 gen_set_access_type(ctx, ACCESS_RES);
3151 gen_addr_reg_index(ctx, t0);
3152 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN);
3153 tcg_gen_mov_tl(cpu_reserve, t0);
3154 tcg_gen_mov_tl(cpu_reserve_val, gpr);
3155 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
3156 tcg_temp_free(t0);
3157 }
3158
3159 #define LARX(name, memop) \
3160 static void gen_##name(DisasContext *ctx) \
3161 { \
3162 gen_load_locked(ctx, memop); \
3163 }
3164
3165 /* lwarx */
3166 LARX(lbarx, DEF_MEMOP(MO_UB))
3167 LARX(lharx, DEF_MEMOP(MO_UW))
3168 LARX(lwarx, DEF_MEMOP(MO_UL))
3169
3170 static void gen_fetch_inc_conditional(DisasContext *ctx, TCGMemOp memop,
3171 TCGv EA, TCGCond cond, int addend)
3172 {
3173 TCGv t = tcg_temp_new();
3174 TCGv t2 = tcg_temp_new();
3175 TCGv u = tcg_temp_new();
3176
3177 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop);
3178 tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop));
3179 tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop);
3180 tcg_gen_addi_tl(u, t, addend);
3181
3182 /* E.g. for fetch and increment bounded... */
3183 /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */
3184 tcg_gen_movcond_tl(cond, u, t, t2, u, t);
3185 tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop);
3186
3187 /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */
3188 tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1));
3189 tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u);
3190
3191 tcg_temp_free(t);
3192 tcg_temp_free(t2);
3193 tcg_temp_free(u);
3194 }
3195
3196 static void gen_ld_atomic(DisasContext *ctx, TCGMemOp memop)
3197 {
3198 uint32_t gpr_FC = FC(ctx->opcode);
3199 TCGv EA = tcg_temp_new();
3200 int rt = rD(ctx->opcode);
3201 bool need_serial;
3202 TCGv src, dst;
3203
3204 gen_addr_register(ctx, EA);
3205 dst = cpu_gpr[rt];
3206 src = cpu_gpr[(rt + 1) & 31];
3207
3208 need_serial = false;
3209 memop |= MO_ALIGN;
3210 switch (gpr_FC) {
3211 case 0: /* Fetch and add */
3212 tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop);
3213 break;
3214 case 1: /* Fetch and xor */
3215 tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop);
3216 break;
3217 case 2: /* Fetch and or */
3218 tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop);
3219 break;
3220 case 3: /* Fetch and 'and' */
3221 tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop);
3222 break;
3223 case 4: /* Fetch and max unsigned */
3224 tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop);
3225 break;
3226 case 5: /* Fetch and max signed */
3227 tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop);
3228 break;
3229 case 6: /* Fetch and min unsigned */
3230 tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop);
3231 break;
3232 case 7: /* Fetch and min signed */
3233 tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop);
3234 break;
3235 case 8: /* Swap */
3236 tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop);
3237 break;
3238
3239 case 16: /* Compare and swap not equal */
3240 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3241 need_serial = true;
3242 } else {
3243 TCGv t0 = tcg_temp_new();
3244 TCGv t1 = tcg_temp_new();
3245
3246 tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop);
3247 if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) {
3248 tcg_gen_mov_tl(t1, src);
3249 } else {
3250 tcg_gen_ext32u_tl(t1, src);
3251 }
3252 tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1,
3253 cpu_gpr[(rt + 2) & 31], t0);
3254 tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop);
3255 tcg_gen_mov_tl(dst, t0);
3256
3257 tcg_temp_free(t0);
3258 tcg_temp_free(t1);
3259 }
3260 break;
3261
3262 case 24: /* Fetch and increment bounded */
3263 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3264 need_serial = true;
3265 } else {
3266 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1);
3267 }
3268 break;
3269 case 25: /* Fetch and increment equal */
3270 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3271 need_serial = true;
3272 } else {
3273 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1);
3274 }
3275 break;
3276 case 28: /* Fetch and decrement bounded */
3277 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3278 need_serial = true;
3279 } else {
3280 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1);
3281 }
3282 break;
3283
3284 default:
3285 /* invoke data storage error handler */
3286 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL);
3287 }
3288 tcg_temp_free(EA);
3289
3290 if (need_serial) {
3291 /* Restart with exclusive lock. */
3292 gen_helper_exit_atomic(cpu_env);
3293 ctx->base.is_jmp = DISAS_NORETURN;
3294 }
3295 }
3296
3297 static void gen_lwat(DisasContext *ctx)
3298 {
3299 gen_ld_atomic(ctx, DEF_MEMOP(MO_UL));
3300 }
3301
3302 #ifdef TARGET_PPC64
3303 static void gen_ldat(DisasContext *ctx)
3304 {
3305 gen_ld_atomic(ctx, DEF_MEMOP(MO_Q));
3306 }
3307 #endif
3308
3309 static void gen_st_atomic(DisasContext *ctx, TCGMemOp memop)
3310 {
3311 uint32_t gpr_FC = FC(ctx->opcode);
3312 TCGv EA = tcg_temp_new();
3313 TCGv src, discard;
3314
3315 gen_addr_register(ctx, EA);
3316 src = cpu_gpr[rD(ctx->opcode)];
3317 discard = tcg_temp_new();
3318
3319 memop |= MO_ALIGN;
3320 switch (gpr_FC) {
3321 case 0: /* add and Store */
3322 tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3323 break;
3324 case 1: /* xor and Store */
3325 tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3326 break;
3327 case 2: /* Or and Store */
3328 tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3329 break;
3330 case 3: /* 'and' and Store */
3331 tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3332 break;
3333 case 4: /* Store max unsigned */
3334 tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3335 break;
3336 case 5: /* Store max signed */
3337 tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3338 break;
3339 case 6: /* Store min unsigned */
3340 tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3341 break;
3342 case 7: /* Store min signed */
3343 tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3344 break;
3345 case 24: /* Store twin */
3346 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3347 /* Restart with exclusive lock. */
3348 gen_helper_exit_atomic(cpu_env);
3349 ctx->base.is_jmp = DISAS_NORETURN;
3350 } else {
3351 TCGv t = tcg_temp_new();
3352 TCGv t2 = tcg_temp_new();
3353 TCGv s = tcg_temp_new();
3354 TCGv s2 = tcg_temp_new();
3355 TCGv ea_plus_s = tcg_temp_new();
3356
3357 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop);
3358 tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop));
3359 tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop);
3360 tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t);
3361 tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2);
3362 tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop);
3363 tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop);
3364
3365 tcg_temp_free(ea_plus_s);
3366 tcg_temp_free(s2);
3367 tcg_temp_free(s);
3368 tcg_temp_free(t2);
3369 tcg_temp_free(t);
3370 }
3371 break;
3372 default:
3373 /* invoke data storage error handler */
3374 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL);
3375 }
3376 tcg_temp_free(discard);
3377 tcg_temp_free(EA);
3378 }
3379
3380 static void gen_stwat(DisasContext *ctx)
3381 {
3382 gen_st_atomic(ctx, DEF_MEMOP(MO_UL));
3383 }
3384
3385 #ifdef TARGET_PPC64
3386 static void gen_stdat(DisasContext *ctx)
3387 {
3388 gen_st_atomic(ctx, DEF_MEMOP(MO_Q));
3389 }
3390 #endif
3391
3392 static void gen_conditional_store(DisasContext *ctx, TCGMemOp memop)
3393 {
3394 TCGLabel *l1 = gen_new_label();
3395 TCGLabel *l2 = gen_new_label();
3396 TCGv t0 = tcg_temp_new();
3397 int reg = rS(ctx->opcode);
3398
3399 gen_set_access_type(ctx, ACCESS_RES);
3400 gen_addr_reg_index(ctx, t0);
3401 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3402 tcg_temp_free(t0);
3403
3404 t0 = tcg_temp_new();
3405 tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val,
3406 cpu_gpr[reg], ctx->mem_idx,
3407 DEF_MEMOP(memop) | MO_ALIGN);
3408 tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val);
3409 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT);
3410 tcg_gen_or_tl(t0, t0, cpu_so);
3411 tcg_gen_trunc_tl_i32(cpu_crf[0], t0);
3412 tcg_temp_free(t0);
3413 tcg_gen_br(l2);
3414
3415 gen_set_label(l1);
3416
3417 /*
3418 * Address mismatch implies failure. But we still need to provide
3419 * the memory barrier semantics of the instruction.
3420 */
3421 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
3422 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3423
3424 gen_set_label(l2);
3425 tcg_gen_movi_tl(cpu_reserve, -1);
3426 }
3427
3428 #define STCX(name, memop) \
3429 static void gen_##name(DisasContext *ctx) \
3430 { \
3431 gen_conditional_store(ctx, memop); \
3432 }
3433
3434 STCX(stbcx_, DEF_MEMOP(MO_UB))
3435 STCX(sthcx_, DEF_MEMOP(MO_UW))
3436 STCX(stwcx_, DEF_MEMOP(MO_UL))
3437
3438 #if defined(TARGET_PPC64)
3439 /* ldarx */
3440 LARX(ldarx, DEF_MEMOP(MO_Q))
3441 /* stdcx. */
3442 STCX(stdcx_, DEF_MEMOP(MO_Q))
3443
3444 /* lqarx */
3445 static void gen_lqarx(DisasContext *ctx)
3446 {
3447 int rd = rD(ctx->opcode);
3448 TCGv EA, hi, lo;
3449
3450 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3451 (rd == rB(ctx->opcode)))) {
3452 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3453 return;
3454 }
3455
3456 gen_set_access_type(ctx, ACCESS_RES);
3457 EA = tcg_temp_new();
3458 gen_addr_reg_index(ctx, EA);
3459
3460 /* Note that the low part is always in RD+1, even in LE mode. */
3461 lo = cpu_gpr[rd + 1];
3462 hi = cpu_gpr[rd];
3463
3464 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3465 if (HAVE_ATOMIC128) {
3466 TCGv_i32 oi = tcg_temp_new_i32();
3467 if (ctx->le_mode) {
3468 tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16,
3469 ctx->mem_idx));
3470 gen_helper_lq_le_parallel(lo, cpu_env, EA, oi);
3471 } else {
3472 tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16,
3473 ctx->mem_idx));
3474 gen_helper_lq_be_parallel(lo, cpu_env, EA, oi);
3475 }
3476 tcg_temp_free_i32(oi);
3477 tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh));
3478 } else {
3479 /* Restart with exclusive lock. */
3480 gen_helper_exit_atomic(cpu_env);
3481 ctx->base.is_jmp = DISAS_NORETURN;
3482 tcg_temp_free(EA);
3483 return;
3484 }
3485 } else if (ctx->le_mode) {
3486 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16);
3487 tcg_gen_mov_tl(cpu_reserve, EA);
3488 gen_addr_add(ctx, EA, EA, 8);
3489 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ);
3490 } else {
3491 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ | MO_ALIGN_16);
3492 tcg_gen_mov_tl(cpu_reserve, EA);
3493 gen_addr_add(ctx, EA, EA, 8);
3494 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ);
3495 }
3496 tcg_temp_free(EA);
3497
3498 tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val));
3499 tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2));
3500 }
3501
3502 /* stqcx. */
3503 static void gen_stqcx_(DisasContext *ctx)
3504 {
3505 int rs = rS(ctx->opcode);
3506 TCGv EA, hi, lo;
3507
3508 if (unlikely(rs & 1)) {
3509 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3510 return;
3511 }
3512
3513 gen_set_access_type(ctx, ACCESS_RES);
3514 EA = tcg_temp_new();
3515 gen_addr_reg_index(ctx, EA);
3516
3517 /* Note that the low part is always in RS+1, even in LE mode. */
3518 lo = cpu_gpr[rs + 1];
3519 hi = cpu_gpr[rs];
3520
3521 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3522 if (HAVE_CMPXCHG128) {
3523 TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16);
3524 if (ctx->le_mode) {
3525 gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env,
3526 EA, lo, hi, oi);
3527 } else {
3528 gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env,
3529 EA, lo, hi, oi);
3530 }
3531 tcg_temp_free_i32(oi);
3532 } else {
3533 /* Restart with exclusive lock. */
3534 gen_helper_exit_atomic(cpu_env);
3535 ctx->base.is_jmp = DISAS_NORETURN;
3536 }
3537 tcg_temp_free(EA);
3538 } else {
3539 TCGLabel *lab_fail = gen_new_label();
3540 TCGLabel *lab_over = gen_new_label();
3541 TCGv_i64 t0 = tcg_temp_new_i64();
3542 TCGv_i64 t1 = tcg_temp_new_i64();
3543
3544 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail);
3545 tcg_temp_free(EA);
3546
3547 gen_qemu_ld64_i64(ctx, t0, cpu_reserve);
3548 tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode
3549 ? offsetof(CPUPPCState, reserve_val2)
3550 : offsetof(CPUPPCState, reserve_val)));
3551 tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail);
3552
3553 tcg_gen_addi_i64(t0, cpu_reserve, 8);
3554 gen_qemu_ld64_i64(ctx, t0, t0);
3555 tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode
3556 ? offsetof(CPUPPCState, reserve_val)
3557 : offsetof(CPUPPCState, reserve_val2)));
3558 tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail);
3559
3560 /* Success */
3561 gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve);
3562 tcg_gen_addi_i64(t0, cpu_reserve, 8);
3563 gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0);
3564
3565 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3566 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
3567 tcg_gen_br(lab_over);
3568
3569 gen_set_label(lab_fail);
3570 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3571
3572 gen_set_label(lab_over);
3573 tcg_gen_movi_tl(cpu_reserve, -1);
3574 tcg_temp_free_i64(t0);
3575 tcg_temp_free_i64(t1);
3576 }
3577 }
3578 #endif /* defined(TARGET_PPC64) */
3579
3580 /* sync */
3581 static void gen_sync(DisasContext *ctx)
3582 {
3583 uint32_t l = (ctx->opcode >> 21) & 3;
3584
3585 /*
3586 * We may need to check for a pending TLB flush.
3587 *
3588 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3589 *
3590 * Additionally, this can only happen in kernel mode however so
3591 * check MSR_PR as well.
3592 */
3593 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
3594 gen_check_tlb_flush(ctx, true);
3595 }
3596 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
3597 }
3598
3599 /* wait */
3600 static void gen_wait(DisasContext *ctx)
3601 {
3602 TCGv_i32 t0 = tcg_const_i32(1);
3603 tcg_gen_st_i32(t0, cpu_env,
3604 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3605 tcg_temp_free_i32(t0);
3606 /* Stop translation, as the CPU is supposed to sleep from now */
3607 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
3608 }
3609
3610 #if defined(TARGET_PPC64)
3611 static void gen_doze(DisasContext *ctx)
3612 {
3613 #if defined(CONFIG_USER_ONLY)
3614 GEN_PRIV;
3615 #else
3616 TCGv_i32 t;
3617
3618 CHK_HV;
3619 t = tcg_const_i32(PPC_PM_DOZE);
3620 gen_helper_pminsn(cpu_env, t);
3621 tcg_temp_free_i32(t);
3622 /* Stop translation, as the CPU is supposed to sleep from now */
3623 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
3624 #endif /* defined(CONFIG_USER_ONLY) */
3625 }
3626
3627 static void gen_nap(DisasContext *ctx)
3628 {
3629 #if defined(CONFIG_USER_ONLY)
3630 GEN_PRIV;
3631 #else
3632 TCGv_i32 t;
3633
3634 CHK_HV;
3635 t = tcg_const_i32(PPC_PM_NAP);
3636 gen_helper_pminsn(cpu_env, t);
3637 tcg_temp_free_i32(t);
3638 /* Stop translation, as the CPU is supposed to sleep from now */
3639 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
3640 #endif /* defined(CONFIG_USER_ONLY) */
3641 }
3642
3643 static void gen_stop(DisasContext *ctx)
3644 {
3645 #if defined(CONFIG_USER_ONLY)
3646 GEN_PRIV;
3647 #else
3648 TCGv_i32 t;
3649
3650 CHK_HV;
3651 t = tcg_const_i32(PPC_PM_STOP);
3652 gen_helper_pminsn(cpu_env, t);
3653 tcg_temp_free_i32(t);
3654 /* Stop translation, as the CPU is supposed to sleep from now */
3655 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
3656 #endif /* defined(CONFIG_USER_ONLY) */
3657 }
3658
3659 static void gen_sleep(DisasContext *ctx)
3660 {
3661 #if defined(CONFIG_USER_ONLY)
3662 GEN_PRIV;
3663 #else
3664 TCGv_i32 t;
3665
3666 CHK_HV;
3667 t = tcg_const_i32(PPC_PM_SLEEP);
3668 gen_helper_pminsn(cpu_env, t);
3669 tcg_temp_free_i32(t);
3670 /* Stop translation, as the CPU is supposed to sleep from now */
3671 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
3672 #endif /* defined(CONFIG_USER_ONLY) */
3673 }
3674
3675 static void gen_rvwinkle(DisasContext *ctx)
3676 {
3677 #if defined(CONFIG_USER_ONLY)
3678 GEN_PRIV;
3679 #else
3680 TCGv_i32 t;
3681
3682 CHK_HV;
3683 t = tcg_const_i32(PPC_PM_RVWINKLE);
3684 gen_helper_pminsn(cpu_env, t);
3685 tcg_temp_free_i32(t);
3686 /* Stop translation, as the CPU is supposed to sleep from now */
3687 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
3688 #endif /* defined(CONFIG_USER_ONLY) */
3689 }
3690 #endif /* #if defined(TARGET_PPC64) */
3691
3692 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3693 {
3694 #if defined(TARGET_PPC64)
3695 if (ctx->has_cfar) {
3696 tcg_gen_movi_tl(cpu_cfar, nip);
3697 }
3698 #endif
3699 }
3700
3701 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
3702 {
3703 if (unlikely(ctx->singlestep_enabled)) {
3704 return false;
3705 }
3706
3707 #ifndef CONFIG_USER_ONLY
3708 return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
3709 #else
3710 return true;
3711 #endif
3712 }
3713
3714 static void gen_lookup_and_goto_ptr(DisasContext *ctx)
3715 {
3716 int sse = ctx->singlestep_enabled;
3717 if (unlikely(sse)) {
3718 if (sse & GDBSTUB_SINGLE_STEP) {
3719 gen_debug_exception(ctx);
3720 } else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) {
3721 uint32_t excp = gen_prep_dbgex(ctx);
3722 gen_exception(ctx, excp);
3723 }
3724 tcg_gen_exit_tb(NULL, 0);
3725 } else {
3726 tcg_gen_lookup_and_goto_ptr();
3727 }
3728 }
3729
3730 /*** Branch ***/
3731 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3732 {
3733 if (NARROW_MODE(ctx)) {
3734 dest = (uint32_t) dest;
3735 }
3736 if (use_goto_tb(ctx, dest)) {
3737 tcg_gen_goto_tb(n);
3738 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3739 tcg_gen_exit_tb(ctx->base.tb, n);
3740 } else {
3741 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3742 gen_lookup_and_goto_ptr(ctx);
3743 }
3744 }
3745
3746 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3747 {
3748 if (NARROW_MODE(ctx)) {
3749 nip = (uint32_t)nip;
3750 }
3751 tcg_gen_movi_tl(cpu_lr, nip);
3752 }
3753
3754 /* b ba bl bla */
3755 static void gen_b(DisasContext *ctx)
3756 {
3757 target_ulong li, target;
3758
3759 ctx->exception = POWERPC_EXCP_BRANCH;
3760 /* sign extend LI */
3761 li = LI(ctx->opcode);
3762 li = (li ^ 0x02000000) - 0x02000000;
3763 if (likely(AA(ctx->opcode) == 0)) {
3764 target = ctx->base.pc_next + li - 4;
3765 } else {
3766 target = li;
3767 }
3768 if (LK(ctx->opcode)) {
3769 gen_setlr(ctx, ctx->base.pc_next);
3770 }
3771 gen_update_cfar(ctx, ctx->base.pc_next - 4);
3772 gen_goto_tb(ctx, 0, target);
3773 }
3774
3775 #define BCOND_IM 0
3776 #define BCOND_LR 1
3777 #define BCOND_CTR 2
3778 #define BCOND_TAR 3
3779
3780 static void gen_bcond(DisasContext *ctx, int type)
3781 {
3782 uint32_t bo = BO(ctx->opcode);
3783 TCGLabel *l1;
3784 TCGv target;
3785 ctx->exception = POWERPC_EXCP_BRANCH;
3786
3787 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3788 target = tcg_temp_local_new();
3789 if (type == BCOND_CTR) {
3790 tcg_gen_mov_tl(target, cpu_ctr);
3791 } else if (type == BCOND_TAR) {
3792 gen_load_spr(target, SPR_TAR);
3793 } else {
3794 tcg_gen_mov_tl(target, cpu_lr);
3795 }
3796 } else {
3797 target = NULL;
3798 }
3799 if (LK(ctx->opcode)) {
3800 gen_setlr(ctx, ctx->base.pc_next);
3801 }
3802 l1 = gen_new_label();
3803 if ((bo & 0x4) == 0) {
3804 /* Decrement and test CTR */
3805 TCGv temp = tcg_temp_new();
3806
3807 if (type == BCOND_CTR) {
3808 /*
3809 * All ISAs up to v3 describe this form of bcctr as invalid but
3810 * some processors, ie. 64-bit server processors compliant with
3811 * arch 2.x, do implement a "test and decrement" logic instead,
3812 * as described in their respective UMs. This logic involves CTR
3813 * to act as both the branch target and a counter, which makes
3814 * it basically useless and thus never used in real code.
3815 *
3816 * This form was hence chosen to trigger extra micro-architectural
3817 * side-effect on real HW needed for the Spectre v2 workaround.
3818 * It is up to guests that implement such workaround, ie. linux, to
3819 * use this form in a way it just triggers the side-effect without
3820 * doing anything else harmful.
3821 */
3822 if (unlikely(!is_book3s_arch2x(ctx))) {
3823 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3824 tcg_temp_free(temp);
3825 tcg_temp_free(target);
3826 return;
3827 }
3828
3829 if (NARROW_MODE(ctx)) {
3830 tcg_gen_ext32u_tl(temp, cpu_ctr);
3831 } else {
3832 tcg_gen_mov_tl(temp, cpu_ctr);
3833 }
3834 if (bo & 0x2) {
3835 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3836 } else {
3837 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3838 }
3839 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3840 } else {
3841 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3842 if (NARROW_MODE(ctx)) {
3843 tcg_gen_ext32u_tl(temp, cpu_ctr);
3844 } else {
3845 tcg_gen_mov_tl(temp, cpu_ctr);
3846 }
3847 if (bo & 0x2) {
3848 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3849 } else {
3850 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3851 }
3852 }
3853 tcg_temp_free(temp);
3854 }
3855 if ((bo & 0x10) == 0) {
3856 /* Test CR */
3857 uint32_t bi = BI(ctx->opcode);
3858 uint32_t mask = 0x08 >> (bi & 0x03);
3859 TCGv_i32 temp = tcg_temp_new_i32();
3860
3861 if (bo & 0x8) {
3862 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3863 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3864 } else {
3865 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3866 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3867 }
3868 tcg_temp_free_i32(temp);
3869 }
3870 gen_update_cfar(ctx, ctx->base.pc_next - 4);
3871 if (type == BCOND_IM) {
3872 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3873 if (likely(AA(ctx->opcode) == 0)) {
3874 gen_goto_tb(ctx, 0, ctx->base.pc_next + li - 4);
3875 } else {
3876 gen_goto_tb(ctx, 0, li);
3877 }
3878 } else {
3879 if (NARROW_MODE(ctx)) {
3880 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3881 } else {
3882 tcg_gen_andi_tl(cpu_nip, target, ~3);
3883 }
3884 gen_lookup_and_goto_ptr(ctx);
3885 tcg_temp_free(target);
3886 }
3887 if ((bo & 0x14) != 0x14) {
3888 /* fallthrough case */
3889 gen_set_label(l1);
3890 gen_goto_tb(ctx, 1, ctx->base.pc_next);
3891 }
3892 }
3893
3894 static void gen_bc(DisasContext *ctx)
3895 {
3896 gen_bcond(ctx, BCOND_IM);
3897 }
3898
3899 static void gen_bcctr(DisasContext *ctx)
3900 {
3901 gen_bcond(ctx, BCOND_CTR);
3902 }
3903
3904 static void gen_bclr(DisasContext *ctx)
3905 {
3906 gen_bcond(ctx, BCOND_LR);
3907 }
3908
3909 static void gen_bctar(DisasContext *ctx)
3910 {
3911 gen_bcond(ctx, BCOND_TAR);
3912 }
3913
3914 /*** Condition register logical ***/
3915 #define GEN_CRLOGIC(name, tcg_op, opc) \
3916 static void glue(gen_, name)(DisasContext *ctx) \
3917 { \
3918 uint8_t bitmask; \
3919 int sh; \
3920 TCGv_i32 t0, t1; \
3921 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3922 t0 = tcg_temp_new_i32(); \
3923 if (sh > 0) \
3924 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3925 else if (sh < 0) \
3926 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3927 else \
3928 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3929 t1 = tcg_temp_new_i32(); \
3930 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3931 if (sh > 0) \
3932 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3933 else if (sh < 0) \
3934 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3935 else \
3936 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3937 tcg_op(t0, t0, t1); \
3938 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
3939 tcg_gen_andi_i32(t0, t0, bitmask); \
3940 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3941 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3942 tcg_temp_free_i32(t0); \
3943 tcg_temp_free_i32(t1); \
3944 }
3945
3946 /* crand */
3947 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3948 /* crandc */
3949 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3950 /* creqv */
3951 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3952 /* crnand */
3953 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3954 /* crnor */
3955 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3956 /* cror */
3957 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3958 /* crorc */
3959 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3960 /* crxor */
3961 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3962
3963 /* mcrf */
3964 static void gen_mcrf(DisasContext *ctx)
3965 {
3966 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3967 }
3968
3969 /*** System linkage ***/
3970
3971 /* rfi (supervisor only) */
3972 static void gen_rfi(DisasContext *ctx)
3973 {
3974 #if defined(CONFIG_USER_ONLY)
3975 GEN_PRIV;
3976 #else
3977 /*
3978 * This instruction doesn't exist anymore on 64-bit server
3979 * processors compliant with arch 2.x
3980 */
3981 if (is_book3s_arch2x(ctx)) {
3982 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3983 return;
3984 }
3985 /* Restore CPU state */
3986 CHK_SV;
3987 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
3988 gen_io_start();
3989 }
3990 gen_update_cfar(ctx, ctx->base.pc_next - 4);
3991 gen_helper_rfi(cpu_env);
3992 gen_sync_exception(ctx);
3993 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
3994 gen_io_end();
3995 }
3996 #endif
3997 }
3998
3999 #if defined(TARGET_PPC64)
4000 static void gen_rfid(DisasContext *ctx)
4001 {
4002 #if defined(CONFIG_USER_ONLY)
4003 GEN_PRIV;
4004 #else
4005 /* Restore CPU state */
4006 CHK_SV;
4007 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
4008 gen_io_start();
4009 }
4010 gen_update_cfar(ctx, ctx->base.pc_next - 4);
4011 gen_helper_rfid(cpu_env);
4012 gen_sync_exception(ctx);
4013 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
4014 gen_io_end();
4015 }
4016 #endif
4017 }
4018
4019 static void gen_hrfid(DisasContext *ctx)
4020 {
4021 #if defined(CONFIG_USER_ONLY)
4022 GEN_PRIV;
4023 #else
4024 /* Restore CPU state */
4025 CHK_HV;
4026 gen_helper_hrfid(cpu_env);
4027 gen_sync_exception(ctx);
4028 #endif
4029 }
4030 #endif
4031
4032 /* sc */
4033 #if defined(CONFIG_USER_ONLY)
4034 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4035 #else
4036 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4037 #endif
4038 static void gen_sc(DisasContext *ctx)
4039 {
4040 uint32_t lev;
4041
4042 lev = (ctx->opcode >> 5) & 0x7F;
4043 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
4044 }
4045
4046 /*** Trap ***/
4047
4048 /* Check for unconditional traps (always or never) */
4049 static bool check_unconditional_trap(DisasContext *ctx)
4050 {
4051 /* Trap never */
4052 if (TO(ctx->opcode) == 0) {
4053 return true;
4054 }
4055 /* Trap always */
4056 if (TO(ctx->opcode) == 31) {
4057 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
4058 return true;
4059 }
4060 return false;
4061 }
4062
4063 /* tw */
4064 static void gen_tw(DisasContext *ctx)
4065 {
4066 TCGv_i32 t0;
4067
4068 if (check_unconditional_trap(ctx)) {
4069 return;
4070 }
4071 t0 = tcg_const_i32(TO(ctx->opcode));
4072 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4073 t0);
4074 tcg_temp_free_i32(t0);
4075 }
4076
4077 /* twi */
4078 static void gen_twi(DisasContext *ctx)
4079 {
4080 TCGv t0;
4081 TCGv_i32 t1;
4082
4083 if (check_unconditional_trap(ctx)) {
4084 return;
4085 }
4086 t0 = tcg_const_tl(SIMM(ctx->opcode));
4087 t1 = tcg_const_i32(TO(ctx->opcode));
4088 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4089 tcg_temp_free(t0);
4090 tcg_temp_free_i32(t1);
4091 }
4092
4093 #if defined(TARGET_PPC64)
4094 /* td */
4095 static void gen_td(DisasContext *ctx)
4096 {
4097 TCGv_i32 t0;
4098
4099 if (check_unconditional_trap(ctx)) {
4100 return;
4101 }
4102 t0 = tcg_const_i32(TO(ctx->opcode));
4103 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4104 t0);
4105 tcg_temp_free_i32(t0);
4106 }
4107
4108 /* tdi */
4109 static void gen_tdi(DisasContext *ctx)
4110 {
4111 TCGv t0;
4112 TCGv_i32 t1;
4113
4114 if (check_unconditional_trap(ctx)) {
4115 return;
4116 }
4117 t0 = tcg_const_tl(SIMM(ctx->opcode));
4118 t1 = tcg_const_i32(TO(ctx->opcode));
4119 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4120 tcg_temp_free(t0);
4121 tcg_temp_free_i32(t1);
4122 }
4123 #endif
4124
4125 /*** Processor control ***/
4126
4127 static void gen_read_xer(DisasContext *ctx, TCGv dst)
4128 {
4129 TCGv t0 = tcg_temp_new();
4130 TCGv t1 = tcg_temp_new();
4131 TCGv t2 = tcg_temp_new();
4132 tcg_gen_mov_tl(dst, cpu_xer);
4133 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
4134 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
4135 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
4136 tcg_gen_or_tl(t0, t0, t1);
4137 tcg_gen_or_tl(dst, dst, t2);
4138 tcg_gen_or_tl(dst, dst, t0);
4139 if (is_isa300(ctx)) {
4140 tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32);
4141 tcg_gen_or_tl(dst, dst, t0);
4142 tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32);
4143 tcg_gen_or_tl(dst, dst, t0);
4144 }
4145 tcg_temp_free(t0);
4146 tcg_temp_free(t1);
4147 tcg_temp_free(t2);
4148 }
4149
4150 static void gen_write_xer(TCGv src)
4151 {
4152 /* Write all flags, while reading back check for isa300 */
4153 tcg_gen_andi_tl(cpu_xer, src,
4154 ~((1u << XER_SO) |
4155 (1u << XER_OV) | (1u << XER_OV32) |
4156 (1u << XER_CA) | (1u << XER_CA32)));
4157 tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1);
4158 tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1);
4159 tcg_gen_extract_tl(cpu_so, src, XER_SO, 1);
4160 tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1);
4161 tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1);
4162 }
4163
4164 /* mcrxr */
4165 static void gen_mcrxr(DisasContext *ctx)
4166 {
4167 TCGv_i32 t0 = tcg_temp_new_i32();
4168 TCGv_i32 t1 = tcg_temp_new_i32();
4169 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4170
4171 tcg_gen_trunc_tl_i32(t0, cpu_so);
4172 tcg_gen_trunc_tl_i32(t1, cpu_ov);
4173 tcg_gen_trunc_tl_i32(dst, cpu_ca);
4174 tcg_gen_shli_i32(t0, t0, 3);
4175 tcg_gen_shli_i32(t1, t1, 2);
4176 tcg_gen_shli_i32(dst, dst, 1);
4177 tcg_gen_or_i32(dst, dst, t0);
4178 tcg_gen_or_i32(dst, dst, t1);
4179 tcg_temp_free_i32(t0);
4180 tcg_temp_free_i32(t1);
4181
4182 tcg_gen_movi_tl(cpu_so, 0);
4183 tcg_gen_movi_tl(cpu_ov, 0);
4184 tcg_gen_movi_tl(cpu_ca, 0);
4185 }
4186
4187 #ifdef TARGET_PPC64
4188 /* mcrxrx */
4189 static void gen_mcrxrx(DisasContext *ctx)
4190 {
4191 TCGv t0 = tcg_temp_new();
4192 TCGv t1 = tcg_temp_new();
4193 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4194
4195 /* copy OV and OV32 */
4196 tcg_gen_shli_tl(t0, cpu_ov, 1);
4197 tcg_gen_or_tl(t0, t0, cpu_ov32);
4198 tcg_gen_shli_tl(t0, t0, 2);
4199 /* copy CA and CA32 */
4200 tcg_gen_shli_tl(t1, cpu_ca, 1);
4201 tcg_gen_or_tl(t1, t1, cpu_ca32);
4202 tcg_gen_or_tl(t0, t0, t1);
4203 tcg_gen_trunc_tl_i32(dst, t0);
4204 tcg_temp_free(t0);
4205 tcg_temp_free(t1);
4206 }
4207 #endif
4208
4209 /* mfcr mfocrf */
4210 static void gen_mfcr(DisasContext *ctx)
4211 {
4212 uint32_t crm, crn;
4213
4214 if (likely(ctx->opcode & 0x00100000)) {
4215 crm = CRM(ctx->opcode);
4216 if (likely(crm && ((crm & (crm - 1)) == 0))) {
4217 crn = ctz32(crm);
4218 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
4219 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4220 cpu_gpr[rD(ctx->opcode)], crn * 4);
4221 }
4222 } else {
4223 TCGv_i32 t0 = tcg_temp_new_i32();
4224 tcg_gen_mov_i32(t0, cpu_crf[0]);
4225 tcg_gen_shli_i32(t0, t0, 4);
4226 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4227 tcg_gen_shli_i32(t0, t0, 4);
4228 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4229 tcg_gen_shli_i32(t0, t0, 4);
4230 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4231 tcg_gen_shli_i32(t0, t0, 4);
4232 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4233 tcg_gen_shli_i32(t0, t0, 4);
4234 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4235 tcg_gen_shli_i32(t0, t0, 4);
4236 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4237 tcg_gen_shli_i32(t0, t0, 4);
4238 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4239 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4240 tcg_temp_free_i32(t0);
4241 }
4242 }
4243
4244 /* mfmsr */
4245 static void gen_mfmsr(DisasContext *ctx)
4246 {
4247 CHK_SV;
4248 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
4249 }
4250
4251 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
4252 {
4253 #if 0
4254 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
4255 printf("ERROR: try to access SPR %d !\n", sprn);
4256 #endif
4257 }
4258 #define SPR_NOACCESS (&spr_noaccess)
4259
4260 /* mfspr */
4261 static inline void gen_op_mfspr(DisasContext *ctx)
4262 {
4263 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
4264 uint32_t sprn = SPR(ctx->opcode);
4265
4266 #if defined(CONFIG_USER_ONLY)
4267 read_cb = ctx->spr_cb[sprn].uea_read;
4268 #else
4269 if (ctx->pr) {
4270 read_cb = ctx->spr_cb[sprn].uea_read;
4271 } else if (ctx->hv) {
4272 read_cb = ctx->spr_cb[sprn].hea_read;
4273 } else {
4274 read_cb = ctx->spr_cb[sprn].oea_read;
4275 }
4276 #endif
4277 if (likely(read_cb != NULL)) {
4278 if (likely(read_cb != SPR_NOACCESS)) {
4279 (*read_cb)(ctx, rD(ctx->opcode), sprn);
4280 } else {
4281 /* Privilege exception */
4282 /*
4283 * This is a hack to avoid warnings when running Linux:
4284 * this OS breaks the PowerPC virtualisation model,
4285 * allowing userland application to read the PVR
4286 */
4287 if (sprn != SPR_PVR) {
4288 qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr "
4289 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn,
4290 ctx->base.pc_next - 4);
4291 }
4292 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4293 }
4294 } else {
4295 /* ISA 2.07 defines these as no-ops */
4296 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
4297 (sprn >= 808 && sprn <= 811)) {
4298 /* This is a nop */
4299 return;
4300 }
4301 /* Not defined */
4302 qemu_log_mask(LOG_GUEST_ERROR,
4303 "Trying to read invalid spr %d (0x%03x) at "
4304 TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4);
4305
4306 /*
4307 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can
4308 * generate a priv, a hv emu or a no-op
4309 */
4310 if (sprn & 0x10) {
4311 if (ctx->pr) {
4312 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4313 }
4314 } else {
4315 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) {
4316 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4317 }
4318 }
4319 }
4320 }
4321
4322 static void gen_mfspr(DisasContext *ctx)
4323 {
4324 gen_op_mfspr(ctx);
4325 }
4326
4327 /* mftb */
4328 static void gen_mftb(DisasContext *ctx)
4329 {
4330 gen_op_mfspr(ctx);
4331 }
4332
4333 /* mtcrf mtocrf*/
4334 static void gen_mtcrf(DisasContext *ctx)
4335 {
4336 uint32_t crm, crn;
4337
4338 crm = CRM(ctx->opcode);
4339 if (likely((ctx->opcode & 0x00100000))) {
4340 if (crm && ((crm & (crm - 1)) == 0)) {
4341 TCGv_i32 temp = tcg_temp_new_i32();
4342 crn = ctz32(crm);
4343 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4344 tcg_gen_shri_i32(temp, temp, crn * 4);
4345 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4346 tcg_temp_free_i32(temp);
4347 }
4348 } else {
4349 TCGv_i32 temp = tcg_temp_new_i32();
4350 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4351 for (crn = 0 ; crn < 8 ; crn++) {
4352 if (crm & (1 << crn)) {
4353 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4354 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4355 }
4356 }
4357 tcg_temp_free_i32(temp);
4358 }
4359 }
4360
4361 /* mtmsr */
4362 #if defined(TARGET_PPC64)
4363 static void gen_mtmsrd(DisasContext *ctx)
4364 {
4365 CHK_SV;
4366
4367 #if !defined(CONFIG_USER_ONLY)
4368 if (ctx->opcode & 0x00010000) {
4369 /* Special form that does not need any synchronisation */
4370 TCGv t0 = tcg_temp_new();
4371 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)],
4372 (1 << MSR_RI) | (1 << MSR_EE));
4373 tcg_gen_andi_tl(cpu_msr, cpu_msr,
4374 ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
4375 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4376 tcg_temp_free(t0);
4377 } else {
4378 /*
4379 * XXX: we need to update nip before the store if we enter
4380 * power saving mode, we will exit the loop directly from
4381 * ppc_store_msr
4382 */
4383 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
4384 gen_io_start();
4385 }
4386 gen_update_nip(ctx, ctx->base.pc_next);
4387 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4388 /* Must stop the translation as machine state (may have) changed */
4389 /* Note that mtmsr is not always defined as context-synchronizing */
4390 gen_stop_exception(ctx);
4391 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
4392 gen_io_end();
4393 }
4394 }
4395 #endif /* !defined(CONFIG_USER_ONLY) */
4396 }
4397 #endif /* defined(TARGET_PPC64) */
4398
4399 static void gen_mtmsr(DisasContext *ctx)
4400 {
4401 CHK_SV;
4402
4403 #if !defined(CONFIG_USER_ONLY)
4404 if (ctx->opcode & 0x00010000) {
4405 /* Special form that does not need any synchronisation */
4406 TCGv t0 = tcg_temp_new();
4407 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)],
4408 (1 << MSR_RI) | (1 << MSR_EE));
4409 tcg_gen_andi_tl(cpu_msr, cpu_msr,
4410 ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
4411 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4412 tcg_temp_free(t0);
4413 } else {
4414 TCGv msr = tcg_temp_new();
4415
4416 /*
4417 * XXX: we need to update nip before the store if we enter
4418 * power saving mode, we will exit the loop directly from
4419 * ppc_store_msr
4420 */
4421 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
4422 gen_io_start();
4423 }
4424 gen_update_nip(ctx, ctx->base.pc_next);
4425 #if defined(TARGET_PPC64)
4426 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4427 #else
4428 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4429 #endif
4430 gen_helper_store_msr(cpu_env, msr);
4431 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
4432 gen_io_end();
4433 }
4434 tcg_temp_free(msr);
4435 /* Must stop the translation as machine state (may have) changed */
4436 /* Note that mtmsr is not always defined as context-synchronizing */
4437 gen_stop_exception(ctx);
4438 }
4439 #endif
4440 }
4441
4442 /* mtspr */
4443 static void gen_mtspr(DisasContext *ctx)
4444 {
4445 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
4446 uint32_t sprn = SPR(ctx->opcode);
4447
4448 #if defined(CONFIG_USER_ONLY)
4449 write_cb = ctx->spr_cb[sprn].uea_write;
4450 #else
4451 if (ctx->pr) {
4452 write_cb = ctx->spr_cb[sprn].uea_write;
4453 } else if (ctx->hv) {
4454 write_cb = ctx->spr_cb[sprn].hea_write;
4455 } else {
4456 write_cb = ctx->spr_cb[sprn].oea_write;
4457 }
4458 #endif
4459 if (likely(write_cb != NULL)) {
4460 if (likely(write_cb != SPR_NOACCESS)) {
4461 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4462 } else {
4463 /* Privilege exception */
4464 qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr "
4465 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn,
4466 ctx->base.pc_next - 4);
4467 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4468 }
4469 } else {
4470 /* ISA 2.07 defines these as no-ops */
4471 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
4472 (sprn >= 808 && sprn <= 811)) {
4473 /* This is a nop */
4474 return;
4475 }
4476
4477 /* Not defined */
4478 qemu_log_mask(LOG_GUEST_ERROR,
4479 "Trying to write invalid spr %d (0x%03x) at "
4480 TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4);
4481
4482
4483 /*
4484 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can
4485 * generate a priv, a hv emu or a no-op
4486 */
4487 if (sprn & 0x10) {
4488 if (ctx->pr) {
4489 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4490 }
4491 } else {
4492 if (ctx->pr || sprn == 0) {
4493 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4494 }
4495 }
4496 }
4497 }
4498
4499 #if defined(TARGET_PPC64)
4500 /* setb */
4501 static void gen_setb(DisasContext *ctx)
4502 {
4503 TCGv_i32 t0 = tcg_temp_new_i32();
4504 TCGv_i32 t8 = tcg_temp_new_i32();
4505 TCGv_i32 tm1 = tcg_temp_new_i32();
4506 int crf = crfS(ctx->opcode);
4507
4508 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4);
4509 tcg_gen_movi_i32(t8, 8);
4510 tcg_gen_movi_i32(tm1, -1);
4511 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0);
4512 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4513
4514 tcg_temp_free_i32(t0);
4515 tcg_temp_free_i32(t8);
4516 tcg_temp_free_i32(tm1);
4517 }
4518 #endif
4519
4520 /*** Cache management ***/
4521
4522 /* dcbf */
4523 static void gen_dcbf(DisasContext *ctx)
4524 {
4525 /* XXX: specification says this is treated as a load by the MMU */
4526 TCGv t0;
4527 gen_set_access_type(ctx, ACCESS_CACHE);
4528 t0 = tcg_temp_new();
4529 gen_addr_reg_index(ctx, t0);
4530 gen_qemu_ld8u(ctx, t0, t0);
4531 tcg_temp_free(t0);
4532 }
4533
4534 /* dcbfep (external PID dcbf) */
4535 static void gen_dcbfep(DisasContext *ctx)
4536 {
4537 /* XXX: specification says this is treated as a load by the MMU */
4538 TCGv t0;
4539 CHK_SV;
4540 gen_set_access_type(ctx, ACCESS_CACHE);
4541 t0 = tcg_temp_new();
4542 gen_addr_reg_index(ctx, t0);
4543 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB));
4544 tcg_temp_free(t0);
4545 }
4546
4547 /* dcbi (Supervisor only) */
4548 static void gen_dcbi(DisasContext *ctx)
4549 {
4550 #if defined(CONFIG_USER_ONLY)
4551 GEN_PRIV;
4552 #else
4553 TCGv EA, val;
4554
4555 CHK_SV;
4556 EA = tcg_temp_new();
4557 gen_set_access_type(ctx, ACCESS_CACHE);
4558 gen_addr_reg_index(ctx, EA);
4559 val = tcg_temp_new();
4560 /* XXX: specification says this should be treated as a store by the MMU */
4561 gen_qemu_ld8u(ctx, val, EA);
4562 gen_qemu_st8(ctx, val, EA);
4563 tcg_temp_free(val);
4564 tcg_temp_free(EA);
4565 #endif /* defined(CONFIG_USER_ONLY) */
4566 }
4567
4568 /* dcdst */
4569 static void gen_dcbst(DisasContext *ctx)
4570 {
4571 /* XXX: specification say this is treated as a load by the MMU */
4572 TCGv t0;
4573 gen_set_access_type(ctx, ACCESS_CACHE);
4574 t0 = tcg_temp_new();
4575 gen_addr_reg_index(ctx, t0);
4576 gen_qemu_ld8u(ctx, t0, t0);
4577 tcg_temp_free(t0);
4578 }
4579
4580 /* dcbstep (dcbstep External PID version) */
4581 static void gen_dcbstep(DisasContext *ctx)
4582 {
4583 /* XXX: specification say this is treated as a load by the MMU */
4584 TCGv t0;
4585 gen_set_access_type(ctx, ACCESS_CACHE);
4586 t0 = tcg_temp_new();
4587 gen_addr_reg_index(ctx, t0);
4588 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB));
4589 tcg_temp_free(t0);
4590 }
4591
4592 /* dcbt */
4593 static void gen_dcbt(DisasContext *ctx)
4594 {
4595 /*
4596 * interpreted as no-op
4597 * XXX: specification say this is treated as a load by the MMU but
4598 * does not generate any exception
4599 */
4600 }
4601
4602 /* dcbtep */
4603 static void gen_dcbtep(DisasContext *ctx)
4604 {
4605 /*
4606 * interpreted as no-op
4607 * XXX: specification say this is treated as a load by the MMU but
4608 * does not generate any exception
4609 */
4610 }
4611
4612 /* dcbtst */
4613 static void gen_dcbtst(DisasContext *ctx)
4614 {
4615 /*
4616 * interpreted as no-op
4617 * XXX: specification say this is treated as a load by the MMU but
4618 * does not generate any exception
4619 */
4620 }
4621
4622 /* dcbtstep */
4623 static void gen_dcbtstep(DisasContext *ctx)
4624 {
4625 /*
4626 * interpreted as no-op
4627 * XXX: specification say this is treated as a load by the MMU but
4628 * does not generate any exception
4629 */
4630 }
4631
4632 /* dcbtls */
4633 static void gen_dcbtls(DisasContext *ctx)
4634 {
4635 /* Always fails locking the cache */
4636 TCGv t0 = tcg_temp_new();
4637 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4638 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4639 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4640 tcg_temp_free(t0);
4641 }
4642
4643 /* dcbz */
4644 static void gen_dcbz(DisasContext *ctx)
4645 {
4646 TCGv tcgv_addr;
4647 TCGv_i32 tcgv_op;
4648
4649 gen_set_access_type(ctx, ACCESS_CACHE);
4650 tcgv_addr = tcg_temp_new();
4651 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
4652 gen_addr_reg_index(ctx, tcgv_addr);
4653 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op);
4654 tcg_temp_free(tcgv_addr);
4655 tcg_temp_free_i32(tcgv_op);
4656 }
4657
4658 /* dcbzep */
4659 static void gen_dcbzep(DisasContext *ctx)
4660 {
4661 TCGv tcgv_addr;
4662 TCGv_i32 tcgv_op;
4663
4664 gen_set_access_type(ctx, ACCESS_CACHE);
4665 tcgv_addr = tcg_temp_new();
4666 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
4667 gen_addr_reg_index(ctx, tcgv_addr);
4668 gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op);
4669 tcg_temp_free(tcgv_addr);
4670 tcg_temp_free_i32(tcgv_op);
4671 }
4672
4673 /* dst / dstt */
4674 static void gen_dst(DisasContext *ctx)
4675 {
4676 if (rA(ctx->opcode) == 0) {
4677 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4678 } else {
4679 /* interpreted as no-op */
4680 }
4681 }
4682
4683 /* dstst /dststt */
4684 static void gen_dstst(DisasContext *ctx)
4685 {
4686 if (rA(ctx->opcode) == 0) {
4687 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4688 } else {
4689 /* interpreted as no-op */
4690 }
4691
4692 }
4693
4694 /* dss / dssall */
4695 static void gen_dss(DisasContext *ctx)
4696 {
4697 /* interpreted as no-op */
4698 }
4699
4700 /* icbi */
4701 static void gen_icbi(DisasContext *ctx)
4702 {
4703 TCGv t0;
4704 gen_set_access_type(ctx, ACCESS_CACHE);
4705 t0 = tcg_temp_new();
4706 gen_addr_reg_index(ctx, t0);
4707 gen_helper_icbi(cpu_env, t0);
4708 tcg_temp_free(t0);
4709 }
4710
4711 /* icbiep */
4712 static void gen_icbiep(DisasContext *ctx)
4713 {
4714 TCGv t0;
4715 gen_set_access_type(ctx, ACCESS_CACHE);
4716 t0 = tcg_temp_new();
4717 gen_addr_reg_index(ctx, t0);
4718 gen_helper_icbiep(cpu_env, t0);
4719 tcg_temp_free(t0);
4720 }
4721
4722 /* Optional: */
4723 /* dcba */
4724 static void gen_dcba(DisasContext *ctx)
4725 {
4726 /*
4727 * interpreted as no-op
4728 * XXX: specification say this is treated as a store by the MMU
4729 * but does not generate any exception
4730 */
4731 }
4732
4733 /*** Segment register manipulation ***/
4734 /* Supervisor only: */
4735
4736 /* mfsr */
4737 static void gen_mfsr(DisasContext *ctx)
4738 {
4739 #if defined(CONFIG_USER_ONLY)
4740 GEN_PRIV;
4741 #else
4742 TCGv t0;
4743
4744 CHK_SV;
4745 t0 = tcg_const_tl(SR(ctx->opcode));
4746 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4747 tcg_temp_free(t0);
4748 #endif /* defined(CONFIG_USER_ONLY) */
4749 }
4750
4751 /* mfsrin */
4752 static void gen_mfsrin(DisasContext *ctx)
4753 {
4754 #if defined(CONFIG_USER_ONLY)
4755 GEN_PRIV;
4756 #else
4757 TCGv t0;
4758
4759 CHK_SV;
4760 t0 = tcg_temp_new();
4761 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
4762 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4763 tcg_temp_free(t0);
4764 #endif /* defined(CONFIG_USER_ONLY) */
4765 }
4766
4767 /* mtsr */
4768 static void gen_mtsr(DisasContext *ctx)
4769 {
4770 #if defined(CONFIG_USER_ONLY)
4771 GEN_PRIV;
4772 #else
4773 TCGv t0;
4774
4775 CHK_SV;
4776 t0 = tcg_const_tl(SR(ctx->opcode));
4777 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4778 tcg_temp_free(t0);
4779 #endif /* defined(CONFIG_USER_ONLY) */
4780 }
4781
4782 /* mtsrin */
4783 static void gen_mtsrin(DisasContext *ctx)
4784 {
4785 #if defined(CONFIG_USER_ONLY)
4786 GEN_PRIV;
4787 #else
4788 TCGv t0;
4789 CHK_SV;
4790
4791 t0 = tcg_temp_new();
4792 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
4793 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4794 tcg_temp_free(t0);
4795 #endif /* defined(CONFIG_USER_ONLY) */
4796 }
4797
4798 #if defined(TARGET_PPC64)
4799 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4800
4801 /* mfsr */
4802 static void gen_mfsr_64b(DisasContext *ctx)
4803 {
4804 #if defined(CONFIG_USER_ONLY)
4805 GEN_PRIV;
4806 #else
4807 TCGv t0;
4808
4809 CHK_SV;
4810 t0 = tcg_const_tl(SR(ctx->opcode));
4811 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4812 tcg_temp_free(t0);
4813 #endif /* defined(CONFIG_USER_ONLY) */
4814 }
4815
4816 /* mfsrin */
4817 static void gen_mfsrin_64b(DisasContext *ctx)
4818 {
4819 #if defined(CONFIG_USER_ONLY)
4820 GEN_PRIV;
4821 #else
4822 TCGv t0;
4823
4824 CHK_SV;
4825 t0 = tcg_temp_new();
4826 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
4827 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4828 tcg_temp_free(t0);
4829 #endif /* defined(CONFIG_USER_ONLY) */
4830 }
4831
4832 /* mtsr */
4833 static void gen_mtsr_64b(DisasContext *ctx)
4834 {
4835 #if defined(CONFIG_USER_ONLY)
4836 GEN_PRIV;
4837 #else
4838 TCGv t0;
4839
4840 CHK_SV;
4841 t0 = tcg_const_tl(SR(ctx->opcode));
4842 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4843 tcg_temp_free(t0);
4844 #endif /* defined(CONFIG_USER_ONLY) */
4845 }
4846
4847 /* mtsrin */
4848 static void gen_mtsrin_64b(DisasContext *ctx)
4849 {
4850 #if defined(CONFIG_USER_ONLY)
4851 GEN_PRIV;
4852 #else
4853 TCGv t0;
4854
4855 CHK_SV;
4856 t0 = tcg_temp_new();
4857 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
4858 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4859 tcg_temp_free(t0);
4860 #endif /* defined(CONFIG_USER_ONLY) */
4861 }
4862
4863 /* slbmte */
4864 static void gen_slbmte(DisasContext *ctx)
4865 {
4866 #if defined(CONFIG_USER_ONLY)
4867 GEN_PRIV;
4868 #else
4869 CHK_SV;
4870
4871 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4872 cpu_gpr[rS(ctx->opcode)]);
4873 #endif /* defined(CONFIG_USER_ONLY) */
4874 }
4875
4876 static void gen_slbmfee(DisasContext *ctx)
4877 {
4878 #if defined(CONFIG_USER_ONLY)
4879 GEN_PRIV;
4880 #else
4881 CHK_SV;
4882
4883 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4884 cpu_gpr[rB(ctx->opcode)]);
4885 #endif /* defined(CONFIG_USER_ONLY) */
4886 }
4887
4888 static void gen_slbmfev(DisasContext *ctx)
4889 {
4890 #if defined(CONFIG_USER_ONLY)
4891 GEN_PRIV;
4892 #else
4893 CHK_SV;
4894
4895 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4896 cpu_gpr[rB(ctx->opcode)]);
4897 #endif /* defined(CONFIG_USER_ONLY) */
4898 }
4899
4900 static void gen_slbfee_(DisasContext *ctx)
4901 {
4902 #if defined(CONFIG_USER_ONLY)
4903 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4904 #else
4905 TCGLabel *l1, *l2;
4906
4907 if (unlikely(ctx->pr)) {
4908 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4909 return;
4910 }
4911 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4912 cpu_gpr[rB(ctx->opcode)]);
4913 l1 = gen_new_label();
4914 l2 = gen_new_label();
4915 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
4916 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
4917 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
4918 tcg_gen_br(l2);
4919 gen_set_label(l1);
4920 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
4921 gen_set_label(l2);
4922 #endif
4923 }
4924 #endif /* defined(TARGET_PPC64) */
4925
4926 /*** Lookaside buffer management ***/
4927 /* Optional & supervisor only: */
4928
4929 /* tlbia */
4930 static void gen_tlbia(DisasContext *ctx)
4931 {
4932 #if defined(CONFIG_USER_ONLY)
4933 GEN_PRIV;
4934 #else
4935 CHK_HV;
4936
4937 gen_helper_tlbia(cpu_env);
4938 #endif /* defined(CONFIG_USER_ONLY) */
4939 }
4940
4941 /* tlbiel */
4942 static void gen_tlbiel(DisasContext *ctx)
4943 {
4944 #if defined(CONFIG_USER_ONLY)
4945 GEN_PRIV;
4946 #else
4947 CHK_SV;
4948
4949 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4950 #endif /* defined(CONFIG_USER_ONLY) */
4951 }
4952
4953 /* tlbie */
4954 static void gen_tlbie(DisasContext *ctx)
4955 {
4956 #if defined(CONFIG_USER_ONLY)
4957 GEN_PRIV;
4958 #else
4959 TCGv_i32 t1;
4960
4961 if (ctx->gtse) {
4962 CHK_SV; /* If gtse is set then tlbie is supervisor privileged */
4963 } else {
4964 CHK_HV; /* Else hypervisor privileged */
4965 }
4966
4967 if (NARROW_MODE(ctx)) {
4968 TCGv t0 = tcg_temp_new();
4969 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4970 gen_helper_tlbie(cpu_env, t0);
4971 tcg_temp_free(t0);
4972 } else {
4973 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4974 }
4975 t1 = tcg_temp_new_i32();
4976 tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
4977 tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH);
4978 tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
4979 tcg_temp_free_i32(t1);
4980 #endif /* defined(CONFIG_USER_ONLY) */
4981 }
4982
4983 /* tlbsync */
4984 static void gen_tlbsync(DisasContext *ctx)
4985 {
4986 #if defined(CONFIG_USER_ONLY)
4987 GEN_PRIV;
4988 #else
4989
4990 if (ctx->gtse) {
4991 CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */
4992 } else {
4993 CHK_HV; /* Else hypervisor privileged */
4994 }
4995
4996 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */
4997 if (ctx->insns_flags & PPC_BOOKE) {
4998 gen_check_tlb_flush(ctx, true);
4999 }
5000 #endif /* defined(CONFIG_USER_ONLY) */
5001 }
5002
5003 #if defined(TARGET_PPC64)
5004 /* slbia */
5005 static void gen_slbia(DisasContext *ctx)
5006 {
5007 #if defined(CONFIG_USER_ONLY)
5008 GEN_PRIV;
5009 #else
5010 CHK_SV;
5011
5012 gen_helper_slbia(cpu_env);
5013 #endif /* defined(CONFIG_USER_ONLY) */
5014 }
5015
5016 /* slbie */
5017 static void gen_slbie(DisasContext *ctx)
5018 {
5019 #if defined(CONFIG_USER_ONLY)
5020 GEN_PRIV;
5021 #else
5022 CHK_SV;
5023
5024 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5025 #endif /* defined(CONFIG_USER_ONLY) */
5026 }
5027
5028 /* slbieg */
5029 static void gen_slbieg(DisasContext *ctx)
5030 {
5031 #if defined(CONFIG_USER_ONLY)
5032 GEN_PRIV;
5033 #else
5034 CHK_SV;
5035
5036 gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5037 #endif /* defined(CONFIG_USER_ONLY) */
5038 }
5039
5040 /* slbsync */
5041 static void gen_slbsync(DisasContext *ctx)
5042 {
5043 #if defined(CONFIG_USER_ONLY)
5044 GEN_PRIV;
5045 #else
5046 CHK_SV;
5047 gen_check_tlb_flush(ctx, true);
5048 #endif /* defined(CONFIG_USER_ONLY) */
5049 }
5050
5051 #endif /* defined(TARGET_PPC64) */
5052
5053 /*** External control ***/
5054 /* Optional: */
5055
5056 /* eciwx */
5057 static void gen_eciwx(DisasContext *ctx)
5058 {
5059 TCGv t0;
5060 /* Should check EAR[E] ! */
5061 gen_set_access_type(ctx, ACCESS_EXT);
5062 t0 = tcg_temp_new();
5063 gen_addr_reg_index(ctx, t0);
5064 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx,
5065 DEF_MEMOP(MO_UL | MO_ALIGN));
5066 tcg_temp_free(t0);
5067 }
5068
5069 /* ecowx */
5070 static void gen_ecowx(DisasContext *ctx)
5071 {
5072 TCGv t0;
5073 /* Should check EAR[E] ! */
5074 gen_set_access_type(ctx, ACCESS_EXT);
5075 t0 = tcg_temp_new();
5076 gen_addr_reg_index(ctx, t0);
5077 tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx,
5078 DEF_MEMOP(MO_UL | MO_ALIGN));
5079 tcg_temp_free(t0);
5080 }
5081
5082 /* PowerPC 601 specific instructions */
5083
5084 /* abs - abs. */
5085 static void gen_abs(DisasContext *ctx)
5086 {
5087 TCGv d = cpu_gpr[rD(ctx->opcode)];
5088 TCGv a = cpu_gpr[rA(ctx->opcode)];
5089
5090 tcg_gen_abs_tl(d, a);
5091 if (unlikely(Rc(ctx->opcode) != 0)) {
5092 gen_set_Rc0(ctx, d);
5093 }
5094 }
5095
5096 /* abso - abso. */
5097 static void gen_abso(DisasContext *ctx)
5098 {
5099 TCGv d = cpu_gpr[rD(ctx->opcode)];
5100 TCGv a = cpu_gpr[rA(ctx->opcode)];
5101
5102 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_ov, a, 0x80000000);
5103 tcg_gen_abs_tl(d, a);
5104 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
5105 if (unlikely(Rc(ctx->opcode) != 0)) {
5106 gen_set_Rc0(ctx, d);
5107 }
5108 }
5109
5110 /* clcs */
5111 static void gen_clcs(DisasContext *ctx)
5112 {
5113 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
5114 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5115 tcg_temp_free_i32(t0);
5116 /* Rc=1 sets CR0 to an undefined state */
5117 }
5118
5119 /* div - div. */
5120 static void gen_div(DisasContext *ctx)
5121 {
5122 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5123 cpu_gpr[rB(ctx->opcode)]);
5124 if (unlikely(Rc(ctx->opcode) != 0)) {
5125 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5126 }
5127 }
5128
5129 /* divo - divo. */
5130 static void gen_divo(DisasContext *ctx)
5131 {
5132 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5133 cpu_gpr[rB(ctx->opcode)]);
5134 if (unlikely(Rc(ctx->opcode) != 0)) {
5135 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5136 }
5137 }
5138
5139 /* divs - divs. */
5140 static void gen_divs(DisasContext *ctx)
5141 {
5142 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5143 cpu_gpr[rB(ctx->opcode)]);
5144 if (unlikely(Rc(ctx->opcode) != 0)) {
5145 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5146 }
5147 }
5148
5149 /* divso - divso. */
5150 static void gen_divso(DisasContext *ctx)
5151 {
5152 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
5153 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5154 if (unlikely(Rc(ctx->opcode) != 0)) {
5155 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5156 }
5157 }
5158
5159 /* doz - doz. */
5160 static void gen_doz(DisasContext *ctx)
5161 {
5162 TCGLabel *l1 = gen_new_label();
5163 TCGLabel *l2 = gen_new_label();
5164 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)],
5165 cpu_gpr[rA(ctx->opcode)], l1);
5166 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
5167 cpu_gpr[rA(ctx->opcode)]);
5168 tcg_gen_br(l2);
5169 gen_set_label(l1);
5170 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5171 gen_set_label(l2);
5172 if (unlikely(Rc(ctx->opcode) != 0)) {
5173 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5174 }
5175 }
5176
5177 /* dozo - dozo. */
5178 static void gen_dozo(DisasContext *ctx)
5179 {
5180 TCGLabel *l1 = gen_new_label();
5181 TCGLabel *l2 = gen_new_label();
5182 TCGv t0 = tcg_temp_new();
5183 TCGv t1 = tcg_temp_new();
5184 TCGv t2 = tcg_temp_new();
5185 /* Start with XER OV disabled, the most likely case */
5186 tcg_gen_movi_tl(cpu_ov, 0);
5187 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)],
5188 cpu_gpr[rA(ctx->opcode)], l1);
5189 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5190 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5191 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
5192 tcg_gen_andc_tl(t1, t1, t2);
5193 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
5194 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5195 tcg_gen_movi_tl(cpu_ov, 1);
5196 tcg_gen_movi_tl(cpu_so, 1);
5197 tcg_gen_br(l2);
5198 gen_set_label(l1);
5199 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5200 gen_set_label(l2);
5201 tcg_temp_free(t0);
5202 tcg_temp_free(t1);
5203 tcg_temp_free(t2);
5204 if (unlikely(Rc(ctx->opcode) != 0)) {
5205 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5206 }
5207 }
5208
5209 /* dozi */
5210 static void gen_dozi(DisasContext *ctx)
5211 {
5212 target_long simm = SIMM(ctx->opcode);
5213 TCGLabel *l1 = gen_new_label();
5214 TCGLabel *l2 = gen_new_label();
5215 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
5216 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
5217 tcg_gen_br(l2);
5218 gen_set_label(l1);
5219 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5220 gen_set_label(l2);
5221 if (unlikely(Rc(ctx->opcode) != 0)) {
5222 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5223 }
5224 }
5225
5226 /* lscbx - lscbx. */
5227 static void gen_lscbx(DisasContext *ctx)
5228 {
5229 TCGv t0 = tcg_temp_new();
5230 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
5231 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
5232 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
5233
5234 gen_addr_reg_index(ctx, t0);
5235 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
5236 tcg_temp_free_i32(t1);
5237 tcg_temp_free_i32(t2);
5238 tcg_temp_free_i32(t3);
5239 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5240 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
5241 if (unlikely(Rc(ctx->opcode) != 0)) {
5242 gen_set_Rc0(ctx, t0);
5243 }
5244 tcg_temp_free(t0);
5245 }
5246
5247 /* maskg - maskg. */
5248 static void gen_maskg(DisasContext *ctx)
5249 {
5250 TCGLabel *l1 = gen_new_label();
5251 TCGv t0 = tcg_temp_new();
5252 TCGv t1 = tcg_temp_new();
5253 TCGv t2 = tcg_temp_new();
5254 TCGv t3 = tcg_temp_new();
5255 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
5256 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5257 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
5258 tcg_gen_addi_tl(t2, t0, 1);
5259 tcg_gen_shr_tl(t2, t3, t2);
5260 tcg_gen_shr_tl(t3, t3, t1);
5261 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
5262 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
5263 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5264 gen_set_label(l1);
5265 tcg_temp_free(t0);
5266 tcg_temp_free(t1);
5267 tcg_temp_free(t2);
5268 tcg_temp_free(t3);
5269 if (unlikely(Rc(ctx->opcode) != 0)) {
5270 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5271 }
5272 }
5273
5274 /* maskir - maskir. */
5275 static void gen_maskir(DisasContext *ctx)
5276 {
5277 TCGv t0 = tcg_temp_new();
5278 TCGv t1 = tcg_temp_new();
5279 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5280 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5281 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5282 tcg_temp_free(t0);
5283 tcg_temp_free(t1);
5284 if (unlikely(Rc(ctx->opcode) != 0)) {
5285 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5286 }
5287 }
5288
5289 /* mul - mul. */
5290 static void gen_mul(DisasContext *ctx)
5291 {
5292 TCGv_i64 t0 = tcg_temp_new_i64();
5293 TCGv_i64 t1 = tcg_temp_new_i64();
5294 TCGv t2 = tcg_temp_new();
5295 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5296 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5297 tcg_gen_mul_i64(t0, t0, t1);
5298 tcg_gen_trunc_i64_tl(t2, t0);
5299 gen_store_spr(SPR_MQ, t2);
5300 tcg_gen_shri_i64(t1, t0, 32);
5301 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5302 tcg_temp_free_i64(t0);
5303 tcg_temp_free_i64(t1);
5304 tcg_temp_free(t2);
5305 if (unlikely(Rc(ctx->opcode) != 0)) {
5306 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5307 }
5308 }
5309
5310 /* mulo - mulo. */
5311 static void gen_mulo(DisasContext *ctx)
5312 {
5313 TCGLabel *l1 = gen_new_label();
5314 TCGv_i64 t0 = tcg_temp_new_i64();
5315 TCGv_i64 t1 = tcg_temp_new_i64();
5316 TCGv t2 = tcg_temp_new();
5317 /* Start with XER OV disabled, the most likely case */
5318 tcg_gen_movi_tl(cpu_ov, 0);
5319 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5320 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5321 tcg_gen_mul_i64(t0, t0, t1);
5322 tcg_gen_trunc_i64_tl(t2, t0);
5323 gen_store_spr(SPR_MQ, t2);
5324 tcg_gen_shri_i64(t1, t0, 32);
5325 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5326 tcg_gen_ext32s_i64(t1, t0);
5327 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
5328 tcg_gen_movi_tl(cpu_ov, 1);
5329 tcg_gen_movi_tl(cpu_so, 1);
5330 gen_set_label(l1);
5331 tcg_temp_free_i64(t0);
5332 tcg_temp_free_i64(t1);
5333 tcg_temp_free(t2);
5334 if (unlikely(Rc(ctx->opcode) != 0)) {
5335 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5336 }
5337 }
5338
5339 /* nabs - nabs. */
5340 static void gen_nabs(DisasContext *ctx)
5341 {
5342 TCGv d = cpu_gpr[rD(ctx->opcode)];
5343 TCGv a = cpu_gpr[rA(ctx->opcode)];
5344
5345 tcg_gen_abs_tl(d, a);
5346 tcg_gen_neg_tl(d, d);
5347 if (unlikely(Rc(ctx->opcode) != 0)) {
5348 gen_set_Rc0(ctx, d);
5349 }
5350 }
5351
5352 /* nabso - nabso. */
5353 static void gen_nabso(DisasContext *ctx)
5354 {
5355 TCGv d = cpu_gpr[rD(ctx->opcode)];
5356 TCGv a = cpu_gpr[rA(ctx->opcode)];
5357
5358 tcg_gen_abs_tl(d, a);
5359 tcg_gen_neg_tl(d, d);
5360 /* nabs never overflows */
5361 tcg_gen_movi_tl(cpu_ov, 0);
5362 if (unlikely(Rc(ctx->opcode) != 0)) {
5363 gen_set_Rc0(ctx, d);
5364 }
5365 }
5366
5367 /* rlmi - rlmi. */
5368 static void gen_rlmi(DisasContext *ctx)
5369 {
5370 uint32_t mb = MB(ctx->opcode);
5371 uint32_t me = ME(ctx->opcode);
5372 TCGv t0 = tcg_temp_new();
5373 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5374 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5375 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
5376 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
5377 ~MASK(mb, me));
5378 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
5379 tcg_temp_free(t0);
5380 if (unlikely(Rc(ctx->opcode) != 0)) {
5381 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5382 }
5383 }
5384
5385 /* rrib - rrib. */
5386 static void gen_rrib(DisasContext *ctx)
5387 {
5388 TCGv t0 = tcg_temp_new();
5389 TCGv t1 = tcg_temp_new();
5390 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5391 tcg_gen_movi_tl(t1, 0x80000000);
5392 tcg_gen_shr_tl(t1, t1, t0);
5393 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5394 tcg_gen_and_tl(t0, t0, t1);
5395 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
5396 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5397 tcg_temp_free(t0);
5398 tcg_temp_free(t1);
5399 if (unlikely(Rc(ctx->opcode) != 0)) {
5400 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5401 }
5402 }
5403
5404 /* sle - sle. */
5405 static void gen_sle(DisasContext *ctx)
5406 {
5407 TCGv t0 = tcg_temp_new();
5408 TCGv t1 = tcg_temp_new();
5409 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5410 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5411 tcg_gen_subfi_tl(t1, 32, t1);
5412 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5413 tcg_gen_or_tl(t1, t0, t1);
5414 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5415 gen_store_spr(SPR_MQ, t1);
5416 tcg_temp_free(t0);
5417 tcg_temp_free(t1);
5418 if (unlikely(Rc(ctx->opcode) != 0)) {
5419 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5420 }
5421 }
5422
5423 /* sleq - sleq. */
5424 static void gen_sleq(DisasContext *ctx)
5425 {
5426 TCGv t0 = tcg_temp_new();
5427 TCGv t1 = tcg_temp_new();
5428 TCGv t2 = tcg_temp_new();
5429 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5430 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5431 tcg_gen_shl_tl(t2, t2, t0);
5432 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5433 gen_load_spr(t1, SPR_MQ);
5434 gen_store_spr(SPR_MQ, t0);
5435 tcg_gen_and_tl(t0, t0, t2);
5436 tcg_gen_andc_tl(t1, t1, t2);
5437 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5438 tcg_temp_free(t0);
5439 tcg_temp_free(t1);
5440 tcg_temp_free(t2);
5441 if (unlikely(Rc(ctx->opcode) != 0)) {
5442 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5443 }
5444 }
5445
5446 /* sliq - sliq. */
5447 static void gen_sliq(DisasContext *ctx)
5448 {
5449 int sh = SH(ctx->opcode);
5450 TCGv t0 = tcg_temp_new();
5451 TCGv t1 = tcg_temp_new();
5452 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5453 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5454 tcg_gen_or_tl(t1, t0, t1);
5455 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5456 gen_store_spr(SPR_MQ, t1);
5457 tcg_temp_free(t0);
5458 tcg_temp_free(t1);
5459 if (unlikely(Rc(ctx->opcode) != 0)) {
5460 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5461 }
5462 }
5463
5464 /* slliq - slliq. */
5465 static void gen_slliq(DisasContext *ctx)
5466 {
5467 int sh = SH(ctx->opcode);
5468 TCGv t0 = tcg_temp_new();
5469 TCGv t1 = tcg_temp_new();
5470 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5471 gen_load_spr(t1, SPR_MQ);
5472 gen_store_spr(SPR_MQ, t0);
5473 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5474 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5475 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5476 tcg_temp_free(t0);
5477 tcg_temp_free(t1);
5478 if (unlikely(Rc(ctx->opcode) != 0)) {
5479 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5480 }
5481 }
5482
5483 /* sllq - sllq. */
5484 static void gen_sllq(DisasContext *ctx)
5485 {
5486 TCGLabel *l1 = gen_new_label();
5487 TCGLabel *l2 = gen_new_label();
5488 TCGv t0 = tcg_temp_local_new();
5489 TCGv t1 = tcg_temp_local_new();
5490 TCGv t2 = tcg_temp_local_new();
5491 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5492 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5493 tcg_gen_shl_tl(t1, t1, t2);
5494 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5495 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5496 gen_load_spr(t0, SPR_MQ);
5497 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5498 tcg_gen_br(l2);
5499 gen_set_label(l1);
5500 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5501 gen_load_spr(t2, SPR_MQ);
5502 tcg_gen_andc_tl(t1, t2, t1);
5503 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5504 gen_set_label(l2);
5505 tcg_temp_free(t0);
5506 tcg_temp_free(t1);
5507 tcg_temp_free(t2);
5508 if (unlikely(Rc(ctx->opcode) != 0)) {
5509 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5510 }
5511 }
5512
5513 /* slq - slq. */
5514 static void gen_slq(DisasContext *ctx)
5515 {
5516 TCGLabel *l1 = gen_new_label();
5517 TCGv t0 = tcg_temp_new();
5518 TCGv t1 = tcg_temp_new();
5519 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5520 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5521 tcg_gen_subfi_tl(t1, 32, t1);
5522 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5523 tcg_gen_or_tl(t1, t0, t1);
5524 gen_store_spr(SPR_MQ, t1);
5525 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5526 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5527 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5528 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5529 gen_set_label(l1);
5530 tcg_temp_free(t0);
5531 tcg_temp_free(t1);
5532 if (unlikely(Rc(ctx->opcode) != 0)) {
5533 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5534 }
5535 }
5536
5537 /* sraiq - sraiq. */
5538 static void gen_sraiq(DisasContext *ctx)
5539 {
5540 int sh = SH(ctx->opcode);
5541 TCGLabel *l1 = gen_new_label();
5542 TCGv t0 = tcg_temp_new();
5543 TCGv t1 = tcg_temp_new();
5544 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5545 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5546 tcg_gen_or_tl(t0, t0, t1);
5547 gen_store_spr(SPR_MQ, t0);
5548 tcg_gen_movi_tl(cpu_ca, 0);
5549 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5550 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5551 tcg_gen_movi_tl(cpu_ca, 1);
5552 gen_set_label(l1);
5553 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5554 tcg_temp_free(t0);
5555 tcg_temp_free(t1);
5556 if (unlikely(Rc(ctx->opcode) != 0)) {
5557 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5558 }
5559 }
5560
5561 /* sraq - sraq. */
5562 static void gen_sraq(DisasContext *ctx)
5563 {
5564 TCGLabel *l1 = gen_new_label();
5565 TCGLabel *l2 = gen_new_label();
5566 TCGv t0 = tcg_temp_new();
5567 TCGv t1 = tcg_temp_local_new();
5568 TCGv t2 = tcg_temp_local_new();
5569 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5570 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5571 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5572 tcg_gen_subfi_tl(t2, 32, t2);
5573 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5574 tcg_gen_or_tl(t0, t0, t2);
5575 gen_store_spr(SPR_MQ, t0);
5576 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5577 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5578 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5579 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5580 gen_set_label(l1);
5581 tcg_temp_free(t0);
5582 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5583 tcg_gen_movi_tl(cpu_ca, 0);
5584 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5585 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5586 tcg_gen_movi_tl(cpu_ca, 1);
5587 gen_set_label(l2);
5588 tcg_temp_free(t1);
5589 tcg_temp_free(t2);
5590 if (unlikely(Rc(ctx->opcode) != 0)) {
5591 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5592 }
5593 }
5594
5595 /* sre - sre. */
5596 static void gen_sre(DisasContext *ctx)
5597 {
5598 TCGv t0 = tcg_temp_new();
5599 TCGv t1 = tcg_temp_new();
5600 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5601 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5602 tcg_gen_subfi_tl(t1, 32, t1);
5603 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5604 tcg_gen_or_tl(t1, t0, t1);
5605 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5606 gen_store_spr(SPR_MQ, t1);
5607 tcg_temp_free(t0);
5608 tcg_temp_free(t1);
5609 if (unlikely(Rc(ctx->opcode) != 0)) {
5610 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5611 }
5612 }
5613
5614 /* srea - srea. */
5615 static void gen_srea(DisasContext *ctx)
5616 {
5617 TCGv t0 = tcg_temp_new();
5618 TCGv t1 = tcg_temp_new();
5619 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5620 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5621 gen_store_spr(SPR_MQ, t0);
5622 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5623 tcg_temp_free(t0);
5624 tcg_temp_free(t1);
5625 if (unlikely(Rc(ctx->opcode) != 0)) {
5626 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5627 }
5628 }
5629
5630 /* sreq */
5631 static void gen_sreq(DisasContext *ctx)
5632 {
5633 TCGv t0 = tcg_temp_new();
5634 TCGv t1 = tcg_temp_new();
5635 TCGv t2 = tcg_temp_new();
5636 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5637 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5638 tcg_gen_shr_tl(t1, t1, t0);
5639 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5640 gen_load_spr(t2, SPR_MQ);
5641 gen_store_spr(SPR_MQ, t0);
5642 tcg_gen_and_tl(t0, t0, t1);
5643 tcg_gen_andc_tl(t2, t2, t1);
5644 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5645 tcg_temp_free(t0);
5646 tcg_temp_free(t1);
5647 tcg_temp_free(t2);
5648 if (unlikely(Rc(ctx->opcode) != 0)) {
5649 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5650 }
5651 }
5652
5653 /* sriq */
5654 static void gen_sriq(DisasContext *ctx)
5655 {
5656 int sh = SH(ctx->opcode);
5657 TCGv t0 = tcg_temp_new();
5658 TCGv t1 = tcg_temp_new();
5659 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5660 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5661 tcg_gen_or_tl(t1, t0, t1);
5662 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5663 gen_store_spr(SPR_MQ, t1);
5664 tcg_temp_free(t0);
5665 tcg_temp_free(t1);
5666 if (unlikely(Rc(ctx->opcode) != 0)) {
5667 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5668 }
5669 }
5670
5671 /* srliq */
5672 static void gen_srliq(DisasContext *ctx)
5673 {
5674 int sh = SH(ctx->opcode);
5675 TCGv t0 = tcg_temp_new();
5676 TCGv t1 = tcg_temp_new();
5677 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5678 gen_load_spr(t1, SPR_MQ);
5679 gen_store_spr(SPR_MQ, t0);
5680 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5681 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5682 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5683 tcg_temp_free(t0);
5684 tcg_temp_free(t1);
5685 if (unlikely(Rc(ctx->opcode) != 0)) {
5686 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5687 }
5688 }
5689
5690 /* srlq */
5691 static void gen_srlq(DisasContext *ctx)
5692 {
5693 TCGLabel *l1 = gen_new_label();
5694 TCGLabel *l2 = gen_new_label();
5695 TCGv t0 = tcg_temp_local_new();
5696 TCGv t1 = tcg_temp_local_new();
5697 TCGv t2 = tcg_temp_local_new();
5698 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5699 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5700 tcg_gen_shr_tl(t2, t1, t2);
5701 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5702 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5703 gen_load_spr(t0, SPR_MQ);
5704 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5705 tcg_gen_br(l2);
5706 gen_set_label(l1);
5707 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5708 tcg_gen_and_tl(t0, t0, t2);
5709 gen_load_spr(t1, SPR_MQ);
5710 tcg_gen_andc_tl(t1, t1, t2);
5711 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5712 gen_set_label(l2);
5713 tcg_temp_free(t0);
5714 tcg_temp_free(t1);
5715 tcg_temp_free(t2);
5716 if (unlikely(Rc(ctx->opcode) != 0)) {
5717 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5718 }
5719 }
5720
5721 /* srq */
5722 static void gen_srq(DisasContext *ctx)
5723 {
5724 TCGLabel *l1 = gen_new_label();
5725 TCGv t0 = tcg_temp_new();
5726 TCGv t1 = tcg_temp_new();
5727 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5728 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5729 tcg_gen_subfi_tl(t1, 32, t1);
5730 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5731 tcg_gen_or_tl(t1, t0, t1);
5732 gen_store_spr(SPR_MQ, t1);
5733 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5734 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5735 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5736 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5737 gen_set_label(l1);
5738 tcg_temp_free(t0);
5739 tcg_temp_free(t1);
5740 if (unlikely(Rc(ctx->opcode) != 0)) {
5741 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5742 }
5743 }
5744
5745 /* PowerPC 602 specific instructions */
5746
5747 /* dsa */
5748 static void gen_dsa(DisasContext *ctx)
5749 {
5750 /* XXX: TODO */
5751 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5752 }
5753
5754 /* esa */
5755 static void gen_esa(DisasContext *ctx)
5756 {
5757 /* XXX: TODO */
5758 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5759 }
5760
5761 /* mfrom */
5762 static void gen_mfrom(DisasContext *ctx)
5763 {
5764 #if defined(CONFIG_USER_ONLY)
5765 GEN_PRIV;
5766 #else
5767 CHK_SV;
5768 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5769 #endif /* defined(CONFIG_USER_ONLY) */
5770 }
5771
5772 /* 602 - 603 - G2 TLB management */
5773
5774 /* tlbld */
5775 static void gen_tlbld_6xx(DisasContext *ctx)
5776 {
5777 #if defined(CONFIG_USER_ONLY)
5778 GEN_PRIV;
5779 #else
5780 CHK_SV;
5781 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5782 #endif /* defined(CONFIG_USER_ONLY) */
5783 }
5784
5785 /* tlbli */
5786 static void gen_tlbli_6xx(DisasContext *ctx)
5787 {
5788 #if defined(CONFIG_USER_ONLY)
5789 GEN_PRIV;
5790 #else
5791 CHK_SV;
5792 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5793 #endif /* defined(CONFIG_USER_ONLY) */
5794 }
5795
5796 /* 74xx TLB management */
5797
5798 /* tlbld */
5799 static void gen_tlbld_74xx(DisasContext *ctx)
5800 {
5801 #if defined(CONFIG_USER_ONLY)
5802 GEN_PRIV;
5803 #else
5804 CHK_SV;
5805 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5806 #endif /* defined(CONFIG_USER_ONLY) */
5807 }
5808
5809 /* tlbli */
5810 static void gen_tlbli_74xx(DisasContext *ctx)
5811 {
5812 #if defined(CONFIG_USER_ONLY)
5813 GEN_PRIV;
5814 #else
5815 CHK_SV;
5816 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5817 #endif /* defined(CONFIG_USER_ONLY) */
5818 }
5819
5820 /* POWER instructions not in PowerPC 601 */
5821
5822 /* clf */
5823 static void gen_clf(DisasContext *ctx)
5824 {
5825 /* Cache line flush: implemented as no-op */
5826 }
5827
5828 /* cli */
5829 static void gen_cli(DisasContext *ctx)
5830 {
5831 #if defined(CONFIG_USER_ONLY)
5832 GEN_PRIV;
5833 #else
5834 /* Cache line invalidate: privileged and treated as no-op */
5835 CHK_SV;
5836 #endif /* defined(CONFIG_USER_ONLY) */
5837 }
5838
5839 /* dclst */
5840 static void gen_dclst(DisasContext *ctx)
5841 {
5842 /* Data cache line store: treated as no-op */
5843 }
5844
5845 static void gen_mfsri(DisasContext *ctx)
5846 {
5847 #if defined(CONFIG_USER_ONLY)
5848 GEN_PRIV;
5849 #else
5850 int ra = rA(ctx->opcode);
5851 int rd = rD(ctx->opcode);
5852 TCGv t0;
5853
5854 CHK_SV;
5855 t0 = tcg_temp_new();
5856 gen_addr_reg_index(ctx, t0);
5857 tcg_gen_extract_tl(t0, t0, 28, 4);
5858 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5859 tcg_temp_free(t0);
5860 if (ra != 0 && ra != rd) {
5861 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5862 }
5863 #endif /* defined(CONFIG_USER_ONLY) */
5864 }
5865
5866 static void gen_rac(DisasContext *ctx)
5867 {
5868 #if defined(CONFIG_USER_ONLY)
5869 GEN_PRIV;
5870 #else
5871 TCGv t0;
5872
5873 CHK_SV;
5874 t0 = tcg_temp_new();
5875 gen_addr_reg_index(ctx, t0);
5876 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5877 tcg_temp_free(t0);
5878 #endif /* defined(CONFIG_USER_ONLY) */
5879 }
5880
5881 static void gen_rfsvc(DisasContext *ctx)
5882 {
5883 #if defined(CONFIG_USER_ONLY)
5884 GEN_PRIV;
5885 #else
5886 CHK_SV;
5887
5888 gen_helper_rfsvc(cpu_env);
5889 gen_sync_exception(ctx);
5890 #endif /* defined(CONFIG_USER_ONLY) */
5891 }
5892
5893 /* svc is not implemented for now */
5894
5895 /* BookE specific instructions */
5896
5897 /* XXX: not implemented on 440 ? */
5898 static void gen_mfapidi(DisasContext *ctx)
5899 {
5900 /* XXX: TODO */
5901 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5902 }
5903
5904 /* XXX: not implemented on 440 ? */
5905 static void gen_tlbiva(DisasContext *ctx)
5906 {
5907 #if defined(CONFIG_USER_ONLY)
5908 GEN_PRIV;
5909 #else
5910 TCGv t0;
5911
5912 CHK_SV;
5913 t0 = tcg_temp_new();
5914 gen_addr_reg_index(ctx, t0);
5915 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5916 tcg_temp_free(t0);
5917 #endif /* defined(CONFIG_USER_ONLY) */
5918 }
5919
5920 /* All 405 MAC instructions are translated here */
5921 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5922 int ra, int rb, int rt, int Rc)
5923 {
5924 TCGv t0, t1;
5925
5926 t0 = tcg_temp_local_new();
5927 t1 = tcg_temp_local_new();
5928
5929 switch (opc3 & 0x0D) {
5930 case 0x05:
5931 /* macchw - macchw. - macchwo - macchwo. */
5932 /* macchws - macchws. - macchwso - macchwso. */
5933 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5934 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5935 /* mulchw - mulchw. */
5936 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5937 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5938 tcg_gen_ext16s_tl(t1, t1);
5939 break;
5940 case 0x04:
5941 /* macchwu - macchwu. - macchwuo - macchwuo. */
5942 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5943 /* mulchwu - mulchwu. */
5944 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5945 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5946 tcg_gen_ext16u_tl(t1, t1);
5947 break;
5948 case 0x01:
5949 /* machhw - machhw. - machhwo - machhwo. */
5950 /* machhws - machhws. - machhwso - machhwso. */
5951 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5952 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5953 /* mulhhw - mulhhw. */
5954 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5955 tcg_gen_ext16s_tl(t0, t0);
5956 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5957 tcg_gen_ext16s_tl(t1, t1);
5958 break;
5959 case 0x00:
5960 /* machhwu - machhwu. - machhwuo - machhwuo. */
5961 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5962 /* mulhhwu - mulhhwu. */
5963 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5964 tcg_gen_ext16u_tl(t0, t0);
5965 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5966 tcg_gen_ext16u_tl(t1, t1);
5967 break;
5968 case 0x0D:
5969 /* maclhw - maclhw. - maclhwo - maclhwo. */
5970 /* maclhws - maclhws. - maclhwso - maclhwso. */
5971 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5972 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5973 /* mullhw - mullhw. */
5974 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5975 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5976 break;
5977 case 0x0C:
5978 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5979 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5980 /* mullhwu - mullhwu. */
5981 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5982 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5983 break;
5984 }
5985 if (opc2 & 0x04) {
5986 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5987 tcg_gen_mul_tl(t1, t0, t1);
5988 if (opc2 & 0x02) {
5989 /* nmultiply-and-accumulate (0x0E) */
5990 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5991 } else {
5992 /* multiply-and-accumulate (0x0C) */
5993 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5994 }
5995
5996 if (opc3 & 0x12) {
5997 /* Check overflow and/or saturate */
5998 TCGLabel *l1 = gen_new_label();
5999
6000 if (opc3 & 0x10) {
6001 /* Start with XER OV disabled, the most likely case */
6002 tcg_gen_movi_tl(cpu_ov, 0);
6003 }
6004 if (opc3 & 0x01) {
6005 /* Signed */
6006 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
6007 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
6008 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
6009 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
6010 if (opc3 & 0x02) {
6011 /* Saturate */
6012 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
6013 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
6014 }
6015 } else {
6016 /* Unsigned */
6017 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
6018 if (opc3 & 0x02) {
6019 /* Saturate */
6020 tcg_gen_movi_tl(t0, UINT32_MAX);
6021 }
6022 }
6023 if (opc3 & 0x10) {
6024 /* Check overflow */
6025 tcg_gen_movi_tl(cpu_ov, 1);
6026 tcg_gen_movi_tl(cpu_so, 1);
6027 }
6028 gen_set_label(l1);
6029 tcg_gen_mov_tl(cpu_gpr[rt], t0);
6030 }
6031 } else {
6032 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
6033 }
6034 tcg_temp_free(t0);
6035 tcg_temp_free(t1);
6036 if (unlikely(Rc) != 0) {
6037 /* Update Rc0 */
6038 gen_set_Rc0(ctx, cpu_gpr[rt]);
6039 }
6040 }
6041
6042 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6043 static void glue(gen_, name)(DisasContext *ctx) \
6044 { \
6045 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
6046 rD(ctx->opcode), Rc(ctx->opcode)); \
6047 }
6048
6049 /* macchw - macchw. */
6050 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
6051 /* macchwo - macchwo. */
6052 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
6053 /* macchws - macchws. */
6054 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
6055 /* macchwso - macchwso. */
6056 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
6057 /* macchwsu - macchwsu. */
6058 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
6059 /* macchwsuo - macchwsuo. */
6060 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
6061 /* macchwu - macchwu. */
6062 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
6063 /* macchwuo - macchwuo. */
6064 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
6065 /* machhw - machhw. */
6066 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
6067 /* machhwo - machhwo. */
6068 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
6069 /* machhws - machhws. */
6070 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
6071 /* machhwso - machhwso. */
6072 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
6073 /* machhwsu - machhwsu. */
6074 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
6075 /* machhwsuo - machhwsuo. */
6076 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
6077 /* machhwu - machhwu. */
6078 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
6079 /* machhwuo - machhwuo. */
6080 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
6081 /* maclhw - maclhw. */
6082 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
6083 /* maclhwo - maclhwo. */
6084 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
6085 /* maclhws - maclhws. */
6086 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
6087 /* maclhwso - maclhwso. */
6088 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
6089 /* maclhwu - maclhwu. */
6090 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
6091 /* maclhwuo - maclhwuo. */
6092 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
6093 /* maclhwsu - maclhwsu. */
6094 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
6095 /* maclhwsuo - maclhwsuo. */
6096 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
6097 /* nmacchw - nmacchw. */
6098 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
6099 /* nmacchwo - nmacchwo. */
6100 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
6101 /* nmacchws - nmacchws. */
6102 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
6103 /* nmacchwso - nmacchwso. */
6104 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
6105 /* nmachhw - nmachhw. */
6106 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
6107 /* nmachhwo - nmachhwo. */
6108 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
6109 /* nmachhws - nmachhws. */
6110 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
6111 /* nmachhwso - nmachhwso. */
6112 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
6113 /* nmaclhw - nmaclhw. */
6114 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
6115 /* nmaclhwo - nmaclhwo. */
6116 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
6117 /* nmaclhws - nmaclhws. */
6118 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
6119 /* nmaclhwso - nmaclhwso. */
6120 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
6121
6122 /* mulchw - mulchw. */
6123 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
6124 /* mulchwu - mulchwu. */
6125 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
6126 /* mulhhw - mulhhw. */
6127 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
6128 /* mulhhwu - mulhhwu. */
6129 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
6130 /* mullhw - mullhw. */
6131 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
6132 /* mullhwu - mullhwu. */
6133 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
6134
6135 /* mfdcr */
6136 static void gen_mfdcr(DisasContext *ctx)
6137 {
6138 #if defined(CONFIG_USER_ONLY)
6139 GEN_PRIV;
6140 #else
6141 TCGv dcrn;
6142
6143 CHK_SV;
6144 dcrn = tcg_const_tl(SPR(ctx->opcode));
6145 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
6146 tcg_temp_free(dcrn);
6147 #endif /* defined(CONFIG_USER_ONLY) */
6148 }
6149
6150 /* mtdcr */
6151 static void gen_mtdcr(DisasContext *ctx)
6152 {
6153 #if defined(CONFIG_USER_ONLY)
6154 GEN_PRIV;
6155 #else
6156 TCGv dcrn;
6157
6158 CHK_SV;
6159 dcrn = tcg_const_tl(SPR(ctx->opcode));
6160 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
6161 tcg_temp_free(dcrn);
6162 #endif /* defined(CONFIG_USER_ONLY) */
6163 }
6164
6165 /* mfdcrx */
6166 /* XXX: not implemented on 440 ? */
6167 static void gen_mfdcrx(DisasContext *ctx)
6168 {
6169 #if defined(CONFIG_USER_ONLY)
6170 GEN_PRIV;
6171 #else
6172 CHK_SV;
6173 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6174 cpu_gpr[rA(ctx->opcode)]);
6175 /* Note: Rc update flag set leads to undefined state of Rc0 */
6176 #endif /* defined(CONFIG_USER_ONLY) */
6177 }
6178
6179 /* mtdcrx */
6180 /* XXX: not implemented on 440 ? */
6181 static void gen_mtdcrx(DisasContext *ctx)
6182 {
6183 #if defined(CONFIG_USER_ONLY)
6184 GEN_PRIV;
6185 #else
6186 CHK_SV;
6187 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6188 cpu_gpr[rS(ctx->opcode)]);
6189 /* Note: Rc update flag set leads to undefined state of Rc0 */
6190 #endif /* defined(CONFIG_USER_ONLY) */
6191 }
6192
6193 /* mfdcrux (PPC 460) : user-mode access to DCR */
6194 static void gen_mfdcrux(DisasContext *ctx)
6195 {
6196 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6197 cpu_gpr[rA(ctx->opcode)]);
6198 /* Note: Rc update flag set leads to undefined state of Rc0 */
6199 }
6200
6201 /* mtdcrux (PPC 460) : user-mode access to DCR */
6202 static void gen_mtdcrux(DisasContext *ctx)
6203 {
6204 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6205 cpu_gpr[rS(ctx->opcode)]);
6206 /* Note: Rc update flag set leads to undefined state of Rc0 */
6207 }
6208
6209 /* dccci */
6210 static void gen_dccci(DisasContext *ctx)
6211 {
6212 CHK_SV;
6213 /* interpreted as no-op */
6214 }
6215
6216 /* dcread */
6217 static void gen_dcread(DisasContext *ctx)
6218 {
6219 #if defined(CONFIG_USER_ONLY)
6220 GEN_PRIV;
6221 #else
6222 TCGv EA, val;
6223
6224 CHK_SV;
6225 gen_set_access_type(ctx, ACCESS_CACHE);
6226 EA = tcg_temp_new();
6227 gen_addr_reg_index(ctx, EA);
6228 val = tcg_temp_new();
6229 gen_qemu_ld32u(ctx, val, EA);
6230 tcg_temp_free(val);
6231 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
6232 tcg_temp_free(EA);
6233 #endif /* defined(CONFIG_USER_ONLY) */
6234 }
6235
6236 /* icbt */
6237 static void gen_icbt_40x(DisasContext *ctx)
6238 {
6239 /*
6240 * interpreted as no-op
6241 * XXX: specification say this is treated as a load by the MMU but
6242 * does not generate any exception
6243 */
6244 }
6245
6246 /* iccci */
6247 static void gen_iccci(DisasContext *ctx)
6248 {
6249 CHK_SV;
6250 /* interpreted as no-op */
6251 }
6252
6253 /* icread */
6254 static void gen_icread(DisasContext *ctx)
6255 {
6256 CHK_SV;
6257 /* interpreted as no-op */
6258 }
6259
6260 /* rfci (supervisor only) */
6261 static void gen_rfci_40x(DisasContext *ctx)
6262 {
6263 #if defined(CONFIG_USER_ONLY)
6264 GEN_PRIV;
6265 #else
6266 CHK_SV;
6267 /* Restore CPU state */
6268 gen_helper_40x_rfci(cpu_env);
6269 gen_sync_exception(ctx);
6270 #endif /* defined(CONFIG_USER_ONLY) */
6271 }
6272
6273 static void gen_rfci(DisasContext *ctx)
6274 {
6275 #if defined(CONFIG_USER_ONLY)
6276 GEN_PRIV;
6277 #else
6278 CHK_SV;
6279 /* Restore CPU state */
6280 gen_helper_rfci(cpu_env);
6281 gen_sync_exception(ctx);
6282 #endif /* defined(CONFIG_USER_ONLY) */
6283 }
6284
6285 /* BookE specific */
6286
6287 /* XXX: not implemented on 440 ? */
6288 static void gen_rfdi(DisasContext *ctx)
6289 {
6290 #if defined(CONFIG_USER_ONLY)
6291 GEN_PRIV;
6292 #else
6293 CHK_SV;
6294 /* Restore CPU state */
6295 gen_helper_rfdi(cpu_env);
6296 gen_sync_exception(ctx);
6297 #endif /* defined(CONFIG_USER_ONLY) */
6298 }
6299
6300 /* XXX: not implemented on 440 ? */
6301 static void gen_rfmci(DisasContext *ctx)
6302 {
6303 #if defined(CONFIG_USER_ONLY)
6304 GEN_PRIV;
6305 #else
6306 CHK_SV;
6307 /* Restore CPU state */
6308 gen_helper_rfmci(cpu_env);
6309 gen_sync_exception(ctx);
6310 #endif /* defined(CONFIG_USER_ONLY) */
6311 }
6312
6313 /* TLB management - PowerPC 405 implementation */
6314
6315 /* tlbre */
6316 static void gen_tlbre_40x(DisasContext *ctx)
6317 {
6318 #if defined(CONFIG_USER_ONLY)
6319 GEN_PRIV;
6320 #else
6321 CHK_SV;
6322 switch (rB(ctx->opcode)) {
6323 case 0:
6324 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6325 cpu_gpr[rA(ctx->opcode)]);
6326 break;
6327 case 1:
6328 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6329 cpu_gpr[rA(ctx->opcode)]);
6330 break;
6331 default:
6332 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6333 break;
6334 }
6335 #endif /* defined(CONFIG_USER_ONLY) */
6336 }
6337
6338 /* tlbsx - tlbsx. */
6339 static void gen_tlbsx_40x(DisasContext *ctx)
6340 {
6341 #if defined(CONFIG_USER_ONLY)
6342 GEN_PRIV;
6343 #else
6344 TCGv t0;
6345
6346 CHK_SV;
6347 t0 = tcg_temp_new();
6348 gen_addr_reg_index(ctx, t0);
6349 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6350 tcg_temp_free(t0);
6351 if (Rc(ctx->opcode)) {
6352 TCGLabel *l1 = gen_new_label();
6353 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6354 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6355 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6356 gen_set_label(l1);
6357 }
6358 #endif /* defined(CONFIG_USER_ONLY) */
6359 }
6360
6361 /* tlbwe */
6362 static void gen_tlbwe_40x(DisasContext *ctx)
6363 {
6364 #if defined(CONFIG_USER_ONLY)
6365 GEN_PRIV;
6366 #else
6367 CHK_SV;
6368
6369 switch (rB(ctx->opcode)) {
6370 case 0:
6371 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6372 cpu_gpr[rS(ctx->opcode)]);
6373 break;
6374 case 1:
6375 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6376 cpu_gpr[rS(ctx->opcode)]);
6377 break;
6378 default:
6379 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6380 break;
6381 }
6382 #endif /* defined(CONFIG_USER_ONLY) */
6383 }
6384
6385 /* TLB management - PowerPC 440 implementation */
6386
6387 /* tlbre */
6388 static void gen_tlbre_440(DisasContext *ctx)
6389 {
6390 #if defined(CONFIG_USER_ONLY)
6391 GEN_PRIV;
6392 #else
6393 CHK_SV;
6394
6395 switch (rB(ctx->opcode)) {
6396 case 0:
6397 case 1:
6398 case 2:
6399 {
6400 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6401 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6402 t0, cpu_gpr[rA(ctx->opcode)]);
6403 tcg_temp_free_i32(t0);
6404 }
6405 break;
6406 default:
6407 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6408 break;
6409 }
6410 #endif /* defined(CONFIG_USER_ONLY) */
6411 }
6412
6413 /* tlbsx - tlbsx. */
6414 static void gen_tlbsx_440(DisasContext *ctx)
6415 {
6416 #if defined(CONFIG_USER_ONLY)
6417 GEN_PRIV;
6418 #else
6419 TCGv t0;
6420
6421 CHK_SV;
6422 t0 = tcg_temp_new();
6423 gen_addr_reg_index(ctx, t0);
6424 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6425 tcg_temp_free(t0);
6426 if (Rc(ctx->opcode)) {
6427 TCGLabel *l1 = gen_new_label();
6428 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6429 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6430 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6431 gen_set_label(l1);
6432 }
6433 #endif /* defined(CONFIG_USER_ONLY) */
6434 }
6435
6436 /* tlbwe */
6437 static void gen_tlbwe_440(DisasContext *ctx)
6438 {
6439 #if defined(CONFIG_USER_ONLY)
6440 GEN_PRIV;
6441 #else
6442 CHK_SV;
6443 switch (rB(ctx->opcode)) {
6444 case 0:
6445 case 1:
6446 case 2:
6447 {
6448 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6449 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6450 cpu_gpr[rS(ctx->opcode)]);
6451 tcg_temp_free_i32(t0);
6452 }
6453 break;
6454 default:
6455 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6456 break;
6457 }
6458 #endif /* defined(CONFIG_USER_ONLY) */
6459 }
6460
6461 /* TLB management - PowerPC BookE 2.06 implementation */
6462
6463 /* tlbre */
6464 static void gen_tlbre_booke206(DisasContext *ctx)
6465 {
6466 #if defined(CONFIG_USER_ONLY)
6467 GEN_PRIV;
6468 #else
6469 CHK_SV;
6470 gen_helper_booke206_tlbre(cpu_env);
6471 #endif /* defined(CONFIG_USER_ONLY) */
6472 }
6473
6474 /* tlbsx - tlbsx. */
6475 static void gen_tlbsx_booke206(DisasContext *ctx)
6476 {
6477 #if defined(CONFIG_USER_ONLY)
6478 GEN_PRIV;
6479 #else
6480 TCGv t0;
6481
6482 CHK_SV;
6483 if (rA(ctx->opcode)) {
6484 t0 = tcg_temp_new();
6485 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6486 } else {
6487 t0 = tcg_const_tl(0);
6488 }
6489
6490 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6491 gen_helper_booke206_tlbsx(cpu_env, t0);
6492 tcg_temp_free(t0);
6493 #endif /* defined(CONFIG_USER_ONLY) */
6494 }
6495
6496 /* tlbwe */
6497 static void gen_tlbwe_booke206(DisasContext *ctx)
6498 {
6499 #if defined(CONFIG_USER_ONLY)
6500 GEN_PRIV;
6501 #else
6502 CHK_SV;
6503 gen_helper_booke206_tlbwe(cpu_env);
6504 #endif /* defined(CONFIG_USER_ONLY) */
6505 }
6506
6507 static void gen_tlbivax_booke206(DisasContext *ctx)
6508 {
6509 #if defined(CONFIG_USER_ONLY)
6510 GEN_PRIV;
6511 #else
6512 TCGv t0;
6513
6514 CHK_SV;
6515 t0 = tcg_temp_new();
6516 gen_addr_reg_index(ctx, t0);
6517 gen_helper_booke206_tlbivax(cpu_env, t0);
6518 tcg_temp_free(t0);
6519 #endif /* defined(CONFIG_USER_ONLY) */
6520 }
6521
6522 static void gen_tlbilx_booke206(DisasContext *ctx)
6523 {
6524 #if defined(CONFIG_USER_ONLY)
6525 GEN_PRIV;
6526 #else
6527 TCGv t0;
6528
6529 CHK_SV;
6530 t0 = tcg_temp_new();
6531 gen_addr_reg_index(ctx, t0);
6532
6533 switch ((ctx->opcode >> 21) & 0x3) {
6534 case 0:
6535 gen_helper_booke206_tlbilx0(cpu_env, t0);
6536 break;
6537 case 1:
6538 gen_helper_booke206_tlbilx1(cpu_env, t0);
6539 break;
6540 case 3:
6541 gen_helper_booke206_tlbilx3(cpu_env, t0);
6542 break;
6543 default:
6544 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6545 break;
6546 }
6547
6548 tcg_temp_free(t0);
6549 #endif /* defined(CONFIG_USER_ONLY) */
6550 }
6551
6552
6553 /* wrtee */
6554 static void gen_wrtee(DisasContext *ctx)
6555 {
6556 #if defined(CONFIG_USER_ONLY)
6557 GEN_PRIV;
6558 #else
6559 TCGv t0;
6560
6561 CHK_SV;
6562 t0 = tcg_temp_new();
6563 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6564 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6565 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6566 tcg_temp_free(t0);
6567 /*
6568 * Stop translation to have a chance to raise an exception if we
6569 * just set msr_ee to 1
6570 */
6571 gen_stop_exception(ctx);
6572 #endif /* defined(CONFIG_USER_ONLY) */
6573 }
6574
6575 /* wrteei */
6576 static void gen_wrteei(DisasContext *ctx)
6577 {
6578 #if defined(CONFIG_USER_ONLY)
6579 GEN_PRIV;
6580 #else
6581 CHK_SV;
6582 if (ctx->opcode & 0x00008000) {
6583 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6584 /* Stop translation to have a chance to raise an exception */
6585 gen_stop_exception(ctx);
6586 } else {
6587 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6588 }
6589 #endif /* defined(CONFIG_USER_ONLY) */
6590 }
6591
6592 /* PowerPC 440 specific instructions */
6593
6594 /* dlmzb */
6595 static void gen_dlmzb(DisasContext *ctx)
6596 {
6597 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6598 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6599 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6600 tcg_temp_free_i32(t0);
6601 }
6602
6603 /* mbar replaces eieio on 440 */
6604 static void gen_mbar(DisasContext *ctx)
6605 {
6606 /* interpreted as no-op */
6607 }
6608
6609 /* msync replaces sync on 440 */
6610 static void gen_msync_4xx(DisasContext *ctx)
6611 {
6612 /* Only e500 seems to treat reserved bits as invalid */
6613 if ((ctx->insns_flags2 & PPC2_BOOKE206) &&
6614 (ctx->opcode & 0x03FFF801)) {
6615 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6616 }
6617 /* otherwise interpreted as no-op */
6618 }
6619
6620 /* icbt */
6621 static void gen_icbt_440(DisasContext *ctx)
6622 {
6623 /*
6624 * interpreted as no-op
6625 * XXX: specification say this is treated as a load by the MMU but
6626 * does not generate any exception
6627 */
6628 }
6629
6630 /* Embedded.Processor Control */
6631
6632 static void gen_msgclr(DisasContext *ctx)
6633 {
6634 #if defined(CONFIG_USER_ONLY)
6635 GEN_PRIV;
6636 #else
6637 CHK_HV;
6638 if (is_book3s_arch2x(ctx)) {
6639 gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6640 } else {
6641 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6642 }
6643 #endif /* defined(CONFIG_USER_ONLY) */
6644 }
6645
6646 static void gen_msgsnd(DisasContext *ctx)
6647 {
6648 #if defined(CONFIG_USER_ONLY)
6649 GEN_PRIV;
6650 #else
6651 CHK_HV;
6652 if (is_book3s_arch2x(ctx)) {
6653 gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6654 } else {
6655 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6656 }
6657 #endif /* defined(CONFIG_USER_ONLY) */
6658 }
6659
6660 static void gen_msgsync(DisasContext *ctx)
6661 {
6662 #if defined(CONFIG_USER_ONLY)
6663 GEN_PRIV;
6664 #else
6665 CHK_HV;
6666 #endif /* defined(CONFIG_USER_ONLY) */
6667 /* interpreted as no-op */
6668 }
6669
6670 #if defined(TARGET_PPC64)
6671 static void gen_maddld(DisasContext *ctx)
6672 {
6673 TCGv_i64 t1 = tcg_temp_new_i64();
6674
6675 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6676 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]);
6677 tcg_temp_free_i64(t1);
6678 }
6679
6680 /* maddhd maddhdu */
6681 static void gen_maddhd_maddhdu(DisasContext *ctx)
6682 {
6683 TCGv_i64 lo = tcg_temp_new_i64();
6684 TCGv_i64 hi = tcg_temp_new_i64();
6685 TCGv_i64 t1 = tcg_temp_new_i64();
6686
6687 if (Rc(ctx->opcode)) {
6688 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6689 cpu_gpr[rB(ctx->opcode)]);
6690 tcg_gen_movi_i64(t1, 0);
6691 } else {
6692 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6693 cpu_gpr[rB(ctx->opcode)]);
6694 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63);
6695 }
6696 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi,
6697 cpu_gpr[rC(ctx->opcode)], t1);
6698 tcg_temp_free_i64(lo);
6699 tcg_temp_free_i64(hi);
6700 tcg_temp_free_i64(t1);
6701 }
6702 #endif /* defined(TARGET_PPC64) */
6703
6704 static void gen_tbegin(DisasContext *ctx)
6705 {
6706 if (unlikely(!ctx->tm_enabled)) {
6707 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6708 return;
6709 }
6710 gen_helper_tbegin(cpu_env);
6711 }
6712
6713 #define GEN_TM_NOOP(name) \
6714 static inline void gen_##name(DisasContext *ctx) \
6715 { \
6716 if (unlikely(!ctx->tm_enabled)) { \
6717 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6718 return; \
6719 } \
6720 /* \
6721 * Because tbegin always fails in QEMU, these user \
6722 * space instructions all have a simple implementation: \
6723 * \
6724 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6725 * = 0b0 || 0b00 || 0b0 \
6726 */ \
6727 tcg_gen_movi_i32(cpu_crf[0], 0); \
6728 }
6729
6730 GEN_TM_NOOP(tend);
6731 GEN_TM_NOOP(tabort);
6732 GEN_TM_NOOP(tabortwc);
6733 GEN_TM_NOOP(tabortwci);
6734 GEN_TM_NOOP(tabortdc);
6735 GEN_TM_NOOP(tabortdci);
6736 GEN_TM_NOOP(tsr);
6737
6738 static inline void gen_cp_abort(DisasContext *ctx)
6739 {
6740 /* Do Nothing */
6741 }
6742
6743 #define GEN_CP_PASTE_NOOP(name) \
6744 static inline void gen_##name(DisasContext *ctx) \
6745 { \
6746 /* \
6747 * Generate invalid exception until we have an \
6748 * implementation of the copy paste facility \
6749 */ \
6750 gen_invalid(ctx); \
6751 }
6752
6753 GEN_CP_PASTE_NOOP(copy)
6754 GEN_CP_PASTE_NOOP(paste)
6755
6756 static void gen_tcheck(DisasContext *ctx)
6757 {
6758 if (unlikely(!ctx->tm_enabled)) {
6759 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6760 return;
6761 }
6762 /*
6763 * Because tbegin always fails, the tcheck implementation is
6764 * simple:
6765 *
6766 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
6767 * = 0b1 || 0b00 || 0b0
6768 */
6769 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
6770 }
6771
6772 #if defined(CONFIG_USER_ONLY)
6773 #define GEN_TM_PRIV_NOOP(name) \
6774 static inline void gen_##name(DisasContext *ctx) \
6775 { \
6776 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
6777 }
6778
6779 #else
6780
6781 #define GEN_TM_PRIV_NOOP(name) \
6782 static inline void gen_##name(DisasContext *ctx) \
6783 { \
6784 CHK_SV; \
6785 if (unlikely(!ctx->tm_enabled)) { \
6786 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6787 return; \
6788 } \
6789 /* \
6790 * Because tbegin always fails, the implementation is \
6791 * simple: \
6792 * \
6793 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6794 * = 0b0 || 0b00 | 0b0 \
6795 */ \
6796 tcg_gen_movi_i32(cpu_crf[0], 0); \
6797 }
6798
6799 #endif
6800
6801 GEN_TM_PRIV_NOOP(treclaim);
6802 GEN_TM_PRIV_NOOP(trechkpt);
6803
6804 static inline void get_fpr(TCGv_i64 dst, int regno)
6805 {
6806 tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno));
6807 }
6808
6809 static inline void set_fpr(int regno, TCGv_i64 src)
6810 {
6811 tcg_gen_st_i64(src, cpu_env, fpr_offset(regno));
6812 }
6813
6814 static inline void get_avr64(TCGv_i64 dst, int regno, bool high)
6815 {
6816 tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high));
6817 }
6818
6819 static inline void set_avr64(int regno, TCGv_i64 src, bool high)
6820 {
6821 tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high));
6822 }
6823
6824 #include "translate/fp-impl.inc.c"
6825
6826 #include "translate/vmx-impl.inc.c"
6827
6828 #include "translate/vsx-impl.inc.c"
6829
6830 #include "translate/dfp-impl.inc.c"
6831
6832 #include "translate/spe-impl.inc.c"
6833
6834 /* Handles lfdp, lxsd, lxssp */
6835 static void gen_dform39(DisasContext *ctx)
6836 {
6837 switch (ctx->opcode & 0x3) {
6838 case 0: /* lfdp */
6839 if (ctx->insns_flags2 & PPC2_ISA205) {
6840 return gen_lfdp(ctx);
6841 }
6842 break;
6843 case 2: /* lxsd */
6844 if (ctx->insns_flags2 & PPC2_ISA300) {
6845 return gen_lxsd(ctx);
6846 }
6847 break;
6848 case 3: /* lxssp */
6849 if (ctx->insns_flags2 & PPC2_ISA300) {
6850 return gen_lxssp(ctx);
6851 }
6852 break;
6853 }
6854 return gen_invalid(ctx);
6855 }
6856
6857 /* handles stfdp, lxv, stxsd, stxssp lxvx */
6858 static void gen_dform3D(DisasContext *ctx)
6859 {
6860 if ((ctx->opcode & 3) == 1) { /* DQ-FORM */
6861 switch (ctx->opcode & 0x7) {
6862 case 1: /* lxv */
6863 if (ctx->insns_flags2 & PPC2_ISA300) {
6864 return gen_lxv(ctx);
6865 }
6866 break;
6867 case 5: /* stxv */
6868 if (ctx->insns_flags2 & PPC2_ISA300) {
6869 return gen_stxv(ctx);
6870 }
6871 break;
6872 }
6873 } else { /* DS-FORM */
6874 switch (ctx->opcode & 0x3) {
6875 case 0: /* stfdp */
6876 if (ctx->insns_flags2 & PPC2_ISA205) {
6877 return gen_stfdp(ctx);
6878 }
6879 break;
6880 case 2: /* stxsd */
6881 if (ctx->insns_flags2 & PPC2_ISA300) {
6882 return gen_stxsd(ctx);
6883 }
6884 break;
6885 case 3: /* stxssp */
6886 if (ctx->insns_flags2 & PPC2_ISA300) {
6887 return gen_stxssp(ctx);
6888 }
6889 break;
6890 }
6891 }
6892 return gen_invalid(ctx);
6893 }
6894
6895 static opcode_t opcodes[] = {
6896 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
6897 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
6898 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6899 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER),
6900 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6901 #if defined(TARGET_PPC64)
6902 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
6903 #endif
6904 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
6905 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
6906 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
6907 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6908 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6909 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6910 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6911 GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6912 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
6913 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
6914 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
6915 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
6916 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6917 #if defined(TARGET_PPC64)
6918 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
6919 #endif
6920 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
6921 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
6922 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6923 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6924 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6925 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
6926 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300),
6927 GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300),
6928 GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
6929 GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300),
6930 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
6931 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
6932 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6933 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6934 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6935 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6936 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
6937 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
6938 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
6939 #if defined(TARGET_PPC64)
6940 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
6941 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
6942 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300),
6943 GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300),
6944 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
6945 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
6946 #endif
6947 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6948 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6949 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6950 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
6951 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
6952 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
6953 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
6954 #if defined(TARGET_PPC64)
6955 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
6956 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
6957 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
6958 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
6959 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
6960 GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000,
6961 PPC_NONE, PPC2_ISA300),
6962 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
6963 PPC_NONE, PPC2_ISA300),
6964 #endif
6965 #if defined(TARGET_PPC64)
6966 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
6967 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
6968 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
6969 #endif
6970 /* handles lfdp, lxsd, lxssp */
6971 GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
6972 /* handles stfdp, lxv, stxsd, stxssp, stxv */
6973 GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
6974 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6975 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6976 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
6977 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
6978 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
6979 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
6980 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO),
6981 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
6982 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6983 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6984 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
6985 GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300),
6986 GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300),
6987 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6988 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6989 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
6990 #if defined(TARGET_PPC64)
6991 GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300),
6992 GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300),
6993 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
6994 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
6995 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
6996 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
6997 #endif
6998 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
6999 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
7000 GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300),
7001 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
7002 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
7003 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
7004 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
7005 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207),
7006 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
7007 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
7008 #if defined(TARGET_PPC64)
7009 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
7010 GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300),
7011 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
7012 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
7013 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
7014 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
7015 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
7016 #endif
7017 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
7018 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
7019 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
7020 #if defined(TARGET_PPC64)
7021 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
7022 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
7023 #endif
7024 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
7025 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
7026 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
7027 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
7028 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
7029 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
7030 #if defined(TARGET_PPC64)
7031 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
7032 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300),
7033 GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300),
7034 #endif
7035 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
7036 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
7037 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
7038 GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206),
7039 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
7040 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
7041 GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206),
7042 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
7043 GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206),
7044 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
7045 GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206),
7046 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
7047 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
7048 GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206),
7049 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
7050 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC),
7051 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
7052 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
7053 GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206),
7054 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
7055 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
7056 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
7057 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
7058 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
7059 #if defined(TARGET_PPC64)
7060 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
7061 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
7062 PPC_SEGMENT_64B),
7063 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
7064 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
7065 PPC_SEGMENT_64B),
7066 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
7067 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
7068 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
7069 GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
7070 #endif
7071 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
7072 /*
7073 * XXX Those instructions will need to be handled differently for
7074 * different ISA versions
7075 */
7076 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
7077 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
7078 GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300),
7079 GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300),
7080 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
7081 #if defined(TARGET_PPC64)
7082 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
7083 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
7084 GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300),
7085 GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
7086 #endif
7087 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
7088 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
7089 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
7090 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
7091 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
7092 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
7093 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
7094 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
7095 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
7096 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
7097 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
7098 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
7099 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
7100 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
7101 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
7102 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
7103 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
7104 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
7105 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
7106 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
7107 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
7108 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
7109 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
7110 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
7111 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
7112 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
7113 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
7114 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
7115 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
7116 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
7117 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
7118 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
7119 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
7120 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
7121 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
7122 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
7123 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
7124 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
7125 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
7126 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
7127 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
7128 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
7129 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
7130 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
7131 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
7132 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
7133 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
7134 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
7135 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
7136 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
7137 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
7138 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
7139 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
7140 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
7141 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
7142 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
7143 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
7144 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
7145 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
7146 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
7147 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
7148 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
7149 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
7150 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
7151 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
7152 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
7153 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
7154 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
7155 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
7156 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
7157 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
7158 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
7159 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
7160 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
7161 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
7162 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
7163 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
7164 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
7165 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
7166 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
7167 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
7168 PPC_NONE, PPC2_BOOKE206),
7169 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
7170 PPC_NONE, PPC2_BOOKE206),
7171 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
7172 PPC_NONE, PPC2_BOOKE206),
7173 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
7174 PPC_NONE, PPC2_BOOKE206),
7175 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
7176 PPC_NONE, PPC2_BOOKE206),
7177 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
7178 PPC_NONE, PPC2_PRCNTL),
7179 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
7180 PPC_NONE, PPC2_PRCNTL),
7181 GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000,
7182 PPC_NONE, PPC2_PRCNTL),
7183 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
7184 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
7185 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
7186 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
7187 PPC_BOOKE, PPC2_BOOKE206),
7188 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE),
7189 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
7190 PPC_BOOKE, PPC2_BOOKE206),
7191 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001,
7192 PPC_440_SPEC),
7193 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
7194 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
7195 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
7196 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
7197 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
7198 #if defined(TARGET_PPC64)
7199 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE,
7200 PPC2_ISA300),
7201 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
7202 #endif
7203
7204 #undef GEN_INT_ARITH_ADD
7205 #undef GEN_INT_ARITH_ADD_CONST
7206 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
7207 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
7208 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
7209 add_ca, compute_ca, compute_ov) \
7210 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
7211 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
7212 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
7213 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
7214 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
7215 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
7216 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
7217 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
7218 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
7219 GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300),
7220 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
7221 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
7222
7223 #undef GEN_INT_ARITH_DIVW
7224 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
7225 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
7226 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
7227 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
7228 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
7229 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
7230 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
7231 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
7232 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
7233 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
7234 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
7235 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
7236
7237 #if defined(TARGET_PPC64)
7238 #undef GEN_INT_ARITH_DIVD
7239 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
7240 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
7241 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
7242 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
7243 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
7244 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
7245
7246 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
7247 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
7248 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
7249 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
7250 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
7251 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
7252
7253 #undef GEN_INT_ARITH_MUL_HELPER
7254 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
7255 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
7256 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
7257 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
7258 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
7259 #endif
7260
7261 #undef GEN_INT_ARITH_SUBF
7262 #undef GEN_INT_ARITH_SUBF_CONST
7263 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
7264 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
7265 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
7266 add_ca, compute_ca, compute_ov) \
7267 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
7268 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
7269 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
7270 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
7271 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
7272 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
7273 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
7274 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
7275 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
7276 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
7277 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
7278
7279 #undef GEN_LOGICAL1
7280 #undef GEN_LOGICAL2
7281 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
7282 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
7283 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
7284 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
7285 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
7286 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
7287 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
7288 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
7289 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
7290 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
7291 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
7292 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
7293 #if defined(TARGET_PPC64)
7294 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
7295 #endif
7296
7297 #if defined(TARGET_PPC64)
7298 #undef GEN_PPC64_R2
7299 #undef GEN_PPC64_R4
7300 #define GEN_PPC64_R2(name, opc1, opc2) \
7301 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
7302 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
7303 PPC_64B)
7304 #define GEN_PPC64_R4(name, opc1, opc2) \
7305 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
7306 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
7307 PPC_64B), \
7308 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
7309 PPC_64B), \
7310 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
7311 PPC_64B)
7312 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
7313 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
7314 GEN_PPC64_R4(rldic, 0x1E, 0x04),
7315 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
7316 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
7317 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
7318 #endif
7319
7320 #undef GEN_LD
7321 #undef GEN_LDU
7322 #undef GEN_LDUX
7323 #undef GEN_LDX_E
7324 #undef GEN_LDS
7325 #define GEN_LD(name, ldop, opc, type) \
7326 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
7327 #define GEN_LDU(name, ldop, opc, type) \
7328 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
7329 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
7330 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
7331 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
7332 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
7333 #define GEN_LDS(name, ldop, op, type) \
7334 GEN_LD(name, ldop, op | 0x20, type) \
7335 GEN_LDU(name, ldop, op | 0x21, type) \
7336 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
7337 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
7338
7339 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
7340 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
7341 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
7342 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
7343 #if defined(TARGET_PPC64)
7344 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
7345 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
7346 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B)
7347 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B)
7348 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE)
7349
7350 /* HV/P7 and later only */
7351 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
7352 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST)
7353 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
7354 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
7355 #endif
7356 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
7357 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
7358
7359 /* External PID based load */
7360 #undef GEN_LDEPX
7361 #define GEN_LDEPX(name, ldop, opc2, opc3) \
7362 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \
7363 0x00000001, PPC_NONE, PPC2_BOOKE206),
7364
7365 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02)
7366 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08)
7367 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00)
7368 #if defined(TARGET_PPC64)
7369 GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00)
7370 #endif
7371
7372 #undef GEN_ST
7373 #undef GEN_STU
7374 #undef GEN_STUX
7375 #undef GEN_STX_E
7376 #undef GEN_STS
7377 #define GEN_ST(name, stop, opc, type) \
7378 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
7379 #define GEN_STU(name, stop, opc, type) \
7380 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
7381 #define GEN_STUX(name, stop, opc2, opc3, type) \
7382 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
7383 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
7384 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2),
7385 #define GEN_STS(name, stop, op, type) \
7386 GEN_ST(name, stop, op | 0x20, type) \
7387 GEN_STU(name, stop, op | 0x21, type) \
7388 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
7389 GEN_STX(name, stop, 0x17, op | 0x00, type)
7390
7391 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
7392 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
7393 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
7394 #if defined(TARGET_PPC64)
7395 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B)
7396 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B)
7397 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
7398 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
7399 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
7400 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
7401 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
7402 #endif
7403 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
7404 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
7405
7406 #undef GEN_STEPX
7407 #define GEN_STEPX(name, ldop, opc2, opc3) \
7408 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \
7409 0x00000001, PPC_NONE, PPC2_BOOKE206),
7410
7411 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06)
7412 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C)
7413 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04)
7414 #if defined(TARGET_PPC64)
7415 GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1D, 0x04)
7416 #endif
7417
7418 #undef GEN_CRLOGIC
7419 #define GEN_CRLOGIC(name, tcg_op, opc) \
7420 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
7421 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
7422 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
7423 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
7424 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
7425 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
7426 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
7427 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
7428 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
7429
7430 #undef GEN_MAC_HANDLER
7431 #define GEN_MAC_HANDLER(name, opc2, opc3) \
7432 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
7433 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
7434 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
7435 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
7436 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
7437 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
7438 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
7439 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
7440 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
7441 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
7442 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
7443 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
7444 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
7445 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
7446 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
7447 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
7448 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
7449 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
7450 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
7451 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
7452 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
7453 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
7454 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
7455 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
7456 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
7457 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
7458 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
7459 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
7460 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
7461 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
7462 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
7463 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
7464 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
7465 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
7466 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
7467 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
7468 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
7469 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
7470 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
7471 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
7472 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
7473 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
7474 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
7475
7476 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
7477 PPC_NONE, PPC2_TM),
7478 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
7479 PPC_NONE, PPC2_TM),
7480 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
7481 PPC_NONE, PPC2_TM),
7482 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
7483 PPC_NONE, PPC2_TM),
7484 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
7485 PPC_NONE, PPC2_TM),
7486 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
7487 PPC_NONE, PPC2_TM),
7488 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
7489 PPC_NONE, PPC2_TM),
7490 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
7491 PPC_NONE, PPC2_TM),
7492 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
7493 PPC_NONE, PPC2_TM),
7494 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
7495 PPC_NONE, PPC2_TM),
7496 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
7497 PPC_NONE, PPC2_TM),
7498
7499 #include "translate/fp-ops.inc.c"
7500
7501 #include "translate/vmx-ops.inc.c"
7502
7503 #include "translate/vsx-ops.inc.c"
7504
7505 #include "translate/dfp-ops.inc.c"
7506
7507 #include "translate/spe-ops.inc.c"
7508 };
7509
7510 #include "helper_regs.h"
7511 #include "translate_init.inc.c"
7512
7513 /*****************************************************************************/
7514 /* Misc PowerPC helpers */
7515 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
7516 {
7517 #define RGPL 4
7518 #define RFPL 4
7519
7520 PowerPCCPU *cpu = POWERPC_CPU(cs);
7521 CPUPPCState *env = &cpu->env;
7522 int i;
7523
7524 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
7525 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
7526 env->nip, env->lr, env->ctr, cpu_read_xer(env),
7527 cs->cpu_index);
7528 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
7529 TARGET_FMT_lx " iidx %d didx %d\n",
7530 env->msr, env->spr[SPR_HID0],
7531 env->hflags, env->immu_idx, env->dmmu_idx);
7532 #if !defined(NO_TIMER_DUMP)
7533 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
7534 #if !defined(CONFIG_USER_ONLY)
7535 " DECR " TARGET_FMT_lu
7536 #endif
7537 "\n",
7538 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
7539 #if !defined(CONFIG_USER_ONLY)
7540 , cpu_ppc_load_decr(env)
7541 #endif
7542 );
7543 #endif
7544 for (i = 0; i < 32; i++) {
7545 if ((i & (RGPL - 1)) == 0) {
7546 qemu_fprintf(f, "GPR%02d", i);
7547 }
7548 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
7549 if ((i & (RGPL - 1)) == (RGPL - 1)) {
7550 qemu_fprintf(f, "\n");
7551 }
7552 }
7553 qemu_fprintf(f, "CR ");
7554 for (i = 0; i < 8; i++)
7555 qemu_fprintf(f, "%01x", env->crf[i]);
7556 qemu_fprintf(f, " [");
7557 for (i = 0; i < 8; i++) {
7558 char a = '-';
7559 if (env->crf[i] & 0x08) {
7560 a = 'L';
7561 } else if (env->crf[i] & 0x04) {
7562 a = 'G';
7563 } else if (env->crf[i] & 0x02) {
7564 a = 'E';
7565 }
7566 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
7567 }
7568 qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
7569 env->reserve_addr);
7570
7571 if (flags & CPU_DUMP_FPU) {
7572 for (i = 0; i < 32; i++) {
7573 if ((i & (RFPL - 1)) == 0) {
7574 qemu_fprintf(f, "FPR%02d", i);
7575 }
7576 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i));
7577 if ((i & (RFPL - 1)) == (RFPL - 1)) {
7578 qemu_fprintf(f, "\n");
7579 }
7580 }
7581 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
7582 }
7583
7584 #if !defined(CONFIG_USER_ONLY)
7585 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
7586 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
7587 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
7588 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
7589
7590 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
7591 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
7592 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
7593 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
7594
7595 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
7596 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
7597 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
7598 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
7599
7600 #if defined(TARGET_PPC64)
7601 if (env->excp_model == POWERPC_EXCP_POWER7 ||
7602 env->excp_model == POWERPC_EXCP_POWER8 ||
7603 env->excp_model == POWERPC_EXCP_POWER9) {
7604 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
7605 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
7606 }
7607 #endif
7608 if (env->excp_model == POWERPC_EXCP_BOOKE) {
7609 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
7610 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
7611 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
7612 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
7613
7614 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
7615 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
7616 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
7617 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
7618
7619 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
7620 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
7621 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
7622 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
7623
7624 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
7625 " EPR " TARGET_FMT_lx "\n",
7626 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
7627 env->spr[SPR_BOOKE_EPR]);
7628
7629 /* FSL-specific */
7630 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
7631 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
7632 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
7633 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
7634
7635 /*
7636 * IVORs are left out as they are large and do not change often --
7637 * they can be read with "p $ivor0", "p $ivor1", etc.
7638 */
7639 }
7640
7641 #if defined(TARGET_PPC64)
7642 if (env->flags & POWERPC_FLAG_CFAR) {
7643 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
7644 }
7645 #endif
7646
7647 if (env->spr_cb[SPR_LPCR].name) {
7648 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
7649 }
7650
7651 switch (env->mmu_model) {
7652 case POWERPC_MMU_32B:
7653 case POWERPC_MMU_601:
7654 case POWERPC_MMU_SOFT_6xx:
7655 case POWERPC_MMU_SOFT_74xx:
7656 #if defined(TARGET_PPC64)
7657 case POWERPC_MMU_64B:
7658 case POWERPC_MMU_2_03:
7659 case POWERPC_MMU_2_06:
7660 case POWERPC_MMU_2_07:
7661 case POWERPC_MMU_3_00:
7662 #endif
7663 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
7664 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
7665 }
7666 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */
7667 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]);
7668 }
7669 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n",
7670 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
7671 break;
7672 case POWERPC_MMU_BOOKE206:
7673 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
7674 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
7675 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
7676 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
7677
7678 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
7679 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
7680 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
7681 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
7682
7683 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
7684 " TLB1CFG " TARGET_FMT_lx "\n",
7685 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
7686 env->spr[SPR_BOOKE_TLB1CFG]);
7687 break;
7688 default:
7689 break;
7690 }
7691 #endif
7692
7693 #undef RGPL
7694 #undef RFPL
7695 }
7696
7697 void ppc_cpu_dump_statistics(CPUState *cs, int flags)
7698 {
7699 #if defined(DO_PPC_STATISTICS)
7700 PowerPCCPU *cpu = POWERPC_CPU(cs);
7701 opc_handler_t **t1, **t2, **t3, *handler;
7702 int op1, op2, op3;
7703
7704 t1 = cpu->env.opcodes;
7705 for (op1 = 0; op1 < 64; op1++) {
7706 handler = t1[op1];
7707 if (is_indirect_opcode(handler)) {
7708 t2 = ind_table(handler);
7709 for (op2 = 0; op2 < 32; op2++) {
7710 handler = t2[op2];
7711 if (is_indirect_opcode(handler)) {
7712 t3 = ind_table(handler);
7713 for (op3 = 0; op3 < 32; op3++) {
7714 handler = t3[op3];
7715 if (handler->count == 0) {
7716 continue;
7717 }
7718 qemu_printf("%02x %02x %02x (%02x %04d) %16s: "
7719 "%016" PRIx64 " %" PRId64 "\n",
7720 op1, op2, op3, op1, (op3 << 5) | op2,
7721 handler->oname,
7722 handler->count, handler->count);
7723 }
7724 } else {
7725 if (handler->count == 0) {
7726 continue;
7727 }
7728 qemu_printf("%02x %02x (%02x %04d) %16s: "
7729 "%016" PRIx64 " %" PRId64 "\n",
7730 op1, op2, op1, op2, handler->oname,
7731 handler->count, handler->count);
7732 }
7733 }
7734 } else {
7735 if (handler->count == 0) {
7736 continue;
7737 }
7738 qemu_printf("%02x (%02x ) %16s: %016" PRIx64
7739 " %" PRId64 "\n",
7740 op1, op1, handler->oname,
7741 handler->count, handler->count);
7742 }
7743 }
7744 #endif
7745 }
7746
7747 static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
7748 {
7749 DisasContext *ctx = container_of(dcbase, DisasContext, base);
7750 CPUPPCState *env = cs->env_ptr;
7751 int bound;
7752
7753 ctx->exception = POWERPC_EXCP_NONE;
7754 ctx->spr_cb = env->spr_cb;
7755 ctx->pr = msr_pr;
7756 ctx->mem_idx = env->dmmu_idx;
7757 ctx->dr = msr_dr;
7758 #if !defined(CONFIG_USER_ONLY)
7759 ctx->hv = msr_hv || !env->has_hv_mode;
7760 #endif
7761 ctx->insns_flags = env->insns_flags;
7762 ctx->insns_flags2 = env->insns_flags2;
7763 ctx->access_type = -1;
7764 ctx->need_access_type = !(env->mmu_model & POWERPC_MMU_64B);
7765 ctx->le_mode = !!(env->hflags & (1 << MSR_LE));
7766 ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE;
7767 ctx->flags = env->flags;
7768 #if defined(TARGET_PPC64)
7769 ctx->sf_mode = msr_is_64bit(env, env->msr);
7770 ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
7771 #endif
7772 ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B
7773 || env->mmu_model == POWERPC_MMU_601
7774 || (env->mmu_model & POWERPC_MMU_64B);
7775
7776 ctx->fpu_enabled = !!msr_fp;
7777 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) {
7778 ctx->spe_enabled = !!msr_spe;
7779 } else {
7780 ctx->spe_enabled = false;
7781 }
7782 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) {
7783 ctx->altivec_enabled = !!msr_vr;
7784 } else {
7785 ctx->altivec_enabled = false;
7786 }
7787 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
7788 ctx->vsx_enabled = !!msr_vsx;
7789 } else {
7790 ctx->vsx_enabled = false;
7791 }
7792 #if defined(TARGET_PPC64)
7793 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
7794 ctx->tm_enabled = !!msr_tm;
7795 } else {
7796 ctx->tm_enabled = false;
7797 }
7798 #endif
7799 ctx->gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE);
7800 if ((env->flags & POWERPC_FLAG_SE) && msr_se) {
7801 ctx->singlestep_enabled = CPU_SINGLE_STEP;
7802 } else {
7803 ctx->singlestep_enabled = 0;
7804 }
7805 if ((env->flags & POWERPC_FLAG_BE) && msr_be) {
7806 ctx->singlestep_enabled |= CPU_BRANCH_STEP;
7807 }
7808 if ((env->flags & POWERPC_FLAG_DE) && msr_de) {
7809 ctx->singlestep_enabled = 0;
7810 target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0];
7811 if (dbcr0 & DBCR0_ICMP) {
7812 ctx->singlestep_enabled |= CPU_SINGLE_STEP;
7813 }
7814 if (dbcr0 & DBCR0_BRT) {
7815 ctx->singlestep_enabled |= CPU_BRANCH_STEP;
7816 }
7817
7818 }
7819 if (unlikely(ctx->base.singlestep_enabled)) {
7820 ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP;
7821 }
7822 #if defined(DO_SINGLE_STEP) && 0
7823 /* Single step trace mode */
7824 msr_se = 1;
7825 #endif
7826
7827 bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
7828 ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
7829 }
7830
7831 static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs)
7832 {
7833 }
7834
7835 static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
7836 {
7837 tcg_gen_insn_start(dcbase->pc_next);
7838 }
7839
7840 static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs,
7841 const CPUBreakpoint *bp)
7842 {
7843 DisasContext *ctx = container_of(dcbase, DisasContext, base);
7844
7845 gen_debug_exception(ctx);
7846 dcbase->is_jmp = DISAS_NORETURN;
7847 /*
7848 * The address covered by the breakpoint must be included in
7849 * [tb->pc, tb->pc + tb->size) in order to for it to be properly
7850 * cleared -- thus we increment the PC here so that the logic
7851 * setting tb->size below does the right thing.
7852 */
7853 ctx->base.pc_next += 4;
7854 return true;
7855 }
7856
7857 static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
7858 {
7859 DisasContext *ctx = container_of(dcbase, DisasContext, base);
7860 CPUPPCState *env = cs->env_ptr;
7861 opc_handler_t **table, *handler;
7862
7863 LOG_DISAS("----------------\n");
7864 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
7865 ctx->base.pc_next, ctx->mem_idx, (int)msr_ir);
7866
7867 if (unlikely(need_byteswap(ctx))) {
7868 ctx->opcode = bswap32(cpu_ldl_code(env, ctx->base.pc_next));
7869 } else {
7870 ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
7871 }
7872 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
7873 ctx->opcode, opc1(ctx->opcode), opc2(ctx->opcode),
7874 opc3(ctx->opcode), opc4(ctx->opcode),
7875 ctx->le_mode ? "little" : "big");
7876 ctx->base.pc_next += 4;
7877 table = env->opcodes;
7878 handler = table[opc1(ctx->opcode)];
7879 if (is_indirect_opcode(handler)) {
7880 table = ind_table(handler);
7881 handler = table[opc2(ctx->opcode)];
7882 if (is_indirect_opcode(handler)) {
7883 table = ind_table(handler);
7884 handler = table[opc3(ctx->opcode)];
7885 if (is_indirect_opcode(handler)) {
7886 table = ind_table(handler);
7887 handler = table[opc4(ctx->opcode)];
7888 }
7889 }
7890 }
7891 /* Is opcode *REALLY* valid ? */
7892 if (unlikely(handler->handler == &gen_invalid)) {
7893 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
7894 "%02x - %02x - %02x - %02x (%08x) "
7895 TARGET_FMT_lx " %d\n",
7896 opc1(ctx->opcode), opc2(ctx->opcode),
7897 opc3(ctx->opcode), opc4(ctx->opcode),
7898 ctx->opcode, ctx->base.pc_next - 4, (int)msr_ir);
7899 } else {
7900 uint32_t inval;
7901
7902 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE)
7903 && Rc(ctx->opcode))) {
7904 inval = handler->inval2;
7905 } else {
7906 inval = handler->inval1;
7907 }
7908
7909 if (unlikely((ctx->opcode & inval) != 0)) {
7910 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
7911 "%02x - %02x - %02x - %02x (%08x) "
7912 TARGET_FMT_lx "\n", ctx->opcode & inval,
7913 opc1(ctx->opcode), opc2(ctx->opcode),
7914 opc3(ctx->opcode), opc4(ctx->opcode),
7915 ctx->opcode, ctx->base.pc_next - 4);
7916 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
7917 ctx->base.is_jmp = DISAS_NORETURN;
7918 return;
7919 }
7920 }
7921 (*(handler->handler))(ctx);
7922 #if defined(DO_PPC_STATISTICS)
7923 handler->count++;
7924 #endif
7925 /* Check trace mode exceptions */
7926 if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP &&
7927 (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) &&
7928 ctx->exception != POWERPC_SYSCALL &&
7929 ctx->exception != POWERPC_EXCP_TRAP &&
7930 ctx->exception != POWERPC_EXCP_BRANCH)) {
7931 uint32_t excp = gen_prep_dbgex(ctx);
7932 gen_exception_nip(ctx, excp, ctx->base.pc_next);
7933 }
7934
7935 if (tcg_check_temp_count()) {
7936 qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked "
7937 "temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode),
7938 opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode);
7939 }
7940
7941 ctx->base.is_jmp = ctx->exception == POWERPC_EXCP_NONE ?
7942 DISAS_NEXT : DISAS_NORETURN;
7943 }
7944
7945 static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
7946 {
7947 DisasContext *ctx = container_of(dcbase, DisasContext, base);
7948
7949 if (ctx->exception == POWERPC_EXCP_NONE) {
7950 gen_goto_tb(ctx, 0, ctx->base.pc_next);
7951 } else if (ctx->exception != POWERPC_EXCP_BRANCH) {
7952 if (unlikely(ctx->base.singlestep_enabled)) {
7953 gen_debug_exception(ctx);
7954 }
7955 /* Generate the return instruction */
7956 tcg_gen_exit_tb(NULL, 0);
7957 }
7958 }
7959
7960 static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs)
7961 {
7962 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
7963 log_target_disas(cs, dcbase->pc_first, dcbase->tb->size);
7964 }
7965
7966 static const TranslatorOps ppc_tr_ops = {
7967 .init_disas_context = ppc_tr_init_disas_context,
7968 .tb_start = ppc_tr_tb_start,
7969 .insn_start = ppc_tr_insn_start,
7970 .breakpoint_check = ppc_tr_breakpoint_check,
7971 .translate_insn = ppc_tr_translate_insn,
7972 .tb_stop = ppc_tr_tb_stop,
7973 .disas_log = ppc_tr_disas_log,
7974 };
7975
7976 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
7977 {
7978 DisasContext ctx;
7979
7980 translator_loop(&ppc_tr_ops, &ctx.base, cs, tb, max_insns);
7981 }
7982
7983 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
7984 target_ulong *data)
7985 {
7986 env->nip = data[0];
7987 }
AR7 emulation for QEMU