?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Remove blanks before \n in output strings
[qemu/ar7.git] / hw / omap2.c
blobca088d9f5384f725d33729cba7152dabb902856f
1 /*
2 * TI OMAP processors emulation.
3 *
4 * Copyright (C) 2007-2008 Nokia Corporation
5 * Written by Andrzej Zaborowski <andrew@openedhand.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "blockdev.h"
22 #include "hw.h"
23 #include "arm-misc.h"
24 #include "omap.h"
25 #include "sysemu.h"
26 #include "qemu-timer.h"
27 #include "qemu-char.h"
28 #include "flash.h"
29 #include "soc_dma.h"
30 #include "sysbus.h"
31 #include "audio/audio.h"
32
33 /* Enhanced Audio Controller (CODEC only) */
34 struct omap_eac_s {
35 qemu_irq irq;
36
37 uint16_t sysconfig;
38 uint8_t config[4];
39 uint8_t control;
40 uint8_t address;
41 uint16_t data;
42 uint8_t vtol;
43 uint8_t vtsl;
44 uint16_t mixer;
45 uint16_t gain[4];
46 uint8_t att;
47 uint16_t max[7];
48
49 struct {
50 qemu_irq txdrq;
51 qemu_irq rxdrq;
52 uint32_t (*txrx)(void *opaque, uint32_t, int);
53 void *opaque;
54
55 #define EAC_BUF_LEN 1024
56 uint32_t rxbuf[EAC_BUF_LEN];
57 int rxoff;
58 int rxlen;
59 int rxavail;
60 uint32_t txbuf[EAC_BUF_LEN];
61 int txlen;
62 int txavail;
63
64 int enable;
65 int rate;
66
67 uint16_t config[4];
68
69 /* These need to be moved to the actual codec */
70 QEMUSoundCard card;
71 SWVoiceIn *in_voice;
72 SWVoiceOut *out_voice;
73 int hw_enable;
74 } codec;
75
76 struct {
77 uint8_t control;
78 uint16_t config;
79 } modem, bt;
80 };
81
82 static inline void omap_eac_interrupt_update(struct omap_eac_s *s)
83 {
84 qemu_set_irq(s->irq, (s->codec.config[1] >> 14) & 1); /* AURDI */
85 }
86
87 static inline void omap_eac_in_dmarequest_update(struct omap_eac_s *s)
88 {
89 qemu_set_irq(s->codec.rxdrq, (s->codec.rxavail || s->codec.rxlen) &&
90 ((s->codec.config[1] >> 12) & 1)); /* DMAREN */
91 }
92
93 static inline void omap_eac_out_dmarequest_update(struct omap_eac_s *s)
94 {
95 qemu_set_irq(s->codec.txdrq, s->codec.txlen < s->codec.txavail &&
96 ((s->codec.config[1] >> 11) & 1)); /* DMAWEN */
97 }
98
99 static inline void omap_eac_in_refill(struct omap_eac_s *s)
100 {
101 int left = MIN(EAC_BUF_LEN - s->codec.rxlen, s->codec.rxavail) << 2;
102 int start = ((s->codec.rxoff + s->codec.rxlen) & (EAC_BUF_LEN - 1)) << 2;
103 int leftwrap = MIN(left, (EAC_BUF_LEN << 2) - start);
104 int recv = 1;
105 uint8_t *buf = (uint8_t *) s->codec.rxbuf + start;
106
107 left -= leftwrap;
108 start = 0;
109 while (leftwrap && (recv = AUD_read(s->codec.in_voice, buf + start,
110 leftwrap)) > 0) { /* Be defensive */
111 start += recv;
112 leftwrap -= recv;
113 }
114 if (recv <= 0)
115 s->codec.rxavail = 0;
116 else
117 s->codec.rxavail -= start >> 2;
118 s->codec.rxlen += start >> 2;
119
120 if (recv > 0 && left > 0) {
121 start = 0;
122 while (left && (recv = AUD_read(s->codec.in_voice,
123 (uint8_t *) s->codec.rxbuf + start,
124 left)) > 0) { /* Be defensive */
125 start += recv;
126 left -= recv;
127 }
128 if (recv <= 0)
129 s->codec.rxavail = 0;
130 else
131 s->codec.rxavail -= start >> 2;
132 s->codec.rxlen += start >> 2;
133 }
134 }
135
136 static inline void omap_eac_out_empty(struct omap_eac_s *s)
137 {
138 int left = s->codec.txlen << 2;
139 int start = 0;
140 int sent = 1;
141
142 while (left && (sent = AUD_write(s->codec.out_voice,
143 (uint8_t *) s->codec.txbuf + start,
144 left)) > 0) { /* Be defensive */
145 start += sent;
146 left -= sent;
147 }
148
149 if (!sent) {
150 s->codec.txavail = 0;
151 omap_eac_out_dmarequest_update(s);
152 }
153
154 if (start)
155 s->codec.txlen = 0;
156 }
157
158 static void omap_eac_in_cb(void *opaque, int avail_b)
159 {
160 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
161
162 s->codec.rxavail = avail_b >> 2;
163 omap_eac_in_refill(s);
164 /* TODO: possibly discard current buffer if overrun */
165 omap_eac_in_dmarequest_update(s);
166 }
167
168 static void omap_eac_out_cb(void *opaque, int free_b)
169 {
170 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
171
172 s->codec.txavail = free_b >> 2;
173 if (s->codec.txlen)
174 omap_eac_out_empty(s);
175 else
176 omap_eac_out_dmarequest_update(s);
177 }
178
179 static void omap_eac_enable_update(struct omap_eac_s *s)
180 {
181 s->codec.enable = !(s->codec.config[1] & 1) && /* EACPWD */
182 (s->codec.config[1] & 2) && /* AUDEN */
183 s->codec.hw_enable;
184 }
185
186 static const int omap_eac_fsint[4] = {
187 8000,
188 11025,
189 22050,
190 44100,
191 };
192
193 static const int omap_eac_fsint2[8] = {
194 8000,
195 11025,
196 22050,
197 44100,
198 48000,
199 0, 0, 0,
200 };
201
202 static const int omap_eac_fsint3[16] = {
203 8000,
204 11025,
205 16000,
206 22050,
207 24000,
208 32000,
209 44100,
210 48000,
211 0, 0, 0, 0, 0, 0, 0, 0,
212 };
213
214 static void omap_eac_rate_update(struct omap_eac_s *s)
215 {
216 int fsint[3];
217
218 fsint[2] = (s->codec.config[3] >> 9) & 0xf;
219 fsint[1] = (s->codec.config[2] >> 0) & 0x7;
220 fsint[0] = (s->codec.config[0] >> 6) & 0x3;
221 if (fsint[2] < 0xf)
222 s->codec.rate = omap_eac_fsint3[fsint[2]];
223 else if (fsint[1] < 0x7)
224 s->codec.rate = omap_eac_fsint2[fsint[1]];
225 else
226 s->codec.rate = omap_eac_fsint[fsint[0]];
227 }
228
229 static void omap_eac_volume_update(struct omap_eac_s *s)
230 {
231 /* TODO */
232 }
233
234 static void omap_eac_format_update(struct omap_eac_s *s)
235 {
236 struct audsettings fmt;
237
238 /* The hardware buffers at most one sample */
239 if (s->codec.rxlen)
240 s->codec.rxlen = 1;
241
242 if (s->codec.in_voice) {
243 AUD_set_active_in(s->codec.in_voice, 0);
244 AUD_close_in(&s->codec.card, s->codec.in_voice);
245 s->codec.in_voice = NULL;
246 }
247 if (s->codec.out_voice) {
248 omap_eac_out_empty(s);
249 AUD_set_active_out(s->codec.out_voice, 0);
250 AUD_close_out(&s->codec.card, s->codec.out_voice);
251 s->codec.out_voice = NULL;
252 s->codec.txavail = 0;
253 }
254 /* Discard what couldn't be written */
255 s->codec.txlen = 0;
256
257 omap_eac_enable_update(s);
258 if (!s->codec.enable)
259 return;
260
261 omap_eac_rate_update(s);
262 fmt.endianness = ((s->codec.config[0] >> 8) & 1); /* LI_BI */
263 fmt.nchannels = ((s->codec.config[0] >> 10) & 1) ? 2 : 1; /* MN_ST */
264 fmt.freq = s->codec.rate;
265 /* TODO: signedness possibly depends on the CODEC hardware - or
266 * does I2S specify it? */
267 /* All register writes are 16 bits so we we store 16-bit samples
268 * in the buffers regardless of AGCFR[B8_16] value. */
269 fmt.fmt = AUD_FMT_U16;
270
271 s->codec.in_voice = AUD_open_in(&s->codec.card, s->codec.in_voice,
272 "eac.codec.in", s, omap_eac_in_cb, &fmt);
273 s->codec.out_voice = AUD_open_out(&s->codec.card, s->codec.out_voice,
274 "eac.codec.out", s, omap_eac_out_cb, &fmt);
275
276 omap_eac_volume_update(s);
277
278 AUD_set_active_in(s->codec.in_voice, 1);
279 AUD_set_active_out(s->codec.out_voice, 1);
280 }
281
282 static void omap_eac_reset(struct omap_eac_s *s)
283 {
284 s->sysconfig = 0;
285 s->config[0] = 0x0c;
286 s->config[1] = 0x09;
287 s->config[2] = 0xab;
288 s->config[3] = 0x03;
289 s->control = 0x00;
290 s->address = 0x00;
291 s->data = 0x0000;
292 s->vtol = 0x00;
293 s->vtsl = 0x00;
294 s->mixer = 0x0000;
295 s->gain[0] = 0xe7e7;
296 s->gain[1] = 0x6767;
297 s->gain[2] = 0x6767;
298 s->gain[3] = 0x6767;
299 s->att = 0xce;
300 s->max[0] = 0;
301 s->max[1] = 0;
302 s->max[2] = 0;
303 s->max[3] = 0;
304 s->max[4] = 0;
305 s->max[5] = 0;
306 s->max[6] = 0;
307
308 s->modem.control = 0x00;
309 s->modem.config = 0x0000;
310 s->bt.control = 0x00;
311 s->bt.config = 0x0000;
312 s->codec.config[0] = 0x0649;
313 s->codec.config[1] = 0x0000;
314 s->codec.config[2] = 0x0007;
315 s->codec.config[3] = 0x1ffc;
316 s->codec.rxoff = 0;
317 s->codec.rxlen = 0;
318 s->codec.txlen = 0;
319 s->codec.rxavail = 0;
320 s->codec.txavail = 0;
321
322 omap_eac_format_update(s);
323 omap_eac_interrupt_update(s);
324 }
325
326 static uint32_t omap_eac_read(void *opaque, target_phys_addr_t addr)
327 {
328 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
329 uint32_t ret;
330
331 switch (addr) {
332 case 0x000: /* CPCFR1 */
333 return s->config[0];
334 case 0x004: /* CPCFR2 */
335 return s->config[1];
336 case 0x008: /* CPCFR3 */
337 return s->config[2];
338 case 0x00c: /* CPCFR4 */
339 return s->config[3];
340
341 case 0x010: /* CPTCTL */
342 return s->control | ((s->codec.rxavail + s->codec.rxlen > 0) << 7) |
343 ((s->codec.txlen < s->codec.txavail) << 5);
344
345 case 0x014: /* CPTTADR */
346 return s->address;
347 case 0x018: /* CPTDATL */
348 return s->data & 0xff;
349 case 0x01c: /* CPTDATH */
350 return s->data >> 8;
351 case 0x020: /* CPTVSLL */
352 return s->vtol;
353 case 0x024: /* CPTVSLH */
354 return s->vtsl | (3 << 5); /* CRDY1 | CRDY2 */
355 case 0x040: /* MPCTR */
356 return s->modem.control;
357 case 0x044: /* MPMCCFR */
358 return s->modem.config;
359 case 0x060: /* BPCTR */
360 return s->bt.control;
361 case 0x064: /* BPMCCFR */
362 return s->bt.config;
363 case 0x080: /* AMSCFR */
364 return s->mixer;
365 case 0x084: /* AMVCTR */
366 return s->gain[0];
367 case 0x088: /* AM1VCTR */
368 return s->gain[1];
369 case 0x08c: /* AM2VCTR */
370 return s->gain[2];
371 case 0x090: /* AM3VCTR */
372 return s->gain[3];
373 case 0x094: /* ASTCTR */
374 return s->att;
375 case 0x098: /* APD1LCR */
376 return s->max[0];
377 case 0x09c: /* APD1RCR */
378 return s->max[1];
379 case 0x0a0: /* APD2LCR */
380 return s->max[2];
381 case 0x0a4: /* APD2RCR */
382 return s->max[3];
383 case 0x0a8: /* APD3LCR */
384 return s->max[4];
385 case 0x0ac: /* APD3RCR */
386 return s->max[5];
387 case 0x0b0: /* APD4R */
388 return s->max[6];
389 case 0x0b4: /* ADWR */
390 /* This should be write-only? Docs list it as read-only. */
391 return 0x0000;
392 case 0x0b8: /* ADRDR */
393 if (likely(s->codec.rxlen > 1)) {
394 ret = s->codec.rxbuf[s->codec.rxoff ++];
395 s->codec.rxlen --;
396 s->codec.rxoff &= EAC_BUF_LEN - 1;
397 return ret;
398 } else if (s->codec.rxlen) {
399 ret = s->codec.rxbuf[s->codec.rxoff ++];
400 s->codec.rxlen --;
401 s->codec.rxoff &= EAC_BUF_LEN - 1;
402 if (s->codec.rxavail)
403 omap_eac_in_refill(s);
404 omap_eac_in_dmarequest_update(s);
405 return ret;
406 }
407 return 0x0000;
408 case 0x0bc: /* AGCFR */
409 return s->codec.config[0];
410 case 0x0c0: /* AGCTR */
411 return s->codec.config[1] | ((s->codec.config[1] & 2) << 14);
412 case 0x0c4: /* AGCFR2 */
413 return s->codec.config[2];
414 case 0x0c8: /* AGCFR3 */
415 return s->codec.config[3];
416 case 0x0cc: /* MBPDMACTR */
417 case 0x0d0: /* MPDDMARR */
418 case 0x0d8: /* MPUDMARR */
419 case 0x0e4: /* BPDDMARR */
420 case 0x0ec: /* BPUDMARR */
421 return 0x0000;
422
423 case 0x100: /* VERSION_NUMBER */
424 return 0x0010;
425
426 case 0x104: /* SYSCONFIG */
427 return s->sysconfig;
428
429 case 0x108: /* SYSSTATUS */
430 return 1 | 0xe; /* RESETDONE | stuff */
431 }
432
433 OMAP_BAD_REG(addr);
434 return 0;
435 }
436
437 static void omap_eac_write(void *opaque, target_phys_addr_t addr,
438 uint32_t value)
439 {
440 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
441
442 switch (addr) {
443 case 0x098: /* APD1LCR */
444 case 0x09c: /* APD1RCR */
445 case 0x0a0: /* APD2LCR */
446 case 0x0a4: /* APD2RCR */
447 case 0x0a8: /* APD3LCR */
448 case 0x0ac: /* APD3RCR */
449 case 0x0b0: /* APD4R */
450 case 0x0b8: /* ADRDR */
451 case 0x0d0: /* MPDDMARR */
452 case 0x0d8: /* MPUDMARR */
453 case 0x0e4: /* BPDDMARR */
454 case 0x0ec: /* BPUDMARR */
455 case 0x100: /* VERSION_NUMBER */
456 case 0x108: /* SYSSTATUS */
457 OMAP_RO_REG(addr);
458 return;
459
460 case 0x000: /* CPCFR1 */
461 s->config[0] = value & 0xff;
462 omap_eac_format_update(s);
463 break;
464 case 0x004: /* CPCFR2 */
465 s->config[1] = value & 0xff;
466 omap_eac_format_update(s);
467 break;
468 case 0x008: /* CPCFR3 */
469 s->config[2] = value & 0xff;
470 omap_eac_format_update(s);
471 break;
472 case 0x00c: /* CPCFR4 */
473 s->config[3] = value & 0xff;
474 omap_eac_format_update(s);
475 break;
476
477 case 0x010: /* CPTCTL */
478 /* Assuming TXF and TXE bits are read-only... */
479 s->control = value & 0x5f;
480 omap_eac_interrupt_update(s);
481 break;
482
483 case 0x014: /* CPTTADR */
484 s->address = value & 0xff;
485 break;
486 case 0x018: /* CPTDATL */
487 s->data &= 0xff00;
488 s->data |= value & 0xff;
489 break;
490 case 0x01c: /* CPTDATH */
491 s->data &= 0x00ff;
492 s->data |= value << 8;
493 break;
494 case 0x020: /* CPTVSLL */
495 s->vtol = value & 0xf8;
496 break;
497 case 0x024: /* CPTVSLH */
498 s->vtsl = value & 0x9f;
499 break;
500 case 0x040: /* MPCTR */
501 s->modem.control = value & 0x8f;
502 break;
503 case 0x044: /* MPMCCFR */
504 s->modem.config = value & 0x7fff;
505 break;
506 case 0x060: /* BPCTR */
507 s->bt.control = value & 0x8f;
508 break;
509 case 0x064: /* BPMCCFR */
510 s->bt.config = value & 0x7fff;
511 break;
512 case 0x080: /* AMSCFR */
513 s->mixer = value & 0x0fff;
514 break;
515 case 0x084: /* AMVCTR */
516 s->gain[0] = value & 0xffff;
517 break;
518 case 0x088: /* AM1VCTR */
519 s->gain[1] = value & 0xff7f;
520 break;
521 case 0x08c: /* AM2VCTR */
522 s->gain[2] = value & 0xff7f;
523 break;
524 case 0x090: /* AM3VCTR */
525 s->gain[3] = value & 0xff7f;
526 break;
527 case 0x094: /* ASTCTR */
528 s->att = value & 0xff;
529 break;
530
531 case 0x0b4: /* ADWR */
532 s->codec.txbuf[s->codec.txlen ++] = value;
533 if (unlikely(s->codec.txlen == EAC_BUF_LEN ||
534 s->codec.txlen == s->codec.txavail)) {
535 if (s->codec.txavail)
536 omap_eac_out_empty(s);
537 /* Discard what couldn't be written */
538 s->codec.txlen = 0;
539 }
540 break;
541
542 case 0x0bc: /* AGCFR */
543 s->codec.config[0] = value & 0x07ff;
544 omap_eac_format_update(s);
545 break;
546 case 0x0c0: /* AGCTR */
547 s->codec.config[1] = value & 0x780f;
548 omap_eac_format_update(s);
549 break;
550 case 0x0c4: /* AGCFR2 */
551 s->codec.config[2] = value & 0x003f;
552 omap_eac_format_update(s);
553 break;
554 case 0x0c8: /* AGCFR3 */
555 s->codec.config[3] = value & 0xffff;
556 omap_eac_format_update(s);
557 break;
558 case 0x0cc: /* MBPDMACTR */
559 case 0x0d4: /* MPDDMAWR */
560 case 0x0e0: /* MPUDMAWR */
561 case 0x0e8: /* BPDDMAWR */
562 case 0x0f0: /* BPUDMAWR */
563 break;
564
565 case 0x104: /* SYSCONFIG */
566 if (value & (1 << 1)) /* SOFTRESET */
567 omap_eac_reset(s);
568 s->sysconfig = value & 0x31d;
569 break;
570
571 default:
572 OMAP_BAD_REG(addr);
573 return;
574 }
575 }
576
577 static CPUReadMemoryFunc * const omap_eac_readfn[] = {
578 omap_badwidth_read16,
579 omap_eac_read,
580 omap_badwidth_read16,
581 };
582
583 static CPUWriteMemoryFunc * const omap_eac_writefn[] = {
584 omap_badwidth_write16,
585 omap_eac_write,
586 omap_badwidth_write16,
587 };
588
589 static struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta,
590 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk)
591 {
592 int iomemtype;
593 struct omap_eac_s *s = (struct omap_eac_s *)
594 g_malloc0(sizeof(struct omap_eac_s));
595
596 s->irq = irq;
597 s->codec.rxdrq = *drq ++;
598 s->codec.txdrq = *drq;
599 omap_eac_reset(s);
600
601 AUD_register_card("OMAP EAC", &s->codec.card);
602
603 iomemtype = cpu_register_io_memory(omap_eac_readfn,
604 omap_eac_writefn, s, DEVICE_NATIVE_ENDIAN);
605 omap_l4_attach(ta, 0, iomemtype);
606
607 return s;
608 }
609
610 /* STI/XTI (emulation interface) console - reverse engineered only */
611 struct omap_sti_s {
612 qemu_irq irq;
613 CharDriverState *chr;
614
615 uint32_t sysconfig;
616 uint32_t systest;
617 uint32_t irqst;
618 uint32_t irqen;
619 uint32_t clkcontrol;
620 uint32_t serial_config;
621 };
622
623 #define STI_TRACE_CONSOLE_CHANNEL 239
624 #define STI_TRACE_CONTROL_CHANNEL 253
625
626 static inline void omap_sti_interrupt_update(struct omap_sti_s *s)
627 {
628 qemu_set_irq(s->irq, s->irqst & s->irqen);
629 }
630
631 static void omap_sti_reset(struct omap_sti_s *s)
632 {
633 s->sysconfig = 0;
634 s->irqst = 0;
635 s->irqen = 0;
636 s->clkcontrol = 0;
637 s->serial_config = 0;
638
639 omap_sti_interrupt_update(s);
640 }
641
642 static uint32_t omap_sti_read(void *opaque, target_phys_addr_t addr)
643 {
644 struct omap_sti_s *s = (struct omap_sti_s *) opaque;
645
646 switch (addr) {
647 case 0x00: /* STI_REVISION */
648 return 0x10;
649
650 case 0x10: /* STI_SYSCONFIG */
651 return s->sysconfig;
652
653 case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */
654 return 0x00;
655
656 case 0x18: /* STI_IRQSTATUS */
657 return s->irqst;
658
659 case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */
660 return s->irqen;
661
662 case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */
663 case 0x28: /* STI_RX_DR / XTI_RXDATA */
664 /* TODO */
665 return 0;
666
667 case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */
668 return s->clkcontrol;
669
670 case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */
671 return s->serial_config;
672 }
673
674 OMAP_BAD_REG(addr);
675 return 0;
676 }
677
678 static void omap_sti_write(void *opaque, target_phys_addr_t addr,
679 uint32_t value)
680 {
681 struct omap_sti_s *s = (struct omap_sti_s *) opaque;
682
683 switch (addr) {
684 case 0x00: /* STI_REVISION */
685 case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */
686 OMAP_RO_REG(addr);
687 return;
688
689 case 0x10: /* STI_SYSCONFIG */
690 if (value & (1 << 1)) /* SOFTRESET */
691 omap_sti_reset(s);
692 s->sysconfig = value & 0xfe;
693 break;
694
695 case 0x18: /* STI_IRQSTATUS */
696 s->irqst &= ~value;
697 omap_sti_interrupt_update(s);
698 break;
699
700 case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */
701 s->irqen = value & 0xffff;
702 omap_sti_interrupt_update(s);
703 break;
704
705 case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */
706 s->clkcontrol = value & 0xff;
707 break;
708
709 case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */
710 s->serial_config = value & 0xff;
711 break;
712
713 case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */
714 case 0x28: /* STI_RX_DR / XTI_RXDATA */
715 /* TODO */
716 return;
717
718 default:
719 OMAP_BAD_REG(addr);
720 return;
721 }
722 }
723
724 static CPUReadMemoryFunc * const omap_sti_readfn[] = {
725 omap_badwidth_read32,
726 omap_badwidth_read32,
727 omap_sti_read,
728 };
729
730 static CPUWriteMemoryFunc * const omap_sti_writefn[] = {
731 omap_badwidth_write32,
732 omap_badwidth_write32,
733 omap_sti_write,
734 };
735
736 static uint32_t omap_sti_fifo_read(void *opaque, target_phys_addr_t addr)
737 {
738 OMAP_BAD_REG(addr);
739 return 0;
740 }
741
742 static void omap_sti_fifo_write(void *opaque, target_phys_addr_t addr,
743 uint32_t value)
744 {
745 struct omap_sti_s *s = (struct omap_sti_s *) opaque;
746 int ch = addr >> 6;
747 uint8_t byte = value;
748
749 if (ch == STI_TRACE_CONTROL_CHANNEL) {
750 /* Flush channel <i>value</i>. */
751 qemu_chr_fe_write(s->chr, (const uint8_t *) "\r", 1);
752 } else if (ch == STI_TRACE_CONSOLE_CHANNEL || 1) {
753 if (value == 0xc0 || value == 0xc3) {
754 /* Open channel <i>ch</i>. */
755 } else if (value == 0x00)
756 qemu_chr_fe_write(s->chr, (const uint8_t *) "\n", 1);
757 else
758 qemu_chr_fe_write(s->chr, &byte, 1);
759 }
760 }
761
762 static CPUReadMemoryFunc * const omap_sti_fifo_readfn[] = {
763 omap_sti_fifo_read,
764 omap_badwidth_read8,
765 omap_badwidth_read8,
766 };
767
768 static CPUWriteMemoryFunc * const omap_sti_fifo_writefn[] = {
769 omap_sti_fifo_write,
770 omap_badwidth_write8,
771 omap_badwidth_write8,
772 };
773
774 static struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta,
775 target_phys_addr_t channel_base, qemu_irq irq, omap_clk clk,
776 CharDriverState *chr)
777 {
778 int iomemtype;
779 struct omap_sti_s *s = (struct omap_sti_s *)
780 g_malloc0(sizeof(struct omap_sti_s));
781
782 s->irq = irq;
783 omap_sti_reset(s);
784
785 s->chr = chr ?: qemu_chr_new("null", "null", NULL);
786
787 iomemtype = l4_register_io_memory(omap_sti_readfn,
788 omap_sti_writefn, s);
789 omap_l4_attach(ta, 0, iomemtype);
790
791 iomemtype = cpu_register_io_memory(omap_sti_fifo_readfn,
792 omap_sti_fifo_writefn, s, DEVICE_NATIVE_ENDIAN);
793 cpu_register_physical_memory(channel_base, 0x10000, iomemtype);
794
795 return s;
796 }
797
798 /* L4 Interconnect */
799 #define L4TA(n) (n)
800 #define L4TAO(n) ((n) + 39)
801
802 static const struct omap_l4_region_s omap_l4_region[125] = {
803 [ 1] = { 0x40800, 0x800, 32 }, /* Initiator agent */
804 [ 2] = { 0x41000, 0x1000, 32 }, /* Link agent */
805 [ 0] = { 0x40000, 0x800, 32 }, /* Address and protection */
806 [ 3] = { 0x00000, 0x1000, 32 | 16 | 8 }, /* System Control and Pinout */
807 [ 4] = { 0x01000, 0x1000, 32 | 16 | 8 }, /* L4TAO1 */
808 [ 5] = { 0x04000, 0x1000, 32 | 16 }, /* 32K Timer */
809 [ 6] = { 0x05000, 0x1000, 32 | 16 | 8 }, /* L4TAO2 */
810 [ 7] = { 0x08000, 0x800, 32 }, /* PRCM Region A */
811 [ 8] = { 0x08800, 0x800, 32 }, /* PRCM Region B */
812 [ 9] = { 0x09000, 0x1000, 32 | 16 | 8 }, /* L4TAO */
813 [ 10] = { 0x12000, 0x1000, 32 | 16 | 8 }, /* Test (BCM) */
814 [ 11] = { 0x13000, 0x1000, 32 | 16 | 8 }, /* L4TA1 */
815 [ 12] = { 0x14000, 0x1000, 32 }, /* Test/emulation (TAP) */
816 [ 13] = { 0x15000, 0x1000, 32 | 16 | 8 }, /* L4TA2 */
817 [ 14] = { 0x18000, 0x1000, 32 | 16 | 8 }, /* GPIO1 */
818 [ 16] = { 0x1a000, 0x1000, 32 | 16 | 8 }, /* GPIO2 */
819 [ 18] = { 0x1c000, 0x1000, 32 | 16 | 8 }, /* GPIO3 */
820 [ 19] = { 0x1e000, 0x1000, 32 | 16 | 8 }, /* GPIO4 */
821 [ 15] = { 0x19000, 0x1000, 32 | 16 | 8 }, /* Quad GPIO TOP */
822 [ 17] = { 0x1b000, 0x1000, 32 | 16 | 8 }, /* L4TA3 */
823 [ 20] = { 0x20000, 0x1000, 32 | 16 | 8 }, /* WD Timer 1 (Secure) */
824 [ 22] = { 0x22000, 0x1000, 32 | 16 | 8 }, /* WD Timer 2 (OMAP) */
825 [ 21] = { 0x21000, 0x1000, 32 | 16 | 8 }, /* Dual WD timer TOP */
826 [ 23] = { 0x23000, 0x1000, 32 | 16 | 8 }, /* L4TA4 */
827 [ 24] = { 0x28000, 0x1000, 32 | 16 | 8 }, /* GP Timer 1 */
828 [ 25] = { 0x29000, 0x1000, 32 | 16 | 8 }, /* L4TA7 */
829 [ 26] = { 0x48000, 0x2000, 32 | 16 | 8 }, /* Emulation (ARM11ETB) */
830 [ 27] = { 0x4a000, 0x1000, 32 | 16 | 8 }, /* L4TA9 */
831 [ 28] = { 0x50000, 0x400, 32 | 16 | 8 }, /* Display top */
832 [ 29] = { 0x50400, 0x400, 32 | 16 | 8 }, /* Display control */
833 [ 30] = { 0x50800, 0x400, 32 | 16 | 8 }, /* Display RFBI */
834 [ 31] = { 0x50c00, 0x400, 32 | 16 | 8 }, /* Display encoder */
835 [ 32] = { 0x51000, 0x1000, 32 | 16 | 8 }, /* L4TA10 */
836 [ 33] = { 0x52000, 0x400, 32 | 16 | 8 }, /* Camera top */
837 [ 34] = { 0x52400, 0x400, 32 | 16 | 8 }, /* Camera core */
838 [ 35] = { 0x52800, 0x400, 32 | 16 | 8 }, /* Camera DMA */
839 [ 36] = { 0x52c00, 0x400, 32 | 16 | 8 }, /* Camera MMU */
840 [ 37] = { 0x53000, 0x1000, 32 | 16 | 8 }, /* L4TA11 */
841 [ 38] = { 0x56000, 0x1000, 32 | 16 | 8 }, /* sDMA */
842 [ 39] = { 0x57000, 0x1000, 32 | 16 | 8 }, /* L4TA12 */
843 [ 40] = { 0x58000, 0x1000, 32 | 16 | 8 }, /* SSI top */
844 [ 41] = { 0x59000, 0x1000, 32 | 16 | 8 }, /* SSI GDD */
845 [ 42] = { 0x5a000, 0x1000, 32 | 16 | 8 }, /* SSI Port1 */
846 [ 43] = { 0x5b000, 0x1000, 32 | 16 | 8 }, /* SSI Port2 */
847 [ 44] = { 0x5c000, 0x1000, 32 | 16 | 8 }, /* L4TA13 */
848 [ 45] = { 0x5e000, 0x1000, 32 | 16 | 8 }, /* USB OTG */
849 [ 46] = { 0x5f000, 0x1000, 32 | 16 | 8 }, /* L4TAO4 */
850 [ 47] = { 0x60000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER1SDRC) */
851 [ 48] = { 0x61000, 0x1000, 32 | 16 | 8 }, /* L4TA14 */
852 [ 49] = { 0x62000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER2GPMC) */
853 [ 50] = { 0x63000, 0x1000, 32 | 16 | 8 }, /* L4TA15 */
854 [ 51] = { 0x64000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER3OCM) */
855 [ 52] = { 0x65000, 0x1000, 32 | 16 | 8 }, /* L4TA16 */
856 [ 53] = { 0x66000, 0x300, 32 | 16 | 8 }, /* Emulation (WIN_TRACER4L4) */
857 [ 54] = { 0x67000, 0x1000, 32 | 16 | 8 }, /* L4TA17 */
858 [ 55] = { 0x68000, 0x1000, 32 | 16 | 8 }, /* Emulation (XTI) */
859 [ 56] = { 0x69000, 0x1000, 32 | 16 | 8 }, /* L4TA18 */
860 [ 57] = { 0x6a000, 0x1000, 16 | 8 }, /* UART1 */
861 [ 58] = { 0x6b000, 0x1000, 32 | 16 | 8 }, /* L4TA19 */
862 [ 59] = { 0x6c000, 0x1000, 16 | 8 }, /* UART2 */
863 [ 60] = { 0x6d000, 0x1000, 32 | 16 | 8 }, /* L4TA20 */
864 [ 61] = { 0x6e000, 0x1000, 16 | 8 }, /* UART3 */
865 [ 62] = { 0x6f000, 0x1000, 32 | 16 | 8 }, /* L4TA21 */
866 [ 63] = { 0x70000, 0x1000, 16 }, /* I2C1 */
867 [ 64] = { 0x71000, 0x1000, 32 | 16 | 8 }, /* L4TAO5 */
868 [ 65] = { 0x72000, 0x1000, 16 }, /* I2C2 */
869 [ 66] = { 0x73000, 0x1000, 32 | 16 | 8 }, /* L4TAO6 */
870 [ 67] = { 0x74000, 0x1000, 16 }, /* McBSP1 */
871 [ 68] = { 0x75000, 0x1000, 32 | 16 | 8 }, /* L4TAO7 */
872 [ 69] = { 0x76000, 0x1000, 16 }, /* McBSP2 */
873 [ 70] = { 0x77000, 0x1000, 32 | 16 | 8 }, /* L4TAO8 */
874 [ 71] = { 0x24000, 0x1000, 32 | 16 | 8 }, /* WD Timer 3 (DSP) */
875 [ 72] = { 0x25000, 0x1000, 32 | 16 | 8 }, /* L4TA5 */
876 [ 73] = { 0x26000, 0x1000, 32 | 16 | 8 }, /* WD Timer 4 (IVA) */
877 [ 74] = { 0x27000, 0x1000, 32 | 16 | 8 }, /* L4TA6 */
878 [ 75] = { 0x2a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 2 */
879 [ 76] = { 0x2b000, 0x1000, 32 | 16 | 8 }, /* L4TA8 */
880 [ 77] = { 0x78000, 0x1000, 32 | 16 | 8 }, /* GP Timer 3 */
881 [ 78] = { 0x79000, 0x1000, 32 | 16 | 8 }, /* L4TA22 */
882 [ 79] = { 0x7a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 4 */
883 [ 80] = { 0x7b000, 0x1000, 32 | 16 | 8 }, /* L4TA23 */
884 [ 81] = { 0x7c000, 0x1000, 32 | 16 | 8 }, /* GP Timer 5 */
885 [ 82] = { 0x7d000, 0x1000, 32 | 16 | 8 }, /* L4TA24 */
886 [ 83] = { 0x7e000, 0x1000, 32 | 16 | 8 }, /* GP Timer 6 */
887 [ 84] = { 0x7f000, 0x1000, 32 | 16 | 8 }, /* L4TA25 */
888 [ 85] = { 0x80000, 0x1000, 32 | 16 | 8 }, /* GP Timer 7 */
889 [ 86] = { 0x81000, 0x1000, 32 | 16 | 8 }, /* L4TA26 */
890 [ 87] = { 0x82000, 0x1000, 32 | 16 | 8 }, /* GP Timer 8 */
891 [ 88] = { 0x83000, 0x1000, 32 | 16 | 8 }, /* L4TA27 */
892 [ 89] = { 0x84000, 0x1000, 32 | 16 | 8 }, /* GP Timer 9 */
893 [ 90] = { 0x85000, 0x1000, 32 | 16 | 8 }, /* L4TA28 */
894 [ 91] = { 0x86000, 0x1000, 32 | 16 | 8 }, /* GP Timer 10 */
895 [ 92] = { 0x87000, 0x1000, 32 | 16 | 8 }, /* L4TA29 */
896 [ 93] = { 0x88000, 0x1000, 32 | 16 | 8 }, /* GP Timer 11 */
897 [ 94] = { 0x89000, 0x1000, 32 | 16 | 8 }, /* L4TA30 */
898 [ 95] = { 0x8a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 12 */
899 [ 96] = { 0x8b000, 0x1000, 32 | 16 | 8 }, /* L4TA31 */
900 [ 97] = { 0x90000, 0x1000, 16 }, /* EAC */
901 [ 98] = { 0x91000, 0x1000, 32 | 16 | 8 }, /* L4TA32 */
902 [ 99] = { 0x92000, 0x1000, 16 }, /* FAC */
903 [100] = { 0x93000, 0x1000, 32 | 16 | 8 }, /* L4TA33 */
904 [101] = { 0x94000, 0x1000, 32 | 16 | 8 }, /* IPC (MAILBOX) */
905 [102] = { 0x95000, 0x1000, 32 | 16 | 8 }, /* L4TA34 */
906 [103] = { 0x98000, 0x1000, 32 | 16 | 8 }, /* SPI1 */
907 [104] = { 0x99000, 0x1000, 32 | 16 | 8 }, /* L4TA35 */
908 [105] = { 0x9a000, 0x1000, 32 | 16 | 8 }, /* SPI2 */
909 [106] = { 0x9b000, 0x1000, 32 | 16 | 8 }, /* L4TA36 */
910 [107] = { 0x9c000, 0x1000, 16 | 8 }, /* MMC SDIO */
911 [108] = { 0x9d000, 0x1000, 32 | 16 | 8 }, /* L4TAO9 */
912 [109] = { 0x9e000, 0x1000, 32 | 16 | 8 }, /* MS_PRO */
913 [110] = { 0x9f000, 0x1000, 32 | 16 | 8 }, /* L4TAO10 */
914 [111] = { 0xa0000, 0x1000, 32 }, /* RNG */
915 [112] = { 0xa1000, 0x1000, 32 | 16 | 8 }, /* L4TAO11 */
916 [113] = { 0xa2000, 0x1000, 32 }, /* DES3DES */
917 [114] = { 0xa3000, 0x1000, 32 | 16 | 8 }, /* L4TAO12 */
918 [115] = { 0xa4000, 0x1000, 32 }, /* SHA1MD5 */
919 [116] = { 0xa5000, 0x1000, 32 | 16 | 8 }, /* L4TAO13 */
920 [117] = { 0xa6000, 0x1000, 32 }, /* AES */
921 [118] = { 0xa7000, 0x1000, 32 | 16 | 8 }, /* L4TA37 */
922 [119] = { 0xa8000, 0x2000, 32 }, /* PKA */
923 [120] = { 0xaa000, 0x1000, 32 | 16 | 8 }, /* L4TA38 */
924 [121] = { 0xb0000, 0x1000, 32 }, /* MG */
925 [122] = { 0xb1000, 0x1000, 32 | 16 | 8 },
926 [123] = { 0xb2000, 0x1000, 32 }, /* HDQ/1-Wire */
927 [124] = { 0xb3000, 0x1000, 32 | 16 | 8 }, /* L4TA39 */
928 };
929
930 static const struct omap_l4_agent_info_s omap_l4_agent_info[54] = {
931 { 0, 0, 3, 2 }, /* L4IA initiatior agent */
932 { L4TAO(1), 3, 2, 1 }, /* Control and pinout module */
933 { L4TAO(2), 5, 2, 1 }, /* 32K timer */
934 { L4TAO(3), 7, 3, 2 }, /* PRCM */
935 { L4TA(1), 10, 2, 1 }, /* BCM */
936 { L4TA(2), 12, 2, 1 }, /* Test JTAG */
937 { L4TA(3), 14, 6, 3 }, /* Quad GPIO */
938 { L4TA(4), 20, 4, 3 }, /* WD timer 1/2 */
939 { L4TA(7), 24, 2, 1 }, /* GP timer 1 */
940 { L4TA(9), 26, 2, 1 }, /* ATM11 ETB */
941 { L4TA(10), 28, 5, 4 }, /* Display subsystem */
942 { L4TA(11), 33, 5, 4 }, /* Camera subsystem */
943 { L4TA(12), 38, 2, 1 }, /* sDMA */
944 { L4TA(13), 40, 5, 4 }, /* SSI */
945 { L4TAO(4), 45, 2, 1 }, /* USB */
946 { L4TA(14), 47, 2, 1 }, /* Win Tracer1 */
947 { L4TA(15), 49, 2, 1 }, /* Win Tracer2 */
948 { L4TA(16), 51, 2, 1 }, /* Win Tracer3 */
949 { L4TA(17), 53, 2, 1 }, /* Win Tracer4 */
950 { L4TA(18), 55, 2, 1 }, /* XTI */
951 { L4TA(19), 57, 2, 1 }, /* UART1 */
952 { L4TA(20), 59, 2, 1 }, /* UART2 */
953 { L4TA(21), 61, 2, 1 }, /* UART3 */
954 { L4TAO(5), 63, 2, 1 }, /* I2C1 */
955 { L4TAO(6), 65, 2, 1 }, /* I2C2 */
956 { L4TAO(7), 67, 2, 1 }, /* McBSP1 */
957 { L4TAO(8), 69, 2, 1 }, /* McBSP2 */
958 { L4TA(5), 71, 2, 1 }, /* WD Timer 3 (DSP) */
959 { L4TA(6), 73, 2, 1 }, /* WD Timer 4 (IVA) */
960 { L4TA(8), 75, 2, 1 }, /* GP Timer 2 */
961 { L4TA(22), 77, 2, 1 }, /* GP Timer 3 */
962 { L4TA(23), 79, 2, 1 }, /* GP Timer 4 */
963 { L4TA(24), 81, 2, 1 }, /* GP Timer 5 */
964 { L4TA(25), 83, 2, 1 }, /* GP Timer 6 */
965 { L4TA(26), 85, 2, 1 }, /* GP Timer 7 */
966 { L4TA(27), 87, 2, 1 }, /* GP Timer 8 */
967 { L4TA(28), 89, 2, 1 }, /* GP Timer 9 */
968 { L4TA(29), 91, 2, 1 }, /* GP Timer 10 */
969 { L4TA(30), 93, 2, 1 }, /* GP Timer 11 */
970 { L4TA(31), 95, 2, 1 }, /* GP Timer 12 */
971 { L4TA(32), 97, 2, 1 }, /* EAC */
972 { L4TA(33), 99, 2, 1 }, /* FAC */
973 { L4TA(34), 101, 2, 1 }, /* IPC */
974 { L4TA(35), 103, 2, 1 }, /* SPI1 */
975 { L4TA(36), 105, 2, 1 }, /* SPI2 */
976 { L4TAO(9), 107, 2, 1 }, /* MMC SDIO */
977 { L4TAO(10), 109, 2, 1 },
978 { L4TAO(11), 111, 2, 1 }, /* RNG */
979 { L4TAO(12), 113, 2, 1 }, /* DES3DES */
980 { L4TAO(13), 115, 2, 1 }, /* SHA1MD5 */
981 { L4TA(37), 117, 2, 1 }, /* AES */
982 { L4TA(38), 119, 2, 1 }, /* PKA */
983 { -1, 121, 2, 1 },
984 { L4TA(39), 123, 2, 1 }, /* HDQ/1-Wire */
985 };
986
987 #define omap_l4ta(bus, cs) \
988 omap_l4ta_get(bus, omap_l4_region, omap_l4_agent_info, L4TA(cs))
989 #define omap_l4tao(bus, cs) \
990 omap_l4ta_get(bus, omap_l4_region, omap_l4_agent_info, L4TAO(cs))
991
992 /* Power, Reset, and Clock Management */
993 struct omap_prcm_s {
994 qemu_irq irq[3];
995 struct omap_mpu_state_s *mpu;
996
997 uint32_t irqst[3];
998 uint32_t irqen[3];
999
1000 uint32_t sysconfig;
1001 uint32_t voltctrl;
1002 uint32_t scratch[20];
1003
1004 uint32_t clksrc[1];
1005 uint32_t clkout[1];
1006 uint32_t clkemul[1];
1007 uint32_t clkpol[1];
1008 uint32_t clksel[8];
1009 uint32_t clken[12];
1010 uint32_t clkctrl[4];
1011 uint32_t clkidle[7];
1012 uint32_t setuptime[2];
1013
1014 uint32_t wkup[3];
1015 uint32_t wken[3];
1016 uint32_t wkst[3];
1017 uint32_t rst[4];
1018 uint32_t rstctrl[1];
1019 uint32_t power[4];
1020 uint32_t rsttime_wkup;
1021
1022 uint32_t ev;
1023 uint32_t evtime[2];
1024
1025 int dpll_lock, apll_lock[2];
1026 };
1027
1028 static void omap_prcm_int_update(struct omap_prcm_s *s, int dom)
1029 {
1030 qemu_set_irq(s->irq[dom], s->irqst[dom] & s->irqen[dom]);
1031 /* XXX or is the mask applied before PRCM_IRQSTATUS_* ? */
1032 }
1033
1034 static uint32_t omap_prcm_read(void *opaque, target_phys_addr_t addr)
1035 {
1036 struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
1037 uint32_t ret;
1038
1039 switch (addr) {
1040 case 0x000: /* PRCM_REVISION */
1041 return 0x10;
1042
1043 case 0x010: /* PRCM_SYSCONFIG */
1044 return s->sysconfig;
1045
1046 case 0x018: /* PRCM_IRQSTATUS_MPU */
1047 return s->irqst[0];
1048
1049 case 0x01c: /* PRCM_IRQENABLE_MPU */
1050 return s->irqen[0];
1051
1052 case 0x050: /* PRCM_VOLTCTRL */
1053 return s->voltctrl;
1054 case 0x054: /* PRCM_VOLTST */
1055 return s->voltctrl & 3;
1056
1057 case 0x060: /* PRCM_CLKSRC_CTRL */
1058 return s->clksrc[0];
1059 case 0x070: /* PRCM_CLKOUT_CTRL */
1060 return s->clkout[0];
1061 case 0x078: /* PRCM_CLKEMUL_CTRL */
1062 return s->clkemul[0];
1063 case 0x080: /* PRCM_CLKCFG_CTRL */
1064 case 0x084: /* PRCM_CLKCFG_STATUS */
1065 return 0;
1066
1067 case 0x090: /* PRCM_VOLTSETUP */
1068 return s->setuptime[0];
1069
1070 case 0x094: /* PRCM_CLKSSETUP */
1071 return s->setuptime[1];
1072
1073 case 0x098: /* PRCM_POLCTRL */
1074 return s->clkpol[0];
1075
1076 case 0x0b0: /* GENERAL_PURPOSE1 */
1077 case 0x0b4: /* GENERAL_PURPOSE2 */
1078 case 0x0b8: /* GENERAL_PURPOSE3 */
1079 case 0x0bc: /* GENERAL_PURPOSE4 */
1080 case 0x0c0: /* GENERAL_PURPOSE5 */
1081 case 0x0c4: /* GENERAL_PURPOSE6 */
1082 case 0x0c8: /* GENERAL_PURPOSE7 */
1083 case 0x0cc: /* GENERAL_PURPOSE8 */
1084 case 0x0d0: /* GENERAL_PURPOSE9 */
1085 case 0x0d4: /* GENERAL_PURPOSE10 */
1086 case 0x0d8: /* GENERAL_PURPOSE11 */
1087 case 0x0dc: /* GENERAL_PURPOSE12 */
1088 case 0x0e0: /* GENERAL_PURPOSE13 */
1089 case 0x0e4: /* GENERAL_PURPOSE14 */
1090 case 0x0e8: /* GENERAL_PURPOSE15 */
1091 case 0x0ec: /* GENERAL_PURPOSE16 */
1092 case 0x0f0: /* GENERAL_PURPOSE17 */
1093 case 0x0f4: /* GENERAL_PURPOSE18 */
1094 case 0x0f8: /* GENERAL_PURPOSE19 */
1095 case 0x0fc: /* GENERAL_PURPOSE20 */
1096 return s->scratch[(addr - 0xb0) >> 2];
1097
1098 case 0x140: /* CM_CLKSEL_MPU */
1099 return s->clksel[0];
1100 case 0x148: /* CM_CLKSTCTRL_MPU */
1101 return s->clkctrl[0];
1102
1103 case 0x158: /* RM_RSTST_MPU */
1104 return s->rst[0];
1105 case 0x1c8: /* PM_WKDEP_MPU */
1106 return s->wkup[0];
1107 case 0x1d4: /* PM_EVGENCTRL_MPU */
1108 return s->ev;
1109 case 0x1d8: /* PM_EVEGENONTIM_MPU */
1110 return s->evtime[0];
1111 case 0x1dc: /* PM_EVEGENOFFTIM_MPU */
1112 return s->evtime[1];
1113 case 0x1e0: /* PM_PWSTCTRL_MPU */
1114 return s->power[0];
1115 case 0x1e4: /* PM_PWSTST_MPU */
1116 return 0;
1117
1118 case 0x200: /* CM_FCLKEN1_CORE */
1119 return s->clken[0];
1120 case 0x204: /* CM_FCLKEN2_CORE */
1121 return s->clken[1];
1122 case 0x210: /* CM_ICLKEN1_CORE */
1123 return s->clken[2];
1124 case 0x214: /* CM_ICLKEN2_CORE */
1125 return s->clken[3];
1126 case 0x21c: /* CM_ICLKEN4_CORE */
1127 return s->clken[4];
1128
1129 case 0x220: /* CM_IDLEST1_CORE */
1130 /* TODO: check the actual iclk status */
1131 return 0x7ffffff9;
1132 case 0x224: /* CM_IDLEST2_CORE */
1133 /* TODO: check the actual iclk status */
1134 return 0x00000007;
1135 case 0x22c: /* CM_IDLEST4_CORE */
1136 /* TODO: check the actual iclk status */
1137 return 0x0000001f;
1138
1139 case 0x230: /* CM_AUTOIDLE1_CORE */
1140 return s->clkidle[0];
1141 case 0x234: /* CM_AUTOIDLE2_CORE */
1142 return s->clkidle[1];
1143 case 0x238: /* CM_AUTOIDLE3_CORE */
1144 return s->clkidle[2];
1145 case 0x23c: /* CM_AUTOIDLE4_CORE */
1146 return s->clkidle[3];
1147
1148 case 0x240: /* CM_CLKSEL1_CORE */
1149 return s->clksel[1];
1150 case 0x244: /* CM_CLKSEL2_CORE */
1151 return s->clksel[2];
1152
1153 case 0x248: /* CM_CLKSTCTRL_CORE */
1154 return s->clkctrl[1];
1155
1156 case 0x2a0: /* PM_WKEN1_CORE */
1157 return s->wken[0];
1158 case 0x2a4: /* PM_WKEN2_CORE */
1159 return s->wken[1];
1160
1161 case 0x2b0: /* PM_WKST1_CORE */
1162 return s->wkst[0];
1163 case 0x2b4: /* PM_WKST2_CORE */
1164 return s->wkst[1];
1165 case 0x2c8: /* PM_WKDEP_CORE */
1166 return 0x1e;
1167
1168 case 0x2e0: /* PM_PWSTCTRL_CORE */
1169 return s->power[1];
1170 case 0x2e4: /* PM_PWSTST_CORE */
1171 return 0x000030 | (s->power[1] & 0xfc00);
1172
1173 case 0x300: /* CM_FCLKEN_GFX */
1174 return s->clken[5];
1175 case 0x310: /* CM_ICLKEN_GFX */
1176 return s->clken[6];
1177 case 0x320: /* CM_IDLEST_GFX */
1178 /* TODO: check the actual iclk status */
1179 return 0x00000001;
1180 case 0x340: /* CM_CLKSEL_GFX */
1181 return s->clksel[3];
1182 case 0x348: /* CM_CLKSTCTRL_GFX */
1183 return s->clkctrl[2];
1184 case 0x350: /* RM_RSTCTRL_GFX */
1185 return s->rstctrl[0];
1186 case 0x358: /* RM_RSTST_GFX */
1187 return s->rst[1];
1188 case 0x3c8: /* PM_WKDEP_GFX */
1189 return s->wkup[1];
1190
1191 case 0x3e0: /* PM_PWSTCTRL_GFX */
1192 return s->power[2];
1193 case 0x3e4: /* PM_PWSTST_GFX */
1194 return s->power[2] & 3;
1195
1196 case 0x400: /* CM_FCLKEN_WKUP */
1197 return s->clken[7];
1198 case 0x410: /* CM_ICLKEN_WKUP */
1199 return s->clken[8];
1200 case 0x420: /* CM_IDLEST_WKUP */
1201 /* TODO: check the actual iclk status */
1202 return 0x0000003f;
1203 case 0x430: /* CM_AUTOIDLE_WKUP */
1204 return s->clkidle[4];
1205 case 0x440: /* CM_CLKSEL_WKUP */
1206 return s->clksel[4];
1207 case 0x450: /* RM_RSTCTRL_WKUP */
1208 return 0;
1209 case 0x454: /* RM_RSTTIME_WKUP */
1210 return s->rsttime_wkup;
1211 case 0x458: /* RM_RSTST_WKUP */
1212 return s->rst[2];
1213 case 0x4a0: /* PM_WKEN_WKUP */
1214 return s->wken[2];
1215 case 0x4b0: /* PM_WKST_WKUP */
1216 return s->wkst[2];
1217
1218 case 0x500: /* CM_CLKEN_PLL */
1219 return s->clken[9];
1220 case 0x520: /* CM_IDLEST_CKGEN */
1221 ret = 0x0000070 | (s->apll_lock[0] << 9) | (s->apll_lock[1] << 8);
1222 if (!(s->clksel[6] & 3))
1223 /* Core uses 32-kHz clock */
1224 ret |= 3 << 0;
1225 else if (!s->dpll_lock)
1226 /* DPLL not locked, core uses ref_clk */
1227 ret |= 1 << 0;
1228 else
1229 /* Core uses DPLL */
1230 ret |= 2 << 0;
1231 return ret;
1232 case 0x530: /* CM_AUTOIDLE_PLL */
1233 return s->clkidle[5];
1234 case 0x540: /* CM_CLKSEL1_PLL */
1235 return s->clksel[5];
1236 case 0x544: /* CM_CLKSEL2_PLL */
1237 return s->clksel[6];
1238
1239 case 0x800: /* CM_FCLKEN_DSP */
1240 return s->clken[10];
1241 case 0x810: /* CM_ICLKEN_DSP */
1242 return s->clken[11];
1243 case 0x820: /* CM_IDLEST_DSP */
1244 /* TODO: check the actual iclk status */
1245 return 0x00000103;
1246 case 0x830: /* CM_AUTOIDLE_DSP */
1247 return s->clkidle[6];
1248 case 0x840: /* CM_CLKSEL_DSP */
1249 return s->clksel[7];
1250 case 0x848: /* CM_CLKSTCTRL_DSP */
1251 return s->clkctrl[3];
1252 case 0x850: /* RM_RSTCTRL_DSP */
1253 return 0;
1254 case 0x858: /* RM_RSTST_DSP */
1255 return s->rst[3];
1256 case 0x8c8: /* PM_WKDEP_DSP */
1257 return s->wkup[2];
1258 case 0x8e0: /* PM_PWSTCTRL_DSP */
1259 return s->power[3];
1260 case 0x8e4: /* PM_PWSTST_DSP */
1261 return 0x008030 | (s->power[3] & 0x3003);
1262
1263 case 0x8f0: /* PRCM_IRQSTATUS_DSP */
1264 return s->irqst[1];
1265 case 0x8f4: /* PRCM_IRQENABLE_DSP */
1266 return s->irqen[1];
1267
1268 case 0x8f8: /* PRCM_IRQSTATUS_IVA */
1269 return s->irqst[2];
1270 case 0x8fc: /* PRCM_IRQENABLE_IVA */
1271 return s->irqen[2];
1272 }
1273
1274 OMAP_BAD_REG(addr);
1275 return 0;
1276 }
1277
1278 static void omap_prcm_apll_update(struct omap_prcm_s *s)
1279 {
1280 int mode[2];
1281
1282 mode[0] = (s->clken[9] >> 6) & 3;
1283 s->apll_lock[0] = (mode[0] == 3);
1284 mode[1] = (s->clken[9] >> 2) & 3;
1285 s->apll_lock[1] = (mode[1] == 3);
1286 /* TODO: update clocks */
1287
1288 if (mode[0] == 1 || mode[0] == 2 || mode[1] == 1 || mode[1] == 2)
1289 fprintf(stderr, "%s: bad EN_54M_PLL or bad EN_96M_PLL\n",
1290 __FUNCTION__);
1291 }
1292
1293 static void omap_prcm_dpll_update(struct omap_prcm_s *s)
1294 {
1295 omap_clk dpll = omap_findclk(s->mpu, "dpll");
1296 omap_clk dpll_x2 = omap_findclk(s->mpu, "dpll");
1297 omap_clk core = omap_findclk(s->mpu, "core_clk");
1298 int mode = (s->clken[9] >> 0) & 3;
1299 int mult, div;
1300
1301 mult = (s->clksel[5] >> 12) & 0x3ff;
1302 div = (s->clksel[5] >> 8) & 0xf;
1303 if (mult == 0 || mult == 1)
1304 mode = 1; /* Bypass */
1305
1306 s->dpll_lock = 0;
1307 switch (mode) {
1308 case 0:
1309 fprintf(stderr, "%s: bad EN_DPLL\n", __FUNCTION__);
1310 break;
1311 case 1: /* Low-power bypass mode (Default) */
1312 case 2: /* Fast-relock bypass mode */
1313 omap_clk_setrate(dpll, 1, 1);
1314 omap_clk_setrate(dpll_x2, 1, 1);
1315 break;
1316 case 3: /* Lock mode */
1317 s->dpll_lock = 1; /* After 20 FINT cycles (ref_clk / (div + 1)). */
1318
1319 omap_clk_setrate(dpll, div + 1, mult);
1320 omap_clk_setrate(dpll_x2, div + 1, mult * 2);
1321 break;
1322 }
1323
1324 switch ((s->clksel[6] >> 0) & 3) {
1325 case 0:
1326 omap_clk_reparent(core, omap_findclk(s->mpu, "clk32-kHz"));
1327 break;
1328 case 1:
1329 omap_clk_reparent(core, dpll);
1330 break;
1331 case 2:
1332 /* Default */
1333 omap_clk_reparent(core, dpll_x2);
1334 break;
1335 case 3:
1336 fprintf(stderr, "%s: bad CORE_CLK_SRC\n", __FUNCTION__);
1337 break;
1338 }
1339 }
1340
1341 static void omap_prcm_write(void *opaque, target_phys_addr_t addr,
1342 uint32_t value)
1343 {
1344 struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
1345
1346 switch (addr) {
1347 case 0x000: /* PRCM_REVISION */
1348 case 0x054: /* PRCM_VOLTST */
1349 case 0x084: /* PRCM_CLKCFG_STATUS */
1350 case 0x1e4: /* PM_PWSTST_MPU */
1351 case 0x220: /* CM_IDLEST1_CORE */
1352 case 0x224: /* CM_IDLEST2_CORE */
1353 case 0x22c: /* CM_IDLEST4_CORE */
1354 case 0x2c8: /* PM_WKDEP_CORE */
1355 case 0x2e4: /* PM_PWSTST_CORE */
1356 case 0x320: /* CM_IDLEST_GFX */
1357 case 0x3e4: /* PM_PWSTST_GFX */
1358 case 0x420: /* CM_IDLEST_WKUP */
1359 case 0x520: /* CM_IDLEST_CKGEN */
1360 case 0x820: /* CM_IDLEST_DSP */
1361 case 0x8e4: /* PM_PWSTST_DSP */
1362 OMAP_RO_REG(addr);
1363 return;
1364
1365 case 0x010: /* PRCM_SYSCONFIG */
1366 s->sysconfig = value & 1;
1367 break;
1368
1369 case 0x018: /* PRCM_IRQSTATUS_MPU */
1370 s->irqst[0] &= ~value;
1371 omap_prcm_int_update(s, 0);
1372 break;
1373 case 0x01c: /* PRCM_IRQENABLE_MPU */
1374 s->irqen[0] = value & 0x3f;
1375 omap_prcm_int_update(s, 0);
1376 break;
1377
1378 case 0x050: /* PRCM_VOLTCTRL */
1379 s->voltctrl = value & 0xf1c3;
1380 break;
1381
1382 case 0x060: /* PRCM_CLKSRC_CTRL */
1383 s->clksrc[0] = value & 0xdb;
1384 /* TODO update clocks */
1385 break;
1386
1387 case 0x070: /* PRCM_CLKOUT_CTRL */
1388 s->clkout[0] = value & 0xbbbb;
1389 /* TODO update clocks */
1390 break;
1391
1392 case 0x078: /* PRCM_CLKEMUL_CTRL */
1393 s->clkemul[0] = value & 1;
1394 /* TODO update clocks */
1395 break;
1396
1397 case 0x080: /* PRCM_CLKCFG_CTRL */
1398 break;
1399
1400 case 0x090: /* PRCM_VOLTSETUP */
1401 s->setuptime[0] = value & 0xffff;
1402 break;
1403 case 0x094: /* PRCM_CLKSSETUP */
1404 s->setuptime[1] = value & 0xffff;
1405 break;
1406
1407 case 0x098: /* PRCM_POLCTRL */
1408 s->clkpol[0] = value & 0x701;
1409 break;
1410
1411 case 0x0b0: /* GENERAL_PURPOSE1 */
1412 case 0x0b4: /* GENERAL_PURPOSE2 */
1413 case 0x0b8: /* GENERAL_PURPOSE3 */
1414 case 0x0bc: /* GENERAL_PURPOSE4 */
1415 case 0x0c0: /* GENERAL_PURPOSE5 */
1416 case 0x0c4: /* GENERAL_PURPOSE6 */
1417 case 0x0c8: /* GENERAL_PURPOSE7 */
1418 case 0x0cc: /* GENERAL_PURPOSE8 */
1419 case 0x0d0: /* GENERAL_PURPOSE9 */
1420 case 0x0d4: /* GENERAL_PURPOSE10 */
1421 case 0x0d8: /* GENERAL_PURPOSE11 */
1422 case 0x0dc: /* GENERAL_PURPOSE12 */
1423 case 0x0e0: /* GENERAL_PURPOSE13 */
1424 case 0x0e4: /* GENERAL_PURPOSE14 */
1425 case 0x0e8: /* GENERAL_PURPOSE15 */
1426 case 0x0ec: /* GENERAL_PURPOSE16 */
1427 case 0x0f0: /* GENERAL_PURPOSE17 */
1428 case 0x0f4: /* GENERAL_PURPOSE18 */
1429 case 0x0f8: /* GENERAL_PURPOSE19 */
1430 case 0x0fc: /* GENERAL_PURPOSE20 */
1431 s->scratch[(addr - 0xb0) >> 2] = value;
1432 break;
1433
1434 case 0x140: /* CM_CLKSEL_MPU */
1435 s->clksel[0] = value & 0x1f;
1436 /* TODO update clocks */
1437 break;
1438 case 0x148: /* CM_CLKSTCTRL_MPU */
1439 s->clkctrl[0] = value & 0x1f;
1440 break;
1441
1442 case 0x158: /* RM_RSTST_MPU */
1443 s->rst[0] &= ~value;
1444 break;
1445 case 0x1c8: /* PM_WKDEP_MPU */
1446 s->wkup[0] = value & 0x15;
1447 break;
1448
1449 case 0x1d4: /* PM_EVGENCTRL_MPU */
1450 s->ev = value & 0x1f;
1451 break;
1452 case 0x1d8: /* PM_EVEGENONTIM_MPU */
1453 s->evtime[0] = value;
1454 break;
1455 case 0x1dc: /* PM_EVEGENOFFTIM_MPU */
1456 s->evtime[1] = value;
1457 break;
1458
1459 case 0x1e0: /* PM_PWSTCTRL_MPU */
1460 s->power[0] = value & 0xc0f;
1461 break;
1462
1463 case 0x200: /* CM_FCLKEN1_CORE */
1464 s->clken[0] = value & 0xbfffffff;
1465 /* TODO update clocks */
1466 /* The EN_EAC bit only gets/puts func_96m_clk. */
1467 break;
1468 case 0x204: /* CM_FCLKEN2_CORE */
1469 s->clken[1] = value & 0x00000007;
1470 /* TODO update clocks */
1471 break;
1472 case 0x210: /* CM_ICLKEN1_CORE */
1473 s->clken[2] = value & 0xfffffff9;
1474 /* TODO update clocks */
1475 /* The EN_EAC bit only gets/puts core_l4_iclk. */
1476 break;
1477 case 0x214: /* CM_ICLKEN2_CORE */
1478 s->clken[3] = value & 0x00000007;
1479 /* TODO update clocks */
1480 break;
1481 case 0x21c: /* CM_ICLKEN4_CORE */
1482 s->clken[4] = value & 0x0000001f;
1483 /* TODO update clocks */
1484 break;
1485
1486 case 0x230: /* CM_AUTOIDLE1_CORE */
1487 s->clkidle[0] = value & 0xfffffff9;
1488 /* TODO update clocks */
1489 break;
1490 case 0x234: /* CM_AUTOIDLE2_CORE */
1491 s->clkidle[1] = value & 0x00000007;
1492 /* TODO update clocks */
1493 break;
1494 case 0x238: /* CM_AUTOIDLE3_CORE */
1495 s->clkidle[2] = value & 0x00000007;
1496 /* TODO update clocks */
1497 break;
1498 case 0x23c: /* CM_AUTOIDLE4_CORE */
1499 s->clkidle[3] = value & 0x0000001f;
1500 /* TODO update clocks */
1501 break;
1502
1503 case 0x240: /* CM_CLKSEL1_CORE */
1504 s->clksel[1] = value & 0x0fffbf7f;
1505 /* TODO update clocks */
1506 break;
1507
1508 case 0x244: /* CM_CLKSEL2_CORE */
1509 s->clksel[2] = value & 0x00fffffc;
1510 /* TODO update clocks */
1511 break;
1512
1513 case 0x248: /* CM_CLKSTCTRL_CORE */
1514 s->clkctrl[1] = value & 0x7;
1515 break;
1516
1517 case 0x2a0: /* PM_WKEN1_CORE */
1518 s->wken[0] = value & 0x04667ff8;
1519 break;
1520 case 0x2a4: /* PM_WKEN2_CORE */
1521 s->wken[1] = value & 0x00000005;
1522 break;
1523
1524 case 0x2b0: /* PM_WKST1_CORE */
1525 s->wkst[0] &= ~value;
1526 break;
1527 case 0x2b4: /* PM_WKST2_CORE */
1528 s->wkst[1] &= ~value;
1529 break;
1530
1531 case 0x2e0: /* PM_PWSTCTRL_CORE */
1532 s->power[1] = (value & 0x00fc3f) | (1 << 2);
1533 break;
1534
1535 case 0x300: /* CM_FCLKEN_GFX */
1536 s->clken[5] = value & 6;
1537 /* TODO update clocks */
1538 break;
1539 case 0x310: /* CM_ICLKEN_GFX */
1540 s->clken[6] = value & 1;
1541 /* TODO update clocks */
1542 break;
1543 case 0x340: /* CM_CLKSEL_GFX */
1544 s->clksel[3] = value & 7;
1545 /* TODO update clocks */
1546 break;
1547 case 0x348: /* CM_CLKSTCTRL_GFX */
1548 s->clkctrl[2] = value & 1;
1549 break;
1550 case 0x350: /* RM_RSTCTRL_GFX */
1551 s->rstctrl[0] = value & 1;
1552 /* TODO: reset */
1553 break;
1554 case 0x358: /* RM_RSTST_GFX */
1555 s->rst[1] &= ~value;
1556 break;
1557 case 0x3c8: /* PM_WKDEP_GFX */
1558 s->wkup[1] = value & 0x13;
1559 break;
1560 case 0x3e0: /* PM_PWSTCTRL_GFX */
1561 s->power[2] = (value & 0x00c0f) | (3 << 2);
1562 break;
1563
1564 case 0x400: /* CM_FCLKEN_WKUP */
1565 s->clken[7] = value & 0xd;
1566 /* TODO update clocks */
1567 break;
1568 case 0x410: /* CM_ICLKEN_WKUP */
1569 s->clken[8] = value & 0x3f;
1570 /* TODO update clocks */
1571 break;
1572 case 0x430: /* CM_AUTOIDLE_WKUP */
1573 s->clkidle[4] = value & 0x0000003f;
1574 /* TODO update clocks */
1575 break;
1576 case 0x440: /* CM_CLKSEL_WKUP */
1577 s->clksel[4] = value & 3;
1578 /* TODO update clocks */
1579 break;
1580 case 0x450: /* RM_RSTCTRL_WKUP */
1581 /* TODO: reset */
1582 if (value & 2)
1583 qemu_system_reset_request();
1584 break;
1585 case 0x454: /* RM_RSTTIME_WKUP */
1586 s->rsttime_wkup = value & 0x1fff;
1587 break;
1588 case 0x458: /* RM_RSTST_WKUP */
1589 s->rst[2] &= ~value;
1590 break;
1591 case 0x4a0: /* PM_WKEN_WKUP */
1592 s->wken[2] = value & 0x00000005;
1593 break;
1594 case 0x4b0: /* PM_WKST_WKUP */
1595 s->wkst[2] &= ~value;
1596 break;
1597
1598 case 0x500: /* CM_CLKEN_PLL */
1599 if (value & 0xffffff30)
1600 fprintf(stderr, "%s: write 0s in CM_CLKEN_PLL for "
1601 "future compatiblity\n", __FUNCTION__);
1602 if ((s->clken[9] ^ value) & 0xcc) {
1603 s->clken[9] &= ~0xcc;
1604 s->clken[9] |= value & 0xcc;
1605 omap_prcm_apll_update(s);
1606 }
1607 if ((s->clken[9] ^ value) & 3) {
1608 s->clken[9] &= ~3;
1609 s->clken[9] |= value & 3;
1610 omap_prcm_dpll_update(s);
1611 }
1612 break;
1613 case 0x530: /* CM_AUTOIDLE_PLL */
1614 s->clkidle[5] = value & 0x000000cf;
1615 /* TODO update clocks */
1616 break;
1617 case 0x540: /* CM_CLKSEL1_PLL */
1618 if (value & 0xfc4000d7)
1619 fprintf(stderr, "%s: write 0s in CM_CLKSEL1_PLL for "
1620 "future compatiblity\n", __FUNCTION__);
1621 if ((s->clksel[5] ^ value) & 0x003fff00) {
1622 s->clksel[5] = value & 0x03bfff28;
1623 omap_prcm_dpll_update(s);
1624 }
1625 /* TODO update the other clocks */
1626
1627 s->clksel[5] = value & 0x03bfff28;
1628 break;
1629 case 0x544: /* CM_CLKSEL2_PLL */
1630 if (value & ~3)
1631 fprintf(stderr, "%s: write 0s in CM_CLKSEL2_PLL[31:2] for "
1632 "future compatiblity\n", __FUNCTION__);
1633 if (s->clksel[6] != (value & 3)) {
1634 s->clksel[6] = value & 3;
1635 omap_prcm_dpll_update(s);
1636 }
1637 break;
1638
1639 case 0x800: /* CM_FCLKEN_DSP */
1640 s->clken[10] = value & 0x501;
1641 /* TODO update clocks */
1642 break;
1643 case 0x810: /* CM_ICLKEN_DSP */
1644 s->clken[11] = value & 0x2;
1645 /* TODO update clocks */
1646 break;
1647 case 0x830: /* CM_AUTOIDLE_DSP */
1648 s->clkidle[6] = value & 0x2;
1649 /* TODO update clocks */
1650 break;
1651 case 0x840: /* CM_CLKSEL_DSP */
1652 s->clksel[7] = value & 0x3fff;
1653 /* TODO update clocks */
1654 break;
1655 case 0x848: /* CM_CLKSTCTRL_DSP */
1656 s->clkctrl[3] = value & 0x101;
1657 break;
1658 case 0x850: /* RM_RSTCTRL_DSP */
1659 /* TODO: reset */
1660 break;
1661 case 0x858: /* RM_RSTST_DSP */
1662 s->rst[3] &= ~value;
1663 break;
1664 case 0x8c8: /* PM_WKDEP_DSP */
1665 s->wkup[2] = value & 0x13;
1666 break;
1667 case 0x8e0: /* PM_PWSTCTRL_DSP */
1668 s->power[3] = (value & 0x03017) | (3 << 2);
1669 break;
1670
1671 case 0x8f0: /* PRCM_IRQSTATUS_DSP */
1672 s->irqst[1] &= ~value;
1673 omap_prcm_int_update(s, 1);
1674 break;
1675 case 0x8f4: /* PRCM_IRQENABLE_DSP */
1676 s->irqen[1] = value & 0x7;
1677 omap_prcm_int_update(s, 1);
1678 break;
1679
1680 case 0x8f8: /* PRCM_IRQSTATUS_IVA */
1681 s->irqst[2] &= ~value;
1682 omap_prcm_int_update(s, 2);
1683 break;
1684 case 0x8fc: /* PRCM_IRQENABLE_IVA */
1685 s->irqen[2] = value & 0x7;
1686 omap_prcm_int_update(s, 2);
1687 break;
1688
1689 default:
1690 OMAP_BAD_REG(addr);
1691 return;
1692 }
1693 }
1694
1695 static CPUReadMemoryFunc * const omap_prcm_readfn[] = {
1696 omap_badwidth_read32,
1697 omap_badwidth_read32,
1698 omap_prcm_read,
1699 };
1700
1701 static CPUWriteMemoryFunc * const omap_prcm_writefn[] = {
1702 omap_badwidth_write32,
1703 omap_badwidth_write32,
1704 omap_prcm_write,
1705 };
1706
1707 static void omap_prcm_reset(struct omap_prcm_s *s)
1708 {
1709 s->sysconfig = 0;
1710 s->irqst[0] = 0;
1711 s->irqst[1] = 0;
1712 s->irqst[2] = 0;
1713 s->irqen[0] = 0;
1714 s->irqen[1] = 0;
1715 s->irqen[2] = 0;
1716 s->voltctrl = 0x1040;
1717 s->ev = 0x14;
1718 s->evtime[0] = 0;
1719 s->evtime[1] = 0;
1720 s->clkctrl[0] = 0;
1721 s->clkctrl[1] = 0;
1722 s->clkctrl[2] = 0;
1723 s->clkctrl[3] = 0;
1724 s->clken[1] = 7;
1725 s->clken[3] = 7;
1726 s->clken[4] = 0;
1727 s->clken[5] = 0;
1728 s->clken[6] = 0;
1729 s->clken[7] = 0xc;
1730 s->clken[8] = 0x3e;
1731 s->clken[9] = 0x0d;
1732 s->clken[10] = 0;
1733 s->clken[11] = 0;
1734 s->clkidle[0] = 0;
1735 s->clkidle[2] = 7;
1736 s->clkidle[3] = 0;
1737 s->clkidle[4] = 0;
1738 s->clkidle[5] = 0x0c;
1739 s->clkidle[6] = 0;
1740 s->clksel[0] = 0x01;
1741 s->clksel[1] = 0x02100121;
1742 s->clksel[2] = 0x00000000;
1743 s->clksel[3] = 0x01;
1744 s->clksel[4] = 0;
1745 s->clksel[7] = 0x0121;
1746 s->wkup[0] = 0x15;
1747 s->wkup[1] = 0x13;
1748 s->wkup[2] = 0x13;
1749 s->wken[0] = 0x04667ff8;
1750 s->wken[1] = 0x00000005;
1751 s->wken[2] = 5;
1752 s->wkst[0] = 0;
1753 s->wkst[1] = 0;
1754 s->wkst[2] = 0;
1755 s->power[0] = 0x00c;
1756 s->power[1] = 4;
1757 s->power[2] = 0x0000c;
1758 s->power[3] = 0x14;
1759 s->rstctrl[0] = 1;
1760 s->rst[3] = 1;
1761 omap_prcm_apll_update(s);
1762 omap_prcm_dpll_update(s);
1763 }
1764
1765 static void omap_prcm_coldreset(struct omap_prcm_s *s)
1766 {
1767 s->setuptime[0] = 0;
1768 s->setuptime[1] = 0;
1769 memset(&s->scratch, 0, sizeof(s->scratch));
1770 s->rst[0] = 0x01;
1771 s->rst[1] = 0x00;
1772 s->rst[2] = 0x01;
1773 s->clken[0] = 0;
1774 s->clken[2] = 0;
1775 s->clkidle[1] = 0;
1776 s->clksel[5] = 0;
1777 s->clksel[6] = 2;
1778 s->clksrc[0] = 0x43;
1779 s->clkout[0] = 0x0303;
1780 s->clkemul[0] = 0;
1781 s->clkpol[0] = 0x100;
1782 s->rsttime_wkup = 0x1002;
1783
1784 omap_prcm_reset(s);
1785 }
1786
1787 static struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta,
1788 qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int,
1789 struct omap_mpu_state_s *mpu)
1790 {
1791 int iomemtype;
1792 struct omap_prcm_s *s = (struct omap_prcm_s *)
1793 g_malloc0(sizeof(struct omap_prcm_s));
1794
1795 s->irq[0] = mpu_int;
1796 s->irq[1] = dsp_int;
1797 s->irq[2] = iva_int;
1798 s->mpu = mpu;
1799 omap_prcm_coldreset(s);
1800
1801 iomemtype = l4_register_io_memory(omap_prcm_readfn,
1802 omap_prcm_writefn, s);
1803 omap_l4_attach(ta, 0, iomemtype);
1804 omap_l4_attach(ta, 1, iomemtype);
1805
1806 return s;
1807 }
1808
1809 /* System and Pinout control */
1810 struct omap_sysctl_s {
1811 struct omap_mpu_state_s *mpu;
1812
1813 uint32_t sysconfig;
1814 uint32_t devconfig;
1815 uint32_t psaconfig;
1816 uint32_t padconf[0x45];
1817 uint8_t obs;
1818 uint32_t msuspendmux[5];
1819 };
1820
1821 static uint32_t omap_sysctl_read8(void *opaque, target_phys_addr_t addr)
1822 {
1823
1824 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
1825 int pad_offset, byte_offset;
1826 int value;
1827
1828 switch (addr) {
1829 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
1830 pad_offset = (addr - 0x30) >> 2;
1831 byte_offset = (addr - 0x30) & (4 - 1);
1832
1833 value = s->padconf[pad_offset];
1834 value = (value >> (byte_offset * 8)) & 0xff;
1835
1836 return value;
1837
1838 default:
1839 break;
1840 }
1841
1842 OMAP_BAD_REG(addr);
1843 return 0;
1844 }
1845
1846 static uint32_t omap_sysctl_read(void *opaque, target_phys_addr_t addr)
1847 {
1848 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
1849
1850 switch (addr) {
1851 case 0x000: /* CONTROL_REVISION */
1852 return 0x20;
1853
1854 case 0x010: /* CONTROL_SYSCONFIG */
1855 return s->sysconfig;
1856
1857 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
1858 return s->padconf[(addr - 0x30) >> 2];
1859
1860 case 0x270: /* CONTROL_DEBOBS */
1861 return s->obs;
1862
1863 case 0x274: /* CONTROL_DEVCONF */
1864 return s->devconfig;
1865
1866 case 0x28c: /* CONTROL_EMU_SUPPORT */
1867 return 0;
1868
1869 case 0x290: /* CONTROL_MSUSPENDMUX_0 */
1870 return s->msuspendmux[0];
1871 case 0x294: /* CONTROL_MSUSPENDMUX_1 */
1872 return s->msuspendmux[1];
1873 case 0x298: /* CONTROL_MSUSPENDMUX_2 */
1874 return s->msuspendmux[2];
1875 case 0x29c: /* CONTROL_MSUSPENDMUX_3 */
1876 return s->msuspendmux[3];
1877 case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */
1878 return s->msuspendmux[4];
1879 case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */
1880 return 0;
1881
1882 case 0x2b8: /* CONTROL_PSA_CTRL */
1883 return s->psaconfig;
1884 case 0x2bc: /* CONTROL_PSA_CMD */
1885 case 0x2c0: /* CONTROL_PSA_VALUE */
1886 return 0;
1887
1888 case 0x2b0: /* CONTROL_SEC_CTRL */
1889 return 0x800000f1;
1890 case 0x2d0: /* CONTROL_SEC_EMU */
1891 return 0x80000015;
1892 case 0x2d4: /* CONTROL_SEC_TAP */
1893 return 0x8000007f;
1894 case 0x2b4: /* CONTROL_SEC_TEST */
1895 case 0x2f0: /* CONTROL_SEC_STATUS */
1896 case 0x2f4: /* CONTROL_SEC_ERR_STATUS */
1897 /* Secure mode is not present on general-pusrpose device. Outside
1898 * secure mode these values cannot be read or written. */
1899 return 0;
1900
1901 case 0x2d8: /* CONTROL_OCM_RAM_PERM */
1902 return 0xff;
1903 case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */
1904 case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */
1905 case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */
1906 /* No secure mode so no Extended Secure RAM present. */
1907 return 0;
1908
1909 case 0x2f8: /* CONTROL_STATUS */
1910 /* Device Type => General-purpose */
1911 return 0x0300;
1912 case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */
1913
1914 case 0x300: /* CONTROL_RPUB_KEY_H_0 */
1915 case 0x304: /* CONTROL_RPUB_KEY_H_1 */
1916 case 0x308: /* CONTROL_RPUB_KEY_H_2 */
1917 case 0x30c: /* CONTROL_RPUB_KEY_H_3 */
1918 return 0xdecafbad;
1919
1920 case 0x310: /* CONTROL_RAND_KEY_0 */
1921 case 0x314: /* CONTROL_RAND_KEY_1 */
1922 case 0x318: /* CONTROL_RAND_KEY_2 */
1923 case 0x31c: /* CONTROL_RAND_KEY_3 */
1924 case 0x320: /* CONTROL_CUST_KEY_0 */
1925 case 0x324: /* CONTROL_CUST_KEY_1 */
1926 case 0x330: /* CONTROL_TEST_KEY_0 */
1927 case 0x334: /* CONTROL_TEST_KEY_1 */
1928 case 0x338: /* CONTROL_TEST_KEY_2 */
1929 case 0x33c: /* CONTROL_TEST_KEY_3 */
1930 case 0x340: /* CONTROL_TEST_KEY_4 */
1931 case 0x344: /* CONTROL_TEST_KEY_5 */
1932 case 0x348: /* CONTROL_TEST_KEY_6 */
1933 case 0x34c: /* CONTROL_TEST_KEY_7 */
1934 case 0x350: /* CONTROL_TEST_KEY_8 */
1935 case 0x354: /* CONTROL_TEST_KEY_9 */
1936 /* Can only be accessed in secure mode and when C_FieldAccEnable
1937 * bit is set in CONTROL_SEC_CTRL.
1938 * TODO: otherwise an interconnect access error is generated. */
1939 return 0;
1940 }
1941
1942 OMAP_BAD_REG(addr);
1943 return 0;
1944 }
1945
1946 static void omap_sysctl_write8(void *opaque, target_phys_addr_t addr,
1947 uint32_t value)
1948 {
1949 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
1950 int pad_offset, byte_offset;
1951 int prev_value;
1952
1953 switch (addr) {
1954 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
1955 pad_offset = (addr - 0x30) >> 2;
1956 byte_offset = (addr - 0x30) & (4 - 1);
1957
1958 prev_value = s->padconf[pad_offset];
1959 prev_value &= ~(0xff << (byte_offset * 8));
1960 prev_value |= ((value & 0x1f1f1f1f) << (byte_offset * 8)) & 0x1f1f1f1f;
1961 s->padconf[pad_offset] = prev_value;
1962 break;
1963
1964 default:
1965 OMAP_BAD_REG(addr);
1966 break;
1967 }
1968 }
1969
1970 static void omap_sysctl_write(void *opaque, target_phys_addr_t addr,
1971 uint32_t value)
1972 {
1973 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
1974
1975 switch (addr) {
1976 case 0x000: /* CONTROL_REVISION */
1977 case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */
1978 case 0x2c0: /* CONTROL_PSA_VALUE */
1979 case 0x2f8: /* CONTROL_STATUS */
1980 case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */
1981 case 0x300: /* CONTROL_RPUB_KEY_H_0 */
1982 case 0x304: /* CONTROL_RPUB_KEY_H_1 */
1983 case 0x308: /* CONTROL_RPUB_KEY_H_2 */
1984 case 0x30c: /* CONTROL_RPUB_KEY_H_3 */
1985 case 0x310: /* CONTROL_RAND_KEY_0 */
1986 case 0x314: /* CONTROL_RAND_KEY_1 */
1987 case 0x318: /* CONTROL_RAND_KEY_2 */
1988 case 0x31c: /* CONTROL_RAND_KEY_3 */
1989 case 0x320: /* CONTROL_CUST_KEY_0 */
1990 case 0x324: /* CONTROL_CUST_KEY_1 */
1991 case 0x330: /* CONTROL_TEST_KEY_0 */
1992 case 0x334: /* CONTROL_TEST_KEY_1 */
1993 case 0x338: /* CONTROL_TEST_KEY_2 */
1994 case 0x33c: /* CONTROL_TEST_KEY_3 */
1995 case 0x340: /* CONTROL_TEST_KEY_4 */
1996 case 0x344: /* CONTROL_TEST_KEY_5 */
1997 case 0x348: /* CONTROL_TEST_KEY_6 */
1998 case 0x34c: /* CONTROL_TEST_KEY_7 */
1999 case 0x350: /* CONTROL_TEST_KEY_8 */
2000 case 0x354: /* CONTROL_TEST_KEY_9 */
2001 OMAP_RO_REG(addr);
2002 return;
2003
2004 case 0x010: /* CONTROL_SYSCONFIG */
2005 s->sysconfig = value & 0x1e;
2006 break;
2007
2008 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
2009 /* XXX: should check constant bits */
2010 s->padconf[(addr - 0x30) >> 2] = value & 0x1f1f1f1f;
2011 break;
2012
2013 case 0x270: /* CONTROL_DEBOBS */
2014 s->obs = value & 0xff;
2015 break;
2016
2017 case 0x274: /* CONTROL_DEVCONF */
2018 s->devconfig = value & 0xffffc7ff;
2019 break;
2020
2021 case 0x28c: /* CONTROL_EMU_SUPPORT */
2022 break;
2023
2024 case 0x290: /* CONTROL_MSUSPENDMUX_0 */
2025 s->msuspendmux[0] = value & 0x3fffffff;
2026 break;
2027 case 0x294: /* CONTROL_MSUSPENDMUX_1 */
2028 s->msuspendmux[1] = value & 0x3fffffff;
2029 break;
2030 case 0x298: /* CONTROL_MSUSPENDMUX_2 */
2031 s->msuspendmux[2] = value & 0x3fffffff;
2032 break;
2033 case 0x29c: /* CONTROL_MSUSPENDMUX_3 */
2034 s->msuspendmux[3] = value & 0x3fffffff;
2035 break;
2036 case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */
2037 s->msuspendmux[4] = value & 0x3fffffff;
2038 break;
2039
2040 case 0x2b8: /* CONTROL_PSA_CTRL */
2041 s->psaconfig = value & 0x1c;
2042 s->psaconfig |= (value & 0x20) ? 2 : 1;
2043 break;
2044 case 0x2bc: /* CONTROL_PSA_CMD */
2045 break;
2046
2047 case 0x2b0: /* CONTROL_SEC_CTRL */
2048 case 0x2b4: /* CONTROL_SEC_TEST */
2049 case 0x2d0: /* CONTROL_SEC_EMU */
2050 case 0x2d4: /* CONTROL_SEC_TAP */
2051 case 0x2d8: /* CONTROL_OCM_RAM_PERM */
2052 case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */
2053 case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */
2054 case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */
2055 case 0x2f0: /* CONTROL_SEC_STATUS */
2056 case 0x2f4: /* CONTROL_SEC_ERR_STATUS */
2057 break;
2058
2059 default:
2060 OMAP_BAD_REG(addr);
2061 return;
2062 }
2063 }
2064
2065 static CPUReadMemoryFunc * const omap_sysctl_readfn[] = {
2066 omap_sysctl_read8,
2067 omap_badwidth_read32, /* TODO */
2068 omap_sysctl_read,
2069 };
2070
2071 static CPUWriteMemoryFunc * const omap_sysctl_writefn[] = {
2072 omap_sysctl_write8,
2073 omap_badwidth_write32, /* TODO */
2074 omap_sysctl_write,
2075 };
2076
2077 static void omap_sysctl_reset(struct omap_sysctl_s *s)
2078 {
2079 /* (power-on reset) */
2080 s->sysconfig = 0;
2081 s->obs = 0;
2082 s->devconfig = 0x0c000000;
2083 s->msuspendmux[0] = 0x00000000;
2084 s->msuspendmux[1] = 0x00000000;
2085 s->msuspendmux[2] = 0x00000000;
2086 s->msuspendmux[3] = 0x00000000;
2087 s->msuspendmux[4] = 0x00000000;
2088 s->psaconfig = 1;
2089
2090 s->padconf[0x00] = 0x000f0f0f;
2091 s->padconf[0x01] = 0x00000000;
2092 s->padconf[0x02] = 0x00000000;
2093 s->padconf[0x03] = 0x00000000;
2094 s->padconf[0x04] = 0x00000000;
2095 s->padconf[0x05] = 0x00000000;
2096 s->padconf[0x06] = 0x00000000;
2097 s->padconf[0x07] = 0x00000000;
2098 s->padconf[0x08] = 0x08080800;
2099 s->padconf[0x09] = 0x08080808;
2100 s->padconf[0x0a] = 0x08080808;
2101 s->padconf[0x0b] = 0x08080808;
2102 s->padconf[0x0c] = 0x08080808;
2103 s->padconf[0x0d] = 0x08080800;
2104 s->padconf[0x0e] = 0x08080808;
2105 s->padconf[0x0f] = 0x08080808;
2106 s->padconf[0x10] = 0x18181808; /* | 0x07070700 if SBoot3 */
2107 s->padconf[0x11] = 0x18181818; /* | 0x07070707 if SBoot3 */
2108 s->padconf[0x12] = 0x18181818; /* | 0x07070707 if SBoot3 */
2109 s->padconf[0x13] = 0x18181818; /* | 0x07070707 if SBoot3 */
2110 s->padconf[0x14] = 0x18181818; /* | 0x00070707 if SBoot3 */
2111 s->padconf[0x15] = 0x18181818;
2112 s->padconf[0x16] = 0x18181818; /* | 0x07000000 if SBoot3 */
2113 s->padconf[0x17] = 0x1f001f00;
2114 s->padconf[0x18] = 0x1f1f1f1f;
2115 s->padconf[0x19] = 0x00000000;
2116 s->padconf[0x1a] = 0x1f180000;
2117 s->padconf[0x1b] = 0x00001f1f;
2118 s->padconf[0x1c] = 0x1f001f00;
2119 s->padconf[0x1d] = 0x00000000;
2120 s->padconf[0x1e] = 0x00000000;
2121 s->padconf[0x1f] = 0x08000000;
2122 s->padconf[0x20] = 0x08080808;
2123 s->padconf[0x21] = 0x08080808;
2124 s->padconf[0x22] = 0x0f080808;
2125 s->padconf[0x23] = 0x0f0f0f0f;
2126 s->padconf[0x24] = 0x000f0f0f;
2127 s->padconf[0x25] = 0x1f1f1f0f;
2128 s->padconf[0x26] = 0x080f0f1f;
2129 s->padconf[0x27] = 0x070f1808;
2130 s->padconf[0x28] = 0x0f070707;
2131 s->padconf[0x29] = 0x000f0f1f;
2132 s->padconf[0x2a] = 0x0f0f0f1f;
2133 s->padconf[0x2b] = 0x08000000;
2134 s->padconf[0x2c] = 0x0000001f;
2135 s->padconf[0x2d] = 0x0f0f1f00;
2136 s->padconf[0x2e] = 0x1f1f0f0f;
2137 s->padconf[0x2f] = 0x0f1f1f1f;
2138 s->padconf[0x30] = 0x0f0f0f0f;
2139 s->padconf[0x31] = 0x0f1f0f1f;
2140 s->padconf[0x32] = 0x0f0f0f0f;
2141 s->padconf[0x33] = 0x0f1f0f1f;
2142 s->padconf[0x34] = 0x1f1f0f0f;
2143 s->padconf[0x35] = 0x0f0f1f1f;
2144 s->padconf[0x36] = 0x0f0f1f0f;
2145 s->padconf[0x37] = 0x0f0f0f0f;
2146 s->padconf[0x38] = 0x1f18180f;
2147 s->padconf[0x39] = 0x1f1f1f1f;
2148 s->padconf[0x3a] = 0x00001f1f;
2149 s->padconf[0x3b] = 0x00000000;
2150 s->padconf[0x3c] = 0x00000000;
2151 s->padconf[0x3d] = 0x0f0f0f0f;
2152 s->padconf[0x3e] = 0x18000f0f;
2153 s->padconf[0x3f] = 0x00070000;
2154 s->padconf[0x40] = 0x00000707;
2155 s->padconf[0x41] = 0x0f1f0700;
2156 s->padconf[0x42] = 0x1f1f070f;
2157 s->padconf[0x43] = 0x0008081f;
2158 s->padconf[0x44] = 0x00000800;
2159 }
2160
2161 static struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta,
2162 omap_clk iclk, struct omap_mpu_state_s *mpu)
2163 {
2164 int iomemtype;
2165 struct omap_sysctl_s *s = (struct omap_sysctl_s *)
2166 g_malloc0(sizeof(struct omap_sysctl_s));
2167
2168 s->mpu = mpu;
2169 omap_sysctl_reset(s);
2170
2171 iomemtype = l4_register_io_memory(omap_sysctl_readfn,
2172 omap_sysctl_writefn, s);
2173 omap_l4_attach(ta, 0, iomemtype);
2174
2175 return s;
2176 }
2177
2178 /* General chip reset */
2179 static void omap2_mpu_reset(void *opaque)
2180 {
2181 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
2182
2183 omap_inth_reset(mpu->ih[0]);
2184 omap_dma_reset(mpu->dma);
2185 omap_prcm_reset(mpu->prcm);
2186 omap_sysctl_reset(mpu->sysc);
2187 omap_gp_timer_reset(mpu->gptimer[0]);
2188 omap_gp_timer_reset(mpu->gptimer[1]);
2189 omap_gp_timer_reset(mpu->gptimer[2]);
2190 omap_gp_timer_reset(mpu->gptimer[3]);
2191 omap_gp_timer_reset(mpu->gptimer[4]);
2192 omap_gp_timer_reset(mpu->gptimer[5]);
2193 omap_gp_timer_reset(mpu->gptimer[6]);
2194 omap_gp_timer_reset(mpu->gptimer[7]);
2195 omap_gp_timer_reset(mpu->gptimer[8]);
2196 omap_gp_timer_reset(mpu->gptimer[9]);
2197 omap_gp_timer_reset(mpu->gptimer[10]);
2198 omap_gp_timer_reset(mpu->gptimer[11]);
2199 omap_synctimer_reset(mpu->synctimer);
2200 omap_sdrc_reset(mpu->sdrc);
2201 omap_gpmc_reset(mpu->gpmc);
2202 omap_dss_reset(mpu->dss);
2203 omap_uart_reset(mpu->uart[0]);
2204 omap_uart_reset(mpu->uart[1]);
2205 omap_uart_reset(mpu->uart[2]);
2206 omap_mmc_reset(mpu->mmc);
2207 omap_mcspi_reset(mpu->mcspi[0]);
2208 omap_mcspi_reset(mpu->mcspi[1]);
2209 omap_i2c_reset(mpu->i2c[0]);
2210 omap_i2c_reset(mpu->i2c[1]);
2211 cpu_reset(mpu->env);
2212 }
2213
2214 static int omap2_validate_addr(struct omap_mpu_state_s *s,
2215 target_phys_addr_t addr)
2216 {
2217 return 1;
2218 }
2219
2220 static const struct dma_irq_map omap2_dma_irq_map[] = {
2221 { 0, OMAP_INT_24XX_SDMA_IRQ0 },
2222 { 0, OMAP_INT_24XX_SDMA_IRQ1 },
2223 { 0, OMAP_INT_24XX_SDMA_IRQ2 },
2224 { 0, OMAP_INT_24XX_SDMA_IRQ3 },
2225 };
2226
2227 struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
2228 const char *core)
2229 {
2230 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
2231 g_malloc0(sizeof(struct omap_mpu_state_s));
2232 ram_addr_t sram_base, q2_base;
2233 qemu_irq *cpu_irq;
2234 qemu_irq dma_irqs[4];
2235 DriveInfo *dinfo;
2236 int i;
2237 SysBusDevice *busdev;
2238 struct omap_target_agent_s *ta;
2239
2240 /* Core */
2241 s->mpu_model = omap2420;
2242 s->env = cpu_init(core ?: "arm1136-r2");
2243 if (!s->env) {
2244 fprintf(stderr, "Unable to find CPU definition\n");
2245 exit(1);
2246 }
2247 s->sdram_size = sdram_size;
2248 s->sram_size = OMAP242X_SRAM_SIZE;
2249
2250 s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0];
2251
2252 /* Clocks */
2253 omap_clk_init(s);
2254
2255 /* Memory-mapped stuff */
2256 cpu_register_physical_memory(OMAP2_Q2_BASE, s->sdram_size,
2257 (q2_base = qemu_ram_alloc(NULL, "omap2.dram",
2258 s->sdram_size)) | IO_MEM_RAM);
2259 cpu_register_physical_memory(OMAP2_SRAM_BASE, s->sram_size,
2260 (sram_base = qemu_ram_alloc(NULL, "omap2.sram",
2261 s->sram_size)) | IO_MEM_RAM);
2262
2263 s->l4 = omap_l4_init(OMAP2_L4_BASE, 54);
2264
2265 /* Actually mapped at any 2K boundary in the ARM11 private-peripheral if */
2266 cpu_irq = arm_pic_init_cpu(s->env);
2267 s->ih[0] = omap2_inth_init(0x480fe000, 0x1000, 3, &s->irq[0],
2268 cpu_irq[ARM_PIC_CPU_IRQ], cpu_irq[ARM_PIC_CPU_FIQ],
2269 omap_findclk(s, "mpu_intc_fclk"),
2270 omap_findclk(s, "mpu_intc_iclk"));
2271
2272 s->prcm = omap_prcm_init(omap_l4tao(s->l4, 3),
2273 s->irq[0][OMAP_INT_24XX_PRCM_MPU_IRQ], NULL, NULL, s);
2274
2275 s->sysc = omap_sysctl_init(omap_l4tao(s->l4, 1),
2276 omap_findclk(s, "omapctrl_iclk"), s);
2277
2278 for (i = 0; i < 4; i ++)
2279 dma_irqs[i] =
2280 s->irq[omap2_dma_irq_map[i].ih][omap2_dma_irq_map[i].intr];
2281 s->dma = omap_dma4_init(0x48056000, dma_irqs, s, 256, 32,
2282 omap_findclk(s, "sdma_iclk"),
2283 omap_findclk(s, "sdma_fclk"));
2284 s->port->addr_valid = omap2_validate_addr;
2285
2286 /* Register SDRAM and SRAM ports for fast DMA transfers. */
2287 soc_dma_port_add_mem_ram(s->dma, q2_base, OMAP2_Q2_BASE, s->sdram_size);
2288 soc_dma_port_add_mem_ram(s->dma, sram_base, OMAP2_SRAM_BASE, s->sram_size);
2289
2290 s->uart[0] = omap2_uart_init(omap_l4ta(s->l4, 19),
2291 s->irq[0][OMAP_INT_24XX_UART1_IRQ],
2292 omap_findclk(s, "uart1_fclk"),
2293 omap_findclk(s, "uart1_iclk"),
2294 s->drq[OMAP24XX_DMA_UART1_TX],
2295 s->drq[OMAP24XX_DMA_UART1_RX],
2296 "uart1",
2297 serial_hds[0]);
2298 s->uart[1] = omap2_uart_init(omap_l4ta(s->l4, 20),
2299 s->irq[0][OMAP_INT_24XX_UART2_IRQ],
2300 omap_findclk(s, "uart2_fclk"),
2301 omap_findclk(s, "uart2_iclk"),
2302 s->drq[OMAP24XX_DMA_UART2_TX],
2303 s->drq[OMAP24XX_DMA_UART2_RX],
2304 "uart2",
2305 serial_hds[0] ? serial_hds[1] : NULL);
2306 s->uart[2] = omap2_uart_init(omap_l4ta(s->l4, 21),
2307 s->irq[0][OMAP_INT_24XX_UART3_IRQ],
2308 omap_findclk(s, "uart3_fclk"),
2309 omap_findclk(s, "uart3_iclk"),
2310 s->drq[OMAP24XX_DMA_UART3_TX],
2311 s->drq[OMAP24XX_DMA_UART3_RX],
2312 "uart3",
2313 serial_hds[0] && serial_hds[1] ? serial_hds[2] : NULL);
2314
2315 s->gptimer[0] = omap_gp_timer_init(omap_l4ta(s->l4, 7),
2316 s->irq[0][OMAP_INT_24XX_GPTIMER1],
2317 omap_findclk(s, "wu_gpt1_clk"),
2318 omap_findclk(s, "wu_l4_iclk"));
2319 s->gptimer[1] = omap_gp_timer_init(omap_l4ta(s->l4, 8),
2320 s->irq[0][OMAP_INT_24XX_GPTIMER2],
2321 omap_findclk(s, "core_gpt2_clk"),
2322 omap_findclk(s, "core_l4_iclk"));
2323 s->gptimer[2] = omap_gp_timer_init(omap_l4ta(s->l4, 22),
2324 s->irq[0][OMAP_INT_24XX_GPTIMER3],
2325 omap_findclk(s, "core_gpt3_clk"),
2326 omap_findclk(s, "core_l4_iclk"));
2327 s->gptimer[3] = omap_gp_timer_init(omap_l4ta(s->l4, 23),
2328 s->irq[0][OMAP_INT_24XX_GPTIMER4],
2329 omap_findclk(s, "core_gpt4_clk"),
2330 omap_findclk(s, "core_l4_iclk"));
2331 s->gptimer[4] = omap_gp_timer_init(omap_l4ta(s->l4, 24),
2332 s->irq[0][OMAP_INT_24XX_GPTIMER5],
2333 omap_findclk(s, "core_gpt5_clk"),
2334 omap_findclk(s, "core_l4_iclk"));
2335 s->gptimer[5] = omap_gp_timer_init(omap_l4ta(s->l4, 25),
2336 s->irq[0][OMAP_INT_24XX_GPTIMER6],
2337 omap_findclk(s, "core_gpt6_clk"),
2338 omap_findclk(s, "core_l4_iclk"));
2339 s->gptimer[6] = omap_gp_timer_init(omap_l4ta(s->l4, 26),
2340 s->irq[0][OMAP_INT_24XX_GPTIMER7],
2341 omap_findclk(s, "core_gpt7_clk"),
2342 omap_findclk(s, "core_l4_iclk"));
2343 s->gptimer[7] = omap_gp_timer_init(omap_l4ta(s->l4, 27),
2344 s->irq[0][OMAP_INT_24XX_GPTIMER8],
2345 omap_findclk(s, "core_gpt8_clk"),
2346 omap_findclk(s, "core_l4_iclk"));
2347 s->gptimer[8] = omap_gp_timer_init(omap_l4ta(s->l4, 28),
2348 s->irq[0][OMAP_INT_24XX_GPTIMER9],
2349 omap_findclk(s, "core_gpt9_clk"),
2350 omap_findclk(s, "core_l4_iclk"));
2351 s->gptimer[9] = omap_gp_timer_init(omap_l4ta(s->l4, 29),
2352 s->irq[0][OMAP_INT_24XX_GPTIMER10],
2353 omap_findclk(s, "core_gpt10_clk"),
2354 omap_findclk(s, "core_l4_iclk"));
2355 s->gptimer[10] = omap_gp_timer_init(omap_l4ta(s->l4, 30),
2356 s->irq[0][OMAP_INT_24XX_GPTIMER11],
2357 omap_findclk(s, "core_gpt11_clk"),
2358 omap_findclk(s, "core_l4_iclk"));
2359 s->gptimer[11] = omap_gp_timer_init(omap_l4ta(s->l4, 31),
2360 s->irq[0][OMAP_INT_24XX_GPTIMER12],
2361 omap_findclk(s, "core_gpt12_clk"),
2362 omap_findclk(s, "core_l4_iclk"));
2363
2364 omap_tap_init(omap_l4ta(s->l4, 2), s);
2365
2366 s->synctimer = omap_synctimer_init(omap_l4tao(s->l4, 2), s,
2367 omap_findclk(s, "clk32-kHz"),
2368 omap_findclk(s, "core_l4_iclk"));
2369
2370 s->i2c[0] = omap2_i2c_init(omap_l4tao(s->l4, 5),
2371 s->irq[0][OMAP_INT_24XX_I2C1_IRQ],
2372 &s->drq[OMAP24XX_DMA_I2C1_TX],
2373 omap_findclk(s, "i2c1.fclk"),
2374 omap_findclk(s, "i2c1.iclk"));
2375 s->i2c[1] = omap2_i2c_init(omap_l4tao(s->l4, 6),
2376 s->irq[0][OMAP_INT_24XX_I2C2_IRQ],
2377 &s->drq[OMAP24XX_DMA_I2C2_TX],
2378 omap_findclk(s, "i2c2.fclk"),
2379 omap_findclk(s, "i2c2.iclk"));
2380
2381 s->gpio = qdev_create(NULL, "omap2-gpio");
2382 qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model);
2383 qdev_prop_set_ptr(s->gpio, "iclk", omap_findclk(s, "gpio_iclk"));
2384 qdev_prop_set_ptr(s->gpio, "fclk0", omap_findclk(s, "gpio1_dbclk"));
2385 qdev_prop_set_ptr(s->gpio, "fclk1", omap_findclk(s, "gpio2_dbclk"));
2386 qdev_prop_set_ptr(s->gpio, "fclk2", omap_findclk(s, "gpio3_dbclk"));
2387 qdev_prop_set_ptr(s->gpio, "fclk3", omap_findclk(s, "gpio4_dbclk"));
2388 if (s->mpu_model == omap2430) {
2389 qdev_prop_set_ptr(s->gpio, "fclk4", omap_findclk(s, "gpio5_dbclk"));
2390 }
2391 qdev_init_nofail(s->gpio);
2392 busdev = sysbus_from_qdev(s->gpio);
2393 sysbus_connect_irq(busdev, 0, s->irq[0][OMAP_INT_24XX_GPIO_BANK1]);
2394 sysbus_connect_irq(busdev, 3, s->irq[0][OMAP_INT_24XX_GPIO_BANK2]);
2395 sysbus_connect_irq(busdev, 6, s->irq[0][OMAP_INT_24XX_GPIO_BANK3]);
2396 sysbus_connect_irq(busdev, 9, s->irq[0][OMAP_INT_24XX_GPIO_BANK4]);
2397 ta = omap_l4ta(s->l4, 3);
2398 sysbus_mmio_map(busdev, 0, omap_l4_region_base(ta, 1));
2399 sysbus_mmio_map(busdev, 1, omap_l4_region_base(ta, 0));
2400 sysbus_mmio_map(busdev, 2, omap_l4_region_base(ta, 2));
2401 sysbus_mmio_map(busdev, 3, omap_l4_region_base(ta, 4));
2402 sysbus_mmio_map(busdev, 4, omap_l4_region_base(ta, 5));
2403
2404 s->sdrc = omap_sdrc_init(0x68009000);
2405 s->gpmc = omap_gpmc_init(s, 0x6800a000, s->irq[0][OMAP_INT_24XX_GPMC_IRQ],
2406 s->drq[OMAP24XX_DMA_GPMC]);
2407
2408 dinfo = drive_get(IF_SD, 0, 0);
2409 if (!dinfo) {
2410 fprintf(stderr, "qemu: missing SecureDigital device\n");
2411 exit(1);
2412 }
2413 s->mmc = omap2_mmc_init(omap_l4tao(s->l4, 9), dinfo->bdrv,
2414 s->irq[0][OMAP_INT_24XX_MMC_IRQ],
2415 &s->drq[OMAP24XX_DMA_MMC1_TX],
2416 omap_findclk(s, "mmc_fclk"), omap_findclk(s, "mmc_iclk"));
2417
2418 s->mcspi[0] = omap_mcspi_init(omap_l4ta(s->l4, 35), 4,
2419 s->irq[0][OMAP_INT_24XX_MCSPI1_IRQ],
2420 &s->drq[OMAP24XX_DMA_SPI1_TX0],
2421 omap_findclk(s, "spi1_fclk"),
2422 omap_findclk(s, "spi1_iclk"));
2423 s->mcspi[1] = omap_mcspi_init(omap_l4ta(s->l4, 36), 2,
2424 s->irq[0][OMAP_INT_24XX_MCSPI2_IRQ],
2425 &s->drq[OMAP24XX_DMA_SPI2_TX0],
2426 omap_findclk(s, "spi2_fclk"),
2427 omap_findclk(s, "spi2_iclk"));
2428
2429 s->dss = omap_dss_init(omap_l4ta(s->l4, 10), 0x68000800,
2430 /* XXX wire M_IRQ_25, D_L2_IRQ_30 and I_IRQ_13 together */
2431 s->irq[0][OMAP_INT_24XX_DSS_IRQ], s->drq[OMAP24XX_DMA_DSS],
2432 omap_findclk(s, "dss_clk1"), omap_findclk(s, "dss_clk2"),
2433 omap_findclk(s, "dss_54m_clk"),
2434 omap_findclk(s, "dss_l3_iclk"),
2435 omap_findclk(s, "dss_l4_iclk"));
2436
2437 omap_sti_init(omap_l4ta(s->l4, 18), 0x54000000,
2438 s->irq[0][OMAP_INT_24XX_STI], omap_findclk(s, "emul_ck"),
2439 serial_hds[0] && serial_hds[1] && serial_hds[2] ?
2440 serial_hds[3] : NULL);
2441
2442 s->eac = omap_eac_init(omap_l4ta(s->l4, 32),
2443 s->irq[0][OMAP_INT_24XX_EAC_IRQ],
2444 /* Ten consecutive lines */
2445 &s->drq[OMAP24XX_DMA_EAC_AC_RD],
2446 omap_findclk(s, "func_96m_clk"),
2447 omap_findclk(s, "core_l4_iclk"));
2448
2449 /* All register mappings (includin those not currenlty implemented):
2450 * SystemControlMod 48000000 - 48000fff
2451 * SystemControlL4 48001000 - 48001fff
2452 * 32kHz Timer Mod 48004000 - 48004fff
2453 * 32kHz Timer L4 48005000 - 48005fff
2454 * PRCM ModA 48008000 - 480087ff
2455 * PRCM ModB 48008800 - 48008fff
2456 * PRCM L4 48009000 - 48009fff
2457 * TEST-BCM Mod 48012000 - 48012fff
2458 * TEST-BCM L4 48013000 - 48013fff
2459 * TEST-TAP Mod 48014000 - 48014fff
2460 * TEST-TAP L4 48015000 - 48015fff
2461 * GPIO1 Mod 48018000 - 48018fff
2462 * GPIO Top 48019000 - 48019fff
2463 * GPIO2 Mod 4801a000 - 4801afff
2464 * GPIO L4 4801b000 - 4801bfff
2465 * GPIO3 Mod 4801c000 - 4801cfff
2466 * GPIO4 Mod 4801e000 - 4801efff
2467 * WDTIMER1 Mod 48020000 - 48010fff
2468 * WDTIMER Top 48021000 - 48011fff
2469 * WDTIMER2 Mod 48022000 - 48012fff
2470 * WDTIMER L4 48023000 - 48013fff
2471 * WDTIMER3 Mod 48024000 - 48014fff
2472 * WDTIMER3 L4 48025000 - 48015fff
2473 * WDTIMER4 Mod 48026000 - 48016fff
2474 * WDTIMER4 L4 48027000 - 48017fff
2475 * GPTIMER1 Mod 48028000 - 48018fff
2476 * GPTIMER1 L4 48029000 - 48019fff
2477 * GPTIMER2 Mod 4802a000 - 4801afff
2478 * GPTIMER2 L4 4802b000 - 4801bfff
2479 * L4-Config AP 48040000 - 480407ff
2480 * L4-Config IP 48040800 - 48040fff
2481 * L4-Config LA 48041000 - 48041fff
2482 * ARM11ETB Mod 48048000 - 48049fff
2483 * ARM11ETB L4 4804a000 - 4804afff
2484 * DISPLAY Top 48050000 - 480503ff
2485 * DISPLAY DISPC 48050400 - 480507ff
2486 * DISPLAY RFBI 48050800 - 48050bff
2487 * DISPLAY VENC 48050c00 - 48050fff
2488 * DISPLAY L4 48051000 - 48051fff
2489 * CAMERA Top 48052000 - 480523ff
2490 * CAMERA core 48052400 - 480527ff
2491 * CAMERA DMA 48052800 - 48052bff
2492 * CAMERA MMU 48052c00 - 48052fff
2493 * CAMERA L4 48053000 - 48053fff
2494 * SDMA Mod 48056000 - 48056fff
2495 * SDMA L4 48057000 - 48057fff
2496 * SSI Top 48058000 - 48058fff
2497 * SSI GDD 48059000 - 48059fff
2498 * SSI Port1 4805a000 - 4805afff
2499 * SSI Port2 4805b000 - 4805bfff
2500 * SSI L4 4805c000 - 4805cfff
2501 * USB Mod 4805e000 - 480fefff
2502 * USB L4 4805f000 - 480fffff
2503 * WIN_TRACER1 Mod 48060000 - 48060fff
2504 * WIN_TRACER1 L4 48061000 - 48061fff
2505 * WIN_TRACER2 Mod 48062000 - 48062fff
2506 * WIN_TRACER2 L4 48063000 - 48063fff
2507 * WIN_TRACER3 Mod 48064000 - 48064fff
2508 * WIN_TRACER3 L4 48065000 - 48065fff
2509 * WIN_TRACER4 Top 48066000 - 480660ff
2510 * WIN_TRACER4 ETT 48066100 - 480661ff
2511 * WIN_TRACER4 WT 48066200 - 480662ff
2512 * WIN_TRACER4 L4 48067000 - 48067fff
2513 * XTI Mod 48068000 - 48068fff
2514 * XTI L4 48069000 - 48069fff
2515 * UART1 Mod 4806a000 - 4806afff
2516 * UART1 L4 4806b000 - 4806bfff
2517 * UART2 Mod 4806c000 - 4806cfff
2518 * UART2 L4 4806d000 - 4806dfff
2519 * UART3 Mod 4806e000 - 4806efff
2520 * UART3 L4 4806f000 - 4806ffff
2521 * I2C1 Mod 48070000 - 48070fff
2522 * I2C1 L4 48071000 - 48071fff
2523 * I2C2 Mod 48072000 - 48072fff
2524 * I2C2 L4 48073000 - 48073fff
2525 * McBSP1 Mod 48074000 - 48074fff
2526 * McBSP1 L4 48075000 - 48075fff
2527 * McBSP2 Mod 48076000 - 48076fff
2528 * McBSP2 L4 48077000 - 48077fff
2529 * GPTIMER3 Mod 48078000 - 48078fff
2530 * GPTIMER3 L4 48079000 - 48079fff
2531 * GPTIMER4 Mod 4807a000 - 4807afff
2532 * GPTIMER4 L4 4807b000 - 4807bfff
2533 * GPTIMER5 Mod 4807c000 - 4807cfff
2534 * GPTIMER5 L4 4807d000 - 4807dfff
2535 * GPTIMER6 Mod 4807e000 - 4807efff
2536 * GPTIMER6 L4 4807f000 - 4807ffff
2537 * GPTIMER7 Mod 48080000 - 48080fff
2538 * GPTIMER7 L4 48081000 - 48081fff
2539 * GPTIMER8 Mod 48082000 - 48082fff
2540 * GPTIMER8 L4 48083000 - 48083fff
2541 * GPTIMER9 Mod 48084000 - 48084fff
2542 * GPTIMER9 L4 48085000 - 48085fff
2543 * GPTIMER10 Mod 48086000 - 48086fff
2544 * GPTIMER10 L4 48087000 - 48087fff
2545 * GPTIMER11 Mod 48088000 - 48088fff
2546 * GPTIMER11 L4 48089000 - 48089fff
2547 * GPTIMER12 Mod 4808a000 - 4808afff
2548 * GPTIMER12 L4 4808b000 - 4808bfff
2549 * EAC Mod 48090000 - 48090fff
2550 * EAC L4 48091000 - 48091fff
2551 * FAC Mod 48092000 - 48092fff
2552 * FAC L4 48093000 - 48093fff
2553 * MAILBOX Mod 48094000 - 48094fff
2554 * MAILBOX L4 48095000 - 48095fff
2555 * SPI1 Mod 48098000 - 48098fff
2556 * SPI1 L4 48099000 - 48099fff
2557 * SPI2 Mod 4809a000 - 4809afff
2558 * SPI2 L4 4809b000 - 4809bfff
2559 * MMC/SDIO Mod 4809c000 - 4809cfff
2560 * MMC/SDIO L4 4809d000 - 4809dfff
2561 * MS_PRO Mod 4809e000 - 4809efff
2562 * MS_PRO L4 4809f000 - 4809ffff
2563 * RNG Mod 480a0000 - 480a0fff
2564 * RNG L4 480a1000 - 480a1fff
2565 * DES3DES Mod 480a2000 - 480a2fff
2566 * DES3DES L4 480a3000 - 480a3fff
2567 * SHA1MD5 Mod 480a4000 - 480a4fff
2568 * SHA1MD5 L4 480a5000 - 480a5fff
2569 * AES Mod 480a6000 - 480a6fff
2570 * AES L4 480a7000 - 480a7fff
2571 * PKA Mod 480a8000 - 480a9fff
2572 * PKA L4 480aa000 - 480aafff
2573 * MG Mod 480b0000 - 480b0fff
2574 * MG L4 480b1000 - 480b1fff
2575 * HDQ/1-wire Mod 480b2000 - 480b2fff
2576 * HDQ/1-wire L4 480b3000 - 480b3fff
2577 * MPU interrupt 480fe000 - 480fefff
2578 * STI channel base 54000000 - 5400ffff
2579 * IVA RAM 5c000000 - 5c01ffff
2580 * IVA ROM 5c020000 - 5c027fff
2581 * IMG_BUF_A 5c040000 - 5c040fff
2582 * IMG_BUF_B 5c042000 - 5c042fff
2583 * VLCDS 5c048000 - 5c0487ff
2584 * IMX_COEF 5c049000 - 5c04afff
2585 * IMX_CMD 5c051000 - 5c051fff
2586 * VLCDQ 5c053000 - 5c0533ff
2587 * VLCDH 5c054000 - 5c054fff
2588 * SEQ_CMD 5c055000 - 5c055fff
2589 * IMX_REG 5c056000 - 5c0560ff
2590 * VLCD_REG 5c056100 - 5c0561ff
2591 * SEQ_REG 5c056200 - 5c0562ff
2592 * IMG_BUF_REG 5c056300 - 5c0563ff
2593 * SEQIRQ_REG 5c056400 - 5c0564ff
2594 * OCP_REG 5c060000 - 5c060fff
2595 * SYSC_REG 5c070000 - 5c070fff
2596 * MMU_REG 5d000000 - 5d000fff
2597 * sDMA R 68000400 - 680005ff
2598 * sDMA W 68000600 - 680007ff
2599 * Display Control 68000800 - 680009ff
2600 * DSP subsystem 68000a00 - 68000bff
2601 * MPU subsystem 68000c00 - 68000dff
2602 * IVA subsystem 68001000 - 680011ff
2603 * USB 68001200 - 680013ff
2604 * Camera 68001400 - 680015ff
2605 * VLYNQ (firewall) 68001800 - 68001bff
2606 * VLYNQ 68001e00 - 68001fff
2607 * SSI 68002000 - 680021ff
2608 * L4 68002400 - 680025ff
2609 * DSP (firewall) 68002800 - 68002bff
2610 * DSP subsystem 68002e00 - 68002fff
2611 * IVA (firewall) 68003000 - 680033ff
2612 * IVA 68003600 - 680037ff
2613 * GFX 68003a00 - 68003bff
2614 * CMDWR emulation 68003c00 - 68003dff
2615 * SMS 68004000 - 680041ff
2616 * OCM 68004200 - 680043ff
2617 * GPMC 68004400 - 680045ff
2618 * RAM (firewall) 68005000 - 680053ff
2619 * RAM (err login) 68005400 - 680057ff
2620 * ROM (firewall) 68005800 - 68005bff
2621 * ROM (err login) 68005c00 - 68005fff
2622 * GPMC (firewall) 68006000 - 680063ff
2623 * GPMC (err login) 68006400 - 680067ff
2624 * SMS (err login) 68006c00 - 68006fff
2625 * SMS registers 68008000 - 68008fff
2626 * SDRC registers 68009000 - 68009fff
2627 * GPMC registers 6800a000 6800afff
2628 */
2629
2630 qemu_register_reset(omap2_mpu_reset, s);
2631
2632 return s;
2633 }
AR7 emulation for QEMU