4 * Copyright IBM, Corp. 2011
7 * Anthony Liguori <aliguori@us.ibm.com>
9 * This work is licensed under the terms of the GNU GPL, version 2 or later.
10 * See the COPYING file in the top-level directory.
14 #include "qemu/osdep.h"
15 #include "sysemu/qtest.h"
17 #include "sysemu/char.h"
18 #include "exec/ioport.h"
19 #include "exec/memory.h"
21 #include "sysemu/accel.h"
22 #include "sysemu/sysemu.h"
23 #include "sysemu/cpus.h"
24 #include "qemu/config-file.h"
25 #include "qemu/option.h"
26 #include "qemu/error-report.h"
32 static DeviceState
*irq_intercept_dev
;
33 static FILE *qtest_log_fp
;
34 static CharDriverState
*qtest_chr
;
35 static GString
*inbuf
;
36 static int irq_levels
[MAX_IRQ
];
37 static qemu_timeval start_time
;
38 static bool qtest_opened
;
40 #define FMT_timeval "%ld.%06ld"
45 * Line based protocol, request/response based. Server can send async messages
46 * so clients should always handle many async messages before the response
53 * The qtest client is completely in charge of the QEMU_CLOCK_VIRTUAL. qtest commands
54 * let you adjust the value of the clock (monotonically). All the commands
55 * return the current value of the clock in nanoseconds.
60 * Advance the clock to the next deadline. Useful when waiting for
61 * asynchronous events.
66 * Advance the clock by NS nanoseconds.
71 * Advance the clock to NS nanoseconds (do nothing if it's already past).
73 * PIO and memory access:
102 * > writeq ADDR VALUE
120 * > write ADDR SIZE DATA
123 * > b64read ADDR SIZE
126 * > b64write ADDR SIZE B64_DATA
129 * > memset ADDR SIZE VALUE
132 * ADDR, SIZE, VALUE are all integers parsed with strtoul() with a base of 0.
134 * DATA is an arbitrarily long hex number prefixed with '0x'. If it's smaller
135 * than the expected size, the value will be zero filled at the end of the data
138 * B64_DATA is an arbitrarily long base64 encoded string.
139 * If the sizes do not match, the data will be truncated.
143 * > irq_intercept_in QOM-PATH
146 * > irq_intercept_out QOM-PATH
149 * Attach to the gpio-in (resp. gpio-out) pins exported by the device at
150 * QOM-PATH. When the pin is triggered, one of the following async messages
151 * will be printed to the qtest stream:
156 * where NUM is an IRQ number. For the PC, interrupts can be intercepted
157 * simply with "irq_intercept_in ioapic" (note that IRQ0 comes out with
158 * NUM=0 even though it is remapped to GSI 2).
161 static int hex2nib(char ch
)
163 if (ch
>= '0' && ch
<= '9') {
165 } else if (ch
>= 'a' && ch
<= 'f') {
166 return 10 + (ch
- 'a');
167 } else if (ch
>= 'A' && ch
<= 'F') {
168 return 10 + (ch
- 'A');
174 static void qtest_get_time(qemu_timeval
*tv
)
176 qemu_gettimeofday(tv
);
177 tv
->tv_sec
-= start_time
.tv_sec
;
178 tv
->tv_usec
-= start_time
.tv_usec
;
179 if (tv
->tv_usec
< 0) {
180 tv
->tv_usec
+= 1000000;
185 static void qtest_send_prefix(CharDriverState
*chr
)
189 if (!qtest_log_fp
|| !qtest_opened
) {
194 fprintf(qtest_log_fp
, "[S +" FMT_timeval
"] ",
195 (long) tv
.tv_sec
, (long) tv
.tv_usec
);
198 static void GCC_FMT_ATTR(1, 2) qtest_log_send(const char *fmt
, ...)
202 if (!qtest_log_fp
|| !qtest_opened
) {
206 qtest_send_prefix(NULL
);
209 vfprintf(qtest_log_fp
, fmt
, ap
);
213 static void do_qtest_send(CharDriverState
*chr
, const char *str
, size_t len
)
215 qemu_chr_fe_write_all(chr
, (uint8_t *)str
, len
);
216 if (qtest_log_fp
&& qtest_opened
) {
217 fprintf(qtest_log_fp
, "%s", str
);
221 static void qtest_send(CharDriverState
*chr
, const char *str
)
223 do_qtest_send(chr
, str
, strlen(str
));
226 static void GCC_FMT_ATTR(2, 3) qtest_sendf(CharDriverState
*chr
,
227 const char *fmt
, ...)
233 buffer
= g_strdup_vprintf(fmt
, ap
);
234 qtest_send(chr
, buffer
);
238 static void qtest_irq_handler(void *opaque
, int n
, int level
)
240 qemu_irq old_irq
= *(qemu_irq
*)opaque
;
241 qemu_set_irq(old_irq
, level
);
243 if (irq_levels
[n
] != level
) {
244 CharDriverState
*chr
= qtest_chr
;
245 irq_levels
[n
] = level
;
246 qtest_send_prefix(chr
);
247 qtest_sendf(chr
, "IRQ %s %d\n",
248 level
? "raise" : "lower", n
);
252 static void qtest_process_command(CharDriverState
*chr
, gchar
**words
)
254 const gchar
*command
;
265 fprintf(qtest_log_fp
, "[R +" FMT_timeval
"]",
266 (long) tv
.tv_sec
, (long) tv
.tv_usec
);
267 for (i
= 0; words
[i
]; i
++) {
268 fprintf(qtest_log_fp
, " %s", words
[i
]);
270 fprintf(qtest_log_fp
, "\n");
274 if (strcmp(words
[0], "irq_intercept_out") == 0
275 || strcmp(words
[0], "irq_intercept_in") == 0) {
280 dev
= DEVICE(object_resolve_path(words
[1], NULL
));
282 qtest_send_prefix(chr
);
283 qtest_send(chr
, "FAIL Unknown device\n");
287 if (irq_intercept_dev
) {
288 qtest_send_prefix(chr
);
289 if (irq_intercept_dev
!= dev
) {
290 qtest_send(chr
, "FAIL IRQ intercept already enabled\n");
292 qtest_send(chr
, "OK\n");
297 QLIST_FOREACH(ngl
, &dev
->gpios
, node
) {
298 /* We don't support intercept of named GPIOs yet */
302 if (words
[0][14] == 'o') {
304 for (i
= 0; i
< ngl
->num_out
; ++i
) {
305 qemu_irq
*disconnected
= g_new0(qemu_irq
, 1);
306 qemu_irq icpt
= qemu_allocate_irq(qtest_irq_handler
,
309 *disconnected
= qdev_intercept_gpio_out(dev
, icpt
,
313 qemu_irq_intercept_in(ngl
->in
, qtest_irq_handler
,
317 irq_intercept_dev
= dev
;
318 qtest_send_prefix(chr
);
319 qtest_send(chr
, "OK\n");
321 } else if (strcmp(words
[0], "outb") == 0 ||
322 strcmp(words
[0], "outw") == 0 ||
323 strcmp(words
[0], "outl") == 0) {
327 g_assert(words
[1] && words
[2]);
328 addr
= strtoul(words
[1], NULL
, 0);
329 value
= strtoul(words
[2], NULL
, 0);
331 if (words
[0][3] == 'b') {
332 cpu_outb(addr
, value
);
333 } else if (words
[0][3] == 'w') {
334 cpu_outw(addr
, value
);
335 } else if (words
[0][3] == 'l') {
336 cpu_outl(addr
, value
);
338 qtest_send_prefix(chr
);
339 qtest_send(chr
, "OK\n");
340 } else if (strcmp(words
[0], "inb") == 0 ||
341 strcmp(words
[0], "inw") == 0 ||
342 strcmp(words
[0], "inl") == 0) {
344 uint32_t value
= -1U;
347 addr
= strtoul(words
[1], NULL
, 0);
349 if (words
[0][2] == 'b') {
350 value
= cpu_inb(addr
);
351 } else if (words
[0][2] == 'w') {
352 value
= cpu_inw(addr
);
353 } else if (words
[0][2] == 'l') {
354 value
= cpu_inl(addr
);
356 qtest_send_prefix(chr
);
357 qtest_sendf(chr
, "OK 0x%04x\n", value
);
358 } else if (strcmp(words
[0], "writeb") == 0 ||
359 strcmp(words
[0], "writew") == 0 ||
360 strcmp(words
[0], "writel") == 0 ||
361 strcmp(words
[0], "writeq") == 0) {
365 g_assert(words
[1] && words
[2]);
366 addr
= strtoull(words
[1], NULL
, 0);
367 value
= strtoull(words
[2], NULL
, 0);
369 if (words
[0][5] == 'b') {
370 uint8_t data
= value
;
371 cpu_physical_memory_write(addr
, &data
, 1);
372 } else if (words
[0][5] == 'w') {
373 uint16_t data
= value
;
375 cpu_physical_memory_write(addr
, &data
, 2);
376 } else if (words
[0][5] == 'l') {
377 uint32_t data
= value
;
379 cpu_physical_memory_write(addr
, &data
, 4);
380 } else if (words
[0][5] == 'q') {
381 uint64_t data
= value
;
383 cpu_physical_memory_write(addr
, &data
, 8);
385 qtest_send_prefix(chr
);
386 qtest_send(chr
, "OK\n");
387 } else if (strcmp(words
[0], "readb") == 0 ||
388 strcmp(words
[0], "readw") == 0 ||
389 strcmp(words
[0], "readl") == 0 ||
390 strcmp(words
[0], "readq") == 0) {
392 uint64_t value
= UINT64_C(-1);
395 addr
= strtoull(words
[1], NULL
, 0);
397 if (words
[0][4] == 'b') {
399 cpu_physical_memory_read(addr
, &data
, 1);
401 } else if (words
[0][4] == 'w') {
403 cpu_physical_memory_read(addr
, &data
, 2);
404 value
= tswap16(data
);
405 } else if (words
[0][4] == 'l') {
407 cpu_physical_memory_read(addr
, &data
, 4);
408 value
= tswap32(data
);
409 } else if (words
[0][4] == 'q') {
410 cpu_physical_memory_read(addr
, &value
, 8);
413 qtest_send_prefix(chr
);
414 qtest_sendf(chr
, "OK 0x%016" PRIx64
"\n", value
);
415 } else if (strcmp(words
[0], "read") == 0) {
416 uint64_t addr
, len
, i
;
420 g_assert(words
[1] && words
[2]);
421 addr
= strtoull(words
[1], NULL
, 0);
422 len
= strtoull(words
[2], NULL
, 0);
424 data
= g_malloc(len
);
425 cpu_physical_memory_read(addr
, data
, len
);
427 enc
= g_malloc(2 * len
+ 1);
428 for (i
= 0; i
< len
; i
++) {
429 sprintf(&enc
[i
* 2], "%02x", data
[i
]);
432 qtest_send_prefix(chr
);
433 qtest_sendf(chr
, "OK 0x%s\n", enc
);
437 } else if (strcmp(words
[0], "b64read") == 0) {
442 g_assert(words
[1] && words
[2]);
443 addr
= strtoull(words
[1], NULL
, 0);
444 len
= strtoull(words
[2], NULL
, 0);
446 data
= g_malloc(len
);
447 cpu_physical_memory_read(addr
, data
, len
);
448 b64_data
= g_base64_encode(data
, len
);
449 qtest_send_prefix(chr
);
450 qtest_sendf(chr
, "OK %s\n", b64_data
);
454 } else if (strcmp(words
[0], "write") == 0) {
455 uint64_t addr
, len
, i
;
459 g_assert(words
[1] && words
[2] && words
[3]);
460 addr
= strtoull(words
[1], NULL
, 0);
461 len
= strtoull(words
[2], NULL
, 0);
463 data_len
= strlen(words
[3]);
465 qtest_send(chr
, "ERR invalid argument size\n");
469 data
= g_malloc(len
);
470 for (i
= 0; i
< len
; i
++) {
471 if ((i
* 2 + 4) <= data_len
) {
472 data
[i
] = hex2nib(words
[3][i
* 2 + 2]) << 4;
473 data
[i
] |= hex2nib(words
[3][i
* 2 + 3]);
478 cpu_physical_memory_write(addr
, data
, len
);
481 qtest_send_prefix(chr
);
482 qtest_send(chr
, "OK\n");
483 } else if (strcmp(words
[0], "memset") == 0) {
488 g_assert(words
[1] && words
[2] && words
[3]);
489 addr
= strtoull(words
[1], NULL
, 0);
490 len
= strtoull(words
[2], NULL
, 0);
491 pattern
= strtoull(words
[3], NULL
, 0);
493 data
= g_malloc(len
);
494 memset(data
, pattern
, len
);
495 cpu_physical_memory_write(addr
, data
, len
);
498 qtest_send_prefix(chr
);
499 qtest_send(chr
, "OK\n");
500 } else if (strcmp(words
[0], "b64write") == 0) {
506 g_assert(words
[1] && words
[2] && words
[3]);
507 addr
= strtoull(words
[1], NULL
, 0);
508 len
= strtoull(words
[2], NULL
, 0);
510 data_len
= strlen(words
[3]);
512 qtest_send(chr
, "ERR invalid argument size\n");
516 data
= g_base64_decode_inplace(words
[3], &out_len
);
517 if (out_len
!= len
) {
518 qtest_log_send("b64write: data length mismatch (told %"PRIu64
", "
521 out_len
= MIN(out_len
, len
);
524 cpu_physical_memory_write(addr
, data
, out_len
);
526 qtest_send_prefix(chr
);
527 qtest_send(chr
, "OK\n");
528 } else if (qtest_enabled() && strcmp(words
[0], "clock_step") == 0) {
532 ns
= strtoll(words
[1], NULL
, 0);
534 ns
= qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL
);
536 qtest_clock_warp(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + ns
);
537 qtest_send_prefix(chr
);
538 qtest_sendf(chr
, "OK %"PRIi64
"\n",
539 (int64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
));
540 } else if (qtest_enabled() && strcmp(words
[0], "clock_set") == 0) {
544 ns
= strtoll(words
[1], NULL
, 0);
545 qtest_clock_warp(ns
);
546 qtest_send_prefix(chr
);
547 qtest_sendf(chr
, "OK %"PRIi64
"\n",
548 (int64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
));
550 qtest_send_prefix(chr
);
551 qtest_sendf(chr
, "FAIL Unknown command '%s'\n", words
[0]);
555 static void qtest_process_inbuf(CharDriverState
*chr
, GString
*inbuf
)
559 while ((end
= strchr(inbuf
->str
, '\n')) != NULL
) {
564 offset
= end
- inbuf
->str
;
566 cmd
= g_string_new_len(inbuf
->str
, offset
);
567 g_string_erase(inbuf
, 0, offset
+ 1);
569 words
= g_strsplit(cmd
->str
, " ", 0);
570 qtest_process_command(chr
, words
);
573 g_string_free(cmd
, TRUE
);
577 static void qtest_read(void *opaque
, const uint8_t *buf
, int size
)
579 CharDriverState
*chr
= opaque
;
581 g_string_append_len(inbuf
, (const gchar
*)buf
, size
);
582 qtest_process_inbuf(chr
, inbuf
);
585 static int qtest_can_read(void *opaque
)
590 static void qtest_event(void *opaque
, int event
)
595 case CHR_EVENT_OPENED
:
597 * We used to call qemu_system_reset() here, hoping we could
598 * use the same process for multiple tests that way. Never
599 * used. Injects an extra reset even when it's not used, and
600 * that can mess up tests, e.g. -boot once.
602 for (i
= 0; i
< ARRAY_SIZE(irq_levels
); i
++) {
605 qemu_gettimeofday(&start_time
);
608 fprintf(qtest_log_fp
, "[I " FMT_timeval
"] OPENED\n",
609 (long) start_time
.tv_sec
, (long) start_time
.tv_usec
);
612 case CHR_EVENT_CLOSED
:
613 qtest_opened
= false;
617 fprintf(qtest_log_fp
, "[I +" FMT_timeval
"] CLOSED\n",
618 (long) tv
.tv_sec
, (long) tv
.tv_usec
);
626 static int qtest_init_accel(MachineState
*ms
)
628 QemuOpts
*opts
= qemu_opts_create(qemu_find_opts("icount"), NULL
, 0,
630 qemu_opt_set(opts
, "shift", "0", &error_abort
);
631 configure_icount(opts
, &error_abort
);
636 void qtest_init(const char *qtest_chrdev
, const char *qtest_log
, Error
**errp
)
638 CharDriverState
*chr
;
640 chr
= qemu_chr_new("qtest", qtest_chrdev
, NULL
);
643 error_setg(errp
, "Failed to initialize device for qtest: \"%s\"",
649 if (strcmp(qtest_log
, "none") != 0) {
650 qtest_log_fp
= fopen(qtest_log
, "w+");
653 qtest_log_fp
= stderr
;
656 qemu_chr_add_handlers(chr
, qtest_can_read
, qtest_read
, qtest_event
, chr
);
657 qemu_chr_fe_set_echo(chr
, true);
659 inbuf
= g_string_new("");
663 bool qtest_driver(void)
668 static void qtest_accel_class_init(ObjectClass
*oc
, void *data
)
670 AccelClass
*ac
= ACCEL_CLASS(oc
);
672 ac
->available
= qtest_available
;
673 ac
->init_machine
= qtest_init_accel
;
674 ac
->allowed
= &qtest_allowed
;
677 #define TYPE_QTEST_ACCEL ACCEL_CLASS_NAME("qtest")
679 static const TypeInfo qtest_accel_type
= {
680 .name
= TYPE_QTEST_ACCEL
,
681 .parent
= TYPE_ACCEL
,
682 .class_init
= qtest_accel_class_init
,
685 static void qtest_type_init(void)
687 type_register_static(&qtest_accel_type
);
690 type_init(qtest_type_init
);