hw/pci/shpc.c

   1 #include "qemu/osdep.h"
   2 #include "qapi/error.h"
   3 #include "qemu/host-utils.h"
   4 #include "qemu/range.h"
   5 #include "qemu/error-report.h"
   6 #include "hw/pci/shpc.h"
   7 #include "migration/qemu-file-types.h"
   8 #include "hw/pci/pci.h"
   9 #include "hw/pci/pci_bus.h"
  10 #include "hw/pci/msi.h"
  11
  12 /* TODO: model power only and disabled slot states. */
  13 /* TODO: handle SERR and wakeups */
  14 /* TODO: consider enabling 66MHz support */
  15
  16 /* TODO: remove fully only on state DISABLED and LED off.
  17  * track state to properly record this. */
  18
  19 /* SHPC Working Register Set */
  20 #define SHPC_BASE_OFFSET  0x00 /* 4 bytes */
  21 #define SHPC_SLOTS_33     0x04 /* 4 bytes. Also encodes PCI-X slots. */
  22 #define SHPC_SLOTS_66     0x08 /* 4 bytes. */
  23 #define SHPC_NSLOTS       0x0C /* 1 byte */
  24 #define SHPC_FIRST_DEV    0x0D /* 1 byte */
  25 #define SHPC_PHYS_SLOT    0x0E /* 2 byte */
  26 #define SHPC_PHYS_NUM_MAX 0x7ff
  27 #define SHPC_PHYS_NUM_UP  0x2000
  28 #define SHPC_PHYS_MRL     0x4000
  29 #define SHPC_PHYS_BUTTON  0x8000
  30 #define SHPC_SEC_BUS      0x10 /* 2 bytes */
  31 #define SHPC_SEC_BUS_33   0x0
  32 #define SHPC_SEC_BUS_66   0x1 /* Unused */
  33 #define SHPC_SEC_BUS_MASK 0x7
  34 #define SHPC_MSI_CTL      0x12 /* 1 byte */
  35 #define SHPC_PROG_IFC     0x13 /* 1 byte */
  36 #define SHPC_PROG_IFC_1_0 0x1
  37 #define SHPC_CMD_CODE     0x14 /* 1 byte */
  38 #define SHPC_CMD_TRGT     0x15 /* 1 byte */
  39 #define SHPC_CMD_TRGT_MIN 0x1
  40 #define SHPC_CMD_TRGT_MAX 0x1f
  41 #define SHPC_CMD_STATUS   0x16 /* 2 bytes */
  42 #define SHPC_CMD_STATUS_BUSY          0x1
  43 #define SHPC_CMD_STATUS_MRL_OPEN      0x2
  44 #define SHPC_CMD_STATUS_INVALID_CMD   0x4
  45 #define SHPC_CMD_STATUS_INVALID_MODE  0x8
  46 #define SHPC_INT_LOCATOR  0x18 /* 4 bytes */
  47 #define SHPC_INT_COMMAND  0x1
  48 #define SHPC_SERR_LOCATOR 0x1C /* 4 bytes */
  49 #define SHPC_SERR_INT     0x20 /* 4 bytes */
  50 #define SHPC_INT_DIS      0x1
  51 #define SHPC_SERR_DIS     0x2
  52 #define SHPC_CMD_INT_DIS  0x4
  53 #define SHPC_ARB_SERR_DIS 0x8
  54 #define SHPC_CMD_DETECTED 0x10000
  55 #define SHPC_ARB_DETECTED 0x20000
  56  /* 4 bytes * slot # (start from 0) */
  57 #define SHPC_SLOT_REG(s)         (0x24 + (s) * 4)
  58  /* 2 bytes */
  59 #define SHPC_SLOT_STATUS(s)       (0x0 + SHPC_SLOT_REG(s))
  60
  61 /* Same slot state masks are used for command and status registers */
  62 #define SHPC_SLOT_STATE_MASK     0x03
  63 #define SHPC_SLOT_STATE_SHIFT \
  64     ctz32(SHPC_SLOT_STATE_MASK)
  65
  66 #define SHPC_STATE_NO       0x0
  67 #define SHPC_STATE_PWRONLY  0x1
  68 #define SHPC_STATE_ENABLED  0x2
  69 #define SHPC_STATE_DISABLED 0x3
  70
  71 #define SHPC_SLOT_PWR_LED_MASK   0xC
  72 #define SHPC_SLOT_PWR_LED_SHIFT \
  73     ctz32(SHPC_SLOT_PWR_LED_MASK)
  74 #define SHPC_SLOT_ATTN_LED_MASK  0x30
  75 #define SHPC_SLOT_ATTN_LED_SHIFT \
  76     ctz32(SHPC_SLOT_ATTN_LED_MASK)
  77
  78 #define SHPC_LED_NO     0x0
  79 #define SHPC_LED_ON     0x1
  80 #define SHPC_LED_BLINK  0x2
  81 #define SHPC_LED_OFF    0x3
  82
  83 #define SHPC_SLOT_STATUS_PWR_FAULT      0x40
  84 #define SHPC_SLOT_STATUS_BUTTON         0x80
  85 #define SHPC_SLOT_STATUS_MRL_OPEN       0x100
  86 #define SHPC_SLOT_STATUS_66             0x200
  87 #define SHPC_SLOT_STATUS_PRSNT_MASK     0xC00
  88 #define SHPC_SLOT_STATUS_PRSNT_EMPTY    0x3
  89 #define SHPC_SLOT_STATUS_PRSNT_25W      0x1
  90 #define SHPC_SLOT_STATUS_PRSNT_15W      0x2
  91 #define SHPC_SLOT_STATUS_PRSNT_7_5W     0x0
  92
  93 #define SHPC_SLOT_STATUS_PRSNT_PCIX     0x3000
  94
  95
  96  /* 1 byte */
  97 #define SHPC_SLOT_EVENT_LATCH(s)        (0x2 + SHPC_SLOT_REG(s))
  98  /* 1 byte */
  99 #define SHPC_SLOT_EVENT_SERR_INT_DIS(d, s) (0x3 + SHPC_SLOT_REG(s))
 100 #define SHPC_SLOT_EVENT_PRESENCE        0x01
 101 #define SHPC_SLOT_EVENT_ISOLATED_FAULT  0x02
 102 #define SHPC_SLOT_EVENT_BUTTON          0x04
 103 #define SHPC_SLOT_EVENT_MRL             0x08
 104 #define SHPC_SLOT_EVENT_CONNECTED_FAULT 0x10
 105 /* Bits below are used for Serr/Int disable only */
 106 #define SHPC_SLOT_EVENT_MRL_SERR_DIS    0x20
 107 #define SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS 0x40
 108
 109 #define SHPC_MIN_SLOTS        1
 110 #define SHPC_MAX_SLOTS        31
 111 #define SHPC_SIZEOF(d)    SHPC_SLOT_REG((d)->shpc->nslots)
 112
 113 /* SHPC Slot identifiers */
 114
 115 /* Hotplug supported at 31 slots out of the total 32.  We reserve slot 0,
 116    and give the rest of them physical *and* pci numbers starting from 1, so
 117    they match logical numbers.  Note: this means that multiple slots must have
 118    different chassis number values, to make chassis+physical slot unique.
 119    TODO: make this configurable? */
 120 #define SHPC_IDX_TO_LOGICAL(slot) ((slot) + 1)
 121 #define SHPC_LOGICAL_TO_IDX(target) ((target) - 1)
 122 #define SHPC_IDX_TO_PCI(slot) ((slot) + 1)
 123 #define SHPC_PCI_TO_IDX(pci_slot) ((pci_slot) - 1)
 124 #define SHPC_IDX_TO_PHYSICAL(slot) ((slot) + 1)
 125
 126 static uint8_t shpc_get_status(SHPCDevice *shpc, int slot, uint16_t msk)
 127 {
 128     uint8_t *status = shpc->config + SHPC_SLOT_STATUS(slot);
 129     uint16_t result = (pci_get_word(status) & msk) >> ctz32(msk);
 130
 131     assert(result <= UINT8_MAX);
 132     return result;
 133 }
 134
 135 static void shpc_set_status(SHPCDevice *shpc,
 136                             int slot, uint8_t value, uint16_t msk)
 137 {
 138     uint8_t *status = shpc->config + SHPC_SLOT_STATUS(slot);
 139     pci_word_test_and_clear_mask(status, msk);
 140     pci_word_test_and_set_mask(status, value << ctz32(msk));
 141 }
 142
 143 static void shpc_interrupt_update(PCIDevice *d)
 144 {
 145     SHPCDevice *shpc = d->shpc;
 146     int slot;
 147     int level = 0;
 148     uint32_t serr_int;
 149     uint32_t int_locator = 0;
 150
 151     /* Update interrupt locator register */
 152     for (slot = 0; slot < shpc->nslots; ++slot) {
 153         uint8_t event = shpc->config[SHPC_SLOT_EVENT_LATCH(slot)];
 154         uint8_t disable = shpc->config[SHPC_SLOT_EVENT_SERR_INT_DIS(d, slot)];
 155         uint32_t mask = 1U << SHPC_IDX_TO_LOGICAL(slot);
 156         if (event & ~disable) {
 157             int_locator |= mask;
 158         }
 159     }
 160     serr_int = pci_get_long(shpc->config + SHPC_SERR_INT);
 161     if ((serr_int & SHPC_CMD_DETECTED) && !(serr_int & SHPC_CMD_INT_DIS)) {
 162         int_locator |= SHPC_INT_COMMAND;
 163     }
 164     pci_set_long(shpc->config + SHPC_INT_LOCATOR, int_locator);
 165     level = (!(serr_int & SHPC_INT_DIS) && int_locator) ? 1 : 0;
 166     if (msi_enabled(d) && shpc->msi_requested != level)
 167         msi_notify(d, 0);
 168     else
 169         pci_set_irq(d, level);
 170     shpc->msi_requested = level;
 171 }
 172
 173 static void shpc_set_sec_bus_speed(SHPCDevice *shpc, uint8_t speed)
 174 {
 175     switch (speed) {
 176     case SHPC_SEC_BUS_33:
 177         shpc->config[SHPC_SEC_BUS] &= ~SHPC_SEC_BUS_MASK;
 178         shpc->config[SHPC_SEC_BUS] |= speed;
 179         break;
 180     default:
 181         pci_word_test_and_set_mask(shpc->config + SHPC_CMD_STATUS,
 182                                    SHPC_CMD_STATUS_INVALID_MODE);
 183     }
 184 }
 185
 186 void shpc_reset(PCIDevice *d)
 187 {
 188     SHPCDevice *shpc = d->shpc;
 189     int nslots = shpc->nslots;
 190     int i;
 191     memset(shpc->config, 0, SHPC_SIZEOF(d));
 192     pci_set_byte(shpc->config + SHPC_NSLOTS, nslots);
 193     pci_set_long(shpc->config + SHPC_SLOTS_33, nslots);
 194     pci_set_long(shpc->config + SHPC_SLOTS_66, 0);
 195     pci_set_byte(shpc->config + SHPC_FIRST_DEV, SHPC_IDX_TO_PCI(0));
 196     pci_set_word(shpc->config + SHPC_PHYS_SLOT,
 197                  SHPC_IDX_TO_PHYSICAL(0) |
 198                  SHPC_PHYS_NUM_UP |
 199                  SHPC_PHYS_MRL |
 200                  SHPC_PHYS_BUTTON);
 201     pci_set_long(shpc->config + SHPC_SERR_INT, SHPC_INT_DIS |
 202                  SHPC_SERR_DIS |
 203                  SHPC_CMD_INT_DIS |
 204                  SHPC_ARB_SERR_DIS);
 205     pci_set_byte(shpc->config + SHPC_PROG_IFC, SHPC_PROG_IFC_1_0);
 206     pci_set_word(shpc->config + SHPC_SEC_BUS, SHPC_SEC_BUS_33);
 207     for (i = 0; i < shpc->nslots; ++i) {
 208         pci_set_byte(shpc->config + SHPC_SLOT_EVENT_SERR_INT_DIS(d, i),
 209                      SHPC_SLOT_EVENT_PRESENCE |
 210                      SHPC_SLOT_EVENT_ISOLATED_FAULT |
 211                      SHPC_SLOT_EVENT_BUTTON |
 212                      SHPC_SLOT_EVENT_MRL |
 213                      SHPC_SLOT_EVENT_CONNECTED_FAULT |
 214                      SHPC_SLOT_EVENT_MRL_SERR_DIS |
 215                      SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS);
 216         if (shpc->sec_bus->devices[PCI_DEVFN(SHPC_IDX_TO_PCI(i), 0)]) {
 217             shpc_set_status(shpc, i, SHPC_STATE_ENABLED, SHPC_SLOT_STATE_MASK);
 218             shpc_set_status(shpc, i, 0, SHPC_SLOT_STATUS_MRL_OPEN);
 219             shpc_set_status(shpc, i, SHPC_SLOT_STATUS_PRSNT_7_5W,
 220                             SHPC_SLOT_STATUS_PRSNT_MASK);
 221             shpc_set_status(shpc, i, SHPC_LED_ON, SHPC_SLOT_PWR_LED_MASK);
 222         } else {
 223             shpc_set_status(shpc, i, SHPC_STATE_DISABLED, SHPC_SLOT_STATE_MASK);
 224             shpc_set_status(shpc, i, 1, SHPC_SLOT_STATUS_MRL_OPEN);
 225             shpc_set_status(shpc, i, SHPC_SLOT_STATUS_PRSNT_EMPTY,
 226                             SHPC_SLOT_STATUS_PRSNT_MASK);
 227             shpc_set_status(shpc, i, SHPC_LED_OFF, SHPC_SLOT_PWR_LED_MASK);
 228         }
 229         shpc_set_status(shpc, i, SHPC_LED_OFF, SHPC_SLOT_ATTN_LED_MASK);
 230         shpc_set_status(shpc, i, 0, SHPC_SLOT_STATUS_66);
 231     }
 232     shpc_set_sec_bus_speed(shpc, SHPC_SEC_BUS_33);
 233     shpc->msi_requested = 0;
 234     shpc_interrupt_update(d);
 235 }
 236
 237 static void shpc_invalid_command(SHPCDevice *shpc)
 238 {
 239     pci_word_test_and_set_mask(shpc->config + SHPC_CMD_STATUS,
 240                                SHPC_CMD_STATUS_INVALID_CMD);
 241 }
 242
 243 static void shpc_free_devices_in_slot(SHPCDevice *shpc, int slot)
 244 {
 245     HotplugHandler *hotplug_ctrl;
 246     int devfn;
 247     int pci_slot = SHPC_IDX_TO_PCI(slot);
 248     for (devfn = PCI_DEVFN(pci_slot, 0);
 249          devfn <= PCI_DEVFN(pci_slot, PCI_FUNC_MAX - 1);
 250          ++devfn) {
 251         PCIDevice *affected_dev = shpc->sec_bus->devices[devfn];
 252         if (affected_dev) {
 253             hotplug_ctrl = qdev_get_hotplug_handler(DEVICE(affected_dev));
 254             hotplug_handler_unplug(hotplug_ctrl, DEVICE(affected_dev),
 255                                    &error_abort);
 256             object_unparent(OBJECT(affected_dev));
 257         }
 258     }
 259 }
 260
 261 static bool shpc_slot_is_off(uint8_t state, uint8_t power, uint8_t attn)
 262 {
 263     return state == SHPC_STATE_DISABLED && power == SHPC_LED_OFF;
 264 }
 265
 266 static void shpc_slot_command(PCIDevice *d, uint8_t target,
 267                               uint8_t state, uint8_t power, uint8_t attn)
 268 {
 269     SHPCDevice *shpc = d->shpc;
 270     int slot = SHPC_LOGICAL_TO_IDX(target);
 271     uint8_t old_state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK);
 272     uint8_t old_power = shpc_get_status(shpc, slot, SHPC_SLOT_PWR_LED_MASK);
 273     uint8_t old_attn = shpc_get_status(shpc, slot, SHPC_SLOT_ATTN_LED_MASK);
 274
 275     if (target < SHPC_CMD_TRGT_MIN || slot >= shpc->nslots) {
 276         shpc_invalid_command(shpc);
 277         return;
 278     }
 279
 280     if (old_state == SHPC_STATE_ENABLED && state == SHPC_STATE_PWRONLY) {
 281         shpc_invalid_command(shpc);
 282         return;
 283     }
 284
 285     if (power == SHPC_LED_NO) {
 286         power = old_power;
 287     } else {
 288         /* TODO: send event to monitor */
 289         shpc_set_status(shpc, slot, power, SHPC_SLOT_PWR_LED_MASK);
 290     }
 291
 292     if (attn == SHPC_LED_NO) {
 293         attn = old_attn;
 294     } else {
 295         /* TODO: send event to monitor */
 296         shpc_set_status(shpc, slot, attn, SHPC_SLOT_ATTN_LED_MASK);
 297     }
 298
 299     if (state == SHPC_STATE_NO) {
 300         state = old_state;
 301     } else {
 302         shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK);
 303     }
 304
 305     if (!shpc_slot_is_off(old_state, old_power, old_attn) &&
 306         shpc_slot_is_off(state, power, attn))
 307     {
 308         shpc_free_devices_in_slot(shpc, slot);
 309         shpc_set_status(shpc, slot, 1, SHPC_SLOT_STATUS_MRL_OPEN);
 310         shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_EMPTY,
 311                         SHPC_SLOT_STATUS_PRSNT_MASK);
 312         shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
 313             SHPC_SLOT_EVENT_MRL |
 314             SHPC_SLOT_EVENT_PRESENCE;
 315     }
 316 }
 317
 318 static void shpc_command(PCIDevice *d)
 319 {
 320     SHPCDevice *shpc = d->shpc;
 321     uint8_t code = pci_get_byte(shpc->config + SHPC_CMD_CODE);
 322     uint8_t speed;
 323     uint8_t target;
 324     uint8_t attn;
 325     uint8_t power;
 326     uint8_t state;
 327     int i;
 328
 329     /* Clear status from the previous command. */
 330     pci_word_test_and_clear_mask(shpc->config + SHPC_CMD_STATUS,
 331                                  SHPC_CMD_STATUS_BUSY |
 332                                  SHPC_CMD_STATUS_MRL_OPEN |
 333                                  SHPC_CMD_STATUS_INVALID_CMD |
 334                                  SHPC_CMD_STATUS_INVALID_MODE);
 335     switch (code) {
 336     case 0x00 ... 0x3f:
 337         target = shpc->config[SHPC_CMD_TRGT] & SHPC_CMD_TRGT_MAX;
 338         state = (code & SHPC_SLOT_STATE_MASK) >> SHPC_SLOT_STATE_SHIFT;
 339         power = (code & SHPC_SLOT_PWR_LED_MASK) >> SHPC_SLOT_PWR_LED_SHIFT;
 340         attn = (code & SHPC_SLOT_ATTN_LED_MASK) >> SHPC_SLOT_ATTN_LED_SHIFT;
 341         shpc_slot_command(d, target, state, power, attn);
 342         break;
 343     case 0x40 ... 0x47:
 344         speed = code & SHPC_SEC_BUS_MASK;
 345         shpc_set_sec_bus_speed(shpc, speed);
 346         break;
 347     case 0x48:
 348         /* Power only all slots */
 349         /* first verify no slots are enabled */
 350         for (i = 0; i < shpc->nslots; ++i) {
 351             state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK);
 352             if (state == SHPC_STATE_ENABLED) {
 353                 shpc_invalid_command(shpc);
 354                 goto done;
 355             }
 356         }
 357         for (i = 0; i < shpc->nslots; ++i) {
 358             if (!(shpc_get_status(shpc, i, SHPC_SLOT_STATUS_MRL_OPEN))) {
 359                 shpc_slot_command(d, i + SHPC_CMD_TRGT_MIN,
 360                                   SHPC_STATE_PWRONLY, SHPC_LED_ON, SHPC_LED_NO);
 361             } else {
 362                 shpc_slot_command(d, i + SHPC_CMD_TRGT_MIN,
 363                                   SHPC_STATE_NO, SHPC_LED_OFF, SHPC_LED_NO);
 364             }
 365         }
 366         break;
 367     case 0x49:
 368         /* Enable all slots */
 369         /* TODO: Spec says this shall fail if some are already enabled.
 370          * This doesn't make sense - why not? a spec bug? */
 371         for (i = 0; i < shpc->nslots; ++i) {
 372             state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK);
 373             if (state == SHPC_STATE_ENABLED) {
 374                 shpc_invalid_command(shpc);
 375                 goto done;
 376             }
 377         }
 378         for (i = 0; i < shpc->nslots; ++i) {
 379             if (!(shpc_get_status(shpc, i, SHPC_SLOT_STATUS_MRL_OPEN))) {
 380                 shpc_slot_command(d, i + SHPC_CMD_TRGT_MIN,
 381                                   SHPC_STATE_ENABLED, SHPC_LED_ON, SHPC_LED_NO);
 382             } else {
 383                 shpc_slot_command(d, i + SHPC_CMD_TRGT_MIN,
 384                                   SHPC_STATE_NO, SHPC_LED_OFF, SHPC_LED_NO);
 385             }
 386         }
 387         break;
 388     default:
 389         shpc_invalid_command(shpc);
 390         break;
 391     }
 392 done:
 393     pci_long_test_and_set_mask(shpc->config + SHPC_SERR_INT, SHPC_CMD_DETECTED);
 394 }
 395
 396 static void shpc_write(PCIDevice *d, unsigned addr, uint64_t val, int l)
 397 {
 398     SHPCDevice *shpc = d->shpc;
 399     int i;
 400     if (addr >= SHPC_SIZEOF(d)) {
 401         return;
 402     }
 403     l = MIN(l, SHPC_SIZEOF(d) - addr);
 404
 405     /* TODO: code duplicated from pci.c */
 406     for (i = 0; i < l; val >>= 8, ++i) {
 407         unsigned a = addr + i;
 408         uint8_t wmask = shpc->wmask[a];
 409         uint8_t w1cmask = shpc->w1cmask[a];
 410         assert(!(wmask & w1cmask));
 411         shpc->config[a] = (shpc->config[a] & ~wmask) | (val & wmask);
 412         shpc->config[a] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
 413     }
 414     if (ranges_overlap(addr, l, SHPC_CMD_CODE, 2)) {
 415         shpc_command(d);
 416     }
 417     shpc_interrupt_update(d);
 418 }
 419
 420 static uint64_t shpc_read(PCIDevice *d, unsigned addr, int l)
 421 {
 422     uint64_t val = 0x0;
 423     if (addr >= SHPC_SIZEOF(d)) {
 424         return val;
 425     }
 426     l = MIN(l, SHPC_SIZEOF(d) - addr);
 427     memcpy(&val, d->shpc->config + addr, l);
 428     return val;
 429 }
 430
 431 /* SHPC Bridge Capability */
 432 #define SHPC_CAP_LENGTH 0x08
 433 #define SHPC_CAP_DWORD_SELECT 0x2 /* 1 byte */
 434 #define SHPC_CAP_CxP 0x3 /* 1 byte: CSP, CIP */
 435 #define SHPC_CAP_DWORD_DATA 0x4 /* 4 bytes */
 436 #define SHPC_CAP_CSP_MASK 0x4
 437 #define SHPC_CAP_CIP_MASK 0x8
 438
 439 static uint8_t shpc_cap_dword(PCIDevice *d)
 440 {
 441     return pci_get_byte(d->config + d->shpc->cap + SHPC_CAP_DWORD_SELECT);
 442 }
 443
 444 /* Update dword data capability register */
 445 static void shpc_cap_update_dword(PCIDevice *d)
 446 {
 447     unsigned data;
 448     data = shpc_read(d, shpc_cap_dword(d) * 4, 4);
 449     pci_set_long(d->config  + d->shpc->cap + SHPC_CAP_DWORD_DATA, data);
 450 }
 451
 452 /* Add SHPC capability to the config space for the device. */
 453 static int shpc_cap_add_config(PCIDevice *d, Error **errp)
 454 {
 455     uint8_t *config;
 456     int config_offset;
 457     config_offset = pci_add_capability(d, PCI_CAP_ID_SHPC,
 458                                        0, SHPC_CAP_LENGTH,
 459                                        errp);
 460     if (config_offset < 0) {
 461         return config_offset;
 462     }
 463     config = d->config + config_offset;
 464
 465     pci_set_byte(config + SHPC_CAP_DWORD_SELECT, 0);
 466     pci_set_byte(config + SHPC_CAP_CxP, 0);
 467     pci_set_long(config + SHPC_CAP_DWORD_DATA, 0);
 468     d->shpc->cap = config_offset;
 469     /* Make dword select and data writable. */
 470     pci_set_byte(d->wmask + config_offset + SHPC_CAP_DWORD_SELECT, 0xff);
 471     pci_set_long(d->wmask + config_offset + SHPC_CAP_DWORD_DATA, 0xffffffff);
 472     return 0;
 473 }
 474
 475 static uint64_t shpc_mmio_read(void *opaque, hwaddr addr,
 476                                unsigned size)
 477 {
 478     return shpc_read(opaque, addr, size);
 479 }
 480
 481 static void shpc_mmio_write(void *opaque, hwaddr addr,
 482                             uint64_t val, unsigned size)
 483 {
 484     shpc_write(opaque, addr, val, size);
 485 }
 486
 487 static const MemoryRegionOps shpc_mmio_ops = {
 488     .read = shpc_mmio_read,
 489     .write = shpc_mmio_write,
 490     .endianness = DEVICE_LITTLE_ENDIAN,
 491     .valid = {
 492         /* SHPC ECN requires dword accesses, but the original 1.0 spec doesn't.
 493          * It's easier to support all sizes than worry about it.
 494          */
 495         .min_access_size = 1,
 496         .max_access_size = 4,
 497     },
 498 };
 499
 500 static bool shpc_device_get_slot(PCIDevice *affected_dev, int *slot,
 501                                  SHPCDevice *shpc, Error **errp)
 502 {
 503     int pci_slot = PCI_SLOT(affected_dev->devfn);
 504     *slot = SHPC_PCI_TO_IDX(pci_slot);
 505
 506     if (pci_slot < SHPC_IDX_TO_PCI(0) || *slot >= shpc->nslots) {
 507         error_setg(errp, "Unsupported PCI slot %d for standard hotplug "
 508                    "controller. Valid slots are between %d and %d.",
 509                    pci_slot, SHPC_IDX_TO_PCI(0),
 510                    SHPC_IDX_TO_PCI(shpc->nslots) - 1);
 511         return false;
 512     }
 513
 514     return true;
 515 }
 516
 517 void shpc_device_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
 518                             Error **errp)
 519 {
 520     PCIDevice *pci_hotplug_dev = PCI_DEVICE(hotplug_dev);
 521     SHPCDevice *shpc = pci_hotplug_dev->shpc;
 522     int slot;
 523
 524     if (!shpc_device_get_slot(PCI_DEVICE(dev), &slot, shpc, errp)) {
 525         return;
 526     }
 527
 528     /* Don't send event when device is enabled during qemu machine creation:
 529      * it is present on boot, no hotplug event is necessary. We do send an
 530      * event when the device is disabled later. */
 531     if (!dev->hotplugged) {
 532         shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_MRL_OPEN);
 533         shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_7_5W,
 534                         SHPC_SLOT_STATUS_PRSNT_MASK);
 535         return;
 536     }
 537
 538     /* This could be a cancellation of the previous removal.
 539      * We check MRL state to figure out. */
 540     if (shpc_get_status(shpc, slot, SHPC_SLOT_STATUS_MRL_OPEN)) {
 541         shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_MRL_OPEN);
 542         shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_7_5W,
 543                         SHPC_SLOT_STATUS_PRSNT_MASK);
 544         shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
 545             SHPC_SLOT_EVENT_BUTTON |
 546             SHPC_SLOT_EVENT_MRL |
 547             SHPC_SLOT_EVENT_PRESENCE;
 548     } else {
 549         /* Press attention button to cancel removal */
 550         shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
 551             SHPC_SLOT_EVENT_BUTTON;
 552     }
 553     shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_66);
 554     shpc_interrupt_update(pci_hotplug_dev);
 555 }
 556
 557 void shpc_device_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
 558                            Error **errp)
 559 {
 560     qdev_unrealize(dev);
 561 }
 562
 563 void shpc_device_unplug_request_cb(HotplugHandler *hotplug_dev,
 564                                    DeviceState *dev, Error **errp)
 565 {
 566     PCIDevice *pci_hotplug_dev = PCI_DEVICE(hotplug_dev);
 567     SHPCDevice *shpc = pci_hotplug_dev->shpc;
 568     uint8_t state;
 569     uint8_t led;
 570     int slot;
 571
 572     if (!shpc_device_get_slot(PCI_DEVICE(dev), &slot, shpc, errp)) {
 573         return;
 574     }
 575
 576     state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK);
 577     led = shpc_get_status(shpc, slot, SHPC_SLOT_PWR_LED_MASK);
 578
 579     if (led == SHPC_LED_BLINK) {
 580         error_setg(errp, "Hot-unplug failed: "
 581                    "guest is busy (power indicator blinking)");
 582         return;
 583     }
 584
 585     if (state == SHPC_STATE_DISABLED && led == SHPC_LED_OFF) {
 586         shpc_free_devices_in_slot(shpc, slot);
 587         shpc_set_status(shpc, slot, 1, SHPC_SLOT_STATUS_MRL_OPEN);
 588         shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_EMPTY,
 589                         SHPC_SLOT_STATUS_PRSNT_MASK);
 590         shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
 591             SHPC_SLOT_EVENT_MRL |
 592             SHPC_SLOT_EVENT_PRESENCE;
 593     } else {
 594         shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |= SHPC_SLOT_EVENT_BUTTON;
 595     }
 596     shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_66);
 597     shpc_interrupt_update(pci_hotplug_dev);
 598 }
 599
 600 /* Initialize the SHPC structure in bridge's BAR. */
 601 int shpc_init(PCIDevice *d, PCIBus *sec_bus, MemoryRegion *bar,
 602               unsigned offset, Error **errp)
 603 {
 604     int i, ret;
 605     int nslots = SHPC_MAX_SLOTS; /* TODO: qdev property? */
 606     SHPCDevice *shpc = d->shpc = g_malloc0(sizeof(*d->shpc));
 607     shpc->sec_bus = sec_bus;
 608     ret = shpc_cap_add_config(d, errp);
 609     if (ret) {
 610         g_free(d->shpc);
 611         return ret;
 612     }
 613     if (nslots < SHPC_MIN_SLOTS) {
 614         return 0;
 615     }
 616     if (nslots > SHPC_MAX_SLOTS ||
 617         SHPC_IDX_TO_PCI(nslots) > PCI_SLOT_MAX) {
 618         /* TODO: report an error mesage that makes sense. */
 619         return -EINVAL;
 620     }
 621     shpc->nslots = nslots;
 622     shpc->config = g_malloc0(SHPC_SIZEOF(d));
 623     shpc->cmask = g_malloc0(SHPC_SIZEOF(d));
 624     shpc->wmask = g_malloc0(SHPC_SIZEOF(d));
 625     shpc->w1cmask = g_malloc0(SHPC_SIZEOF(d));
 626
 627     shpc_reset(d);
 628
 629     pci_set_long(shpc->config + SHPC_BASE_OFFSET, offset);
 630
 631     pci_set_byte(shpc->wmask + SHPC_CMD_CODE, 0xff);
 632     pci_set_byte(shpc->wmask + SHPC_CMD_TRGT, SHPC_CMD_TRGT_MAX);
 633     pci_set_byte(shpc->wmask + SHPC_CMD_TRGT, SHPC_CMD_TRGT_MAX);
 634     pci_set_long(shpc->wmask + SHPC_SERR_INT,
 635                  SHPC_INT_DIS |
 636                  SHPC_SERR_DIS |
 637                  SHPC_CMD_INT_DIS |
 638                  SHPC_ARB_SERR_DIS);
 639     pci_set_long(shpc->w1cmask + SHPC_SERR_INT,
 640                  SHPC_CMD_DETECTED |
 641                  SHPC_ARB_DETECTED);
 642     for (i = 0; i < nslots; ++i) {
 643         pci_set_byte(shpc->wmask +
 644                      SHPC_SLOT_EVENT_SERR_INT_DIS(d, i),
 645                      SHPC_SLOT_EVENT_PRESENCE |
 646                      SHPC_SLOT_EVENT_ISOLATED_FAULT |
 647                      SHPC_SLOT_EVENT_BUTTON |
 648                      SHPC_SLOT_EVENT_MRL |
 649                      SHPC_SLOT_EVENT_CONNECTED_FAULT |
 650                      SHPC_SLOT_EVENT_MRL_SERR_DIS |
 651                      SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS);
 652         pci_set_byte(shpc->w1cmask +
 653                      SHPC_SLOT_EVENT_LATCH(i),
 654                      SHPC_SLOT_EVENT_PRESENCE |
 655                      SHPC_SLOT_EVENT_ISOLATED_FAULT |
 656                      SHPC_SLOT_EVENT_BUTTON |
 657                      SHPC_SLOT_EVENT_MRL |
 658                      SHPC_SLOT_EVENT_CONNECTED_FAULT);
 659     }
 660
 661     /* TODO: init cmask */
 662     memory_region_init_io(&shpc->mmio, OBJECT(d), &shpc_mmio_ops,
 663                           d, "shpc-mmio", SHPC_SIZEOF(d));
 664     shpc_cap_update_dword(d);
 665     memory_region_add_subregion(bar, offset, &shpc->mmio);
 666
 667     qbus_set_hotplug_handler(BUS(sec_bus), OBJECT(d));
 668
 669     d->cap_present |= QEMU_PCI_CAP_SHPC;
 670     return 0;
 671 }
 672
 673 int shpc_bar_size(PCIDevice *d)
 674 {
 675     return pow2roundup32(SHPC_SLOT_REG(SHPC_MAX_SLOTS));
 676 }
 677
 678 void shpc_cleanup(PCIDevice *d, MemoryRegion *bar)
 679 {
 680     SHPCDevice *shpc = d->shpc;
 681     d->cap_present &= ~QEMU_PCI_CAP_SHPC;
 682     memory_region_del_subregion(bar, &shpc->mmio);
 683     /* TODO: cleanup config space changes? */
 684 }
 685
 686 void shpc_free(PCIDevice *d)
 687 {
 688     SHPCDevice *shpc = d->shpc;
 689     if (!shpc) {
 690         return;
 691     }
 692     object_unparent(OBJECT(&shpc->mmio));
 693     g_free(shpc->config);
 694     g_free(shpc->cmask);
 695     g_free(shpc->wmask);
 696     g_free(shpc->w1cmask);
 697     g_free(shpc);
 698     d->shpc = NULL;
 699 }
 700
 701 void shpc_cap_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
 702 {
 703     if (!ranges_overlap(addr, l, d->shpc->cap, SHPC_CAP_LENGTH)) {
 704         return;
 705     }
 706     if (ranges_overlap(addr, l, d->shpc->cap + SHPC_CAP_DWORD_DATA, 4)) {
 707         unsigned dword_data;
 708         dword_data = pci_get_long(d->shpc->config + d->shpc->cap
 709                                   + SHPC_CAP_DWORD_DATA);
 710         shpc_write(d, shpc_cap_dword(d) * 4, dword_data, 4);
 711     }
 712     /* Update cap dword data in case guest is going to read it. */
 713     shpc_cap_update_dword(d);
 714 }
 715
 716 static int shpc_save(QEMUFile *f, void *pv, size_t size,
 717                      const VMStateField *field, JSONWriter *vmdesc)
 718 {
 719     PCIDevice *d = container_of(pv, PCIDevice, shpc);
 720     qemu_put_buffer(f, d->shpc->config, SHPC_SIZEOF(d));
 721
 722     return 0;
 723 }
 724
 725 static int shpc_load(QEMUFile *f, void *pv, size_t size,
 726                      const VMStateField *field)
 727 {
 728     PCIDevice *d = container_of(pv, PCIDevice, shpc);
 729     int ret = qemu_get_buffer(f, d->shpc->config, SHPC_SIZEOF(d));
 730     if (ret != SHPC_SIZEOF(d)) {
 731         return -EINVAL;
 732     }
 733     /* Make sure we don't lose notifications. An extra interrupt is harmless. */
 734     d->shpc->msi_requested = 0;
 735     shpc_interrupt_update(d);
 736     return 0;
 737 }
 738
 739 VMStateInfo shpc_vmstate_info = {
 740     .name = "shpc",
 741     .get  = shpc_load,
 742     .put  = shpc_save,
 743 };