2 * Tiny Code Interpreter for QEMU
4 * Copyright (c) 2009, 2011, 2016 Stefan Weil
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
22 #include "tcg/tcg.h" /* MAX_OPC_PARAM_IARGS */
23 #include "exec/cpu_ldst.h"
24 #include "tcg/tcg-op.h"
25 #include "qemu/compiler.h"
30 * Enable TCI assertions only when debugging TCG (and without NDEBUG defined).
31 * Without assertions, the interpreter runs much faster.
33 #if defined(CONFIG_DEBUG_TCG)
34 # define tci_assert(cond) assert(cond)
36 # define tci_assert(cond) ((void)(cond))
39 __thread
uintptr_t tci_tb_ptr
;
41 static void tci_write_reg64(tcg_target_ulong
*regs
, uint32_t high_index
,
42 uint32_t low_index
, uint64_t value
)
44 regs
[low_index
] = (uint32_t)value
;
45 regs
[high_index
] = value
>> 32;
48 /* Create a 64 bit value from two 32 bit values. */
49 static uint64_t tci_uint64(uint32_t high
, uint32_t low
)
51 return ((uint64_t)high
<< 32) + low
;
55 * Load sets of arguments all at once. The naming convention is:
56 * tci_args_<arguments>
57 * where arguments is a sequence of
59 * b = immediate (bit position)
60 * c = condition (TCGCond)
61 * i = immediate (uint32_t)
62 * I = immediate (tcg_target_ulong)
63 * l = label or pointer
64 * m = immediate (TCGMemOpIdx)
65 * n = immediate (call return length)
67 * s = signed ldst offset
70 static void tci_args_l(uint32_t insn
, const void *tb_ptr
, void **l0
)
72 int diff
= sextract32(insn
, 12, 20);
73 *l0
= diff
? (void *)tb_ptr
+ diff
: NULL
;
76 static void tci_args_r(uint32_t insn
, TCGReg
*r0
)
78 *r0
= extract32(insn
, 8, 4);
81 static void tci_args_nl(uint32_t insn
, const void *tb_ptr
,
82 uint8_t *n0
, void **l1
)
84 *n0
= extract32(insn
, 8, 4);
85 *l1
= sextract32(insn
, 12, 20) + (void *)tb_ptr
;
88 static void tci_args_rl(uint32_t insn
, const void *tb_ptr
,
89 TCGReg
*r0
, void **l1
)
91 *r0
= extract32(insn
, 8, 4);
92 *l1
= sextract32(insn
, 12, 20) + (void *)tb_ptr
;
95 static void tci_args_rr(uint32_t insn
, TCGReg
*r0
, TCGReg
*r1
)
97 *r0
= extract32(insn
, 8, 4);
98 *r1
= extract32(insn
, 12, 4);
101 static void tci_args_ri(uint32_t insn
, TCGReg
*r0
, tcg_target_ulong
*i1
)
103 *r0
= extract32(insn
, 8, 4);
104 *i1
= sextract32(insn
, 12, 20);
107 static void tci_args_rrm(uint32_t insn
, TCGReg
*r0
,
108 TCGReg
*r1
, TCGMemOpIdx
*m2
)
110 *r0
= extract32(insn
, 8, 4);
111 *r1
= extract32(insn
, 12, 4);
112 *m2
= extract32(insn
, 20, 12);
115 static void tci_args_rrr(uint32_t insn
, TCGReg
*r0
, TCGReg
*r1
, TCGReg
*r2
)
117 *r0
= extract32(insn
, 8, 4);
118 *r1
= extract32(insn
, 12, 4);
119 *r2
= extract32(insn
, 16, 4);
122 static void tci_args_rrs(uint32_t insn
, TCGReg
*r0
, TCGReg
*r1
, int32_t *i2
)
124 *r0
= extract32(insn
, 8, 4);
125 *r1
= extract32(insn
, 12, 4);
126 *i2
= sextract32(insn
, 16, 16);
129 static void tci_args_rrbb(uint32_t insn
, TCGReg
*r0
, TCGReg
*r1
,
130 uint8_t *i2
, uint8_t *i3
)
132 *r0
= extract32(insn
, 8, 4);
133 *r1
= extract32(insn
, 12, 4);
134 *i2
= extract32(insn
, 16, 6);
135 *i3
= extract32(insn
, 22, 6);
138 static void tci_args_rrrc(uint32_t insn
,
139 TCGReg
*r0
, TCGReg
*r1
, TCGReg
*r2
, TCGCond
*c3
)
141 *r0
= extract32(insn
, 8, 4);
142 *r1
= extract32(insn
, 12, 4);
143 *r2
= extract32(insn
, 16, 4);
144 *c3
= extract32(insn
, 20, 4);
147 static void tci_args_rrrm(uint32_t insn
,
148 TCGReg
*r0
, TCGReg
*r1
, TCGReg
*r2
, TCGMemOpIdx
*m3
)
150 *r0
= extract32(insn
, 8, 4);
151 *r1
= extract32(insn
, 12, 4);
152 *r2
= extract32(insn
, 16, 4);
153 *m3
= extract32(insn
, 20, 12);
156 static void tci_args_rrrbb(uint32_t insn
, TCGReg
*r0
, TCGReg
*r1
,
157 TCGReg
*r2
, uint8_t *i3
, uint8_t *i4
)
159 *r0
= extract32(insn
, 8, 4);
160 *r1
= extract32(insn
, 12, 4);
161 *r2
= extract32(insn
, 16, 4);
162 *i3
= extract32(insn
, 20, 6);
163 *i4
= extract32(insn
, 26, 6);
166 static void tci_args_rrrrr(uint32_t insn
, TCGReg
*r0
, TCGReg
*r1
,
167 TCGReg
*r2
, TCGReg
*r3
, TCGReg
*r4
)
169 *r0
= extract32(insn
, 8, 4);
170 *r1
= extract32(insn
, 12, 4);
171 *r2
= extract32(insn
, 16, 4);
172 *r3
= extract32(insn
, 20, 4);
173 *r4
= extract32(insn
, 24, 4);
176 static void tci_args_rrrr(uint32_t insn
,
177 TCGReg
*r0
, TCGReg
*r1
, TCGReg
*r2
, TCGReg
*r3
)
179 *r0
= extract32(insn
, 8, 4);
180 *r1
= extract32(insn
, 12, 4);
181 *r2
= extract32(insn
, 16, 4);
182 *r3
= extract32(insn
, 20, 4);
185 static void tci_args_rrrrrc(uint32_t insn
, TCGReg
*r0
, TCGReg
*r1
,
186 TCGReg
*r2
, TCGReg
*r3
, TCGReg
*r4
, TCGCond
*c5
)
188 *r0
= extract32(insn
, 8, 4);
189 *r1
= extract32(insn
, 12, 4);
190 *r2
= extract32(insn
, 16, 4);
191 *r3
= extract32(insn
, 20, 4);
192 *r4
= extract32(insn
, 24, 4);
193 *c5
= extract32(insn
, 28, 4);
196 static void tci_args_rrrrrr(uint32_t insn
, TCGReg
*r0
, TCGReg
*r1
,
197 TCGReg
*r2
, TCGReg
*r3
, TCGReg
*r4
, TCGReg
*r5
)
199 *r0
= extract32(insn
, 8, 4);
200 *r1
= extract32(insn
, 12, 4);
201 *r2
= extract32(insn
, 16, 4);
202 *r3
= extract32(insn
, 20, 4);
203 *r4
= extract32(insn
, 24, 4);
204 *r5
= extract32(insn
, 28, 4);
207 static bool tci_compare32(uint32_t u0
, uint32_t u1
, TCGCond condition
)
244 g_assert_not_reached();
249 static bool tci_compare64(uint64_t u0
, uint64_t u1
, TCGCond condition
)
286 g_assert_not_reached();
291 static uint64_t tci_qemu_ld(CPUArchState
*env
, target_ulong taddr
,
292 TCGMemOpIdx oi
, const void *tb_ptr
)
294 MemOp mop
= get_memop(oi
) & (MO_BSWAP
| MO_SSIZE
);
295 uintptr_t ra
= (uintptr_t)tb_ptr
;
297 #ifdef CONFIG_SOFTMMU
300 return helper_ret_ldub_mmu(env
, taddr
, oi
, ra
);
302 return helper_ret_ldsb_mmu(env
, taddr
, oi
, ra
);
304 return helper_le_lduw_mmu(env
, taddr
, oi
, ra
);
306 return helper_le_ldsw_mmu(env
, taddr
, oi
, ra
);
308 return helper_le_ldul_mmu(env
, taddr
, oi
, ra
);
310 return helper_le_ldsl_mmu(env
, taddr
, oi
, ra
);
312 return helper_le_ldq_mmu(env
, taddr
, oi
, ra
);
314 return helper_be_lduw_mmu(env
, taddr
, oi
, ra
);
316 return helper_be_ldsw_mmu(env
, taddr
, oi
, ra
);
318 return helper_be_ldul_mmu(env
, taddr
, oi
, ra
);
320 return helper_be_ldsl_mmu(env
, taddr
, oi
, ra
);
322 return helper_be_ldq_mmu(env
, taddr
, oi
, ra
);
324 g_assert_not_reached();
327 void *haddr
= g2h(env_cpu(env
), taddr
);
330 set_helper_retaddr(ra
);
339 ret
= lduw_le_p(haddr
);
342 ret
= ldsw_le_p(haddr
);
345 ret
= (uint32_t)ldl_le_p(haddr
);
348 ret
= (int32_t)ldl_le_p(haddr
);
351 ret
= ldq_le_p(haddr
);
354 ret
= lduw_be_p(haddr
);
357 ret
= ldsw_be_p(haddr
);
360 ret
= (uint32_t)ldl_be_p(haddr
);
363 ret
= (int32_t)ldl_be_p(haddr
);
366 ret
= ldq_be_p(haddr
);
369 g_assert_not_reached();
371 clear_helper_retaddr();
376 static void tci_qemu_st(CPUArchState
*env
, target_ulong taddr
, uint64_t val
,
377 TCGMemOpIdx oi
, const void *tb_ptr
)
379 MemOp mop
= get_memop(oi
) & (MO_BSWAP
| MO_SSIZE
);
380 uintptr_t ra
= (uintptr_t)tb_ptr
;
382 #ifdef CONFIG_SOFTMMU
385 helper_ret_stb_mmu(env
, taddr
, val
, oi
, ra
);
388 helper_le_stw_mmu(env
, taddr
, val
, oi
, ra
);
391 helper_le_stl_mmu(env
, taddr
, val
, oi
, ra
);
394 helper_le_stq_mmu(env
, taddr
, val
, oi
, ra
);
397 helper_be_stw_mmu(env
, taddr
, val
, oi
, ra
);
400 helper_be_stl_mmu(env
, taddr
, val
, oi
, ra
);
403 helper_be_stq_mmu(env
, taddr
, val
, oi
, ra
);
406 g_assert_not_reached();
409 void *haddr
= g2h(env_cpu(env
), taddr
);
411 set_helper_retaddr(ra
);
417 stw_le_p(haddr
, val
);
420 stl_le_p(haddr
, val
);
423 stq_le_p(haddr
, val
);
426 stw_be_p(haddr
, val
);
429 stl_be_p(haddr
, val
);
432 stq_be_p(haddr
, val
);
435 g_assert_not_reached();
437 clear_helper_retaddr();
441 #if TCG_TARGET_REG_BITS == 64
442 # define CASE_32_64(x) \
443 case glue(glue(INDEX_op_, x), _i64): \
444 case glue(glue(INDEX_op_, x), _i32):
445 # define CASE_64(x) \
446 case glue(glue(INDEX_op_, x), _i64):
448 # define CASE_32_64(x) \
449 case glue(glue(INDEX_op_, x), _i32):
453 /* Interpret pseudo code in tb. */
455 * Disable CFI checks.
456 * One possible operation in the pseudo code is a call to binary code.
457 * Therefore, disable CFI checks in the interpreter function
459 uintptr_t QEMU_DISABLE_CFI
tcg_qemu_tb_exec(CPUArchState
*env
,
460 const void *v_tb_ptr
)
462 const uint32_t *tb_ptr
= v_tb_ptr
;
463 tcg_target_ulong regs
[TCG_TARGET_NB_REGS
];
464 uint64_t stack
[(TCG_STATIC_CALL_ARGS_SIZE
+ TCG_STATIC_FRAME_SIZE
)
466 void *call_slots
[TCG_STATIC_CALL_ARGS_SIZE
/ sizeof(uint64_t)];
468 regs
[TCG_AREG0
] = (tcg_target_ulong
)env
;
469 regs
[TCG_REG_CALL_STACK
] = (uintptr_t)stack
;
470 /* Other call_slots entries initialized at first use (see below). */
471 call_slots
[0] = NULL
;
477 TCGReg r0
, r1
, r2
, r3
, r4
, r5
;
490 opc
= extract32(insn
, 0, 8);
495 * Set up the ffi_avalue array once, delayed until now
496 * because many TB's do not make any calls. In tcg_gen_callN,
497 * we arranged for every real argument to be "left-aligned"
498 * in each 64-bit slot.
500 if (unlikely(call_slots
[0] == NULL
)) {
501 for (int i
= 0; i
< ARRAY_SIZE(call_slots
); ++i
) {
502 call_slots
[i
] = &stack
[i
];
506 tci_args_nl(insn
, tb_ptr
, &len
, &ptr
);
508 /* Helper functions may need to access the "return address" */
509 tci_tb_ptr
= (uintptr_t)tb_ptr
;
513 ffi_call(pptr
[1], pptr
[0], stack
, call_slots
);
516 /* Any result winds up "left-aligned" in the stack[0] slot. */
520 case 1: /* uint32_t */
522 * Note that libffi has an odd special case in that it will
523 * always widen an integral result to ffi_arg.
525 if (sizeof(ffi_arg
) == 4) {
526 regs
[TCG_REG_R0
] = *(uint32_t *)stack
;
530 case 2: /* uint64_t */
531 if (TCG_TARGET_REG_BITS
== 32) {
532 tci_write_reg64(regs
, TCG_REG_R1
, TCG_REG_R0
, stack
[0]);
534 regs
[TCG_REG_R0
] = stack
[0];
538 g_assert_not_reached();
543 tci_args_l(insn
, tb_ptr
, &ptr
);
546 case INDEX_op_setcond_i32
:
547 tci_args_rrrc(insn
, &r0
, &r1
, &r2
, &condition
);
548 regs
[r0
] = tci_compare32(regs
[r1
], regs
[r2
], condition
);
550 case INDEX_op_movcond_i32
:
551 tci_args_rrrrrc(insn
, &r0
, &r1
, &r2
, &r3
, &r4
, &condition
);
552 tmp32
= tci_compare32(regs
[r1
], regs
[r2
], condition
);
553 regs
[r0
] = regs
[tmp32
? r3
: r4
];
555 #if TCG_TARGET_REG_BITS == 32
556 case INDEX_op_setcond2_i32
:
557 tci_args_rrrrrc(insn
, &r0
, &r1
, &r2
, &r3
, &r4
, &condition
);
558 T1
= tci_uint64(regs
[r2
], regs
[r1
]);
559 T2
= tci_uint64(regs
[r4
], regs
[r3
]);
560 regs
[r0
] = tci_compare64(T1
, T2
, condition
);
562 #elif TCG_TARGET_REG_BITS == 64
563 case INDEX_op_setcond_i64
:
564 tci_args_rrrc(insn
, &r0
, &r1
, &r2
, &condition
);
565 regs
[r0
] = tci_compare64(regs
[r1
], regs
[r2
], condition
);
567 case INDEX_op_movcond_i64
:
568 tci_args_rrrrrc(insn
, &r0
, &r1
, &r2
, &r3
, &r4
, &condition
);
569 tmp32
= tci_compare64(regs
[r1
], regs
[r2
], condition
);
570 regs
[r0
] = regs
[tmp32
? r3
: r4
];
574 tci_args_rr(insn
, &r0
, &r1
);
577 case INDEX_op_tci_movi
:
578 tci_args_ri(insn
, &r0
, &t1
);
581 case INDEX_op_tci_movl
:
582 tci_args_rl(insn
, tb_ptr
, &r0
, &ptr
);
583 regs
[r0
] = *(tcg_target_ulong
*)ptr
;
586 /* Load/store operations (32 bit). */
589 tci_args_rrs(insn
, &r0
, &r1
, &ofs
);
590 ptr
= (void *)(regs
[r1
] + ofs
);
591 regs
[r0
] = *(uint8_t *)ptr
;
594 tci_args_rrs(insn
, &r0
, &r1
, &ofs
);
595 ptr
= (void *)(regs
[r1
] + ofs
);
596 regs
[r0
] = *(int8_t *)ptr
;
599 tci_args_rrs(insn
, &r0
, &r1
, &ofs
);
600 ptr
= (void *)(regs
[r1
] + ofs
);
601 regs
[r0
] = *(uint16_t *)ptr
;
604 tci_args_rrs(insn
, &r0
, &r1
, &ofs
);
605 ptr
= (void *)(regs
[r1
] + ofs
);
606 regs
[r0
] = *(int16_t *)ptr
;
608 case INDEX_op_ld_i32
:
610 tci_args_rrs(insn
, &r0
, &r1
, &ofs
);
611 ptr
= (void *)(regs
[r1
] + ofs
);
612 regs
[r0
] = *(uint32_t *)ptr
;
615 tci_args_rrs(insn
, &r0
, &r1
, &ofs
);
616 ptr
= (void *)(regs
[r1
] + ofs
);
617 *(uint8_t *)ptr
= regs
[r0
];
620 tci_args_rrs(insn
, &r0
, &r1
, &ofs
);
621 ptr
= (void *)(regs
[r1
] + ofs
);
622 *(uint16_t *)ptr
= regs
[r0
];
624 case INDEX_op_st_i32
:
626 tci_args_rrs(insn
, &r0
, &r1
, &ofs
);
627 ptr
= (void *)(regs
[r1
] + ofs
);
628 *(uint32_t *)ptr
= regs
[r0
];
631 /* Arithmetic operations (mixed 32/64 bit). */
634 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
635 regs
[r0
] = regs
[r1
] + regs
[r2
];
638 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
639 regs
[r0
] = regs
[r1
] - regs
[r2
];
642 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
643 regs
[r0
] = regs
[r1
] * regs
[r2
];
646 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
647 regs
[r0
] = regs
[r1
] & regs
[r2
];
650 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
651 regs
[r0
] = regs
[r1
] | regs
[r2
];
654 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
655 regs
[r0
] = regs
[r1
] ^ regs
[r2
];
657 #if TCG_TARGET_HAS_andc_i32 || TCG_TARGET_HAS_andc_i64
659 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
660 regs
[r0
] = regs
[r1
] & ~regs
[r2
];
663 #if TCG_TARGET_HAS_orc_i32 || TCG_TARGET_HAS_orc_i64
665 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
666 regs
[r0
] = regs
[r1
] | ~regs
[r2
];
669 #if TCG_TARGET_HAS_eqv_i32 || TCG_TARGET_HAS_eqv_i64
671 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
672 regs
[r0
] = ~(regs
[r1
] ^ regs
[r2
]);
675 #if TCG_TARGET_HAS_nand_i32 || TCG_TARGET_HAS_nand_i64
677 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
678 regs
[r0
] = ~(regs
[r1
] & regs
[r2
]);
681 #if TCG_TARGET_HAS_nor_i32 || TCG_TARGET_HAS_nor_i64
683 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
684 regs
[r0
] = ~(regs
[r1
] | regs
[r2
]);
688 /* Arithmetic operations (32 bit). */
690 case INDEX_op_div_i32
:
691 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
692 regs
[r0
] = (int32_t)regs
[r1
] / (int32_t)regs
[r2
];
694 case INDEX_op_divu_i32
:
695 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
696 regs
[r0
] = (uint32_t)regs
[r1
] / (uint32_t)regs
[r2
];
698 case INDEX_op_rem_i32
:
699 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
700 regs
[r0
] = (int32_t)regs
[r1
] % (int32_t)regs
[r2
];
702 case INDEX_op_remu_i32
:
703 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
704 regs
[r0
] = (uint32_t)regs
[r1
] % (uint32_t)regs
[r2
];
706 #if TCG_TARGET_HAS_clz_i32
707 case INDEX_op_clz_i32
:
708 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
710 regs
[r0
] = tmp32
? clz32(tmp32
) : regs
[r2
];
713 #if TCG_TARGET_HAS_ctz_i32
714 case INDEX_op_ctz_i32
:
715 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
717 regs
[r0
] = tmp32
? ctz32(tmp32
) : regs
[r2
];
720 #if TCG_TARGET_HAS_ctpop_i32
721 case INDEX_op_ctpop_i32
:
722 tci_args_rr(insn
, &r0
, &r1
);
723 regs
[r0
] = ctpop32(regs
[r1
]);
727 /* Shift/rotate operations (32 bit). */
729 case INDEX_op_shl_i32
:
730 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
731 regs
[r0
] = (uint32_t)regs
[r1
] << (regs
[r2
] & 31);
733 case INDEX_op_shr_i32
:
734 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
735 regs
[r0
] = (uint32_t)regs
[r1
] >> (regs
[r2
] & 31);
737 case INDEX_op_sar_i32
:
738 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
739 regs
[r0
] = (int32_t)regs
[r1
] >> (regs
[r2
] & 31);
741 #if TCG_TARGET_HAS_rot_i32
742 case INDEX_op_rotl_i32
:
743 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
744 regs
[r0
] = rol32(regs
[r1
], regs
[r2
] & 31);
746 case INDEX_op_rotr_i32
:
747 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
748 regs
[r0
] = ror32(regs
[r1
], regs
[r2
] & 31);
751 #if TCG_TARGET_HAS_deposit_i32
752 case INDEX_op_deposit_i32
:
753 tci_args_rrrbb(insn
, &r0
, &r1
, &r2
, &pos
, &len
);
754 regs
[r0
] = deposit32(regs
[r1
], pos
, len
, regs
[r2
]);
757 #if TCG_TARGET_HAS_extract_i32
758 case INDEX_op_extract_i32
:
759 tci_args_rrbb(insn
, &r0
, &r1
, &pos
, &len
);
760 regs
[r0
] = extract32(regs
[r1
], pos
, len
);
763 #if TCG_TARGET_HAS_sextract_i32
764 case INDEX_op_sextract_i32
:
765 tci_args_rrbb(insn
, &r0
, &r1
, &pos
, &len
);
766 regs
[r0
] = sextract32(regs
[r1
], pos
, len
);
769 case INDEX_op_brcond_i32
:
770 tci_args_rl(insn
, tb_ptr
, &r0
, &ptr
);
771 if ((uint32_t)regs
[r0
]) {
775 #if TCG_TARGET_REG_BITS == 32 || TCG_TARGET_HAS_add2_i32
776 case INDEX_op_add2_i32
:
777 tci_args_rrrrrr(insn
, &r0
, &r1
, &r2
, &r3
, &r4
, &r5
);
778 T1
= tci_uint64(regs
[r3
], regs
[r2
]);
779 T2
= tci_uint64(regs
[r5
], regs
[r4
]);
780 tci_write_reg64(regs
, r1
, r0
, T1
+ T2
);
783 #if TCG_TARGET_REG_BITS == 32 || TCG_TARGET_HAS_sub2_i32
784 case INDEX_op_sub2_i32
:
785 tci_args_rrrrrr(insn
, &r0
, &r1
, &r2
, &r3
, &r4
, &r5
);
786 T1
= tci_uint64(regs
[r3
], regs
[r2
]);
787 T2
= tci_uint64(regs
[r5
], regs
[r4
]);
788 tci_write_reg64(regs
, r1
, r0
, T1
- T2
);
791 #if TCG_TARGET_HAS_mulu2_i32
792 case INDEX_op_mulu2_i32
:
793 tci_args_rrrr(insn
, &r0
, &r1
, &r2
, &r3
);
794 tmp64
= (uint64_t)(uint32_t)regs
[r2
] * (uint32_t)regs
[r3
];
795 tci_write_reg64(regs
, r1
, r0
, tmp64
);
798 #if TCG_TARGET_HAS_muls2_i32
799 case INDEX_op_muls2_i32
:
800 tci_args_rrrr(insn
, &r0
, &r1
, &r2
, &r3
);
801 tmp64
= (int64_t)(int32_t)regs
[r2
] * (int32_t)regs
[r3
];
802 tci_write_reg64(regs
, r1
, r0
, tmp64
);
805 #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
807 tci_args_rr(insn
, &r0
, &r1
);
808 regs
[r0
] = (int8_t)regs
[r1
];
811 #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
813 tci_args_rr(insn
, &r0
, &r1
);
814 regs
[r0
] = (int16_t)regs
[r1
];
817 #if TCG_TARGET_HAS_ext8u_i32 || TCG_TARGET_HAS_ext8u_i64
819 tci_args_rr(insn
, &r0
, &r1
);
820 regs
[r0
] = (uint8_t)regs
[r1
];
823 #if TCG_TARGET_HAS_ext16u_i32 || TCG_TARGET_HAS_ext16u_i64
825 tci_args_rr(insn
, &r0
, &r1
);
826 regs
[r0
] = (uint16_t)regs
[r1
];
829 #if TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64
831 tci_args_rr(insn
, &r0
, &r1
);
832 regs
[r0
] = bswap16(regs
[r1
]);
835 #if TCG_TARGET_HAS_bswap32_i32 || TCG_TARGET_HAS_bswap32_i64
837 tci_args_rr(insn
, &r0
, &r1
);
838 regs
[r0
] = bswap32(regs
[r1
]);
841 #if TCG_TARGET_HAS_not_i32 || TCG_TARGET_HAS_not_i64
843 tci_args_rr(insn
, &r0
, &r1
);
844 regs
[r0
] = ~regs
[r1
];
847 #if TCG_TARGET_HAS_neg_i32 || TCG_TARGET_HAS_neg_i64
849 tci_args_rr(insn
, &r0
, &r1
);
850 regs
[r0
] = -regs
[r1
];
853 #if TCG_TARGET_REG_BITS == 64
854 /* Load/store operations (64 bit). */
856 case INDEX_op_ld32s_i64
:
857 tci_args_rrs(insn
, &r0
, &r1
, &ofs
);
858 ptr
= (void *)(regs
[r1
] + ofs
);
859 regs
[r0
] = *(int32_t *)ptr
;
861 case INDEX_op_ld_i64
:
862 tci_args_rrs(insn
, &r0
, &r1
, &ofs
);
863 ptr
= (void *)(regs
[r1
] + ofs
);
864 regs
[r0
] = *(uint64_t *)ptr
;
866 case INDEX_op_st_i64
:
867 tci_args_rrs(insn
, &r0
, &r1
, &ofs
);
868 ptr
= (void *)(regs
[r1
] + ofs
);
869 *(uint64_t *)ptr
= regs
[r0
];
872 /* Arithmetic operations (64 bit). */
874 case INDEX_op_div_i64
:
875 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
876 regs
[r0
] = (int64_t)regs
[r1
] / (int64_t)regs
[r2
];
878 case INDEX_op_divu_i64
:
879 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
880 regs
[r0
] = (uint64_t)regs
[r1
] / (uint64_t)regs
[r2
];
882 case INDEX_op_rem_i64
:
883 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
884 regs
[r0
] = (int64_t)regs
[r1
] % (int64_t)regs
[r2
];
886 case INDEX_op_remu_i64
:
887 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
888 regs
[r0
] = (uint64_t)regs
[r1
] % (uint64_t)regs
[r2
];
890 #if TCG_TARGET_HAS_clz_i64
891 case INDEX_op_clz_i64
:
892 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
893 regs
[r0
] = regs
[r1
] ? clz64(regs
[r1
]) : regs
[r2
];
896 #if TCG_TARGET_HAS_ctz_i64
897 case INDEX_op_ctz_i64
:
898 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
899 regs
[r0
] = regs
[r1
] ? ctz64(regs
[r1
]) : regs
[r2
];
902 #if TCG_TARGET_HAS_ctpop_i64
903 case INDEX_op_ctpop_i64
:
904 tci_args_rr(insn
, &r0
, &r1
);
905 regs
[r0
] = ctpop64(regs
[r1
]);
908 #if TCG_TARGET_HAS_mulu2_i64
909 case INDEX_op_mulu2_i64
:
910 tci_args_rrrr(insn
, &r0
, &r1
, &r2
, &r3
);
911 mulu64(®s
[r0
], ®s
[r1
], regs
[r2
], regs
[r3
]);
914 #if TCG_TARGET_HAS_muls2_i64
915 case INDEX_op_muls2_i64
:
916 tci_args_rrrr(insn
, &r0
, &r1
, &r2
, &r3
);
917 muls64(®s
[r0
], ®s
[r1
], regs
[r2
], regs
[r3
]);
920 #if TCG_TARGET_HAS_add2_i64
921 case INDEX_op_add2_i64
:
922 tci_args_rrrrrr(insn
, &r0
, &r1
, &r2
, &r3
, &r4
, &r5
);
923 T1
= regs
[r2
] + regs
[r4
];
924 T2
= regs
[r3
] + regs
[r5
] + (T1
< regs
[r2
]);
929 #if TCG_TARGET_HAS_add2_i64
930 case INDEX_op_sub2_i64
:
931 tci_args_rrrrrr(insn
, &r0
, &r1
, &r2
, &r3
, &r4
, &r5
);
932 T1
= regs
[r2
] - regs
[r4
];
933 T2
= regs
[r3
] - regs
[r5
] - (regs
[r2
] < regs
[r4
]);
939 /* Shift/rotate operations (64 bit). */
941 case INDEX_op_shl_i64
:
942 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
943 regs
[r0
] = regs
[r1
] << (regs
[r2
] & 63);
945 case INDEX_op_shr_i64
:
946 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
947 regs
[r0
] = regs
[r1
] >> (regs
[r2
] & 63);
949 case INDEX_op_sar_i64
:
950 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
951 regs
[r0
] = (int64_t)regs
[r1
] >> (regs
[r2
] & 63);
953 #if TCG_TARGET_HAS_rot_i64
954 case INDEX_op_rotl_i64
:
955 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
956 regs
[r0
] = rol64(regs
[r1
], regs
[r2
] & 63);
958 case INDEX_op_rotr_i64
:
959 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
960 regs
[r0
] = ror64(regs
[r1
], regs
[r2
] & 63);
963 #if TCG_TARGET_HAS_deposit_i64
964 case INDEX_op_deposit_i64
:
965 tci_args_rrrbb(insn
, &r0
, &r1
, &r2
, &pos
, &len
);
966 regs
[r0
] = deposit64(regs
[r1
], pos
, len
, regs
[r2
]);
969 #if TCG_TARGET_HAS_extract_i64
970 case INDEX_op_extract_i64
:
971 tci_args_rrbb(insn
, &r0
, &r1
, &pos
, &len
);
972 regs
[r0
] = extract64(regs
[r1
], pos
, len
);
975 #if TCG_TARGET_HAS_sextract_i64
976 case INDEX_op_sextract_i64
:
977 tci_args_rrbb(insn
, &r0
, &r1
, &pos
, &len
);
978 regs
[r0
] = sextract64(regs
[r1
], pos
, len
);
981 case INDEX_op_brcond_i64
:
982 tci_args_rl(insn
, tb_ptr
, &r0
, &ptr
);
987 case INDEX_op_ext32s_i64
:
988 case INDEX_op_ext_i32_i64
:
989 tci_args_rr(insn
, &r0
, &r1
);
990 regs
[r0
] = (int32_t)regs
[r1
];
992 case INDEX_op_ext32u_i64
:
993 case INDEX_op_extu_i32_i64
:
994 tci_args_rr(insn
, &r0
, &r1
);
995 regs
[r0
] = (uint32_t)regs
[r1
];
997 #if TCG_TARGET_HAS_bswap64_i64
998 case INDEX_op_bswap64_i64
:
999 tci_args_rr(insn
, &r0
, &r1
);
1000 regs
[r0
] = bswap64(regs
[r1
]);
1003 #endif /* TCG_TARGET_REG_BITS == 64 */
1005 /* QEMU specific operations. */
1007 case INDEX_op_exit_tb
:
1008 tci_args_l(insn
, tb_ptr
, &ptr
);
1009 return (uintptr_t)ptr
;
1011 case INDEX_op_goto_tb
:
1012 tci_args_l(insn
, tb_ptr
, &ptr
);
1013 tb_ptr
= *(void **)ptr
;
1016 case INDEX_op_goto_ptr
:
1017 tci_args_r(insn
, &r0
);
1018 ptr
= (void *)regs
[r0
];
1025 case INDEX_op_qemu_ld_i32
:
1026 if (TARGET_LONG_BITS
<= TCG_TARGET_REG_BITS
) {
1027 tci_args_rrm(insn
, &r0
, &r1
, &oi
);
1030 tci_args_rrrm(insn
, &r0
, &r1
, &r2
, &oi
);
1031 taddr
= tci_uint64(regs
[r2
], regs
[r1
]);
1033 tmp32
= tci_qemu_ld(env
, taddr
, oi
, tb_ptr
);
1037 case INDEX_op_qemu_ld_i64
:
1038 if (TCG_TARGET_REG_BITS
== 64) {
1039 tci_args_rrm(insn
, &r0
, &r1
, &oi
);
1041 } else if (TARGET_LONG_BITS
<= TCG_TARGET_REG_BITS
) {
1042 tci_args_rrrm(insn
, &r0
, &r1
, &r2
, &oi
);
1045 tci_args_rrrrr(insn
, &r0
, &r1
, &r2
, &r3
, &r4
);
1046 taddr
= tci_uint64(regs
[r3
], regs
[r2
]);
1049 tmp64
= tci_qemu_ld(env
, taddr
, oi
, tb_ptr
);
1050 if (TCG_TARGET_REG_BITS
== 32) {
1051 tci_write_reg64(regs
, r1
, r0
, tmp64
);
1057 case INDEX_op_qemu_st_i32
:
1058 if (TARGET_LONG_BITS
<= TCG_TARGET_REG_BITS
) {
1059 tci_args_rrm(insn
, &r0
, &r1
, &oi
);
1062 tci_args_rrrm(insn
, &r0
, &r1
, &r2
, &oi
);
1063 taddr
= tci_uint64(regs
[r2
], regs
[r1
]);
1066 tci_qemu_st(env
, taddr
, tmp32
, oi
, tb_ptr
);
1069 case INDEX_op_qemu_st_i64
:
1070 if (TCG_TARGET_REG_BITS
== 64) {
1071 tci_args_rrm(insn
, &r0
, &r1
, &oi
);
1075 if (TARGET_LONG_BITS
<= TCG_TARGET_REG_BITS
) {
1076 tci_args_rrrm(insn
, &r0
, &r1
, &r2
, &oi
);
1079 tci_args_rrrrr(insn
, &r0
, &r1
, &r2
, &r3
, &r4
);
1080 taddr
= tci_uint64(regs
[r3
], regs
[r2
]);
1083 tmp64
= tci_uint64(regs
[r1
], regs
[r0
]);
1085 tci_qemu_st(env
, taddr
, tmp64
, oi
, tb_ptr
);
1089 /* Ensure ordering for all kinds */
1093 g_assert_not_reached();
1099 * Disassembler that matches the interpreter
1102 static const char *str_r(TCGReg r
)
1104 static const char regs
[TCG_TARGET_NB_REGS
][4] = {
1105 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1106 "r8", "r9", "r10", "r11", "r12", "r13", "env", "sp"
1109 QEMU_BUILD_BUG_ON(TCG_AREG0
!= TCG_REG_R14
);
1110 QEMU_BUILD_BUG_ON(TCG_REG_CALL_STACK
!= TCG_REG_R15
);
1112 assert((unsigned)r
< TCG_TARGET_NB_REGS
);
1116 static const char *str_c(TCGCond c
)
1118 static const char cond
[16][8] = {
1119 [TCG_COND_NEVER
] = "never",
1120 [TCG_COND_ALWAYS
] = "always",
1121 [TCG_COND_EQ
] = "eq",
1122 [TCG_COND_NE
] = "ne",
1123 [TCG_COND_LT
] = "lt",
1124 [TCG_COND_GE
] = "ge",
1125 [TCG_COND_LE
] = "le",
1126 [TCG_COND_GT
] = "gt",
1127 [TCG_COND_LTU
] = "ltu",
1128 [TCG_COND_GEU
] = "geu",
1129 [TCG_COND_LEU
] = "leu",
1130 [TCG_COND_GTU
] = "gtu",
1133 assert((unsigned)c
< ARRAY_SIZE(cond
));
1134 assert(cond
[c
][0] != 0);
1138 /* Disassemble TCI bytecode. */
1139 int print_insn_tci(bfd_vma addr
, disassemble_info
*info
)
1141 const uint32_t *tb_ptr
= (const void *)(uintptr_t)addr
;
1142 const TCGOpDef
*def
;
1143 const char *op_name
;
1146 TCGReg r0
, r1
, r2
, r3
, r4
, r5
;
1147 tcg_target_ulong i1
;
1154 /* TCI is always the host, so we don't need to load indirect. */
1157 info
->fprintf_func(info
->stream
, "%08x ", insn
);
1159 op
= extract32(insn
, 0, 8);
1160 def
= &tcg_op_defs
[op
];
1161 op_name
= def
->name
;
1165 case INDEX_op_exit_tb
:
1166 case INDEX_op_goto_tb
:
1167 tci_args_l(insn
, tb_ptr
, &ptr
);
1168 info
->fprintf_func(info
->stream
, "%-12s %p", op_name
, ptr
);
1171 case INDEX_op_goto_ptr
:
1172 tci_args_r(insn
, &r0
);
1173 info
->fprintf_func(info
->stream
, "%-12s %s", op_name
, str_r(r0
));
1177 tci_args_nl(insn
, tb_ptr
, &len
, &ptr
);
1178 info
->fprintf_func(info
->stream
, "%-12s %d, %p", op_name
, len
, ptr
);
1181 case INDEX_op_brcond_i32
:
1182 case INDEX_op_brcond_i64
:
1183 tci_args_rl(insn
, tb_ptr
, &r0
, &ptr
);
1184 info
->fprintf_func(info
->stream
, "%-12s %s, 0, ne, %p",
1185 op_name
, str_r(r0
), ptr
);
1188 case INDEX_op_setcond_i32
:
1189 case INDEX_op_setcond_i64
:
1190 tci_args_rrrc(insn
, &r0
, &r1
, &r2
, &c
);
1191 info
->fprintf_func(info
->stream
, "%-12s %s, %s, %s, %s",
1192 op_name
, str_r(r0
), str_r(r1
), str_r(r2
), str_c(c
));
1195 case INDEX_op_tci_movi
:
1196 tci_args_ri(insn
, &r0
, &i1
);
1197 info
->fprintf_func(info
->stream
, "%-12s %s, 0x%" TCG_PRIlx
,
1198 op_name
, str_r(r0
), i1
);
1201 case INDEX_op_tci_movl
:
1202 tci_args_rl(insn
, tb_ptr
, &r0
, &ptr
);
1203 info
->fprintf_func(info
->stream
, "%-12s %s, %p",
1204 op_name
, str_r(r0
), ptr
);
1207 case INDEX_op_ld8u_i32
:
1208 case INDEX_op_ld8u_i64
:
1209 case INDEX_op_ld8s_i32
:
1210 case INDEX_op_ld8s_i64
:
1211 case INDEX_op_ld16u_i32
:
1212 case INDEX_op_ld16u_i64
:
1213 case INDEX_op_ld16s_i32
:
1214 case INDEX_op_ld16s_i64
:
1215 case INDEX_op_ld32u_i64
:
1216 case INDEX_op_ld32s_i64
:
1217 case INDEX_op_ld_i32
:
1218 case INDEX_op_ld_i64
:
1219 case INDEX_op_st8_i32
:
1220 case INDEX_op_st8_i64
:
1221 case INDEX_op_st16_i32
:
1222 case INDEX_op_st16_i64
:
1223 case INDEX_op_st32_i64
:
1224 case INDEX_op_st_i32
:
1225 case INDEX_op_st_i64
:
1226 tci_args_rrs(insn
, &r0
, &r1
, &s2
);
1227 info
->fprintf_func(info
->stream
, "%-12s %s, %s, %d",
1228 op_name
, str_r(r0
), str_r(r1
), s2
);
1231 case INDEX_op_mov_i32
:
1232 case INDEX_op_mov_i64
:
1233 case INDEX_op_ext8s_i32
:
1234 case INDEX_op_ext8s_i64
:
1235 case INDEX_op_ext8u_i32
:
1236 case INDEX_op_ext8u_i64
:
1237 case INDEX_op_ext16s_i32
:
1238 case INDEX_op_ext16s_i64
:
1239 case INDEX_op_ext16u_i32
:
1240 case INDEX_op_ext32s_i64
:
1241 case INDEX_op_ext32u_i64
:
1242 case INDEX_op_ext_i32_i64
:
1243 case INDEX_op_extu_i32_i64
:
1244 case INDEX_op_bswap16_i32
:
1245 case INDEX_op_bswap16_i64
:
1246 case INDEX_op_bswap32_i32
:
1247 case INDEX_op_bswap32_i64
:
1248 case INDEX_op_bswap64_i64
:
1249 case INDEX_op_not_i32
:
1250 case INDEX_op_not_i64
:
1251 case INDEX_op_neg_i32
:
1252 case INDEX_op_neg_i64
:
1253 case INDEX_op_ctpop_i32
:
1254 case INDEX_op_ctpop_i64
:
1255 tci_args_rr(insn
, &r0
, &r1
);
1256 info
->fprintf_func(info
->stream
, "%-12s %s, %s",
1257 op_name
, str_r(r0
), str_r(r1
));
1260 case INDEX_op_add_i32
:
1261 case INDEX_op_add_i64
:
1262 case INDEX_op_sub_i32
:
1263 case INDEX_op_sub_i64
:
1264 case INDEX_op_mul_i32
:
1265 case INDEX_op_mul_i64
:
1266 case INDEX_op_and_i32
:
1267 case INDEX_op_and_i64
:
1268 case INDEX_op_or_i32
:
1269 case INDEX_op_or_i64
:
1270 case INDEX_op_xor_i32
:
1271 case INDEX_op_xor_i64
:
1272 case INDEX_op_andc_i32
:
1273 case INDEX_op_andc_i64
:
1274 case INDEX_op_orc_i32
:
1275 case INDEX_op_orc_i64
:
1276 case INDEX_op_eqv_i32
:
1277 case INDEX_op_eqv_i64
:
1278 case INDEX_op_nand_i32
:
1279 case INDEX_op_nand_i64
:
1280 case INDEX_op_nor_i32
:
1281 case INDEX_op_nor_i64
:
1282 case INDEX_op_div_i32
:
1283 case INDEX_op_div_i64
:
1284 case INDEX_op_rem_i32
:
1285 case INDEX_op_rem_i64
:
1286 case INDEX_op_divu_i32
:
1287 case INDEX_op_divu_i64
:
1288 case INDEX_op_remu_i32
:
1289 case INDEX_op_remu_i64
:
1290 case INDEX_op_shl_i32
:
1291 case INDEX_op_shl_i64
:
1292 case INDEX_op_shr_i32
:
1293 case INDEX_op_shr_i64
:
1294 case INDEX_op_sar_i32
:
1295 case INDEX_op_sar_i64
:
1296 case INDEX_op_rotl_i32
:
1297 case INDEX_op_rotl_i64
:
1298 case INDEX_op_rotr_i32
:
1299 case INDEX_op_rotr_i64
:
1300 case INDEX_op_clz_i32
:
1301 case INDEX_op_clz_i64
:
1302 case INDEX_op_ctz_i32
:
1303 case INDEX_op_ctz_i64
:
1304 tci_args_rrr(insn
, &r0
, &r1
, &r2
);
1305 info
->fprintf_func(info
->stream
, "%-12s %s, %s, %s",
1306 op_name
, str_r(r0
), str_r(r1
), str_r(r2
));
1309 case INDEX_op_deposit_i32
:
1310 case INDEX_op_deposit_i64
:
1311 tci_args_rrrbb(insn
, &r0
, &r1
, &r2
, &pos
, &len
);
1312 info
->fprintf_func(info
->stream
, "%-12s %s, %s, %s, %d, %d",
1313 op_name
, str_r(r0
), str_r(r1
), str_r(r2
), pos
, len
);
1316 case INDEX_op_extract_i32
:
1317 case INDEX_op_extract_i64
:
1318 case INDEX_op_sextract_i32
:
1319 case INDEX_op_sextract_i64
:
1320 tci_args_rrbb(insn
, &r0
, &r1
, &pos
, &len
);
1321 info
->fprintf_func(info
->stream
, "%-12s %s,%s,%d,%d",
1322 op_name
, str_r(r0
), str_r(r1
), pos
, len
);
1325 case INDEX_op_movcond_i32
:
1326 case INDEX_op_movcond_i64
:
1327 case INDEX_op_setcond2_i32
:
1328 tci_args_rrrrrc(insn
, &r0
, &r1
, &r2
, &r3
, &r4
, &c
);
1329 info
->fprintf_func(info
->stream
, "%-12s %s, %s, %s, %s, %s, %s",
1330 op_name
, str_r(r0
), str_r(r1
), str_r(r2
),
1331 str_r(r3
), str_r(r4
), str_c(c
));
1334 case INDEX_op_mulu2_i32
:
1335 case INDEX_op_mulu2_i64
:
1336 case INDEX_op_muls2_i32
:
1337 case INDEX_op_muls2_i64
:
1338 tci_args_rrrr(insn
, &r0
, &r1
, &r2
, &r3
);
1339 info
->fprintf_func(info
->stream
, "%-12s %s, %s, %s, %s",
1340 op_name
, str_r(r0
), str_r(r1
),
1341 str_r(r2
), str_r(r3
));
1344 case INDEX_op_add2_i32
:
1345 case INDEX_op_add2_i64
:
1346 case INDEX_op_sub2_i32
:
1347 case INDEX_op_sub2_i64
:
1348 tci_args_rrrrrr(insn
, &r0
, &r1
, &r2
, &r3
, &r4
, &r5
);
1349 info
->fprintf_func(info
->stream
, "%-12s %s, %s, %s, %s, %s, %s",
1350 op_name
, str_r(r0
), str_r(r1
), str_r(r2
),
1351 str_r(r3
), str_r(r4
), str_r(r5
));
1354 case INDEX_op_qemu_ld_i64
:
1355 case INDEX_op_qemu_st_i64
:
1356 len
= DIV_ROUND_UP(64, TCG_TARGET_REG_BITS
);
1358 case INDEX_op_qemu_ld_i32
:
1359 case INDEX_op_qemu_st_i32
:
1362 len
+= DIV_ROUND_UP(TARGET_LONG_BITS
, TCG_TARGET_REG_BITS
);
1365 tci_args_rrm(insn
, &r0
, &r1
, &oi
);
1366 info
->fprintf_func(info
->stream
, "%-12s %s, %s, %x",
1367 op_name
, str_r(r0
), str_r(r1
), oi
);
1370 tci_args_rrrm(insn
, &r0
, &r1
, &r2
, &oi
);
1371 info
->fprintf_func(info
->stream
, "%-12s %s, %s, %s, %x",
1372 op_name
, str_r(r0
), str_r(r1
), str_r(r2
), oi
);
1375 tci_args_rrrrr(insn
, &r0
, &r1
, &r2
, &r3
, &r4
);
1376 info
->fprintf_func(info
->stream
, "%-12s %s, %s, %s, %s, %s",
1377 op_name
, str_r(r0
), str_r(r1
),
1378 str_r(r2
), str_r(r3
), str_r(r4
));
1381 g_assert_not_reached();
1386 /* tcg_out_nop_fill uses zeros */
1388 info
->fprintf_func(info
->stream
, "align");
1394 info
->fprintf_func(info
->stream
, "illegal opcode %d", op
);
1398 return sizeof(insn
);