hw/arm/msf2-soc.c

   1 /*
   2  * SmartFusion2 SoC emulation.
   3  *
   4  * Copyright (c) 2017-2020 Subbaraya Sundeep <sundeep.lkml@gmail.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qemu/units.h"
  27 #include "qapi/error.h"
  28 #include "exec/address-spaces.h"
  29 #include "hw/char/serial.h"
  30 #include "hw/arm/msf2-soc.h"
  31 #include "hw/misc/unimp.h"
  32 #include "sysemu/sysemu.h"
  33
  34 #define MSF2_TIMER_BASE       0x40004000
  35 #define MSF2_SYSREG_BASE      0x40038000
  36 #define MSF2_EMAC_BASE        0x40041000
  37
  38 #define ENVM_BASE_ADDRESS     0x60000000
  39
  40 #define SRAM_BASE_ADDRESS     0x20000000
  41
  42 #define MSF2_EMAC_IRQ         12
  43
  44 #define MSF2_ENVM_MAX_SIZE    (512 * KiB)
  45
  46 /*
  47  * eSRAM max size is 80k without SECDED(Single error correction and
  48  * dual error detection) feature and 64k with SECDED.
  49  * We do not support SECDED now.
  50  */
  51 #define MSF2_ESRAM_MAX_SIZE       (80 * KiB)
  52
  53 static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 };
  54 static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 };
  55
  56 static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };
  57 static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };
  58 static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 };
  59
  60 static void m2sxxx_soc_initfn(Object *obj)
  61 {
  62     MSF2State *s = MSF2_SOC(obj);
  63     int i;
  64
  65     object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
  66
  67     object_initialize_child(obj, "sysreg", &s->sysreg, TYPE_MSF2_SYSREG);
  68
  69     object_initialize_child(obj, "timer", &s->timer, TYPE_MSS_TIMER);
  70
  71     for (i = 0; i < MSF2_NUM_SPIS; i++) {
  72         object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_MSS_SPI);
  73     }
  74
  75     object_initialize_child(obj, "emac", &s->emac, TYPE_MSS_EMAC);
  76 }
  77
  78 static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
  79 {
  80     MSF2State *s = MSF2_SOC(dev_soc);
  81     DeviceState *dev, *armv7m;
  82     SysBusDevice *busdev;
  83     int i;
  84
  85     MemoryRegion *system_memory = get_system_memory();
  86     MemoryRegion *nvm = g_new(MemoryRegion, 1);
  87     MemoryRegion *nvm_alias = g_new(MemoryRegion, 1);
  88     MemoryRegion *sram = g_new(MemoryRegion, 1);
  89
  90     memory_region_init_rom(nvm, OBJECT(dev_soc), "MSF2.eNVM", s->envm_size,
  91                            &error_fatal);
  92     /*
  93      * On power-on, the eNVM region 0x60000000 is automatically
  94      * remapped to the Cortex-M3 processor executable region
  95      * start address (0x0). We do not support remapping other eNVM,
  96      * eSRAM and DDR regions by guest(via Sysreg) currently.
  97      */
  98     memory_region_init_alias(nvm_alias, OBJECT(dev_soc), "MSF2.eNVM", nvm, 0,
  99                              s->envm_size);
 100
 101     memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm);
 102     memory_region_add_subregion(system_memory, 0, nvm_alias);
 103
 104     memory_region_init_ram(sram, NULL, "MSF2.eSRAM", s->esram_size,
 105                            &error_fatal);
 106     memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
 107
 108     armv7m = DEVICE(&s->armv7m);
 109     qdev_prop_set_uint32(armv7m, "num-irq", 81);
 110     qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
 111     qdev_prop_set_bit(armv7m, "enable-bitband", true);
 112     object_property_set_link(OBJECT(&s->armv7m), "memory",
 113                              OBJECT(get_system_memory()), &error_abort);
 114     if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
 115         return;
 116     }
 117
 118     if (!s->m3clk) {
 119         error_setg(errp, "Invalid m3clk value");
 120         error_append_hint(errp, "m3clk can not be zero\n");
 121         return;
 122     }
 123
 124     system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk;
 125
 126     for (i = 0; i < MSF2_NUM_UARTS; i++) {
 127         if (serial_hd(i)) {
 128             serial_mm_init(get_system_memory(), uart_addr[i], 2,
 129                            qdev_get_gpio_in(armv7m, uart_irq[i]),
 130                            115200, serial_hd(i), DEVICE_NATIVE_ENDIAN);
 131         }
 132     }
 133
 134     dev = DEVICE(&s->timer);
 135     /* APB0 clock is the timer input clock */
 136     qdev_prop_set_uint32(dev, "clock-frequency", s->m3clk / s->apb0div);
 137     if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), errp)) {
 138         return;
 139     }
 140     busdev = SYS_BUS_DEVICE(dev);
 141     sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE);
 142     sysbus_connect_irq(busdev, 0,
 143                            qdev_get_gpio_in(armv7m, timer_irq[0]));
 144     sysbus_connect_irq(busdev, 1,
 145                            qdev_get_gpio_in(armv7m, timer_irq[1]));
 146
 147     dev = DEVICE(&s->sysreg);
 148     qdev_prop_set_uint32(dev, "apb0divisor", s->apb0div);
 149     qdev_prop_set_uint32(dev, "apb1divisor", s->apb1div);
 150     if (!sysbus_realize(SYS_BUS_DEVICE(&s->sysreg), errp)) {
 151         return;
 152     }
 153     busdev = SYS_BUS_DEVICE(dev);
 154     sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE);
 155
 156     for (i = 0; i < MSF2_NUM_SPIS; i++) {
 157         gchar *bus_name;
 158
 159         if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
 160             return;
 161         }
 162
 163         sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
 164         sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
 165                            qdev_get_gpio_in(armv7m, spi_irq[i]));
 166
 167         /* Alias controller SPI bus to the SoC itself */
 168         bus_name = g_strdup_printf("spi%d", i);
 169         object_property_add_alias(OBJECT(s), bus_name,
 170                                   OBJECT(&s->spi[i]), "spi");
 171         g_free(bus_name);
 172     }
 173
 174     /* FIXME use qdev NIC properties instead of nd_table[] */
 175     if (nd_table[0].used) {
 176         qemu_check_nic_model(&nd_table[0], TYPE_MSS_EMAC);
 177         qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
 178     }
 179     dev = DEVICE(&s->emac);
 180     object_property_set_link(OBJECT(&s->emac), "ahb-bus",
 181                              OBJECT(get_system_memory()), &error_abort);
 182     if (!sysbus_realize(SYS_BUS_DEVICE(&s->emac), errp)) {
 183         return;
 184     }
 185     busdev = SYS_BUS_DEVICE(dev);
 186     sysbus_mmio_map(busdev, 0, MSF2_EMAC_BASE);
 187     sysbus_connect_irq(busdev, 0,
 188                        qdev_get_gpio_in(armv7m, MSF2_EMAC_IRQ));
 189
 190     /* Below devices are not modelled yet. */
 191     create_unimplemented_device("i2c_0", 0x40002000, 0x1000);
 192     create_unimplemented_device("dma", 0x40003000, 0x1000);
 193     create_unimplemented_device("watchdog", 0x40005000, 0x1000);
 194     create_unimplemented_device("i2c_1", 0x40012000, 0x1000);
 195     create_unimplemented_device("gpio", 0x40013000, 0x1000);
 196     create_unimplemented_device("hs-dma", 0x40014000, 0x1000);
 197     create_unimplemented_device("can", 0x40015000, 0x1000);
 198     create_unimplemented_device("rtc", 0x40017000, 0x1000);
 199     create_unimplemented_device("apb_config", 0x40020000, 0x10000);
 200     create_unimplemented_device("usb", 0x40043000, 0x1000);
 201 }
 202
 203 static Property m2sxxx_soc_properties[] = {
 204     /*
 205      * part name specifies the type of SmartFusion2 device variant(this
 206      * property is for information purpose only.
 207      */
 208     DEFINE_PROP_STRING("cpu-type", MSF2State, cpu_type),
 209     DEFINE_PROP_STRING("part-name", MSF2State, part_name),
 210     DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size, MSF2_ENVM_MAX_SIZE),
 211     DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size,
 212                         MSF2_ESRAM_MAX_SIZE),
 213     /* Libero GUI shows 100Mhz as default for clocks */
 214     DEFINE_PROP_UINT32("m3clk", MSF2State, m3clk, 100 * 1000000),
 215     /* default divisors in Libero GUI */
 216     DEFINE_PROP_UINT8("apb0div", MSF2State, apb0div, 2),
 217     DEFINE_PROP_UINT8("apb1div", MSF2State, apb1div, 2),
 218     DEFINE_PROP_END_OF_LIST(),
 219 };
 220
 221 static void m2sxxx_soc_class_init(ObjectClass *klass, void *data)
 222 {
 223     DeviceClass *dc = DEVICE_CLASS(klass);
 224
 225     dc->realize = m2sxxx_soc_realize;
 226     device_class_set_props(dc, m2sxxx_soc_properties);
 227 }
 228
 229 static const TypeInfo m2sxxx_soc_info = {
 230     .name          = TYPE_MSF2_SOC,
 231     .parent        = TYPE_SYS_BUS_DEVICE,
 232     .instance_size = sizeof(MSF2State),
 233     .instance_init = m2sxxx_soc_initfn,
 234     .class_init    = m2sxxx_soc_class_init,
 235 };
 236
 237 static void m2sxxx_soc_types(void)
 238 {
 239     type_register_static(&m2sxxx_soc_info);
 240 }
 241
 242 type_init(m2sxxx_soc_types)