2 * RISC-V emulation for qemu: main translation routines.
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "tcg/tcg-op.h"
23 #include "disas/disas.h"
24 #include "exec/cpu_ldst.h"
25 #include "exec/exec-all.h"
26 #include "exec/helper-proto.h"
27 #include "exec/helper-gen.h"
29 #include "exec/translator.h"
34 /* global register indices */
35 static TCGv cpu_gpr
[32], cpu_pc
, cpu_vl
;
36 static TCGv_i64 cpu_fpr
[32]; /* assume F and D extensions */
40 #include "exec/gen-icount.h"
42 typedef struct DisasContext
{
43 DisasContextBase base
;
44 /* pc_succ_insn points to the instruction following base.pc_next */
45 target_ulong pc_succ_insn
;
46 target_ulong priv_ver
;
52 /* Remember the rounding mode encoded in the previous fp instruction,
53 which we have already installed into env->fp_status. Or -1 for
54 no previous fp instruction. Note that we exit the TB when writing
55 to any system register, which includes CSR_FRM, so we do not have
56 to reset this known value. */
59 /* vector extension */
69 /* convert riscv funct3 to qemu memop for load/store */
70 static const int tcg_memop_lookup
[8] = {
83 #define CASE_OP_32_64(X) case X: case glue(X, W)
85 #define CASE_OP_32_64(X) case X
88 static inline bool has_ext(DisasContext
*ctx
, uint32_t ext
)
90 return ctx
->misa
& ext
;
94 * RISC-V requires NaN-boxing of narrower width floating point values.
95 * This applies when a 32-bit value is assigned to a 64-bit FP register.
96 * For consistency and simplicity, we nanbox results even when the RVD
97 * extension is not present.
99 static void gen_nanbox_s(TCGv_i64 out
, TCGv_i64 in
)
101 tcg_gen_ori_i64(out
, in
, MAKE_64BIT_MASK(32, 32));
105 * A narrow n-bit operation, where n < FLEN, checks that input operands
106 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1.
107 * If so, the least-significant bits of the input are used, otherwise the
108 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2).
110 * Here, the result is always nan-boxed, even the canonical nan.
112 static void gen_check_nanbox_s(TCGv_i64 out
, TCGv_i64 in
)
114 TCGv_i64 t_max
= tcg_const_i64(0xffffffff00000000ull
);
115 TCGv_i64 t_nan
= tcg_const_i64(0xffffffff7fc00000ull
);
117 tcg_gen_movcond_i64(TCG_COND_GEU
, out
, in
, t_max
, in
, t_nan
);
118 tcg_temp_free_i64(t_max
);
119 tcg_temp_free_i64(t_nan
);
122 static void generate_exception(DisasContext
*ctx
, int excp
)
124 tcg_gen_movi_tl(cpu_pc
, ctx
->base
.pc_next
);
125 TCGv_i32 helper_tmp
= tcg_const_i32(excp
);
126 gen_helper_raise_exception(cpu_env
, helper_tmp
);
127 tcg_temp_free_i32(helper_tmp
);
128 ctx
->base
.is_jmp
= DISAS_NORETURN
;
131 static void generate_exception_mbadaddr(DisasContext
*ctx
, int excp
)
133 tcg_gen_movi_tl(cpu_pc
, ctx
->base
.pc_next
);
134 tcg_gen_st_tl(cpu_pc
, cpu_env
, offsetof(CPURISCVState
, badaddr
));
135 TCGv_i32 helper_tmp
= tcg_const_i32(excp
);
136 gen_helper_raise_exception(cpu_env
, helper_tmp
);
137 tcg_temp_free_i32(helper_tmp
);
138 ctx
->base
.is_jmp
= DISAS_NORETURN
;
141 static void gen_exception_debug(void)
143 TCGv_i32 helper_tmp
= tcg_const_i32(EXCP_DEBUG
);
144 gen_helper_raise_exception(cpu_env
, helper_tmp
);
145 tcg_temp_free_i32(helper_tmp
);
148 /* Wrapper around tcg_gen_exit_tb that handles single stepping */
149 static void exit_tb(DisasContext
*ctx
)
151 if (ctx
->base
.singlestep_enabled
) {
152 gen_exception_debug();
154 tcg_gen_exit_tb(NULL
, 0);
158 /* Wrapper around tcg_gen_lookup_and_goto_ptr that handles single stepping */
159 static void lookup_and_goto_ptr(DisasContext
*ctx
)
161 if (ctx
->base
.singlestep_enabled
) {
162 gen_exception_debug();
164 tcg_gen_lookup_and_goto_ptr();
168 static void gen_exception_illegal(DisasContext
*ctx
)
170 generate_exception(ctx
, RISCV_EXCP_ILLEGAL_INST
);
173 static void gen_exception_inst_addr_mis(DisasContext
*ctx
)
175 generate_exception_mbadaddr(ctx
, RISCV_EXCP_INST_ADDR_MIS
);
178 static inline bool use_goto_tb(DisasContext
*ctx
, target_ulong dest
)
180 if (unlikely(ctx
->base
.singlestep_enabled
)) {
184 #ifndef CONFIG_USER_ONLY
185 return (ctx
->base
.tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
);
191 static void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
193 if (use_goto_tb(ctx
, dest
)) {
194 /* chaining is only allowed when the jump is to the same page */
196 tcg_gen_movi_tl(cpu_pc
, dest
);
198 /* No need to check for single stepping here as use_goto_tb() will
199 * return false in case of single stepping.
201 tcg_gen_exit_tb(ctx
->base
.tb
, n
);
203 tcg_gen_movi_tl(cpu_pc
, dest
);
204 lookup_and_goto_ptr(ctx
);
208 /* Wrapper for getting reg values - need to check of reg is zero since
209 * cpu_gpr[0] is not actually allocated
211 static inline void gen_get_gpr(TCGv t
, int reg_num
)
214 tcg_gen_movi_tl(t
, 0);
216 tcg_gen_mov_tl(t
, cpu_gpr
[reg_num
]);
220 /* Wrapper for setting reg values - need to check of reg is zero since
221 * cpu_gpr[0] is not actually allocated. this is more for safety purposes,
222 * since we usually avoid calling the OP_TYPE_gen function if we see a write to
225 static inline void gen_set_gpr(int reg_num_dst
, TCGv t
)
227 if (reg_num_dst
!= 0) {
228 tcg_gen_mov_tl(cpu_gpr
[reg_num_dst
], t
);
232 static void gen_mulhsu(TCGv ret
, TCGv arg1
, TCGv arg2
)
234 TCGv rl
= tcg_temp_new();
235 TCGv rh
= tcg_temp_new();
237 tcg_gen_mulu2_tl(rl
, rh
, arg1
, arg2
);
238 /* fix up for one negative */
239 tcg_gen_sari_tl(rl
, arg1
, TARGET_LONG_BITS
- 1);
240 tcg_gen_and_tl(rl
, rl
, arg2
);
241 tcg_gen_sub_tl(ret
, rh
, rl
);
247 static void gen_div(TCGv ret
, TCGv source1
, TCGv source2
)
249 TCGv cond1
, cond2
, zeroreg
, resultopt1
;
251 * Handle by altering args to tcg_gen_div to produce req'd results:
252 * For overflow: want source1 in source1 and 1 in source2
253 * For div by zero: want -1 in source1 and 1 in source2 -> -1 result
255 cond1
= tcg_temp_new();
256 cond2
= tcg_temp_new();
257 zeroreg
= tcg_const_tl(0);
258 resultopt1
= tcg_temp_new();
260 tcg_gen_movi_tl(resultopt1
, (target_ulong
)-1);
261 tcg_gen_setcondi_tl(TCG_COND_EQ
, cond2
, source2
, (target_ulong
)(~0L));
262 tcg_gen_setcondi_tl(TCG_COND_EQ
, cond1
, source1
,
263 ((target_ulong
)1) << (TARGET_LONG_BITS
- 1));
264 tcg_gen_and_tl(cond1
, cond1
, cond2
); /* cond1 = overflow */
265 tcg_gen_setcondi_tl(TCG_COND_EQ
, cond2
, source2
, 0); /* cond2 = div 0 */
266 /* if div by zero, set source1 to -1, otherwise don't change */
267 tcg_gen_movcond_tl(TCG_COND_EQ
, source1
, cond2
, zeroreg
, source1
,
269 /* if overflow or div by zero, set source2 to 1, else don't change */
270 tcg_gen_or_tl(cond1
, cond1
, cond2
);
271 tcg_gen_movi_tl(resultopt1
, (target_ulong
)1);
272 tcg_gen_movcond_tl(TCG_COND_EQ
, source2
, cond1
, zeroreg
, source2
,
274 tcg_gen_div_tl(ret
, source1
, source2
);
276 tcg_temp_free(cond1
);
277 tcg_temp_free(cond2
);
278 tcg_temp_free(zeroreg
);
279 tcg_temp_free(resultopt1
);
282 static void gen_divu(TCGv ret
, TCGv source1
, TCGv source2
)
284 TCGv cond1
, zeroreg
, resultopt1
;
285 cond1
= tcg_temp_new();
287 zeroreg
= tcg_const_tl(0);
288 resultopt1
= tcg_temp_new();
290 tcg_gen_setcondi_tl(TCG_COND_EQ
, cond1
, source2
, 0);
291 tcg_gen_movi_tl(resultopt1
, (target_ulong
)-1);
292 tcg_gen_movcond_tl(TCG_COND_EQ
, source1
, cond1
, zeroreg
, source1
,
294 tcg_gen_movi_tl(resultopt1
, (target_ulong
)1);
295 tcg_gen_movcond_tl(TCG_COND_EQ
, source2
, cond1
, zeroreg
, source2
,
297 tcg_gen_divu_tl(ret
, source1
, source2
);
299 tcg_temp_free(cond1
);
300 tcg_temp_free(zeroreg
);
301 tcg_temp_free(resultopt1
);
304 static void gen_rem(TCGv ret
, TCGv source1
, TCGv source2
)
306 TCGv cond1
, cond2
, zeroreg
, resultopt1
;
308 cond1
= tcg_temp_new();
309 cond2
= tcg_temp_new();
310 zeroreg
= tcg_const_tl(0);
311 resultopt1
= tcg_temp_new();
313 tcg_gen_movi_tl(resultopt1
, 1L);
314 tcg_gen_setcondi_tl(TCG_COND_EQ
, cond2
, source2
, (target_ulong
)-1);
315 tcg_gen_setcondi_tl(TCG_COND_EQ
, cond1
, source1
,
316 (target_ulong
)1 << (TARGET_LONG_BITS
- 1));
317 tcg_gen_and_tl(cond2
, cond1
, cond2
); /* cond1 = overflow */
318 tcg_gen_setcondi_tl(TCG_COND_EQ
, cond1
, source2
, 0); /* cond2 = div 0 */
319 /* if overflow or div by zero, set source2 to 1, else don't change */
320 tcg_gen_or_tl(cond2
, cond1
, cond2
);
321 tcg_gen_movcond_tl(TCG_COND_EQ
, source2
, cond2
, zeroreg
, source2
,
323 tcg_gen_rem_tl(resultopt1
, source1
, source2
);
324 /* if div by zero, just return the original dividend */
325 tcg_gen_movcond_tl(TCG_COND_EQ
, ret
, cond1
, zeroreg
, resultopt1
,
328 tcg_temp_free(cond1
);
329 tcg_temp_free(cond2
);
330 tcg_temp_free(zeroreg
);
331 tcg_temp_free(resultopt1
);
334 static void gen_remu(TCGv ret
, TCGv source1
, TCGv source2
)
336 TCGv cond1
, zeroreg
, resultopt1
;
337 cond1
= tcg_temp_new();
338 zeroreg
= tcg_const_tl(0);
339 resultopt1
= tcg_temp_new();
341 tcg_gen_movi_tl(resultopt1
, (target_ulong
)1);
342 tcg_gen_setcondi_tl(TCG_COND_EQ
, cond1
, source2
, 0);
343 tcg_gen_movcond_tl(TCG_COND_EQ
, source2
, cond1
, zeroreg
, source2
,
345 tcg_gen_remu_tl(resultopt1
, source1
, source2
);
346 /* if div by zero, just return the original dividend */
347 tcg_gen_movcond_tl(TCG_COND_EQ
, ret
, cond1
, zeroreg
, resultopt1
,
350 tcg_temp_free(cond1
);
351 tcg_temp_free(zeroreg
);
352 tcg_temp_free(resultopt1
);
355 static void gen_jal(DisasContext
*ctx
, int rd
, target_ulong imm
)
357 target_ulong next_pc
;
359 /* check misaligned: */
360 next_pc
= ctx
->base
.pc_next
+ imm
;
361 if (!has_ext(ctx
, RVC
)) {
362 if ((next_pc
& 0x3) != 0) {
363 gen_exception_inst_addr_mis(ctx
);
368 tcg_gen_movi_tl(cpu_gpr
[rd
], ctx
->pc_succ_insn
);
371 gen_goto_tb(ctx
, 0, ctx
->base
.pc_next
+ imm
); /* must use this for safety */
372 ctx
->base
.is_jmp
= DISAS_NORETURN
;
375 #ifdef TARGET_RISCV64
376 static void gen_load_c(DisasContext
*ctx
, uint32_t opc
, int rd
, int rs1
,
379 TCGv t0
= tcg_temp_new();
380 TCGv t1
= tcg_temp_new();
381 gen_get_gpr(t0
, rs1
);
382 tcg_gen_addi_tl(t0
, t0
, imm
);
383 int memop
= tcg_memop_lookup
[(opc
>> 12) & 0x7];
386 gen_exception_illegal(ctx
);
390 tcg_gen_qemu_ld_tl(t1
, t0
, ctx
->mem_idx
, memop
);
396 static void gen_store_c(DisasContext
*ctx
, uint32_t opc
, int rs1
, int rs2
,
399 TCGv t0
= tcg_temp_new();
400 TCGv dat
= tcg_temp_new();
401 gen_get_gpr(t0
, rs1
);
402 tcg_gen_addi_tl(t0
, t0
, imm
);
403 gen_get_gpr(dat
, rs2
);
404 int memop
= tcg_memop_lookup
[(opc
>> 12) & 0x7];
407 gen_exception_illegal(ctx
);
411 tcg_gen_qemu_st_tl(dat
, t0
, ctx
->mem_idx
, memop
);
417 #ifndef CONFIG_USER_ONLY
418 /* The states of mstatus_fs are:
419 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
420 * We will have already diagnosed disabled state,
421 * and need to turn initial/clean into dirty.
423 static void mark_fs_dirty(DisasContext
*ctx
)
426 if (ctx
->mstatus_fs
== MSTATUS_FS
) {
429 /* Remember the state change for the rest of the TB. */
430 ctx
->mstatus_fs
= MSTATUS_FS
;
432 tmp
= tcg_temp_new();
433 tcg_gen_ld_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus
));
434 tcg_gen_ori_tl(tmp
, tmp
, MSTATUS_FS
| MSTATUS_SD
);
435 tcg_gen_st_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus
));
437 if (ctx
->virt_enabled
) {
438 tcg_gen_ld_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus_hs
));
439 tcg_gen_ori_tl(tmp
, tmp
, MSTATUS_FS
| MSTATUS_SD
);
440 tcg_gen_st_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus_hs
));
445 static inline void mark_fs_dirty(DisasContext
*ctx
) { }
448 #if !defined(TARGET_RISCV64)
449 static void gen_fp_load(DisasContext
*ctx
, uint32_t opc
, int rd
,
450 int rs1
, target_long imm
)
454 if (ctx
->mstatus_fs
== 0) {
455 gen_exception_illegal(ctx
);
460 gen_get_gpr(t0
, rs1
);
461 tcg_gen_addi_tl(t0
, t0
, imm
);
465 if (!has_ext(ctx
, RVF
)) {
468 tcg_gen_qemu_ld_i64(cpu_fpr
[rd
], t0
, ctx
->mem_idx
, MO_TEUL
);
469 /* RISC-V requires NaN-boxing of narrower width floating point values */
470 tcg_gen_ori_i64(cpu_fpr
[rd
], cpu_fpr
[rd
], 0xffffffff00000000ULL
);
473 if (!has_ext(ctx
, RVD
)) {
476 tcg_gen_qemu_ld_i64(cpu_fpr
[rd
], t0
, ctx
->mem_idx
, MO_TEQ
);
480 gen_exception_illegal(ctx
);
488 static void gen_fp_store(DisasContext
*ctx
, uint32_t opc
, int rs1
,
489 int rs2
, target_long imm
)
493 if (ctx
->mstatus_fs
== 0) {
494 gen_exception_illegal(ctx
);
499 gen_get_gpr(t0
, rs1
);
500 tcg_gen_addi_tl(t0
, t0
, imm
);
504 if (!has_ext(ctx
, RVF
)) {
507 tcg_gen_qemu_st_i64(cpu_fpr
[rs2
], t0
, ctx
->mem_idx
, MO_TEUL
);
510 if (!has_ext(ctx
, RVD
)) {
513 tcg_gen_qemu_st_i64(cpu_fpr
[rs2
], t0
, ctx
->mem_idx
, MO_TEQ
);
517 gen_exception_illegal(ctx
);
525 static void gen_set_rm(DisasContext
*ctx
, int rm
)
529 if (ctx
->frm
== rm
) {
533 t0
= tcg_const_i32(rm
);
534 gen_helper_set_rounding_mode(cpu_env
, t0
);
535 tcg_temp_free_i32(t0
);
538 static void decode_RV32_64C0(DisasContext
*ctx
, uint16_t opcode
)
540 uint8_t funct3
= extract16(opcode
, 13, 3);
541 uint8_t rd_rs2
= GET_C_RS2S(opcode
);
542 uint8_t rs1s
= GET_C_RS1S(opcode
);
546 #if defined(TARGET_RISCV64)
547 /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
548 gen_load_c(ctx
, OPC_RISC_LD
, rd_rs2
, rs1s
,
549 GET_C_LD_IMM(opcode
));
551 /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/
552 gen_fp_load(ctx
, OPC_RISC_FLW
, rd_rs2
, rs1s
,
553 GET_C_LW_IMM(opcode
));
557 #if defined(TARGET_RISCV64)
558 /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
559 gen_store_c(ctx
, OPC_RISC_SD
, rs1s
, rd_rs2
,
560 GET_C_LD_IMM(opcode
));
562 /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/
563 gen_fp_store(ctx
, OPC_RISC_FSW
, rs1s
, rd_rs2
,
564 GET_C_LW_IMM(opcode
));
570 static void decode_RV32_64C(DisasContext
*ctx
, uint16_t opcode
)
572 uint8_t op
= extract16(opcode
, 0, 2);
576 decode_RV32_64C0(ctx
, opcode
);
581 static int ex_plus_1(DisasContext
*ctx
, int nf
)
586 #define EX_SH(amount) \
587 static int ex_shift_##amount(DisasContext *ctx, int imm) \
589 return imm << amount; \
597 #define REQUIRE_EXT(ctx, ext) do { \
598 if (!has_ext(ctx, ext)) { \
603 static int ex_rvc_register(DisasContext
*ctx
, int reg
)
608 static int ex_rvc_shifti(DisasContext
*ctx
, int imm
)
610 /* For RV128 a shamt of 0 means a shift by 64. */
611 return imm
? imm
: 64;
614 /* Include the auto-generated decoder for 32 bit insn */
615 #include "decode-insn32.c.inc"
617 static bool gen_arith_imm_fn(DisasContext
*ctx
, arg_i
*a
,
618 void (*func
)(TCGv
, TCGv
, target_long
))
621 source1
= tcg_temp_new();
623 gen_get_gpr(source1
, a
->rs1
);
625 (*func
)(source1
, source1
, a
->imm
);
627 gen_set_gpr(a
->rd
, source1
);
628 tcg_temp_free(source1
);
632 static bool gen_arith_imm_tl(DisasContext
*ctx
, arg_i
*a
,
633 void (*func
)(TCGv
, TCGv
, TCGv
))
635 TCGv source1
, source2
;
636 source1
= tcg_temp_new();
637 source2
= tcg_temp_new();
639 gen_get_gpr(source1
, a
->rs1
);
640 tcg_gen_movi_tl(source2
, a
->imm
);
642 (*func
)(source1
, source1
, source2
);
644 gen_set_gpr(a
->rd
, source1
);
645 tcg_temp_free(source1
);
646 tcg_temp_free(source2
);
650 #ifdef TARGET_RISCV64
651 static void gen_addw(TCGv ret
, TCGv arg1
, TCGv arg2
)
653 tcg_gen_add_tl(ret
, arg1
, arg2
);
654 tcg_gen_ext32s_tl(ret
, ret
);
657 static void gen_subw(TCGv ret
, TCGv arg1
, TCGv arg2
)
659 tcg_gen_sub_tl(ret
, arg1
, arg2
);
660 tcg_gen_ext32s_tl(ret
, ret
);
663 static void gen_mulw(TCGv ret
, TCGv arg1
, TCGv arg2
)
665 tcg_gen_mul_tl(ret
, arg1
, arg2
);
666 tcg_gen_ext32s_tl(ret
, ret
);
669 static bool gen_arith_div_w(DisasContext
*ctx
, arg_r
*a
,
670 void(*func
)(TCGv
, TCGv
, TCGv
))
672 TCGv source1
, source2
;
673 source1
= tcg_temp_new();
674 source2
= tcg_temp_new();
676 gen_get_gpr(source1
, a
->rs1
);
677 gen_get_gpr(source2
, a
->rs2
);
678 tcg_gen_ext32s_tl(source1
, source1
);
679 tcg_gen_ext32s_tl(source2
, source2
);
681 (*func
)(source1
, source1
, source2
);
683 tcg_gen_ext32s_tl(source1
, source1
);
684 gen_set_gpr(a
->rd
, source1
);
685 tcg_temp_free(source1
);
686 tcg_temp_free(source2
);
690 static bool gen_arith_div_uw(DisasContext
*ctx
, arg_r
*a
,
691 void(*func
)(TCGv
, TCGv
, TCGv
))
693 TCGv source1
, source2
;
694 source1
= tcg_temp_new();
695 source2
= tcg_temp_new();
697 gen_get_gpr(source1
, a
->rs1
);
698 gen_get_gpr(source2
, a
->rs2
);
699 tcg_gen_ext32u_tl(source1
, source1
);
700 tcg_gen_ext32u_tl(source2
, source2
);
702 (*func
)(source1
, source1
, source2
);
704 tcg_gen_ext32s_tl(source1
, source1
);
705 gen_set_gpr(a
->rd
, source1
);
706 tcg_temp_free(source1
);
707 tcg_temp_free(source2
);
713 static bool gen_arith(DisasContext
*ctx
, arg_r
*a
,
714 void(*func
)(TCGv
, TCGv
, TCGv
))
716 TCGv source1
, source2
;
717 source1
= tcg_temp_new();
718 source2
= tcg_temp_new();
720 gen_get_gpr(source1
, a
->rs1
);
721 gen_get_gpr(source2
, a
->rs2
);
723 (*func
)(source1
, source1
, source2
);
725 gen_set_gpr(a
->rd
, source1
);
726 tcg_temp_free(source1
);
727 tcg_temp_free(source2
);
731 static bool gen_shift(DisasContext
*ctx
, arg_r
*a
,
732 void(*func
)(TCGv
, TCGv
, TCGv
))
734 TCGv source1
= tcg_temp_new();
735 TCGv source2
= tcg_temp_new();
737 gen_get_gpr(source1
, a
->rs1
);
738 gen_get_gpr(source2
, a
->rs2
);
740 tcg_gen_andi_tl(source2
, source2
, TARGET_LONG_BITS
- 1);
741 (*func
)(source1
, source1
, source2
);
743 gen_set_gpr(a
->rd
, source1
);
744 tcg_temp_free(source1
);
745 tcg_temp_free(source2
);
749 /* Include insn module translation function */
750 #include "insn_trans/trans_rvi.c.inc"
751 #include "insn_trans/trans_rvm.c.inc"
752 #include "insn_trans/trans_rva.c.inc"
753 #include "insn_trans/trans_rvf.c.inc"
754 #include "insn_trans/trans_rvd.c.inc"
755 #include "insn_trans/trans_rvh.c.inc"
756 #include "insn_trans/trans_rvv.c.inc"
757 #include "insn_trans/trans_privileged.c.inc"
759 /* Include the auto-generated decoder for 16 bit insn */
760 #include "decode-insn16.c.inc"
762 static void decode_opc(CPURISCVState
*env
, DisasContext
*ctx
, uint16_t opcode
)
764 /* check for compressed insn */
765 if (extract16(opcode
, 0, 2) != 3) {
766 if (!has_ext(ctx
, RVC
)) {
767 gen_exception_illegal(ctx
);
769 ctx
->pc_succ_insn
= ctx
->base
.pc_next
+ 2;
770 if (!decode_insn16(ctx
, opcode
)) {
771 /* fall back to old decoder */
772 decode_RV32_64C(ctx
, opcode
);
776 uint32_t opcode32
= opcode
;
777 opcode32
= deposit32(opcode32
, 16, 16,
778 translator_lduw(env
, ctx
->base
.pc_next
+ 2));
779 ctx
->pc_succ_insn
= ctx
->base
.pc_next
+ 4;
780 if (!decode_insn32(ctx
, opcode32
)) {
781 gen_exception_illegal(ctx
);
786 static void riscv_tr_init_disas_context(DisasContextBase
*dcbase
, CPUState
*cs
)
788 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
789 CPURISCVState
*env
= cs
->env_ptr
;
790 RISCVCPU
*cpu
= RISCV_CPU(cs
);
791 uint32_t tb_flags
= ctx
->base
.tb
->flags
;
793 ctx
->pc_succ_insn
= ctx
->base
.pc_first
;
794 ctx
->mem_idx
= tb_flags
& TB_FLAGS_MMU_MASK
;
795 ctx
->mstatus_fs
= tb_flags
& TB_FLAGS_MSTATUS_FS
;
796 ctx
->priv_ver
= env
->priv_ver
;
797 #if !defined(CONFIG_USER_ONLY)
798 if (riscv_has_ext(env
, RVH
)) {
799 ctx
->virt_enabled
= riscv_cpu_virt_enabled(env
);
801 ctx
->virt_enabled
= false;
804 ctx
->virt_enabled
= false;
806 ctx
->misa
= env
->misa
;
807 ctx
->frm
= -1; /* unknown rounding mode */
808 ctx
->ext_ifencei
= cpu
->cfg
.ext_ifencei
;
809 ctx
->vlen
= cpu
->cfg
.vlen
;
810 ctx
->vill
= FIELD_EX32(tb_flags
, TB_FLAGS
, VILL
);
811 ctx
->sew
= FIELD_EX32(tb_flags
, TB_FLAGS
, SEW
);
812 ctx
->lmul
= FIELD_EX32(tb_flags
, TB_FLAGS
, LMUL
);
813 ctx
->mlen
= 1 << (ctx
->sew
+ 3 - ctx
->lmul
);
814 ctx
->vl_eq_vlmax
= FIELD_EX32(tb_flags
, TB_FLAGS
, VL_EQ_VLMAX
);
817 static void riscv_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
821 static void riscv_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
823 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
825 tcg_gen_insn_start(ctx
->base
.pc_next
);
828 static bool riscv_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cpu
,
829 const CPUBreakpoint
*bp
)
831 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
833 tcg_gen_movi_tl(cpu_pc
, ctx
->base
.pc_next
);
834 ctx
->base
.is_jmp
= DISAS_NORETURN
;
835 gen_exception_debug();
836 /* The address covered by the breakpoint must be included in
837 [tb->pc, tb->pc + tb->size) in order to for it to be
838 properly cleared -- thus we increment the PC here so that
839 the logic setting tb->size below does the right thing. */
840 ctx
->base
.pc_next
+= 4;
844 static void riscv_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
846 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
847 CPURISCVState
*env
= cpu
->env_ptr
;
848 uint16_t opcode16
= translator_lduw(env
, ctx
->base
.pc_next
);
850 decode_opc(env
, ctx
, opcode16
);
851 ctx
->base
.pc_next
= ctx
->pc_succ_insn
;
853 if (ctx
->base
.is_jmp
== DISAS_NEXT
) {
854 target_ulong page_start
;
856 page_start
= ctx
->base
.pc_first
& TARGET_PAGE_MASK
;
857 if (ctx
->base
.pc_next
- page_start
>= TARGET_PAGE_SIZE
) {
858 ctx
->base
.is_jmp
= DISAS_TOO_MANY
;
863 static void riscv_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
865 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
867 switch (ctx
->base
.is_jmp
) {
869 gen_goto_tb(ctx
, 0, ctx
->base
.pc_next
);
874 g_assert_not_reached();
878 static void riscv_tr_disas_log(const DisasContextBase
*dcbase
, CPUState
*cpu
)
880 #ifndef CONFIG_USER_ONLY
881 RISCVCPU
*rvcpu
= RISCV_CPU(cpu
);
882 CPURISCVState
*env
= &rvcpu
->env
;
885 qemu_log("IN: %s\n", lookup_symbol(dcbase
->pc_first
));
886 #ifndef CONFIG_USER_ONLY
887 qemu_log("Priv: "TARGET_FMT_ld
"; Virt: "TARGET_FMT_ld
"\n", env
->priv
, env
->virt
);
889 log_target_disas(cpu
, dcbase
->pc_first
, dcbase
->tb
->size
);
892 static const TranslatorOps riscv_tr_ops
= {
893 .init_disas_context
= riscv_tr_init_disas_context
,
894 .tb_start
= riscv_tr_tb_start
,
895 .insn_start
= riscv_tr_insn_start
,
896 .breakpoint_check
= riscv_tr_breakpoint_check
,
897 .translate_insn
= riscv_tr_translate_insn
,
898 .tb_stop
= riscv_tr_tb_stop
,
899 .disas_log
= riscv_tr_disas_log
,
902 void gen_intermediate_code(CPUState
*cs
, TranslationBlock
*tb
, int max_insns
)
906 translator_loop(&riscv_tr_ops
, &ctx
.base
, cs
, tb
, max_insns
);
909 void riscv_translate_init(void)
913 /* cpu_gpr[0] is a placeholder for the zero register. Do not use it. */
914 /* Use the gen_set_gpr and gen_get_gpr helper functions when accessing */
915 /* registers, unless you specifically block reads/writes to reg 0 */
918 for (i
= 1; i
< 32; i
++) {
919 cpu_gpr
[i
] = tcg_global_mem_new(cpu_env
,
920 offsetof(CPURISCVState
, gpr
[i
]), riscv_int_regnames
[i
]);
923 for (i
= 0; i
< 32; i
++) {
924 cpu_fpr
[i
] = tcg_global_mem_new_i64(cpu_env
,
925 offsetof(CPURISCVState
, fpr
[i
]), riscv_fpr_regnames
[i
]);
928 cpu_pc
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, pc
), "pc");
929 cpu_vl
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, vl
), "vl");
930 load_res
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, load_res
),
932 load_val
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, load_val
),