4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu/qemu-print.h"
22 #include "qemu/ctype.h"
25 #include "exec/exec-all.h"
26 #include "qapi/error.h"
27 #include "qemu/error-report.h"
28 #include "hw/qdev-properties.h"
29 #include "migration/vmstate.h"
30 #include "fpu/softfloat-helpers.h"
32 /* RISC-V CPU definitions */
34 static const char riscv_exts
[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
36 const char * const riscv_int_regnames
[] = {
37 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
38 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3",
39 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4",
40 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11",
41 "x28/t3", "x29/t4", "x30/t5", "x31/t6"
44 const char * const riscv_fpr_regnames
[] = {
45 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5",
46 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1",
47 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7",
48 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7",
49 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9",
50 "f30/ft10", "f31/ft11"
53 const char * const riscv_excp_names
[] = {
56 "illegal_instruction",
74 "guest_exec_page_fault",
75 "guest_load_page_fault",
77 "guest_store_page_fault",
80 const char * const riscv_intr_names
[] = {
99 const char *riscv_cpu_get_trap_name(target_ulong cause
, bool async
)
102 return (cause
< ARRAY_SIZE(riscv_intr_names
)) ?
103 riscv_intr_names
[cause
] : "(unknown)";
105 return (cause
< ARRAY_SIZE(riscv_excp_names
)) ?
106 riscv_excp_names
[cause
] : "(unknown)";
110 static void set_misa(CPURISCVState
*env
, target_ulong misa
)
112 env
->misa_mask
= env
->misa
= misa
;
115 static void set_priv_version(CPURISCVState
*env
, int priv_ver
)
117 env
->priv_ver
= priv_ver
;
120 static void set_vext_version(CPURISCVState
*env
, int vext_ver
)
122 env
->vext_ver
= vext_ver
;
125 static void set_feature(CPURISCVState
*env
, int feature
)
127 env
->features
|= (1ULL << feature
);
130 static void set_resetvec(CPURISCVState
*env
, int resetvec
)
132 #ifndef CONFIG_USER_ONLY
133 env
->resetvec
= resetvec
;
137 static void riscv_any_cpu_init(Object
*obj
)
139 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
140 set_misa(env
, RVXLEN
| RVI
| RVM
| RVA
| RVF
| RVD
| RVC
| RVU
);
141 set_priv_version(env
, PRIV_VERSION_1_11_0
);
144 static void riscv_base_cpu_init(Object
*obj
)
146 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
147 /* We set this in the realise function */
151 static void rvxx_sifive_u_cpu_init(Object
*obj
)
153 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
154 set_misa(env
, RVXLEN
| RVI
| RVM
| RVA
| RVF
| RVD
| RVC
| RVS
| RVU
);
155 set_priv_version(env
, PRIV_VERSION_1_10_0
);
158 static void rvxx_sifive_e_cpu_init(Object
*obj
)
160 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
161 set_misa(env
, RVXLEN
| RVI
| RVM
| RVA
| RVC
| RVU
);
162 set_priv_version(env
, PRIV_VERSION_1_10_0
);
163 qdev_prop_set_bit(DEVICE(obj
), "mmu", false);
166 #if defined(TARGET_RISCV32)
168 static void rv32_ibex_cpu_init(Object
*obj
)
170 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
171 set_misa(env
, RV32
| RVI
| RVM
| RVC
| RVU
);
172 set_priv_version(env
, PRIV_VERSION_1_10_0
);
173 qdev_prop_set_bit(DEVICE(obj
), "mmu", false);
176 static void rv32_imafcu_nommu_cpu_init(Object
*obj
)
178 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
179 set_misa(env
, RV32
| RVI
| RVM
| RVA
| RVF
| RVC
| RVU
);
180 set_priv_version(env
, PRIV_VERSION_1_10_0
);
181 set_resetvec(env
, DEFAULT_RSTVEC
);
182 qdev_prop_set_bit(DEVICE(obj
), "mmu", false);
187 static ObjectClass
*riscv_cpu_class_by_name(const char *cpu_model
)
193 cpuname
= g_strsplit(cpu_model
, ",", 1);
194 typename
= g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname
[0]);
195 oc
= object_class_by_name(typename
);
198 if (!oc
|| !object_class_dynamic_cast(oc
, TYPE_RISCV_CPU
) ||
199 object_class_is_abstract(oc
)) {
205 static void riscv_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
207 RISCVCPU
*cpu
= RISCV_CPU(cs
);
208 CPURISCVState
*env
= &cpu
->env
;
211 #if !defined(CONFIG_USER_ONLY)
212 if (riscv_has_ext(env
, RVH
)) {
213 qemu_fprintf(f
, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env
));
216 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "pc ", env
->pc
);
217 #ifndef CONFIG_USER_ONLY
218 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "mhartid ", env
->mhartid
);
219 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "mstatus ", env
->mstatus
);
220 #ifdef TARGET_RISCV32
221 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "mstatush ", env
->mstatush
);
223 if (riscv_has_ext(env
, RVH
)) {
224 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "hstatus ", env
->hstatus
);
225 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "vsstatus ", env
->vsstatus
);
227 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "mip ", env
->mip
);
228 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "mie ", env
->mie
);
229 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "mideleg ", env
->mideleg
);
230 if (riscv_has_ext(env
, RVH
)) {
231 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "hideleg ", env
->hideleg
);
233 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "medeleg ", env
->medeleg
);
234 if (riscv_has_ext(env
, RVH
)) {
235 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "hedeleg ", env
->hedeleg
);
237 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "mtvec ", env
->mtvec
);
238 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "stvec ", env
->stvec
);
239 if (riscv_has_ext(env
, RVH
)) {
240 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "vstvec ", env
->vstvec
);
242 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "mepc ", env
->mepc
);
243 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "sepc ", env
->sepc
);
244 if (riscv_has_ext(env
, RVH
)) {
245 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "vsepc ", env
->vsepc
);
247 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "mcause ", env
->mcause
);
248 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "scause ", env
->scause
);
249 if (riscv_has_ext(env
, RVH
)) {
250 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "vscause ", env
->vscause
);
252 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "mtval ", env
->mtval
);
253 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "stval ", env
->sbadaddr
);
254 if (riscv_has_ext(env
, RVH
)) {
255 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "htval ", env
->htval
);
256 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "mtval2 ", env
->mtval2
);
260 for (i
= 0; i
< 32; i
++) {
261 qemu_fprintf(f
, " %s " TARGET_FMT_lx
,
262 riscv_int_regnames
[i
], env
->gpr
[i
]);
264 qemu_fprintf(f
, "\n");
267 if (flags
& CPU_DUMP_FPU
) {
268 for (i
= 0; i
< 32; i
++) {
269 qemu_fprintf(f
, " %s %016" PRIx64
,
270 riscv_fpr_regnames
[i
], env
->fpr
[i
]);
272 qemu_fprintf(f
, "\n");
278 static void riscv_cpu_set_pc(CPUState
*cs
, vaddr value
)
280 RISCVCPU
*cpu
= RISCV_CPU(cs
);
281 CPURISCVState
*env
= &cpu
->env
;
285 static void riscv_cpu_synchronize_from_tb(CPUState
*cs
, TranslationBlock
*tb
)
287 RISCVCPU
*cpu
= RISCV_CPU(cs
);
288 CPURISCVState
*env
= &cpu
->env
;
292 static bool riscv_cpu_has_work(CPUState
*cs
)
294 #ifndef CONFIG_USER_ONLY
295 RISCVCPU
*cpu
= RISCV_CPU(cs
);
296 CPURISCVState
*env
= &cpu
->env
;
298 * Definition of the WFI instruction requires it to ignore the privilege
299 * mode and delegation registers, but respect individual enables
301 return (env
->mip
& env
->mie
) != 0;
307 void restore_state_to_opc(CPURISCVState
*env
, TranslationBlock
*tb
,
313 static void riscv_cpu_reset(DeviceState
*dev
)
315 CPUState
*cs
= CPU(dev
);
316 RISCVCPU
*cpu
= RISCV_CPU(cs
);
317 RISCVCPUClass
*mcc
= RISCV_CPU_GET_CLASS(cpu
);
318 CPURISCVState
*env
= &cpu
->env
;
320 mcc
->parent_reset(dev
);
321 #ifndef CONFIG_USER_ONLY
323 env
->mstatus
&= ~(MSTATUS_MIE
| MSTATUS_MPRV
);
325 env
->pc
= env
->resetvec
;
327 cs
->exception_index
= EXCP_NONE
;
329 set_default_nan_mode(1, &env
->fp_status
);
332 static void riscv_cpu_disas_set_info(CPUState
*s
, disassemble_info
*info
)
334 #if defined(TARGET_RISCV32)
335 info
->print_insn
= print_insn_riscv32
;
336 #elif defined(TARGET_RISCV64)
337 info
->print_insn
= print_insn_riscv64
;
341 static void riscv_cpu_realize(DeviceState
*dev
, Error
**errp
)
343 CPUState
*cs
= CPU(dev
);
344 RISCVCPU
*cpu
= RISCV_CPU(dev
);
345 CPURISCVState
*env
= &cpu
->env
;
346 RISCVCPUClass
*mcc
= RISCV_CPU_GET_CLASS(dev
);
347 int priv_version
= PRIV_VERSION_1_11_0
;
348 int vext_version
= VEXT_VERSION_0_07_1
;
349 target_ulong target_misa
= 0;
350 Error
*local_err
= NULL
;
352 cpu_exec_realizefn(cs
, &local_err
);
353 if (local_err
!= NULL
) {
354 error_propagate(errp
, local_err
);
358 if (cpu
->cfg
.priv_spec
) {
359 if (!g_strcmp0(cpu
->cfg
.priv_spec
, "v1.11.0")) {
360 priv_version
= PRIV_VERSION_1_11_0
;
361 } else if (!g_strcmp0(cpu
->cfg
.priv_spec
, "v1.10.0")) {
362 priv_version
= PRIV_VERSION_1_10_0
;
365 "Unsupported privilege spec version '%s'",
371 set_priv_version(env
, priv_version
);
372 set_vext_version(env
, vext_version
);
375 set_feature(env
, RISCV_FEATURE_MMU
);
379 set_feature(env
, RISCV_FEATURE_PMP
);
382 set_resetvec(env
, cpu
->cfg
.resetvec
);
384 /* If misa isn't set (rv32 and rv64 machines) set it here */
386 /* Do some ISA extension error checking */
387 if (cpu
->cfg
.ext_i
&& cpu
->cfg
.ext_e
) {
389 "I and E extensions are incompatible");
393 if (!cpu
->cfg
.ext_i
&& !cpu
->cfg
.ext_e
) {
395 "Either I or E extension must be set");
399 if (cpu
->cfg
.ext_g
&& !(cpu
->cfg
.ext_i
& cpu
->cfg
.ext_m
&
400 cpu
->cfg
.ext_a
& cpu
->cfg
.ext_f
&
402 warn_report("Setting G will also set IMAFD");
403 cpu
->cfg
.ext_i
= true;
404 cpu
->cfg
.ext_m
= true;
405 cpu
->cfg
.ext_a
= true;
406 cpu
->cfg
.ext_f
= true;
407 cpu
->cfg
.ext_d
= true;
410 /* Set the ISA extensions, checks should have happened above */
411 if (cpu
->cfg
.ext_i
) {
414 if (cpu
->cfg
.ext_e
) {
417 if (cpu
->cfg
.ext_m
) {
420 if (cpu
->cfg
.ext_a
) {
423 if (cpu
->cfg
.ext_f
) {
426 if (cpu
->cfg
.ext_d
) {
429 if (cpu
->cfg
.ext_c
) {
432 if (cpu
->cfg
.ext_s
) {
435 if (cpu
->cfg
.ext_u
) {
438 if (cpu
->cfg
.ext_h
) {
441 if (cpu
->cfg
.ext_v
) {
443 if (!is_power_of_2(cpu
->cfg
.vlen
)) {
445 "Vector extension VLEN must be power of 2");
448 if (cpu
->cfg
.vlen
> RV_VLEN_MAX
|| cpu
->cfg
.vlen
< 128) {
450 "Vector extension implementation only supports VLEN "
451 "in the range [128, %d]", RV_VLEN_MAX
);
454 if (!is_power_of_2(cpu
->cfg
.elen
)) {
456 "Vector extension ELEN must be power of 2");
459 if (cpu
->cfg
.elen
> 64 || cpu
->cfg
.vlen
< 8) {
461 "Vector extension implementation only supports ELEN "
462 "in the range [8, 64]");
465 if (cpu
->cfg
.vext_spec
) {
466 if (!g_strcmp0(cpu
->cfg
.vext_spec
, "v0.7.1")) {
467 vext_version
= VEXT_VERSION_0_07_1
;
470 "Unsupported vector spec version '%s'",
475 qemu_log("vector verison is not specified, "
476 "use the default value v0.7.1\n");
478 set_vext_version(env
, vext_version
);
481 set_misa(env
, RVXLEN
| target_misa
);
484 riscv_cpu_register_gdb_regs_for_features(cs
);
489 mcc
->parent_realize(dev
, errp
);
492 static void riscv_cpu_init(Object
*obj
)
494 RISCVCPU
*cpu
= RISCV_CPU(obj
);
496 cpu_set_cpustate_pointers(cpu
);
499 #ifndef CONFIG_USER_ONLY
500 static const VMStateDescription vmstate_riscv_cpu
= {
506 static Property riscv_cpu_properties
[] = {
507 DEFINE_PROP_BOOL("i", RISCVCPU
, cfg
.ext_i
, true),
508 DEFINE_PROP_BOOL("e", RISCVCPU
, cfg
.ext_e
, false),
509 DEFINE_PROP_BOOL("g", RISCVCPU
, cfg
.ext_g
, true),
510 DEFINE_PROP_BOOL("m", RISCVCPU
, cfg
.ext_m
, true),
511 DEFINE_PROP_BOOL("a", RISCVCPU
, cfg
.ext_a
, true),
512 DEFINE_PROP_BOOL("f", RISCVCPU
, cfg
.ext_f
, true),
513 DEFINE_PROP_BOOL("d", RISCVCPU
, cfg
.ext_d
, true),
514 DEFINE_PROP_BOOL("c", RISCVCPU
, cfg
.ext_c
, true),
515 DEFINE_PROP_BOOL("s", RISCVCPU
, cfg
.ext_s
, true),
516 DEFINE_PROP_BOOL("u", RISCVCPU
, cfg
.ext_u
, true),
517 /* This is experimental so mark with 'x-' */
518 DEFINE_PROP_BOOL("x-h", RISCVCPU
, cfg
.ext_h
, false),
519 DEFINE_PROP_BOOL("x-v", RISCVCPU
, cfg
.ext_v
, false),
520 DEFINE_PROP_BOOL("Counters", RISCVCPU
, cfg
.ext_counters
, true),
521 DEFINE_PROP_BOOL("Zifencei", RISCVCPU
, cfg
.ext_ifencei
, true),
522 DEFINE_PROP_BOOL("Zicsr", RISCVCPU
, cfg
.ext_icsr
, true),
523 DEFINE_PROP_STRING("priv_spec", RISCVCPU
, cfg
.priv_spec
),
524 DEFINE_PROP_STRING("vext_spec", RISCVCPU
, cfg
.vext_spec
),
525 DEFINE_PROP_UINT16("vlen", RISCVCPU
, cfg
.vlen
, 128),
526 DEFINE_PROP_UINT16("elen", RISCVCPU
, cfg
.elen
, 64),
527 DEFINE_PROP_BOOL("mmu", RISCVCPU
, cfg
.mmu
, true),
528 DEFINE_PROP_BOOL("pmp", RISCVCPU
, cfg
.pmp
, true),
529 DEFINE_PROP_UINT64("resetvec", RISCVCPU
, cfg
.resetvec
, DEFAULT_RSTVEC
),
530 DEFINE_PROP_END_OF_LIST(),
533 static void riscv_cpu_class_init(ObjectClass
*c
, void *data
)
535 RISCVCPUClass
*mcc
= RISCV_CPU_CLASS(c
);
536 CPUClass
*cc
= CPU_CLASS(c
);
537 DeviceClass
*dc
= DEVICE_CLASS(c
);
539 device_class_set_parent_realize(dc
, riscv_cpu_realize
,
540 &mcc
->parent_realize
);
542 device_class_set_parent_reset(dc
, riscv_cpu_reset
, &mcc
->parent_reset
);
544 cc
->class_by_name
= riscv_cpu_class_by_name
;
545 cc
->has_work
= riscv_cpu_has_work
;
546 cc
->do_interrupt
= riscv_cpu_do_interrupt
;
547 cc
->cpu_exec_interrupt
= riscv_cpu_exec_interrupt
;
548 cc
->dump_state
= riscv_cpu_dump_state
;
549 cc
->set_pc
= riscv_cpu_set_pc
;
550 cc
->synchronize_from_tb
= riscv_cpu_synchronize_from_tb
;
551 cc
->gdb_read_register
= riscv_cpu_gdb_read_register
;
552 cc
->gdb_write_register
= riscv_cpu_gdb_write_register
;
553 cc
->gdb_num_core_regs
= 33;
554 #if defined(TARGET_RISCV32)
555 cc
->gdb_core_xml_file
= "riscv-32bit-cpu.xml";
556 #elif defined(TARGET_RISCV64)
557 cc
->gdb_core_xml_file
= "riscv-64bit-cpu.xml";
559 cc
->gdb_stop_before_watchpoint
= true;
560 cc
->disas_set_info
= riscv_cpu_disas_set_info
;
561 #ifndef CONFIG_USER_ONLY
562 cc
->do_transaction_failed
= riscv_cpu_do_transaction_failed
;
563 cc
->do_unaligned_access
= riscv_cpu_do_unaligned_access
;
564 cc
->get_phys_page_debug
= riscv_cpu_get_phys_page_debug
;
565 /* For now, mark unmigratable: */
566 cc
->vmsd
= &vmstate_riscv_cpu
;
569 cc
->tcg_initialize
= riscv_translate_init
;
570 cc
->tlb_fill
= riscv_cpu_tlb_fill
;
572 device_class_set_props(dc
, riscv_cpu_properties
);
575 char *riscv_isa_string(RISCVCPU
*cpu
)
578 const size_t maxlen
= sizeof("rv128") + sizeof(riscv_exts
) + 1;
579 char *isa_str
= g_new(char, maxlen
);
580 char *p
= isa_str
+ snprintf(isa_str
, maxlen
, "rv%d", TARGET_LONG_BITS
);
581 for (i
= 0; i
< sizeof(riscv_exts
); i
++) {
582 if (cpu
->env
.misa
& RV(riscv_exts
[i
])) {
583 *p
++ = qemu_tolower(riscv_exts
[i
]);
590 static gint
riscv_cpu_list_compare(gconstpointer a
, gconstpointer b
)
592 ObjectClass
*class_a
= (ObjectClass
*)a
;
593 ObjectClass
*class_b
= (ObjectClass
*)b
;
594 const char *name_a
, *name_b
;
596 name_a
= object_class_get_name(class_a
);
597 name_b
= object_class_get_name(class_b
);
598 return strcmp(name_a
, name_b
);
601 static void riscv_cpu_list_entry(gpointer data
, gpointer user_data
)
603 const char *typename
= object_class_get_name(OBJECT_CLASS(data
));
604 int len
= strlen(typename
) - strlen(RISCV_CPU_TYPE_SUFFIX
);
606 qemu_printf("%.*s\n", len
, typename
);
609 void riscv_cpu_list(void)
613 list
= object_class_get_list(TYPE_RISCV_CPU
, false);
614 list
= g_slist_sort(list
, riscv_cpu_list_compare
);
615 g_slist_foreach(list
, riscv_cpu_list_entry
, NULL
);
619 #define DEFINE_CPU(type_name, initfn) \
622 .parent = TYPE_RISCV_CPU, \
623 .instance_init = initfn \
626 static const TypeInfo riscv_cpu_type_infos
[] = {
628 .name
= TYPE_RISCV_CPU
,
630 .instance_size
= sizeof(RISCVCPU
),
631 .instance_align
= __alignof__(RISCVCPU
),
632 .instance_init
= riscv_cpu_init
,
634 .class_size
= sizeof(RISCVCPUClass
),
635 .class_init
= riscv_cpu_class_init
,
637 DEFINE_CPU(TYPE_RISCV_CPU_ANY
, riscv_any_cpu_init
),
638 #if defined(TARGET_RISCV32)
639 DEFINE_CPU(TYPE_RISCV_CPU_BASE32
, riscv_base_cpu_init
),
640 DEFINE_CPU(TYPE_RISCV_CPU_IBEX
, rv32_ibex_cpu_init
),
641 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31
, rvxx_sifive_e_cpu_init
),
642 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34
, rv32_imafcu_nommu_cpu_init
),
643 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34
, rvxx_sifive_u_cpu_init
),
644 #elif defined(TARGET_RISCV64)
645 DEFINE_CPU(TYPE_RISCV_CPU_BASE64
, riscv_base_cpu_init
),
646 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51
, rvxx_sifive_e_cpu_init
),
647 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54
, rvxx_sifive_u_cpu_init
),
651 DEFINE_TYPES(riscv_cpu_type_infos
)