2 * QEMU PowerPC PowerNV CPU Core model
4 * Copyright (c) 2016, IBM Corporation.
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public License
8 * as published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "sysemu/sysemu.h"
21 #include "qapi/error.h"
23 #include "target/ppc/cpu.h"
24 #include "hw/ppc/ppc.h"
25 #include "hw/ppc/pnv.h"
26 #include "hw/ppc/pnv_core.h"
27 #include "hw/ppc/pnv_xscom.h"
28 #include "hw/ppc/xics.h"
30 static const char *pnv_core_cpu_typename(PnvCore
*pc
)
32 const char *core_type
= object_class_get_name(object_get_class(OBJECT(pc
)));
33 int len
= strlen(core_type
) - strlen(PNV_CORE_TYPE_SUFFIX
);
34 char *s
= g_strdup_printf(POWERPC_CPU_TYPE_NAME("%.*s"), len
, core_type
);
35 const char *cpu_type
= object_class_get_name(object_class_by_name(s
));
40 static void pnv_cpu_reset(void *opaque
)
42 PowerPCCPU
*cpu
= opaque
;
43 CPUState
*cs
= CPU(cpu
);
44 CPUPPCState
*env
= &cpu
->env
;
49 * the skiboot firmware elects a primary thread to initialize the
50 * system and it can be any.
52 env
->gpr
[3] = PNV_FDT_ADDR
;
54 env
->msr
|= MSR_HVB
; /* Hypervisor mode */
57 static void pnv_cpu_init(PowerPCCPU
*cpu
, Error
**errp
)
59 CPUPPCState
*env
= &cpu
->env
;
61 int thread_index
= 0; /* TODO: TCG supports only one thread */
62 ppc_spr_t
*pir
= &env
->spr_cb
[SPR_PIR
];
64 core_pir
= object_property_get_uint(OBJECT(cpu
), "core-pir", &error_abort
);
67 * The PIR of a thread is the core PIR + the thread index. We will
68 * need to find a way to get the thread index when TCG supports
69 * more than 1. We could use the object name ?
71 pir
->default_value
= core_pir
+ thread_index
;
73 /* Set time-base frequency to 512 MHz */
74 cpu_ppc_tb_init(env
, PNV_TIMEBASE_FREQ
);
76 qemu_register_reset(pnv_cpu_reset
, cpu
);
80 * These values are read by the PowerNV HW monitors under Linux
82 #define PNV_XSCOM_EX_DTS_RESULT0 0x50000
83 #define PNV_XSCOM_EX_DTS_RESULT1 0x50001
85 static uint64_t pnv_core_xscom_read(void *opaque
, hwaddr addr
,
88 uint32_t offset
= addr
>> 3;
91 /* The result should be 38 C */
93 case PNV_XSCOM_EX_DTS_RESULT0
:
94 val
= 0x26f024f023f0000ull
;
96 case PNV_XSCOM_EX_DTS_RESULT1
:
97 val
= 0x24f000000000000ull
;
100 qemu_log_mask(LOG_UNIMP
, "Warning: reading reg=0x%" HWADDR_PRIx
,
107 static void pnv_core_xscom_write(void *opaque
, hwaddr addr
, uint64_t val
,
110 qemu_log_mask(LOG_UNIMP
, "Warning: writing to reg=0x%" HWADDR_PRIx
,
114 static const MemoryRegionOps pnv_core_xscom_ops
= {
115 .read
= pnv_core_xscom_read
,
116 .write
= pnv_core_xscom_write
,
117 .valid
.min_access_size
= 8,
118 .valid
.max_access_size
= 8,
119 .impl
.min_access_size
= 8,
120 .impl
.max_access_size
= 8,
121 .endianness
= DEVICE_BIG_ENDIAN
,
124 static void pnv_core_realize_child(Object
*child
, XICSFabric
*xi
, Error
**errp
)
126 Error
*local_err
= NULL
;
127 CPUState
*cs
= CPU(child
);
128 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
130 object_property_set_bool(child
, true, "realized", &local_err
);
132 error_propagate(errp
, local_err
);
136 cpu
->intc
= icp_create(child
, TYPE_PNV_ICP
, xi
, &local_err
);
138 error_propagate(errp
, local_err
);
142 pnv_cpu_init(cpu
, &local_err
);
144 error_propagate(errp
, local_err
);
149 static void pnv_core_realize(DeviceState
*dev
, Error
**errp
)
151 PnvCore
*pc
= PNV_CORE(OBJECT(dev
));
152 CPUCore
*cc
= CPU_CORE(OBJECT(dev
));
153 const char *typename
= pnv_core_cpu_typename(pc
);
154 size_t size
= object_type_get_instance_size(typename
);
155 Error
*local_err
= NULL
;
161 xi
= object_property_get_link(OBJECT(dev
), "xics", &local_err
);
163 error_setg(errp
, "%s: required link 'xics' not found: %s",
164 __func__
, error_get_pretty(local_err
));
168 pc
->threads
= g_malloc0(size
* cc
->nr_threads
);
169 for (i
= 0; i
< cc
->nr_threads
; i
++) {
170 obj
= pc
->threads
+ i
* size
;
172 object_initialize(obj
, size
, typename
);
174 snprintf(name
, sizeof(name
), "thread[%d]", i
);
175 object_property_add_child(OBJECT(pc
), name
, obj
, &local_err
);
176 object_property_add_alias(obj
, "core-pir", OBJECT(pc
),
184 for (j
= 0; j
< cc
->nr_threads
; j
++) {
185 obj
= pc
->threads
+ j
* size
;
187 pnv_core_realize_child(obj
, XICS_FABRIC(xi
), &local_err
);
193 snprintf(name
, sizeof(name
), "xscom-core.%d", cc
->core_id
);
194 pnv_xscom_region_init(&pc
->xscom_regs
, OBJECT(dev
), &pnv_core_xscom_ops
,
195 pc
, name
, PNV_XSCOM_EX_CORE_SIZE
);
200 obj
= pc
->threads
+ i
* size
;
201 object_unparent(obj
);
204 error_propagate(errp
, local_err
);
207 static Property pnv_core_properties
[] = {
208 DEFINE_PROP_UINT32("pir", PnvCore
, pir
, 0),
209 DEFINE_PROP_END_OF_LIST(),
212 static void pnv_core_class_init(ObjectClass
*oc
, void *data
)
214 DeviceClass
*dc
= DEVICE_CLASS(oc
);
216 dc
->realize
= pnv_core_realize
;
217 dc
->props
= pnv_core_properties
;
220 #define DEFINE_PNV_CORE_TYPE(cpu_model) \
222 .parent = TYPE_PNV_CORE, \
223 .name = PNV_CORE_TYPE_NAME(cpu_model), \
226 static const TypeInfo pnv_core_infos
[] = {
228 .name
= TYPE_PNV_CORE
,
229 .parent
= TYPE_CPU_CORE
,
230 .instance_size
= sizeof(PnvCore
),
231 .class_size
= sizeof(PnvCoreClass
),
232 .class_init
= pnv_core_class_init
,
235 DEFINE_PNV_CORE_TYPE("power8e_v2.1"),
236 DEFINE_PNV_CORE_TYPE("power8_v2.0"),
237 DEFINE_PNV_CORE_TYPE("power8nvl_v1.0"),
238 DEFINE_PNV_CORE_TYPE("power9_v2.0"),
241 DEFINE_TYPES(pnv_core_infos
)