2 * Arm PrimeCell PL022 Synchronous Serial Port
4 * Copyright (c) 2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
10 #include "qemu/osdep.h"
11 #include "hw/sysbus.h"
12 #include "hw/ssi/ssi.h"
15 //#define DEBUG_PL022 1
18 #define DPRINTF(fmt, ...) \
19 do { printf("pl022: " fmt , ## __VA_ARGS__); } while (0)
20 #define BADF(fmt, ...) \
21 do { fprintf(stderr, "pl022: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
23 #define DPRINTF(fmt, ...) do {} while(0)
24 #define BADF(fmt, ...) \
25 do { fprintf(stderr, "pl022: error: " fmt , ## __VA_ARGS__);} while (0)
28 #define PL022_CR1_LBM 0x01
29 #define PL022_CR1_SSE 0x02
30 #define PL022_CR1_MS 0x04
31 #define PL022_CR1_SDO 0x08
33 #define PL022_SR_TFE 0x01
34 #define PL022_SR_TNF 0x02
35 #define PL022_SR_RNE 0x04
36 #define PL022_SR_RFF 0x08
37 #define PL022_SR_BSY 0x10
39 #define PL022_INT_ROR 0x01
40 #define PL022_INT_RT 0x04
41 #define PL022_INT_RX 0x04
42 #define PL022_INT_TX 0x08
44 #define TYPE_PL022 "pl022"
45 #define PL022(obj) OBJECT_CHECK(PL022State, (obj), TYPE_PL022)
47 typedef struct PL022State
{
48 SysBusDevice parent_obj
;
58 /* The FIFO head points to the next empty entry. */
69 static const unsigned char pl022_id
[8] =
70 { 0x22, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
72 static void pl022_update(PL022State
*s
)
75 if (s
->tx_fifo_len
== 0)
76 s
->sr
|= PL022_SR_TFE
;
77 if (s
->tx_fifo_len
!= 8)
78 s
->sr
|= PL022_SR_TNF
;
79 if (s
->rx_fifo_len
!= 0)
80 s
->sr
|= PL022_SR_RNE
;
81 if (s
->rx_fifo_len
== 8)
82 s
->sr
|= PL022_SR_RFF
;
84 s
->sr
|= PL022_SR_BSY
;
86 if (s
->rx_fifo_len
>= 4)
87 s
->is
|= PL022_INT_RX
;
88 if (s
->tx_fifo_len
<= 4)
89 s
->is
|= PL022_INT_TX
;
91 qemu_set_irq(s
->irq
, (s
->is
& s
->im
) != 0);
94 static void pl022_xfer(PL022State
*s
)
100 if ((s
->cr1
& PL022_CR1_SSE
) == 0) {
102 DPRINTF("Disabled\n");
106 DPRINTF("Maybe xfer %d/%d\n", s
->tx_fifo_len
, s
->rx_fifo_len
);
107 i
= (s
->tx_fifo_head
- s
->tx_fifo_len
) & 7;
109 /* ??? We do not emulate the line speed.
110 This may break some applications. The are two problematic cases:
111 (a) A driver feeds data into the TX FIFO until it is full,
112 and only then drains the RX FIFO. On real hardware the CPU can
113 feed data fast enough that the RX fifo never gets chance to overflow.
114 (b) A driver transmits data, deliberately allowing the RX FIFO to
115 overflow because it ignores the RX data anyway.
117 We choose to support (a) by stalling the transmit engine if it would
118 cause the RX FIFO to overflow. In practice much transmit-only code
119 falls into (a) because it flushes the RX FIFO to determine when
120 the transfer has completed. */
121 while (s
->tx_fifo_len
&& s
->rx_fifo_len
< 8) {
124 if (s
->cr1
& PL022_CR1_LBM
) {
127 val
= ssi_transfer(s
->ssi
, val
);
129 s
->rx_fifo
[o
] = val
& s
->bitmask
;
139 static uint64_t pl022_read(void *opaque
, hwaddr offset
,
142 PL022State
*s
= (PL022State
*)opaque
;
145 if (offset
>= 0xfe0 && offset
< 0x1000) {
146 return pl022_id
[(offset
- 0xfe0) >> 2];
154 if (s
->rx_fifo_len
) {
155 val
= s
->rx_fifo
[(s
->rx_fifo_head
- s
->rx_fifo_len
) & 7];
156 DPRINTF("RX %02x\n", val
);
165 case 0x10: /* CPSR */
167 case 0x14: /* IMSC */
172 return s
->im
& s
->is
;
173 case 0x20: /* DMACR */
174 /* Not implemented. */
177 qemu_log_mask(LOG_GUEST_ERROR
,
178 "pl022_read: Bad offset %x\n", (int)offset
);
183 static void pl022_write(void *opaque
, hwaddr offset
,
184 uint64_t value
, unsigned size
)
186 PL022State
*s
= (PL022State
*)opaque
;
191 /* Clock rate and format are ignored. */
192 s
->bitmask
= (1 << ((value
& 15) + 1)) - 1;
196 if ((s
->cr1
& (PL022_CR1_MS
| PL022_CR1_SSE
))
197 == (PL022_CR1_MS
| PL022_CR1_SSE
)) {
198 BADF("SPI slave mode not implemented\n");
203 if (s
->tx_fifo_len
< 8) {
204 DPRINTF("TX %02x\n", (unsigned)value
);
205 s
->tx_fifo
[s
->tx_fifo_head
] = value
& s
->bitmask
;
206 s
->tx_fifo_head
= (s
->tx_fifo_head
+ 1) & 7;
211 case 0x10: /* CPSR */
212 /* Prescaler. Ignored. */
213 s
->cpsr
= value
& 0xff;
215 case 0x14: /* IMSC */
219 case 0x20: /* DMACR */
221 qemu_log_mask(LOG_UNIMP
, "pl022: DMA not implemented\n");
225 qemu_log_mask(LOG_GUEST_ERROR
,
226 "pl022_write: Bad offset %x\n", (int)offset
);
230 static void pl022_reset(PL022State
*s
)
235 s
->is
= PL022_INT_TX
;
236 s
->sr
= PL022_SR_TFE
| PL022_SR_TNF
;
239 static const MemoryRegionOps pl022_ops
= {
241 .write
= pl022_write
,
242 .endianness
= DEVICE_NATIVE_ENDIAN
,
245 static int pl022_post_load(void *opaque
, int version_id
)
247 PL022State
*s
= opaque
;
249 if (s
->tx_fifo_head
< 0 ||
250 s
->tx_fifo_head
>= ARRAY_SIZE(s
->tx_fifo
) ||
251 s
->rx_fifo_head
< 0 ||
252 s
->rx_fifo_head
>= ARRAY_SIZE(s
->rx_fifo
)) {
258 static const VMStateDescription vmstate_pl022
= {
261 .minimum_version_id
= 1,
262 .post_load
= pl022_post_load
,
263 .fields
= (VMStateField
[]) {
264 VMSTATE_UINT32(cr0
, PL022State
),
265 VMSTATE_UINT32(cr1
, PL022State
),
266 VMSTATE_UINT32(bitmask
, PL022State
),
267 VMSTATE_UINT32(sr
, PL022State
),
268 VMSTATE_UINT32(cpsr
, PL022State
),
269 VMSTATE_UINT32(is
, PL022State
),
270 VMSTATE_UINT32(im
, PL022State
),
271 VMSTATE_INT32(tx_fifo_head
, PL022State
),
272 VMSTATE_INT32(rx_fifo_head
, PL022State
),
273 VMSTATE_INT32(tx_fifo_len
, PL022State
),
274 VMSTATE_INT32(rx_fifo_len
, PL022State
),
275 VMSTATE_UINT16(tx_fifo
[0], PL022State
),
276 VMSTATE_UINT16(rx_fifo
[0], PL022State
),
277 VMSTATE_UINT16(tx_fifo
[1], PL022State
),
278 VMSTATE_UINT16(rx_fifo
[1], PL022State
),
279 VMSTATE_UINT16(tx_fifo
[2], PL022State
),
280 VMSTATE_UINT16(rx_fifo
[2], PL022State
),
281 VMSTATE_UINT16(tx_fifo
[3], PL022State
),
282 VMSTATE_UINT16(rx_fifo
[3], PL022State
),
283 VMSTATE_UINT16(tx_fifo
[4], PL022State
),
284 VMSTATE_UINT16(rx_fifo
[4], PL022State
),
285 VMSTATE_UINT16(tx_fifo
[5], PL022State
),
286 VMSTATE_UINT16(rx_fifo
[5], PL022State
),
287 VMSTATE_UINT16(tx_fifo
[6], PL022State
),
288 VMSTATE_UINT16(rx_fifo
[6], PL022State
),
289 VMSTATE_UINT16(tx_fifo
[7], PL022State
),
290 VMSTATE_UINT16(rx_fifo
[7], PL022State
),
291 VMSTATE_END_OF_LIST()
295 static int pl022_init(SysBusDevice
*sbd
)
297 DeviceState
*dev
= DEVICE(sbd
);
298 PL022State
*s
= PL022(dev
);
300 memory_region_init_io(&s
->iomem
, OBJECT(s
), &pl022_ops
, s
, "pl022", 0x1000);
301 sysbus_init_mmio(sbd
, &s
->iomem
);
302 sysbus_init_irq(sbd
, &s
->irq
);
303 s
->ssi
= ssi_create_bus(dev
, "ssi");
305 vmstate_register(dev
, -1, &vmstate_pl022
, s
);
309 static void pl022_class_init(ObjectClass
*klass
, void *data
)
311 SysBusDeviceClass
*sdc
= SYS_BUS_DEVICE_CLASS(klass
);
313 sdc
->init
= pl022_init
;
316 static const TypeInfo pl022_info
= {
318 .parent
= TYPE_SYS_BUS_DEVICE
,
319 .instance_size
= sizeof(PL022State
),
320 .class_init
= pl022_class_init
,
323 static void pl022_register_types(void)
325 type_register_static(&pl022_info
);
328 type_init(pl022_register_types
)