2 * QEMU PowerPC PowerNV CPU Core model
4 * Copyright (c) 2016, IBM Corporation.
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public License
8 * as published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "sysemu/reset.h"
22 #include "qapi/error.h"
24 #include "qemu/module.h"
25 #include "target/ppc/cpu.h"
26 #include "hw/ppc/ppc.h"
27 #include "hw/ppc/pnv.h"
28 #include "hw/ppc/pnv_core.h"
29 #include "hw/ppc/pnv_xscom.h"
30 #include "hw/ppc/xics.h"
31 #include "hw/qdev-properties.h"
33 static const char *pnv_core_cpu_typename(PnvCore
*pc
)
35 const char *core_type
= object_class_get_name(object_get_class(OBJECT(pc
)));
36 int len
= strlen(core_type
) - strlen(PNV_CORE_TYPE_SUFFIX
);
37 char *s
= g_strdup_printf(POWERPC_CPU_TYPE_NAME("%.*s"), len
, core_type
);
38 const char *cpu_type
= object_class_get_name(object_class_by_name(s
));
43 static void pnv_core_cpu_reset(PnvCore
*pc
, PowerPCCPU
*cpu
)
45 CPUState
*cs
= CPU(cpu
);
46 CPUPPCState
*env
= &cpu
->env
;
47 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(pc
->chip
);
52 * the skiboot firmware elects a primary thread to initialize the
53 * system and it can be any.
55 env
->gpr
[3] = PNV_FDT_ADDR
;
57 env
->msr
|= MSR_HVB
; /* Hypervisor mode */
59 env
->spr
[SPR_HRMOR
] = pc
->hrmor
;
61 pcc
->intc_reset(pc
->chip
, cpu
);
65 * These values are read by the PowerNV HW monitors under Linux
67 #define PNV_XSCOM_EX_DTS_RESULT0 0x50000
68 #define PNV_XSCOM_EX_DTS_RESULT1 0x50001
70 static uint64_t pnv_core_power8_xscom_read(void *opaque
, hwaddr addr
,
73 uint32_t offset
= addr
>> 3;
76 /* The result should be 38 C */
78 case PNV_XSCOM_EX_DTS_RESULT0
:
79 val
= 0x26f024f023f0000ull
;
81 case PNV_XSCOM_EX_DTS_RESULT1
:
82 val
= 0x24f000000000000ull
;
85 qemu_log_mask(LOG_UNIMP
, "Warning: reading reg=0x%" HWADDR_PRIx
"\n",
92 static void pnv_core_power8_xscom_write(void *opaque
, hwaddr addr
, uint64_t val
,
95 qemu_log_mask(LOG_UNIMP
, "Warning: writing to reg=0x%" HWADDR_PRIx
"\n",
99 static const MemoryRegionOps pnv_core_power8_xscom_ops
= {
100 .read
= pnv_core_power8_xscom_read
,
101 .write
= pnv_core_power8_xscom_write
,
102 .valid
.min_access_size
= 8,
103 .valid
.max_access_size
= 8,
104 .impl
.min_access_size
= 8,
105 .impl
.max_access_size
= 8,
106 .endianness
= DEVICE_BIG_ENDIAN
,
111 * POWER9 core controls
113 #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP 0xf010d
114 #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR 0xf010a
116 static uint64_t pnv_core_power9_xscom_read(void *opaque
, hwaddr addr
,
119 uint32_t offset
= addr
>> 3;
122 /* The result should be 38 C */
124 case PNV_XSCOM_EX_DTS_RESULT0
:
125 val
= 0x26f024f023f0000ull
;
127 case PNV_XSCOM_EX_DTS_RESULT1
:
128 val
= 0x24f000000000000ull
;
130 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP
:
131 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR
:
135 qemu_log_mask(LOG_UNIMP
, "Warning: reading reg=0x%" HWADDR_PRIx
"\n",
142 static void pnv_core_power9_xscom_write(void *opaque
, hwaddr addr
, uint64_t val
,
145 uint32_t offset
= addr
>> 3;
148 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP
:
149 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR
:
152 qemu_log_mask(LOG_UNIMP
, "Warning: writing to reg=0x%" HWADDR_PRIx
"\n",
157 static const MemoryRegionOps pnv_core_power9_xscom_ops
= {
158 .read
= pnv_core_power9_xscom_read
,
159 .write
= pnv_core_power9_xscom_write
,
160 .valid
.min_access_size
= 8,
161 .valid
.max_access_size
= 8,
162 .impl
.min_access_size
= 8,
163 .impl
.max_access_size
= 8,
164 .endianness
= DEVICE_BIG_ENDIAN
,
167 static void pnv_core_cpu_realize(PnvCore
*pc
, PowerPCCPU
*cpu
, Error
**errp
)
169 CPUPPCState
*env
= &cpu
->env
;
171 int thread_index
= 0; /* TODO: TCG supports only one thread */
172 ppc_spr_t
*pir
= &env
->spr_cb
[SPR_PIR
];
173 Error
*local_err
= NULL
;
174 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(pc
->chip
);
176 object_property_set_bool(OBJECT(cpu
), true, "realized", &local_err
);
178 error_propagate(errp
, local_err
);
182 pcc
->intc_create(pc
->chip
, cpu
, &local_err
);
184 error_propagate(errp
, local_err
);
188 core_pir
= object_property_get_uint(OBJECT(pc
), "pir", &error_abort
);
191 * The PIR of a thread is the core PIR + the thread index. We will
192 * need to find a way to get the thread index when TCG supports
193 * more than 1. We could use the object name ?
195 pir
->default_value
= core_pir
+ thread_index
;
197 /* Set time-base frequency to 512 MHz */
198 cpu_ppc_tb_init(env
, PNV_TIMEBASE_FREQ
);
201 static void pnv_core_reset(void *dev
)
203 CPUCore
*cc
= CPU_CORE(dev
);
204 PnvCore
*pc
= PNV_CORE(dev
);
207 for (i
= 0; i
< cc
->nr_threads
; i
++) {
208 pnv_core_cpu_reset(pc
, pc
->threads
[i
]);
212 static void pnv_core_realize(DeviceState
*dev
, Error
**errp
)
214 PnvCore
*pc
= PNV_CORE(OBJECT(dev
));
215 PnvCoreClass
*pcc
= PNV_CORE_GET_CLASS(pc
);
216 CPUCore
*cc
= CPU_CORE(OBJECT(dev
));
217 const char *typename
= pnv_core_cpu_typename(pc
);
218 Error
*local_err
= NULL
;
225 pc
->threads
= g_new(PowerPCCPU
*, cc
->nr_threads
);
226 for (i
= 0; i
< cc
->nr_threads
; i
++) {
229 obj
= object_new(typename
);
230 cpu
= POWERPC_CPU(obj
);
232 pc
->threads
[i
] = POWERPC_CPU(obj
);
234 snprintf(name
, sizeof(name
), "thread[%d]", i
);
235 object_property_add_child(OBJECT(pc
), name
, obj
);
237 cpu
->machine_data
= g_new0(PnvCPUState
, 1);
242 for (j
= 0; j
< cc
->nr_threads
; j
++) {
243 pnv_core_cpu_realize(pc
, pc
->threads
[j
], &local_err
);
249 snprintf(name
, sizeof(name
), "xscom-core.%d", cc
->core_id
);
250 /* TODO: check PNV_XSCOM_EX_SIZE for p10 */
251 pnv_xscom_region_init(&pc
->xscom_regs
, OBJECT(dev
), pcc
->xscom_ops
,
252 pc
, name
, PNV_XSCOM_EX_SIZE
);
254 qemu_register_reset(pnv_core_reset
, pc
);
259 obj
= OBJECT(pc
->threads
[i
]);
260 object_unparent(obj
);
263 error_propagate(errp
, local_err
);
266 static void pnv_core_cpu_unrealize(PnvCore
*pc
, PowerPCCPU
*cpu
)
268 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
269 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(pc
->chip
);
271 pcc
->intc_destroy(pc
->chip
, cpu
);
272 cpu_remove_sync(CPU(cpu
));
273 cpu
->machine_data
= NULL
;
275 object_unparent(OBJECT(cpu
));
278 static void pnv_core_unrealize(DeviceState
*dev
)
280 PnvCore
*pc
= PNV_CORE(dev
);
281 CPUCore
*cc
= CPU_CORE(dev
);
284 qemu_unregister_reset(pnv_core_reset
, pc
);
286 for (i
= 0; i
< cc
->nr_threads
; i
++) {
287 pnv_core_cpu_unrealize(pc
, pc
->threads
[i
]);
292 static Property pnv_core_properties
[] = {
293 DEFINE_PROP_UINT32("pir", PnvCore
, pir
, 0),
294 DEFINE_PROP_UINT64("hrmor", PnvCore
, hrmor
, 0),
295 DEFINE_PROP_LINK("chip", PnvCore
, chip
, TYPE_PNV_CHIP
, PnvChip
*),
296 DEFINE_PROP_END_OF_LIST(),
299 static void pnv_core_power8_class_init(ObjectClass
*oc
, void *data
)
301 PnvCoreClass
*pcc
= PNV_CORE_CLASS(oc
);
303 pcc
->xscom_ops
= &pnv_core_power8_xscom_ops
;
306 static void pnv_core_power9_class_init(ObjectClass
*oc
, void *data
)
308 PnvCoreClass
*pcc
= PNV_CORE_CLASS(oc
);
310 pcc
->xscom_ops
= &pnv_core_power9_xscom_ops
;
313 static void pnv_core_power10_class_init(ObjectClass
*oc
, void *data
)
315 PnvCoreClass
*pcc
= PNV_CORE_CLASS(oc
);
317 /* TODO: Use the P9 XSCOMs for now on P10 */
318 pcc
->xscom_ops
= &pnv_core_power9_xscom_ops
;
321 static void pnv_core_class_init(ObjectClass
*oc
, void *data
)
323 DeviceClass
*dc
= DEVICE_CLASS(oc
);
325 dc
->realize
= pnv_core_realize
;
326 dc
->unrealize
= pnv_core_unrealize
;
327 device_class_set_props(dc
, pnv_core_properties
);
328 dc
->user_creatable
= false;
331 #define DEFINE_PNV_CORE_TYPE(family, cpu_model) \
333 .parent = TYPE_PNV_CORE, \
334 .name = PNV_CORE_TYPE_NAME(cpu_model), \
335 .class_init = pnv_core_##family##_class_init, \
338 static const TypeInfo pnv_core_infos
[] = {
340 .name
= TYPE_PNV_CORE
,
341 .parent
= TYPE_CPU_CORE
,
342 .instance_size
= sizeof(PnvCore
),
343 .class_size
= sizeof(PnvCoreClass
),
344 .class_init
= pnv_core_class_init
,
347 DEFINE_PNV_CORE_TYPE(power8
, "power8e_v2.1"),
348 DEFINE_PNV_CORE_TYPE(power8
, "power8_v2.0"),
349 DEFINE_PNV_CORE_TYPE(power8
, "power8nvl_v1.0"),
350 DEFINE_PNV_CORE_TYPE(power9
, "power9_v2.0"),
351 DEFINE_PNV_CORE_TYPE(power10
, "power10_v1.0"),
354 DEFINE_TYPES(pnv_core_infos
)
360 #define P9X_EX_NCU_SPEC_BAR 0x11010
362 static uint64_t pnv_quad_xscom_read(void *opaque
, hwaddr addr
,
365 uint32_t offset
= addr
>> 3;
369 case P9X_EX_NCU_SPEC_BAR
:
370 case P9X_EX_NCU_SPEC_BAR
+ 0x400: /* Second EX */
374 qemu_log_mask(LOG_UNIMP
, "%s: writing @0x%08x\n", __func__
,
381 static void pnv_quad_xscom_write(void *opaque
, hwaddr addr
, uint64_t val
,
384 uint32_t offset
= addr
>> 3;
387 case P9X_EX_NCU_SPEC_BAR
:
388 case P9X_EX_NCU_SPEC_BAR
+ 0x400: /* Second EX */
391 qemu_log_mask(LOG_UNIMP
, "%s: writing @0x%08x\n", __func__
,
396 static const MemoryRegionOps pnv_quad_xscom_ops
= {
397 .read
= pnv_quad_xscom_read
,
398 .write
= pnv_quad_xscom_write
,
399 .valid
.min_access_size
= 8,
400 .valid
.max_access_size
= 8,
401 .impl
.min_access_size
= 8,
402 .impl
.max_access_size
= 8,
403 .endianness
= DEVICE_BIG_ENDIAN
,
406 static void pnv_quad_realize(DeviceState
*dev
, Error
**errp
)
408 PnvQuad
*eq
= PNV_QUAD(dev
);
411 snprintf(name
, sizeof(name
), "xscom-quad.%d", eq
->id
);
412 pnv_xscom_region_init(&eq
->xscom_regs
, OBJECT(dev
), &pnv_quad_xscom_ops
,
413 eq
, name
, PNV9_XSCOM_EQ_SIZE
);
416 static Property pnv_quad_properties
[] = {
417 DEFINE_PROP_UINT32("id", PnvQuad
, id
, 0),
418 DEFINE_PROP_END_OF_LIST(),
421 static void pnv_quad_class_init(ObjectClass
*oc
, void *data
)
423 DeviceClass
*dc
= DEVICE_CLASS(oc
);
425 dc
->realize
= pnv_quad_realize
;
426 device_class_set_props(dc
, pnv_quad_properties
);
427 dc
->user_creatable
= false;
430 static const TypeInfo pnv_quad_info
= {
431 .name
= TYPE_PNV_QUAD
,
432 .parent
= TYPE_DEVICE
,
433 .instance_size
= sizeof(PnvQuad
),
434 .class_init
= pnv_quad_class_init
,
437 static void pnv_core_register_types(void)
439 type_register_static(&pnv_quad_info
);
442 type_init(pnv_core_register_types
)