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target-tricore: Add instructions of RRR1 opcode format, which have 0x43 as first...
[qemu/ar7.git] / target-tricore / translate.c
blob4f13e4f0bd33acb9092439ac0c9129e16dfc4f31
1 /*
2 * TriCore emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2013-2014 Bastian Koppelmann C-Lab/University Paderborn
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "exec/cpu_ldst.h"
25
26 #include "exec/helper-proto.h"
27 #include "exec/helper-gen.h"
28
29 #include "tricore-opcodes.h"
30
31 /*
32 * TCG registers
33 */
34 static TCGv cpu_PC;
35 static TCGv cpu_PCXI;
36 static TCGv cpu_PSW;
37 static TCGv cpu_ICR;
38 /* GPR registers */
39 static TCGv cpu_gpr_a[16];
40 static TCGv cpu_gpr_d[16];
41 /* PSW Flag cache */
42 static TCGv cpu_PSW_C;
43 static TCGv cpu_PSW_V;
44 static TCGv cpu_PSW_SV;
45 static TCGv cpu_PSW_AV;
46 static TCGv cpu_PSW_SAV;
47 /* CPU env */
48 static TCGv_ptr cpu_env;
49
50 #include "exec/gen-icount.h"
51
52 static const char *regnames_a[] = {
53 "a0" , "a1" , "a2" , "a3" , "a4" , "a5" ,
54 "a6" , "a7" , "a8" , "a9" , "sp" , "a11" ,
55 "a12" , "a13" , "a14" , "a15",
56 };
57
58 static const char *regnames_d[] = {
59 "d0" , "d1" , "d2" , "d3" , "d4" , "d5" ,
60 "d6" , "d7" , "d8" , "d9" , "d10" , "d11" ,
61 "d12" , "d13" , "d14" , "d15",
62 };
63
64 typedef struct DisasContext {
65 struct TranslationBlock *tb;
66 target_ulong pc, saved_pc, next_pc;
67 uint32_t opcode;
68 int singlestep_enabled;
69 /* Routine used to access memory */
70 int mem_idx;
71 uint32_t hflags, saved_hflags;
72 int bstate;
73 } DisasContext;
74
75 enum {
76
77 BS_NONE = 0,
78 BS_STOP = 1,
79 BS_BRANCH = 2,
80 BS_EXCP = 3,
81 };
82
83 enum {
84 MODE_LL = 0,
85 MODE_LU = 1,
86 MODE_UL = 2,
87 MODE_UU = 3,
88 };
89
90 void tricore_cpu_dump_state(CPUState *cs, FILE *f,
91 fprintf_function cpu_fprintf, int flags)
92 {
93 TriCoreCPU *cpu = TRICORE_CPU(cs);
94 CPUTriCoreState *env = &cpu->env;
95 uint32_t psw;
96 int i;
97
98 psw = psw_read(env);
99
100 cpu_fprintf(f, "PC: " TARGET_FMT_lx, env->PC);
101 cpu_fprintf(f, " PSW: " TARGET_FMT_lx, psw);
102 cpu_fprintf(f, " ICR: " TARGET_FMT_lx, env->ICR);
103 cpu_fprintf(f, "\nPCXI: " TARGET_FMT_lx, env->PCXI);
104 cpu_fprintf(f, " FCX: " TARGET_FMT_lx, env->FCX);
105 cpu_fprintf(f, " LCX: " TARGET_FMT_lx, env->LCX);
106
107 for (i = 0; i < 16; ++i) {
108 if ((i & 3) == 0) {
109 cpu_fprintf(f, "\nGPR A%02d:", i);
110 }
111 cpu_fprintf(f, " " TARGET_FMT_lx, env->gpr_a[i]);
112 }
113 for (i = 0; i < 16; ++i) {
114 if ((i & 3) == 0) {
115 cpu_fprintf(f, "\nGPR D%02d:", i);
116 }
117 cpu_fprintf(f, " " TARGET_FMT_lx, env->gpr_d[i]);
118 }
119 cpu_fprintf(f, "\n");
120 }
121
122 /*
123 * Functions to generate micro-ops
124 */
125
126 /* Makros for generating helpers */
127
128 #define gen_helper_1arg(name, arg) do { \
129 TCGv_i32 helper_tmp = tcg_const_i32(arg); \
130 gen_helper_##name(cpu_env, helper_tmp); \
131 tcg_temp_free_i32(helper_tmp); \
132 } while (0)
133
134 #define GEN_HELPER_LL(name, ret, arg0, arg1, n) do { \
135 TCGv arg00 = tcg_temp_new(); \
136 TCGv arg01 = tcg_temp_new(); \
137 TCGv arg11 = tcg_temp_new(); \
138 tcg_gen_sari_tl(arg00, arg0, 16); \
139 tcg_gen_ext16s_tl(arg01, arg0); \
140 tcg_gen_ext16s_tl(arg11, arg1); \
141 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \
142 tcg_temp_free(arg00); \
143 tcg_temp_free(arg01); \
144 tcg_temp_free(arg11); \
145 } while (0)
146
147 #define GEN_HELPER_LU(name, ret, arg0, arg1, n) do { \
148 TCGv arg00 = tcg_temp_new(); \
149 TCGv arg01 = tcg_temp_new(); \
150 TCGv arg10 = tcg_temp_new(); \
151 TCGv arg11 = tcg_temp_new(); \
152 tcg_gen_sari_tl(arg00, arg0, 16); \
153 tcg_gen_ext16s_tl(arg01, arg0); \
154 tcg_gen_sari_tl(arg11, arg1, 16); \
155 tcg_gen_ext16s_tl(arg10, arg1); \
156 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \
157 tcg_temp_free(arg00); \
158 tcg_temp_free(arg01); \
159 tcg_temp_free(arg10); \
160 tcg_temp_free(arg11); \
161 } while (0)
162
163 #define GEN_HELPER_UL(name, ret, arg0, arg1, n) do { \
164 TCGv arg00 = tcg_temp_new(); \
165 TCGv arg01 = tcg_temp_new(); \
166 TCGv arg10 = tcg_temp_new(); \
167 TCGv arg11 = tcg_temp_new(); \
168 tcg_gen_sari_tl(arg00, arg0, 16); \
169 tcg_gen_ext16s_tl(arg01, arg0); \
170 tcg_gen_sari_tl(arg10, arg1, 16); \
171 tcg_gen_ext16s_tl(arg11, arg1); \
172 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \
173 tcg_temp_free(arg00); \
174 tcg_temp_free(arg01); \
175 tcg_temp_free(arg10); \
176 tcg_temp_free(arg11); \
177 } while (0)
178
179 #define GEN_HELPER_UU(name, ret, arg0, arg1, n) do { \
180 TCGv arg00 = tcg_temp_new(); \
181 TCGv arg01 = tcg_temp_new(); \
182 TCGv arg11 = tcg_temp_new(); \
183 tcg_gen_sari_tl(arg01, arg0, 16); \
184 tcg_gen_ext16s_tl(arg00, arg0); \
185 tcg_gen_sari_tl(arg11, arg1, 16); \
186 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \
187 tcg_temp_free(arg00); \
188 tcg_temp_free(arg01); \
189 tcg_temp_free(arg11); \
190 } while (0)
191
192 #define GEN_HELPER_RRR(name, rl, rh, al1, ah1, arg2) do { \
193 TCGv_i64 ret = tcg_temp_new_i64(); \
194 TCGv_i64 arg1 = tcg_temp_new_i64(); \
195 \
196 tcg_gen_concat_i32_i64(arg1, al1, ah1); \
197 gen_helper_##name(ret, arg1, arg2); \
198 tcg_gen_extr_i64_i32(rl, rh, ret); \
199 \
200 tcg_temp_free_i64(ret); \
201 tcg_temp_free_i64(arg1); \
202 } while (0)
203
204 #define EA_ABS_FORMAT(con) (((con & 0x3C000) << 14) + (con & 0x3FFF))
205 #define EA_B_ABSOLUT(con) (((offset & 0xf00000) << 8) | \
206 ((offset & 0x0fffff) << 1))
207
208 /* Functions for load/save to/from memory */
209
210 static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2,
211 int16_t con, TCGMemOp mop)
212 {
213 TCGv temp = tcg_temp_new();
214 tcg_gen_addi_tl(temp, r2, con);
215 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop);
216 tcg_temp_free(temp);
217 }
218
219 static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2,
220 int16_t con, TCGMemOp mop)
221 {
222 TCGv temp = tcg_temp_new();
223 tcg_gen_addi_tl(temp, r2, con);
224 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop);
225 tcg_temp_free(temp);
226 }
227
228 static void gen_st_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
229 {
230 TCGv_i64 temp = tcg_temp_new_i64();
231
232 tcg_gen_concat_i32_i64(temp, rl, rh);
233 tcg_gen_qemu_st_i64(temp, address, ctx->mem_idx, MO_LEQ);
234
235 tcg_temp_free_i64(temp);
236 }
237
238 static void gen_offset_st_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con,
239 DisasContext *ctx)
240 {
241 TCGv temp = tcg_temp_new();
242 tcg_gen_addi_tl(temp, base, con);
243 gen_st_2regs_64(rh, rl, temp, ctx);
244 tcg_temp_free(temp);
245 }
246
247 static void gen_ld_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
248 {
249 TCGv_i64 temp = tcg_temp_new_i64();
250
251 tcg_gen_qemu_ld_i64(temp, address, ctx->mem_idx, MO_LEQ);
252 /* write back to two 32 bit regs */
253 tcg_gen_extr_i64_i32(rl, rh, temp);
254
255 tcg_temp_free_i64(temp);
256 }
257
258 static void gen_offset_ld_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con,
259 DisasContext *ctx)
260 {
261 TCGv temp = tcg_temp_new();
262 tcg_gen_addi_tl(temp, base, con);
263 gen_ld_2regs_64(rh, rl, temp, ctx);
264 tcg_temp_free(temp);
265 }
266
267 static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,
268 TCGMemOp mop)
269 {
270 TCGv temp = tcg_temp_new();
271 tcg_gen_addi_tl(temp, r2, off);
272 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop);
273 tcg_gen_mov_tl(r2, temp);
274 tcg_temp_free(temp);
275 }
276
277 static void gen_ld_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,
278 TCGMemOp mop)
279 {
280 TCGv temp = tcg_temp_new();
281 tcg_gen_addi_tl(temp, r2, off);
282 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop);
283 tcg_gen_mov_tl(r2, temp);
284 tcg_temp_free(temp);
285 }
286
287 /* M(EA, word) = (M(EA, word) & ~E[a][63:32]) | (E[a][31:0] & E[a][63:32]); */
288 static void gen_ldmst(DisasContext *ctx, int ereg, TCGv ea)
289 {
290 TCGv temp = tcg_temp_new();
291 TCGv temp2 = tcg_temp_new();
292
293 /* temp = (M(EA, word) */
294 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
295 /* temp = temp & ~E[a][63:32]) */
296 tcg_gen_andc_tl(temp, temp, cpu_gpr_d[ereg+1]);
297 /* temp2 = (E[a][31:0] & E[a][63:32]); */
298 tcg_gen_and_tl(temp2, cpu_gpr_d[ereg], cpu_gpr_d[ereg+1]);
299 /* temp = temp | temp2; */
300 tcg_gen_or_tl(temp, temp, temp2);
301 /* M(EA, word) = temp; */
302 tcg_gen_qemu_st_tl(temp, ea, ctx->mem_idx, MO_LEUL);
303
304 tcg_temp_free(temp);
305 tcg_temp_free(temp2);
306 }
307
308 /* tmp = M(EA, word);
309 M(EA, word) = D[a];
310 D[a] = tmp[31:0];*/
311 static void gen_swap(DisasContext *ctx, int reg, TCGv ea)
312 {
313 TCGv temp = tcg_temp_new();
314
315 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
316 tcg_gen_qemu_st_tl(cpu_gpr_d[reg], ea, ctx->mem_idx, MO_LEUL);
317 tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
318
319 tcg_temp_free(temp);
320 }
321
322 /* We generate loads and store to core special function register (csfr) through
323 the function gen_mfcr and gen_mtcr. To handle access permissions, we use 3
324 makros R, A and E, which allow read-only, all and endinit protected access.
325 These makros also specify in which ISA version the csfr was introduced. */
326 #define R(ADDRESS, REG, FEATURE) \
327 case ADDRESS: \
328 if (tricore_feature(env, FEATURE)) { \
329 tcg_gen_ld_tl(ret, cpu_env, offsetof(CPUTriCoreState, REG)); \
330 } \
331 break;
332 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)
333 #define E(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)
334 static inline void gen_mfcr(CPUTriCoreState *env, TCGv ret, int32_t offset)
335 {
336 /* since we're caching PSW make this a special case */
337 if (offset == 0xfe04) {
338 gen_helper_psw_read(ret, cpu_env);
339 } else {
340 switch (offset) {
341 #include "csfr.def"
342 }
343 }
344 }
345 #undef R
346 #undef A
347 #undef E
348
349 #define R(ADDRESS, REG, FEATURE) /* don't gen writes to read-only reg,
350 since no execption occurs */
351 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) \
352 case ADDRESS: \
353 if (tricore_feature(env, FEATURE)) { \
354 tcg_gen_st_tl(r1, cpu_env, offsetof(CPUTriCoreState, REG)); \
355 } \
356 break;
357 /* Endinit protected registers
358 TODO: Since the endinit bit is in a register of a not yet implemented
359 watchdog device, we handle endinit protected registers like
360 all-access registers for now. */
361 #define E(ADDRESS, REG, FEATURE) A(ADDRESS, REG, FEATURE)
362 static inline void gen_mtcr(CPUTriCoreState *env, DisasContext *ctx, TCGv r1,
363 int32_t offset)
364 {
365 if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) {
366 /* since we're caching PSW make this a special case */
367 if (offset == 0xfe04) {
368 gen_helper_psw_write(cpu_env, r1);
369 } else {
370 switch (offset) {
371 #include "csfr.def"
372 }
373 }
374 } else {
375 /* generate privilege trap */
376 }
377 }
378
379 /* Functions for arithmetic instructions */
380
381 static inline void gen_add_d(TCGv ret, TCGv r1, TCGv r2)
382 {
383 TCGv t0 = tcg_temp_new_i32();
384 TCGv result = tcg_temp_new_i32();
385 /* Addition and set V/SV bits */
386 tcg_gen_add_tl(result, r1, r2);
387 /* calc V bit */
388 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
389 tcg_gen_xor_tl(t0, r1, r2);
390 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
391 /* Calc SV bit */
392 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
393 /* Calc AV/SAV bits */
394 tcg_gen_add_tl(cpu_PSW_AV, result, result);
395 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
396 /* calc SAV */
397 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
398 /* write back result */
399 tcg_gen_mov_tl(ret, result);
400
401 tcg_temp_free(result);
402 tcg_temp_free(t0);
403 }
404
405 static inline void
406 gen_add64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2)
407 {
408 TCGv temp = tcg_temp_new();
409 TCGv_i64 t0 = tcg_temp_new_i64();
410 TCGv_i64 t1 = tcg_temp_new_i64();
411 TCGv_i64 result = tcg_temp_new_i64();
412
413 tcg_gen_add_i64(result, r1, r2);
414 /* calc v bit */
415 tcg_gen_xor_i64(t1, result, r1);
416 tcg_gen_xor_i64(t0, r1, r2);
417 tcg_gen_andc_i64(t1, t1, t0);
418 tcg_gen_trunc_shr_i64_i32(cpu_PSW_V, t1, 32);
419 /* calc SV bit */
420 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
421 /* calc AV/SAV bits */
422 tcg_gen_trunc_shr_i64_i32(temp, result, 32);
423 tcg_gen_add_tl(cpu_PSW_AV, temp, temp);
424 tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV);
425 /* calc SAV */
426 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
427 /* write back result */
428 tcg_gen_mov_i64(ret, result);
429
430 tcg_temp_free(temp);
431 tcg_temp_free_i64(result);
432 tcg_temp_free_i64(t0);
433 tcg_temp_free_i64(t1);
434 }
435
436 static inline void
437 gen_addsub64_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
438 TCGv r3, void(*op1)(TCGv, TCGv, TCGv),
439 void(*op2)(TCGv, TCGv, TCGv))
440 {
441 TCGv temp = tcg_temp_new();
442 TCGv temp2 = tcg_temp_new();
443 TCGv temp3 = tcg_temp_new();
444 TCGv temp4 = tcg_temp_new();
445
446 (*op1)(temp, r1_low, r2);
447 /* calc V0 bit */
448 tcg_gen_xor_tl(temp2, temp, r1_low);
449 tcg_gen_xor_tl(temp3, r1_low, r2);
450 if (op1 == tcg_gen_add_tl) {
451 tcg_gen_andc_tl(temp2, temp2, temp3);
452 } else {
453 tcg_gen_and_tl(temp2, temp2, temp3);
454 }
455
456 (*op2)(temp3, r1_high, r3);
457 /* calc V1 bit */
458 tcg_gen_xor_tl(cpu_PSW_V, temp3, r1_high);
459 tcg_gen_xor_tl(temp4, r1_high, r3);
460 if (op2 == tcg_gen_add_tl) {
461 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, temp4);
462 } else {
463 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp4);
464 }
465 /* combine V0/V1 bits */
466 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp2);
467 /* calc sv bit */
468 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
469 /* write result */
470 tcg_gen_mov_tl(ret_low, temp);
471 tcg_gen_mov_tl(ret_high, temp3);
472 /* calc AV bit */
473 tcg_gen_add_tl(temp, ret_low, ret_low);
474 tcg_gen_xor_tl(temp, temp, ret_low);
475 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
476 tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, ret_high);
477 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp);
478 /* calc SAV bit */
479 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
480
481 tcg_temp_free(temp);
482 tcg_temp_free(temp2);
483 tcg_temp_free(temp3);
484 tcg_temp_free(temp4);
485 }
486
487 /* ret = r2 + (r1 * r3); */
488 static inline void gen_madd32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3)
489 {
490 TCGv_i64 t1 = tcg_temp_new_i64();
491 TCGv_i64 t2 = tcg_temp_new_i64();
492 TCGv_i64 t3 = tcg_temp_new_i64();
493
494 tcg_gen_ext_i32_i64(t1, r1);
495 tcg_gen_ext_i32_i64(t2, r2);
496 tcg_gen_ext_i32_i64(t3, r3);
497
498 tcg_gen_mul_i64(t1, t1, t3);
499 tcg_gen_add_i64(t1, t2, t1);
500
501 tcg_gen_trunc_i64_i32(ret, t1);
502 /* calc V
503 t1 > 0x7fffffff */
504 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL);
505 /* t1 < -0x80000000 */
506 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL);
507 tcg_gen_or_i64(t2, t2, t3);
508 tcg_gen_trunc_i64_i32(cpu_PSW_V, t2);
509 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
510 /* Calc SV bit */
511 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
512 /* Calc AV/SAV bits */
513 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
514 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
515 /* calc SAV */
516 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
517
518 tcg_temp_free_i64(t1);
519 tcg_temp_free_i64(t2);
520 tcg_temp_free_i64(t3);
521 }
522
523 static inline void gen_maddi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con)
524 {
525 TCGv temp = tcg_const_i32(con);
526 gen_madd32_d(ret, r1, r2, temp);
527 tcg_temp_free(temp);
528 }
529
530 static inline void
531 gen_madd64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
532 TCGv r3)
533 {
534 TCGv t1 = tcg_temp_new();
535 TCGv t2 = tcg_temp_new();
536 TCGv t3 = tcg_temp_new();
537 TCGv t4 = tcg_temp_new();
538
539 tcg_gen_muls2_tl(t1, t2, r1, r3);
540 /* only the add can overflow */
541 tcg_gen_add2_tl(t3, t4, r2_low, r2_high, t1, t2);
542 /* calc V bit */
543 tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high);
544 tcg_gen_xor_tl(t1, r2_high, t2);
545 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t1);
546 /* Calc SV bit */
547 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
548 /* Calc AV/SAV bits */
549 tcg_gen_add_tl(cpu_PSW_AV, t4, t4);
550 tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV);
551 /* calc SAV */
552 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
553 /* write back the result */
554 tcg_gen_mov_tl(ret_low, t3);
555 tcg_gen_mov_tl(ret_high, t4);
556
557 tcg_temp_free(t1);
558 tcg_temp_free(t2);
559 tcg_temp_free(t3);
560 tcg_temp_free(t4);
561 }
562
563 static inline void
564 gen_maddu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
565 TCGv r3)
566 {
567 TCGv_i64 t1 = tcg_temp_new_i64();
568 TCGv_i64 t2 = tcg_temp_new_i64();
569 TCGv_i64 t3 = tcg_temp_new_i64();
570
571 tcg_gen_extu_i32_i64(t1, r1);
572 tcg_gen_concat_i32_i64(t2, r2_low, r2_high);
573 tcg_gen_extu_i32_i64(t3, r3);
574
575 tcg_gen_mul_i64(t1, t1, t3);
576 tcg_gen_add_i64(t2, t2, t1);
577 /* write back result */
578 tcg_gen_extr_i64_i32(ret_low, ret_high, t2);
579 /* only the add overflows, if t2 < t1
580 calc V bit */
581 tcg_gen_setcond_i64(TCG_COND_LTU, t2, t2, t1);
582 tcg_gen_trunc_i64_i32(cpu_PSW_V, t2);
583 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
584 /* Calc SV bit */
585 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
586 /* Calc AV/SAV bits */
587 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
588 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
589 /* calc SAV */
590 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
591
592 tcg_temp_free_i64(t1);
593 tcg_temp_free_i64(t2);
594 tcg_temp_free_i64(t3);
595 }
596
597 static inline void
598 gen_maddi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
599 int32_t con)
600 {
601 TCGv temp = tcg_const_i32(con);
602 gen_madd64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
603 tcg_temp_free(temp);
604 }
605
606 static inline void
607 gen_maddui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
608 int32_t con)
609 {
610 TCGv temp = tcg_const_i32(con);
611 gen_maddu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
612 tcg_temp_free(temp);
613 }
614
615 static inline void
616 gen_madd_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
617 TCGv r3, uint32_t n, uint32_t mode)
618 {
619 TCGv temp = tcg_const_i32(n);
620 TCGv temp2 = tcg_temp_new();
621 TCGv_i64 temp64 = tcg_temp_new_i64();
622 switch (mode) {
623 case MODE_LL:
624 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
625 break;
626 case MODE_LU:
627 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
628 break;
629 case MODE_UL:
630 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
631 break;
632 case MODE_UU:
633 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
634 break;
635 }
636 tcg_gen_extr_i64_i32(temp, temp2, temp64);
637 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
638 tcg_gen_add_tl, tcg_gen_add_tl);
639 tcg_temp_free(temp);
640 tcg_temp_free(temp2);
641 tcg_temp_free_i64(temp64);
642 }
643
644 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2);
645
646 static inline void
647 gen_madds_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
648 TCGv r3, uint32_t n, uint32_t mode)
649 {
650 TCGv temp = tcg_const_i32(n);
651 TCGv temp2 = tcg_temp_new();
652 TCGv temp3 = tcg_temp_new();
653 TCGv_i64 temp64 = tcg_temp_new_i64();
654
655 switch (mode) {
656 case MODE_LL:
657 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
658 break;
659 case MODE_LU:
660 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
661 break;
662 case MODE_UL:
663 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
664 break;
665 case MODE_UU:
666 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
667 break;
668 }
669 tcg_gen_extr_i64_i32(temp, temp2, temp64);
670 gen_adds(ret_low, r1_low, temp);
671 tcg_gen_mov_tl(temp, cpu_PSW_V);
672 tcg_gen_mov_tl(temp3, cpu_PSW_AV);
673 gen_adds(ret_high, r1_high, temp2);
674 /* combine v bits */
675 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
676 /* combine av bits */
677 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
678
679 tcg_temp_free(temp);
680 tcg_temp_free(temp2);
681 tcg_temp_free(temp3);
682 tcg_temp_free_i64(temp64);
683
684 }
685
686 static inline void
687 gen_maddm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
688 TCGv r3, uint32_t n, uint32_t mode)
689 {
690 TCGv temp = tcg_const_i32(n);
691 TCGv_i64 temp64 = tcg_temp_new_i64();
692 TCGv_i64 temp64_2 = tcg_temp_new_i64();
693 TCGv_i64 temp64_3 = tcg_temp_new_i64();
694 switch (mode) {
695 case MODE_LL:
696 GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp);
697 break;
698 case MODE_LU:
699 GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp);
700 break;
701 case MODE_UL:
702 GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp);
703 break;
704 case MODE_UU:
705 GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp);
706 break;
707 }
708 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
709 gen_add64_d(temp64_3, temp64_2, temp64);
710 /* write back result */
711 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3);
712
713 tcg_temp_free(temp);
714 tcg_temp_free_i64(temp64);
715 tcg_temp_free_i64(temp64_2);
716 tcg_temp_free_i64(temp64_3);
717 }
718
719 static inline void
720 gen_maddms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
721 TCGv r3, uint32_t n, uint32_t mode)
722 {
723 TCGv temp = tcg_const_i32(n);
724 TCGv_i64 temp64 = tcg_temp_new_i64();
725 TCGv_i64 temp64_2 = tcg_temp_new_i64();
726 switch (mode) {
727 case MODE_LL:
728 GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp);
729 break;
730 case MODE_LU:
731 GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp);
732 break;
733 case MODE_UL:
734 GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp);
735 break;
736 case MODE_UU:
737 GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp);
738 break;
739 }
740 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
741 gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64);
742 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
743
744 tcg_temp_free(temp);
745 tcg_temp_free_i64(temp64);
746 tcg_temp_free_i64(temp64_2);
747 }
748
749 static inline void
750 gen_maddr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n,
751 uint32_t mode)
752 {
753 TCGv temp = tcg_const_i32(n);
754 TCGv_i64 temp64 = tcg_temp_new_i64();
755 switch (mode) {
756 case MODE_LL:
757 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
758 break;
759 case MODE_LU:
760 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
761 break;
762 case MODE_UL:
763 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
764 break;
765 case MODE_UU:
766 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
767 break;
768 }
769 gen_helper_addr_h(ret, cpu_env, temp64, r1_low, r1_high);
770
771 tcg_temp_free(temp);
772 tcg_temp_free_i64(temp64);
773 }
774
775 static inline void
776 gen_maddr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
777 {
778 TCGv temp = tcg_temp_new();
779 TCGv temp2 = tcg_temp_new();
780
781 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
782 tcg_gen_shli_tl(temp, r1, 16);
783 gen_maddr64_h(ret, temp, temp2, r2, r3, n, mode);
784
785 tcg_temp_free(temp);
786 tcg_temp_free(temp2);
787 }
788
789 static inline void
790 gen_maddr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3,
791 uint32_t n, uint32_t mode)
792 {
793 TCGv temp = tcg_const_i32(n);
794 TCGv_i64 temp64 = tcg_temp_new_i64();
795 switch (mode) {
796 case MODE_LL:
797 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
798 break;
799 case MODE_LU:
800 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
801 break;
802 case MODE_UL:
803 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
804 break;
805 case MODE_UU:
806 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
807 break;
808 }
809 gen_helper_addr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high);
810
811 tcg_temp_free(temp);
812 tcg_temp_free_i64(temp64);
813 }
814
815 static inline void
816 gen_maddr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
817 {
818 TCGv temp = tcg_temp_new();
819 TCGv temp2 = tcg_temp_new();
820
821 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
822 tcg_gen_shli_tl(temp, r1, 16);
823 gen_maddr64s_h(ret, temp, temp2, r2, r3, n, mode);
824
825 tcg_temp_free(temp);
826 tcg_temp_free(temp2);
827 }
828
829 static inline void
830 gen_maddr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
831 {
832 TCGv temp = tcg_const_i32(n);
833 gen_helper_maddr_q(ret, cpu_env, r1, r2, r3, temp);
834 tcg_temp_free(temp);
835 }
836
837 static inline void
838 gen_maddrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
839 {
840 TCGv temp = tcg_const_i32(n);
841 gen_helper_maddr_q_ssov(ret, cpu_env, r1, r2, r3, temp);
842 tcg_temp_free(temp);
843 }
844
845 static inline void
846 gen_madd32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
847 uint32_t up_shift, CPUTriCoreState *env)
848 {
849 TCGv temp = tcg_temp_new();
850 TCGv temp2 = tcg_temp_new();
851 TCGv temp3 = tcg_temp_new();
852 TCGv_i64 t1 = tcg_temp_new_i64();
853 TCGv_i64 t2 = tcg_temp_new_i64();
854 TCGv_i64 t3 = tcg_temp_new_i64();
855
856 tcg_gen_ext_i32_i64(t2, arg2);
857 tcg_gen_ext_i32_i64(t3, arg3);
858
859 tcg_gen_mul_i64(t2, t2, t3);
860 tcg_gen_shli_i64(t2, t2, n);
861
862 tcg_gen_ext_i32_i64(t1, arg1);
863 tcg_gen_sari_i64(t2, t2, up_shift);
864
865 tcg_gen_add_i64(t3, t1, t2);
866 tcg_gen_trunc_i64_i32(temp3, t3);
867 /* calc v bit */
868 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL);
869 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL);
870 tcg_gen_or_i64(t1, t1, t2);
871 tcg_gen_trunc_i64_i32(cpu_PSW_V, t1);
872 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
873 /* We produce an overflow on the host if the mul before was
874 (0x80000000 * 0x80000000) << 1). If this is the
875 case, we negate the ovf. */
876 if (n == 1) {
877 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000);
878 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3);
879 tcg_gen_and_tl(temp, temp, temp2);
880 tcg_gen_shli_tl(temp, temp, 31);
881 /* negate v bit, if special condition */
882 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp);
883 }
884 /* Calc SV bit */
885 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
886 /* Calc AV/SAV bits */
887 tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3);
888 tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV);
889 /* calc SAV */
890 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
891 /* write back result */
892 tcg_gen_mov_tl(ret, temp3);
893
894 tcg_temp_free(temp);
895 tcg_temp_free(temp2);
896 tcg_temp_free(temp3);
897 tcg_temp_free_i64(t1);
898 tcg_temp_free_i64(t2);
899 tcg_temp_free_i64(t3);
900 }
901
902 static inline void
903 gen_m16add32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
904 {
905 TCGv temp = tcg_temp_new();
906 TCGv temp2 = tcg_temp_new();
907 if (n == 0) {
908 tcg_gen_mul_tl(temp, arg2, arg3);
909 } else { /* n is exspected to be 1 */
910 tcg_gen_mul_tl(temp, arg2, arg3);
911 tcg_gen_shli_tl(temp, temp, 1);
912 /* catch special case r1 = r2 = 0x8000 */
913 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
914 tcg_gen_sub_tl(temp, temp, temp2);
915 }
916 gen_add_d(ret, arg1, temp);
917
918 tcg_temp_free(temp);
919 tcg_temp_free(temp2);
920 }
921
922 static inline void
923 gen_m16adds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
924 {
925 TCGv temp = tcg_temp_new();
926 TCGv temp2 = tcg_temp_new();
927 if (n == 0) {
928 tcg_gen_mul_tl(temp, arg2, arg3);
929 } else { /* n is exspected to be 1 */
930 tcg_gen_mul_tl(temp, arg2, arg3);
931 tcg_gen_shli_tl(temp, temp, 1);
932 /* catch special case r1 = r2 = 0x8000 */
933 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
934 tcg_gen_sub_tl(temp, temp, temp2);
935 }
936 gen_adds(ret, arg1, temp);
937
938 tcg_temp_free(temp);
939 tcg_temp_free(temp2);
940 }
941
942 static inline void
943 gen_m16add64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
944 TCGv arg3, uint32_t n)
945 {
946 TCGv temp = tcg_temp_new();
947 TCGv temp2 = tcg_temp_new();
948 TCGv_i64 t1 = tcg_temp_new_i64();
949 TCGv_i64 t2 = tcg_temp_new_i64();
950 TCGv_i64 t3 = tcg_temp_new_i64();
951
952 if (n == 0) {
953 tcg_gen_mul_tl(temp, arg2, arg3);
954 } else { /* n is exspected to be 1 */
955 tcg_gen_mul_tl(temp, arg2, arg3);
956 tcg_gen_shli_tl(temp, temp, 1);
957 /* catch special case r1 = r2 = 0x8000 */
958 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
959 tcg_gen_sub_tl(temp, temp, temp2);
960 }
961 tcg_gen_ext_i32_i64(t2, temp);
962 tcg_gen_shli_i64(t2, t2, 16);
963 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
964 gen_add64_d(t3, t1, t2);
965 /* write back result */
966 tcg_gen_extr_i64_i32(rl, rh, t3);
967
968 tcg_temp_free_i64(t1);
969 tcg_temp_free_i64(t2);
970 tcg_temp_free_i64(t3);
971 tcg_temp_free(temp);
972 tcg_temp_free(temp2);
973 }
974
975 static inline void
976 gen_m16adds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
977 TCGv arg3, uint32_t n)
978 {
979 TCGv temp = tcg_temp_new();
980 TCGv temp2 = tcg_temp_new();
981 TCGv_i64 t1 = tcg_temp_new_i64();
982 TCGv_i64 t2 = tcg_temp_new_i64();
983
984 if (n == 0) {
985 tcg_gen_mul_tl(temp, arg2, arg3);
986 } else { /* n is exspected to be 1 */
987 tcg_gen_mul_tl(temp, arg2, arg3);
988 tcg_gen_shli_tl(temp, temp, 1);
989 /* catch special case r1 = r2 = 0x8000 */
990 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
991 tcg_gen_sub_tl(temp, temp, temp2);
992 }
993 tcg_gen_ext_i32_i64(t2, temp);
994 tcg_gen_shli_i64(t2, t2, 16);
995 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
996
997 gen_helper_add64_ssov(t1, cpu_env, t1, t2);
998 tcg_gen_extr_i64_i32(rl, rh, t1);
999
1000 tcg_temp_free(temp);
1001 tcg_temp_free(temp2);
1002 tcg_temp_free_i64(t1);
1003 tcg_temp_free_i64(t2);
1004 }
1005
1006 static inline void
1007 gen_madd64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1008 TCGv arg3, uint32_t n, CPUTriCoreState *env)
1009 {
1010 TCGv_i64 t1 = tcg_temp_new_i64();
1011 TCGv_i64 t2 = tcg_temp_new_i64();
1012 TCGv_i64 t3 = tcg_temp_new_i64();
1013 TCGv_i64 t4 = tcg_temp_new_i64();
1014 TCGv temp, temp2;
1015
1016 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1017 tcg_gen_ext_i32_i64(t2, arg2);
1018 tcg_gen_ext_i32_i64(t3, arg3);
1019
1020 tcg_gen_mul_i64(t2, t2, t3);
1021 if (n != 0) {
1022 tcg_gen_shli_i64(t2, t2, 1);
1023 }
1024 tcg_gen_add_i64(t4, t1, t2);
1025 /* calc v bit */
1026 tcg_gen_xor_i64(t3, t4, t1);
1027 tcg_gen_xor_i64(t2, t1, t2);
1028 tcg_gen_andc_i64(t3, t3, t2);
1029 tcg_gen_trunc_shr_i64_i32(cpu_PSW_V, t3, 32);
1030 /* We produce an overflow on the host if the mul before was
1031 (0x80000000 * 0x80000000) << 1). If this is the
1032 case, we negate the ovf. */
1033 if (n == 1) {
1034 temp = tcg_temp_new();
1035 temp2 = tcg_temp_new();
1036 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000);
1037 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3);
1038 tcg_gen_and_tl(temp, temp, temp2);
1039 tcg_gen_shli_tl(temp, temp, 31);
1040 /* negate v bit, if special condition */
1041 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp);
1042
1043 tcg_temp_free(temp);
1044 tcg_temp_free(temp2);
1045 }
1046 /* write back result */
1047 tcg_gen_extr_i64_i32(rl, rh, t4);
1048 /* Calc SV bit */
1049 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1050 /* Calc AV/SAV bits */
1051 tcg_gen_add_tl(cpu_PSW_AV, rh, rh);
1052 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV);
1053 /* calc SAV */
1054 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1055
1056 tcg_temp_free_i64(t1);
1057 tcg_temp_free_i64(t2);
1058 tcg_temp_free_i64(t3);
1059 tcg_temp_free_i64(t4);
1060 }
1061
1062 static inline void
1063 gen_madds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
1064 uint32_t up_shift)
1065 {
1066 TCGv_i64 t1 = tcg_temp_new_i64();
1067 TCGv_i64 t2 = tcg_temp_new_i64();
1068 TCGv_i64 t3 = tcg_temp_new_i64();
1069
1070 tcg_gen_ext_i32_i64(t1, arg1);
1071 tcg_gen_ext_i32_i64(t2, arg2);
1072 tcg_gen_ext_i32_i64(t3, arg3);
1073
1074 tcg_gen_mul_i64(t2, t2, t3);
1075 tcg_gen_sari_i64(t2, t2, up_shift - n);
1076
1077 gen_helper_madd32_q_add_ssov(ret, cpu_env, t1, t2);
1078
1079 tcg_temp_free_i64(t1);
1080 tcg_temp_free_i64(t2);
1081 tcg_temp_free_i64(t3);
1082 }
1083
1084 static inline void
1085 gen_madds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1086 TCGv arg3, uint32_t n)
1087 {
1088 TCGv_i64 r1 = tcg_temp_new_i64();
1089 TCGv temp = tcg_const_i32(n);
1090
1091 tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high);
1092 gen_helper_madd64_q_ssov(r1, cpu_env, r1, arg2, arg3, temp);
1093 tcg_gen_extr_i64_i32(rl, rh, r1);
1094
1095 tcg_temp_free_i64(r1);
1096 tcg_temp_free(temp);
1097 }
1098 /* ret = r2 - (r1 * r3); */
1099 static inline void gen_msub32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3)
1100 {
1101 TCGv_i64 t1 = tcg_temp_new_i64();
1102 TCGv_i64 t2 = tcg_temp_new_i64();
1103 TCGv_i64 t3 = tcg_temp_new_i64();
1104
1105 tcg_gen_ext_i32_i64(t1, r1);
1106 tcg_gen_ext_i32_i64(t2, r2);
1107 tcg_gen_ext_i32_i64(t3, r3);
1108
1109 tcg_gen_mul_i64(t1, t1, t3);
1110 tcg_gen_sub_i64(t1, t2, t1);
1111
1112 tcg_gen_trunc_i64_i32(ret, t1);
1113 /* calc V
1114 t2 > 0x7fffffff */
1115 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL);
1116 /* result < -0x80000000 */
1117 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL);
1118 tcg_gen_or_i64(t2, t2, t3);
1119 tcg_gen_trunc_i64_i32(cpu_PSW_V, t2);
1120 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1121
1122 /* Calc SV bit */
1123 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1124 /* Calc AV/SAV bits */
1125 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
1126 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
1127 /* calc SAV */
1128 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1129
1130 tcg_temp_free_i64(t1);
1131 tcg_temp_free_i64(t2);
1132 tcg_temp_free_i64(t3);
1133 }
1134
1135 static inline void gen_msubi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con)
1136 {
1137 TCGv temp = tcg_const_i32(con);
1138 gen_msub32_d(ret, r1, r2, temp);
1139 tcg_temp_free(temp);
1140 }
1141
1142 static inline void
1143 gen_msub64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1144 TCGv r3)
1145 {
1146 TCGv t1 = tcg_temp_new();
1147 TCGv t2 = tcg_temp_new();
1148 TCGv t3 = tcg_temp_new();
1149 TCGv t4 = tcg_temp_new();
1150
1151 tcg_gen_muls2_tl(t1, t2, r1, r3);
1152 /* only the sub can overflow */
1153 tcg_gen_sub2_tl(t3, t4, r2_low, r2_high, t1, t2);
1154 /* calc V bit */
1155 tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high);
1156 tcg_gen_xor_tl(t1, r2_high, t2);
1157 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, t1);
1158 /* Calc SV bit */
1159 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1160 /* Calc AV/SAV bits */
1161 tcg_gen_add_tl(cpu_PSW_AV, t4, t4);
1162 tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV);
1163 /* calc SAV */
1164 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1165 /* write back the result */
1166 tcg_gen_mov_tl(ret_low, t3);
1167 tcg_gen_mov_tl(ret_high, t4);
1168
1169 tcg_temp_free(t1);
1170 tcg_temp_free(t2);
1171 tcg_temp_free(t3);
1172 tcg_temp_free(t4);
1173 }
1174
1175 static inline void
1176 gen_msubi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1177 int32_t con)
1178 {
1179 TCGv temp = tcg_const_i32(con);
1180 gen_msub64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
1181 tcg_temp_free(temp);
1182 }
1183
1184 static inline void
1185 gen_msubu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1186 TCGv r3)
1187 {
1188 TCGv_i64 t1 = tcg_temp_new_i64();
1189 TCGv_i64 t2 = tcg_temp_new_i64();
1190 TCGv_i64 t3 = tcg_temp_new_i64();
1191
1192 tcg_gen_extu_i32_i64(t1, r1);
1193 tcg_gen_concat_i32_i64(t2, r2_low, r2_high);
1194 tcg_gen_extu_i32_i64(t3, r3);
1195
1196 tcg_gen_mul_i64(t1, t1, t3);
1197 tcg_gen_sub_i64(t3, t2, t1);
1198 tcg_gen_extr_i64_i32(ret_low, ret_high, t3);
1199 /* calc V bit, only the sub can overflow, if t1 > t2 */
1200 tcg_gen_setcond_i64(TCG_COND_GTU, t1, t1, t2);
1201 tcg_gen_trunc_i64_i32(cpu_PSW_V, t1);
1202 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1203 /* Calc SV bit */
1204 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1205 /* Calc AV/SAV bits */
1206 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
1207 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
1208 /* calc SAV */
1209 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1210
1211 tcg_temp_free_i64(t1);
1212 tcg_temp_free_i64(t2);
1213 tcg_temp_free_i64(t3);
1214 }
1215
1216 static inline void
1217 gen_msubui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1218 int32_t con)
1219 {
1220 TCGv temp = tcg_const_i32(con);
1221 gen_msubu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
1222 tcg_temp_free(temp);
1223 }
1224
1225 static inline void gen_addi_d(TCGv ret, TCGv r1, target_ulong r2)
1226 {
1227 TCGv temp = tcg_const_i32(r2);
1228 gen_add_d(ret, r1, temp);
1229 tcg_temp_free(temp);
1230 }
1231 /* calculate the carry bit too */
1232 static inline void gen_add_CC(TCGv ret, TCGv r1, TCGv r2)
1233 {
1234 TCGv t0 = tcg_temp_new_i32();
1235 TCGv result = tcg_temp_new_i32();
1236
1237 tcg_gen_movi_tl(t0, 0);
1238 /* Addition and set C/V/SV bits */
1239 tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, r2, t0);
1240 /* calc V bit */
1241 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1242 tcg_gen_xor_tl(t0, r1, r2);
1243 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
1244 /* Calc SV bit */
1245 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1246 /* Calc AV/SAV bits */
1247 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1248 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1249 /* calc SAV */
1250 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1251 /* write back result */
1252 tcg_gen_mov_tl(ret, result);
1253
1254 tcg_temp_free(result);
1255 tcg_temp_free(t0);
1256 }
1257
1258 static inline void gen_addi_CC(TCGv ret, TCGv r1, int32_t con)
1259 {
1260 TCGv temp = tcg_const_i32(con);
1261 gen_add_CC(ret, r1, temp);
1262 tcg_temp_free(temp);
1263 }
1264
1265 static inline void gen_addc_CC(TCGv ret, TCGv r1, TCGv r2)
1266 {
1267 TCGv carry = tcg_temp_new_i32();
1268 TCGv t0 = tcg_temp_new_i32();
1269 TCGv result = tcg_temp_new_i32();
1270
1271 tcg_gen_movi_tl(t0, 0);
1272 tcg_gen_setcondi_tl(TCG_COND_NE, carry, cpu_PSW_C, 0);
1273 /* Addition, carry and set C/V/SV bits */
1274 tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, carry, t0);
1275 tcg_gen_add2_i32(result, cpu_PSW_C, result, cpu_PSW_C, r2, t0);
1276 /* calc V bit */
1277 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1278 tcg_gen_xor_tl(t0, r1, r2);
1279 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
1280 /* Calc SV bit */
1281 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1282 /* Calc AV/SAV bits */
1283 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1284 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1285 /* calc SAV */
1286 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1287 /* write back result */
1288 tcg_gen_mov_tl(ret, result);
1289
1290 tcg_temp_free(result);
1291 tcg_temp_free(t0);
1292 tcg_temp_free(carry);
1293 }
1294
1295 static inline void gen_addci_CC(TCGv ret, TCGv r1, int32_t con)
1296 {
1297 TCGv temp = tcg_const_i32(con);
1298 gen_addc_CC(ret, r1, temp);
1299 tcg_temp_free(temp);
1300 }
1301
1302 static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3,
1303 TCGv r4)
1304 {
1305 TCGv temp = tcg_temp_new();
1306 TCGv temp2 = tcg_temp_new();
1307 TCGv result = tcg_temp_new();
1308 TCGv mask = tcg_temp_new();
1309 TCGv t0 = tcg_const_i32(0);
1310
1311 /* create mask for sticky bits */
1312 tcg_gen_setcond_tl(cond, mask, r4, t0);
1313 tcg_gen_shli_tl(mask, mask, 31);
1314
1315 tcg_gen_add_tl(result, r1, r2);
1316 /* Calc PSW_V */
1317 tcg_gen_xor_tl(temp, result, r1);
1318 tcg_gen_xor_tl(temp2, r1, r2);
1319 tcg_gen_andc_tl(temp, temp, temp2);
1320 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V);
1321 /* Set PSW_SV */
1322 tcg_gen_and_tl(temp, temp, mask);
1323 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV);
1324 /* calc AV bit */
1325 tcg_gen_add_tl(temp, result, result);
1326 tcg_gen_xor_tl(temp, temp, result);
1327 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV);
1328 /* calc SAV bit */
1329 tcg_gen_and_tl(temp, temp, mask);
1330 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV);
1331 /* write back result */
1332 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1);
1333
1334 tcg_temp_free(t0);
1335 tcg_temp_free(temp);
1336 tcg_temp_free(temp2);
1337 tcg_temp_free(result);
1338 tcg_temp_free(mask);
1339 }
1340
1341 static inline void gen_condi_add(TCGCond cond, TCGv r1, int32_t r2,
1342 TCGv r3, TCGv r4)
1343 {
1344 TCGv temp = tcg_const_i32(r2);
1345 gen_cond_add(cond, r1, temp, r3, r4);
1346 tcg_temp_free(temp);
1347 }
1348
1349 static inline void gen_sub_d(TCGv ret, TCGv r1, TCGv r2)
1350 {
1351 TCGv temp = tcg_temp_new_i32();
1352 TCGv result = tcg_temp_new_i32();
1353
1354 tcg_gen_sub_tl(result, r1, r2);
1355 /* calc V bit */
1356 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1357 tcg_gen_xor_tl(temp, r1, r2);
1358 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
1359 /* calc SV bit */
1360 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1361 /* Calc AV bit */
1362 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1363 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1364 /* calc SAV bit */
1365 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1366 /* write back result */
1367 tcg_gen_mov_tl(ret, result);
1368
1369 tcg_temp_free(temp);
1370 tcg_temp_free(result);
1371 }
1372
1373 static inline void gen_sub_CC(TCGv ret, TCGv r1, TCGv r2)
1374 {
1375 TCGv result = tcg_temp_new();
1376 TCGv temp = tcg_temp_new();
1377
1378 tcg_gen_sub_tl(result, r1, r2);
1379 /* calc C bit */
1380 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_PSW_C, r1, r2);
1381 /* calc V bit */
1382 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1383 tcg_gen_xor_tl(temp, r1, r2);
1384 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
1385 /* calc SV bit */
1386 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1387 /* Calc AV bit */
1388 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1389 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1390 /* calc SAV bit */
1391 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1392 /* write back result */
1393 tcg_gen_mov_tl(ret, result);
1394
1395 tcg_temp_free(result);
1396 tcg_temp_free(temp);
1397 }
1398
1399 static inline void gen_subc_CC(TCGv ret, TCGv r1, TCGv r2)
1400 {
1401 TCGv temp = tcg_temp_new();
1402 tcg_gen_not_tl(temp, r2);
1403 gen_addc_CC(ret, r1, temp);
1404 tcg_temp_free(temp);
1405 }
1406
1407 static inline void gen_cond_sub(TCGCond cond, TCGv r1, TCGv r2, TCGv r3,
1408 TCGv r4)
1409 {
1410 TCGv temp = tcg_temp_new();
1411 TCGv temp2 = tcg_temp_new();
1412 TCGv result = tcg_temp_new();
1413 TCGv mask = tcg_temp_new();
1414 TCGv t0 = tcg_const_i32(0);
1415
1416 /* create mask for sticky bits */
1417 tcg_gen_setcond_tl(cond, mask, r4, t0);
1418 tcg_gen_shli_tl(mask, mask, 31);
1419
1420 tcg_gen_sub_tl(result, r1, r2);
1421 /* Calc PSW_V */
1422 tcg_gen_xor_tl(temp, result, r1);
1423 tcg_gen_xor_tl(temp2, r1, r2);
1424 tcg_gen_and_tl(temp, temp, temp2);
1425 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V);
1426 /* Set PSW_SV */
1427 tcg_gen_and_tl(temp, temp, mask);
1428 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV);
1429 /* calc AV bit */
1430 tcg_gen_add_tl(temp, result, result);
1431 tcg_gen_xor_tl(temp, temp, result);
1432 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV);
1433 /* calc SAV bit */
1434 tcg_gen_and_tl(temp, temp, mask);
1435 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV);
1436 /* write back result */
1437 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1);
1438
1439 tcg_temp_free(t0);
1440 tcg_temp_free(temp);
1441 tcg_temp_free(temp2);
1442 tcg_temp_free(result);
1443 tcg_temp_free(mask);
1444 }
1445
1446 static inline void gen_abs(TCGv ret, TCGv r1)
1447 {
1448 TCGv temp = tcg_temp_new();
1449 TCGv t0 = tcg_const_i32(0);
1450
1451 tcg_gen_neg_tl(temp, r1);
1452 tcg_gen_movcond_tl(TCG_COND_GE, ret, r1, t0, r1, temp);
1453 /* overflow can only happen, if r1 = 0x80000000 */
1454 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, r1, 0x80000000);
1455 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1456 /* calc SV bit */
1457 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1458 /* Calc AV bit */
1459 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
1460 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
1461 /* calc SAV bit */
1462 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1463
1464 tcg_temp_free(temp);
1465 tcg_temp_free(t0);
1466 }
1467
1468 static inline void gen_absdif(TCGv ret, TCGv r1, TCGv r2)
1469 {
1470 TCGv temp = tcg_temp_new_i32();
1471 TCGv result = tcg_temp_new_i32();
1472
1473 tcg_gen_sub_tl(result, r1, r2);
1474 tcg_gen_sub_tl(temp, r2, r1);
1475 tcg_gen_movcond_tl(TCG_COND_GT, result, r1, r2, result, temp);
1476
1477 /* calc V bit */
1478 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1479 tcg_gen_xor_tl(temp, result, r2);
1480 tcg_gen_movcond_tl(TCG_COND_GT, cpu_PSW_V, r1, r2, cpu_PSW_V, temp);
1481 tcg_gen_xor_tl(temp, r1, r2);
1482 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
1483 /* calc SV bit */
1484 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1485 /* Calc AV bit */
1486 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1487 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1488 /* calc SAV bit */
1489 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1490 /* write back result */
1491 tcg_gen_mov_tl(ret, result);
1492
1493 tcg_temp_free(temp);
1494 tcg_temp_free(result);
1495 }
1496
1497 static inline void gen_absdifi(TCGv ret, TCGv r1, int32_t con)
1498 {
1499 TCGv temp = tcg_const_i32(con);
1500 gen_absdif(ret, r1, temp);
1501 tcg_temp_free(temp);
1502 }
1503
1504 static inline void gen_absdifsi(TCGv ret, TCGv r1, int32_t con)
1505 {
1506 TCGv temp = tcg_const_i32(con);
1507 gen_helper_absdif_ssov(ret, cpu_env, r1, temp);
1508 tcg_temp_free(temp);
1509 }
1510
1511 static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2)
1512 {
1513 TCGv high = tcg_temp_new();
1514 TCGv low = tcg_temp_new();
1515
1516 tcg_gen_muls2_tl(low, high, r1, r2);
1517 tcg_gen_mov_tl(ret, low);
1518 /* calc V bit */
1519 tcg_gen_sari_tl(low, low, 31);
1520 tcg_gen_setcond_tl(TCG_COND_NE, cpu_PSW_V, high, low);
1521 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1522 /* calc SV bit */
1523 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1524 /* Calc AV bit */
1525 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
1526 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
1527 /* calc SAV bit */
1528 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1529
1530 tcg_temp_free(high);
1531 tcg_temp_free(low);
1532 }
1533
1534 static inline void gen_muli_i32s(TCGv ret, TCGv r1, int32_t con)
1535 {
1536 TCGv temp = tcg_const_i32(con);
1537 gen_mul_i32s(ret, r1, temp);
1538 tcg_temp_free(temp);
1539 }
1540
1541 static inline void gen_mul_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2)
1542 {
1543 tcg_gen_muls2_tl(ret_low, ret_high, r1, r2);
1544 /* clear V bit */
1545 tcg_gen_movi_tl(cpu_PSW_V, 0);
1546 /* calc SV bit */
1547 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1548 /* Calc AV bit */
1549 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
1550 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
1551 /* calc SAV bit */
1552 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1553 }
1554
1555 static inline void gen_muli_i64s(TCGv ret_low, TCGv ret_high, TCGv r1,
1556 int32_t con)
1557 {
1558 TCGv temp = tcg_const_i32(con);
1559 gen_mul_i64s(ret_low, ret_high, r1, temp);
1560 tcg_temp_free(temp);
1561 }
1562
1563 static inline void gen_mul_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2)
1564 {
1565 tcg_gen_mulu2_tl(ret_low, ret_high, r1, r2);
1566 /* clear V bit */
1567 tcg_gen_movi_tl(cpu_PSW_V, 0);
1568 /* calc SV bit */
1569 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1570 /* Calc AV bit */
1571 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
1572 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
1573 /* calc SAV bit */
1574 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1575 }
1576
1577 static inline void gen_muli_i64u(TCGv ret_low, TCGv ret_high, TCGv r1,
1578 int32_t con)
1579 {
1580 TCGv temp = tcg_const_i32(con);
1581 gen_mul_i64u(ret_low, ret_high, r1, temp);
1582 tcg_temp_free(temp);
1583 }
1584
1585 static inline void gen_mulsi_i32(TCGv ret, TCGv r1, int32_t con)
1586 {
1587 TCGv temp = tcg_const_i32(con);
1588 gen_helper_mul_ssov(ret, cpu_env, r1, temp);
1589 tcg_temp_free(temp);
1590 }
1591
1592 static inline void gen_mulsui_i32(TCGv ret, TCGv r1, int32_t con)
1593 {
1594 TCGv temp = tcg_const_i32(con);
1595 gen_helper_mul_suov(ret, cpu_env, r1, temp);
1596 tcg_temp_free(temp);
1597 }
1598 /* gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); */
1599 static inline void gen_maddsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
1600 {
1601 TCGv temp = tcg_const_i32(con);
1602 gen_helper_madd32_ssov(ret, cpu_env, r1, r2, temp);
1603 tcg_temp_free(temp);
1604 }
1605
1606 static inline void gen_maddsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
1607 {
1608 TCGv temp = tcg_const_i32(con);
1609 gen_helper_madd32_suov(ret, cpu_env, r1, r2, temp);
1610 tcg_temp_free(temp);
1611 }
1612
1613 static void
1614 gen_mul_q(TCGv rl, TCGv rh, TCGv arg1, TCGv arg2, uint32_t n, uint32_t up_shift)
1615 {
1616 TCGv temp = tcg_temp_new();
1617 TCGv_i64 temp_64 = tcg_temp_new_i64();
1618 TCGv_i64 temp2_64 = tcg_temp_new_i64();
1619
1620 if (n == 0) {
1621 if (up_shift == 32) {
1622 tcg_gen_muls2_tl(rh, rl, arg1, arg2);
1623 } else if (up_shift == 16) {
1624 tcg_gen_ext_i32_i64(temp_64, arg1);
1625 tcg_gen_ext_i32_i64(temp2_64, arg2);
1626
1627 tcg_gen_mul_i64(temp_64, temp_64, temp2_64);
1628 tcg_gen_shri_i64(temp_64, temp_64, up_shift);
1629 tcg_gen_extr_i64_i32(rl, rh, temp_64);
1630 } else {
1631 tcg_gen_muls2_tl(rl, rh, arg1, arg2);
1632 }
1633 /* reset v bit */
1634 tcg_gen_movi_tl(cpu_PSW_V, 0);
1635 } else { /* n is exspected to be 1 */
1636 tcg_gen_ext_i32_i64(temp_64, arg1);
1637 tcg_gen_ext_i32_i64(temp2_64, arg2);
1638
1639 tcg_gen_mul_i64(temp_64, temp_64, temp2_64);
1640
1641 if (up_shift == 0) {
1642 tcg_gen_shli_i64(temp_64, temp_64, 1);
1643 } else {
1644 tcg_gen_shri_i64(temp_64, temp_64, up_shift - 1);
1645 }
1646 tcg_gen_extr_i64_i32(rl, rh, temp_64);
1647 /* overflow only occours if r1 = r2 = 0x8000 */
1648 if (up_shift == 0) {/* result is 64 bit */
1649 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rh,
1650 0x80000000);
1651 } else { /* result is 32 bit */
1652 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rl,
1653 0x80000000);
1654 }
1655 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1656 /* calc sv overflow bit */
1657 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1658 }
1659 /* calc av overflow bit */
1660 if (up_shift == 0) {
1661 tcg_gen_add_tl(cpu_PSW_AV, rh, rh);
1662 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV);
1663 } else {
1664 tcg_gen_add_tl(cpu_PSW_AV, rl, rl);
1665 tcg_gen_xor_tl(cpu_PSW_AV, rl, cpu_PSW_AV);
1666 }
1667 /* calc sav overflow bit */
1668 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1669 tcg_temp_free(temp);
1670 tcg_temp_free_i64(temp_64);
1671 tcg_temp_free_i64(temp2_64);
1672 }
1673
1674 static void
1675 gen_mul_q_16(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n)
1676 {
1677 TCGv temp = tcg_temp_new();
1678 if (n == 0) {
1679 tcg_gen_mul_tl(ret, arg1, arg2);
1680 } else { /* n is exspected to be 1 */
1681 tcg_gen_mul_tl(ret, arg1, arg2);
1682 tcg_gen_shli_tl(ret, ret, 1);
1683 /* catch special case r1 = r2 = 0x8000 */
1684 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80000000);
1685 tcg_gen_sub_tl(ret, ret, temp);
1686 }
1687 /* reset v bit */
1688 tcg_gen_movi_tl(cpu_PSW_V, 0);
1689 /* calc av overflow bit */
1690 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
1691 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
1692 /* calc sav overflow bit */
1693 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1694
1695 tcg_temp_free(temp);
1696 }
1697
1698 static void gen_mulr_q(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n)
1699 {
1700 TCGv temp = tcg_temp_new();
1701 if (n == 0) {
1702 tcg_gen_mul_tl(ret, arg1, arg2);
1703 tcg_gen_addi_tl(ret, ret, 0x8000);
1704 } else {
1705 tcg_gen_mul_tl(ret, arg1, arg2);
1706 tcg_gen_shli_tl(ret, ret, 1);
1707 tcg_gen_addi_tl(ret, ret, 0x8000);
1708 /* catch special case r1 = r2 = 0x8000 */
1709 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80008000);
1710 tcg_gen_muli_tl(temp, temp, 0x8001);
1711 tcg_gen_sub_tl(ret, ret, temp);
1712 }
1713 /* reset v bit */
1714 tcg_gen_movi_tl(cpu_PSW_V, 0);
1715 /* calc av overflow bit */
1716 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
1717 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
1718 /* calc sav overflow bit */
1719 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1720 /* cut halfword off */
1721 tcg_gen_andi_tl(ret, ret, 0xffff0000);
1722
1723 tcg_temp_free(temp);
1724 }
1725
1726 static inline void
1727 gen_madds_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1728 TCGv r3)
1729 {
1730 TCGv_i64 temp64 = tcg_temp_new_i64();
1731 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
1732 gen_helper_madd64_ssov(temp64, cpu_env, r1, temp64, r3);
1733 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
1734 tcg_temp_free_i64(temp64);
1735 }
1736
1737 static inline void
1738 gen_maddsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1739 int32_t con)
1740 {
1741 TCGv temp = tcg_const_i32(con);
1742 gen_madds_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
1743 tcg_temp_free(temp);
1744 }
1745
1746 static inline void
1747 gen_maddsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1748 TCGv r3)
1749 {
1750 TCGv_i64 temp64 = tcg_temp_new_i64();
1751 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
1752 gen_helper_madd64_suov(temp64, cpu_env, r1, temp64, r3);
1753 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
1754 tcg_temp_free_i64(temp64);
1755 }
1756
1757 static inline void
1758 gen_maddsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1759 int32_t con)
1760 {
1761 TCGv temp = tcg_const_i32(con);
1762 gen_maddsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
1763 tcg_temp_free(temp);
1764 }
1765
1766 static inline void gen_msubsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
1767 {
1768 TCGv temp = tcg_const_i32(con);
1769 gen_helper_msub32_ssov(ret, cpu_env, r1, r2, temp);
1770 tcg_temp_free(temp);
1771 }
1772
1773 static inline void gen_msubsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
1774 {
1775 TCGv temp = tcg_const_i32(con);
1776 gen_helper_msub32_suov(ret, cpu_env, r1, r2, temp);
1777 tcg_temp_free(temp);
1778 }
1779
1780 static inline void
1781 gen_msubs_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1782 TCGv r3)
1783 {
1784 TCGv_i64 temp64 = tcg_temp_new_i64();
1785 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
1786 gen_helper_msub64_ssov(temp64, cpu_env, r1, temp64, r3);
1787 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
1788 tcg_temp_free_i64(temp64);
1789 }
1790
1791 static inline void
1792 gen_msubsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1793 int32_t con)
1794 {
1795 TCGv temp = tcg_const_i32(con);
1796 gen_msubs_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
1797 tcg_temp_free(temp);
1798 }
1799
1800 static inline void
1801 gen_msubsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1802 TCGv r3)
1803 {
1804 TCGv_i64 temp64 = tcg_temp_new_i64();
1805 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
1806 gen_helper_msub64_suov(temp64, cpu_env, r1, temp64, r3);
1807 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
1808 tcg_temp_free_i64(temp64);
1809 }
1810
1811 static inline void
1812 gen_msubsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1813 int32_t con)
1814 {
1815 TCGv temp = tcg_const_i32(con);
1816 gen_msubsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
1817 tcg_temp_free(temp);
1818 }
1819
1820 static void gen_saturate(TCGv ret, TCGv arg, int32_t up, int32_t low)
1821 {
1822 TCGv sat_neg = tcg_const_i32(low);
1823 TCGv temp = tcg_const_i32(up);
1824
1825 /* sat_neg = (arg < low ) ? low : arg; */
1826 tcg_gen_movcond_tl(TCG_COND_LT, sat_neg, arg, sat_neg, sat_neg, arg);
1827
1828 /* ret = (sat_neg > up ) ? up : sat_neg; */
1829 tcg_gen_movcond_tl(TCG_COND_GT, ret, sat_neg, temp, temp, sat_neg);
1830
1831 tcg_temp_free(sat_neg);
1832 tcg_temp_free(temp);
1833 }
1834
1835 static void gen_saturate_u(TCGv ret, TCGv arg, int32_t up)
1836 {
1837 TCGv temp = tcg_const_i32(up);
1838 /* sat_neg = (arg > up ) ? up : arg; */
1839 tcg_gen_movcond_tl(TCG_COND_GTU, ret, arg, temp, temp, arg);
1840 tcg_temp_free(temp);
1841 }
1842
1843 static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count)
1844 {
1845 if (shift_count == -32) {
1846 tcg_gen_movi_tl(ret, 0);
1847 } else if (shift_count >= 0) {
1848 tcg_gen_shli_tl(ret, r1, shift_count);
1849 } else {
1850 tcg_gen_shri_tl(ret, r1, -shift_count);
1851 }
1852 }
1853
1854 static void gen_sh_hi(TCGv ret, TCGv r1, int32_t shiftcount)
1855 {
1856 TCGv temp_low, temp_high;
1857
1858 if (shiftcount == -16) {
1859 tcg_gen_movi_tl(ret, 0);
1860 } else {
1861 temp_high = tcg_temp_new();
1862 temp_low = tcg_temp_new();
1863
1864 tcg_gen_andi_tl(temp_low, r1, 0xffff);
1865 tcg_gen_andi_tl(temp_high, r1, 0xffff0000);
1866 gen_shi(temp_low, temp_low, shiftcount);
1867 gen_shi(ret, temp_high, shiftcount);
1868 tcg_gen_deposit_tl(ret, ret, temp_low, 0, 16);
1869
1870 tcg_temp_free(temp_low);
1871 tcg_temp_free(temp_high);
1872 }
1873 }
1874
1875 static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count)
1876 {
1877 uint32_t msk, msk_start;
1878 TCGv temp = tcg_temp_new();
1879 TCGv temp2 = tcg_temp_new();
1880 TCGv t_0 = tcg_const_i32(0);
1881
1882 if (shift_count == 0) {
1883 /* Clear PSW.C and PSW.V */
1884 tcg_gen_movi_tl(cpu_PSW_C, 0);
1885 tcg_gen_mov_tl(cpu_PSW_V, cpu_PSW_C);
1886 tcg_gen_mov_tl(ret, r1);
1887 } else if (shift_count == -32) {
1888 /* set PSW.C */
1889 tcg_gen_mov_tl(cpu_PSW_C, r1);
1890 /* fill ret completly with sign bit */
1891 tcg_gen_sari_tl(ret, r1, 31);
1892 /* clear PSW.V */
1893 tcg_gen_movi_tl(cpu_PSW_V, 0);
1894 } else if (shift_count > 0) {
1895 TCGv t_max = tcg_const_i32(0x7FFFFFFF >> shift_count);
1896 TCGv t_min = tcg_const_i32(((int32_t) -0x80000000) >> shift_count);
1897
1898 /* calc carry */
1899 msk_start = 32 - shift_count;
1900 msk = ((1 << shift_count) - 1) << msk_start;
1901 tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
1902 /* calc v/sv bits */
1903 tcg_gen_setcond_tl(TCG_COND_GT, temp, r1, t_max);
1904 tcg_gen_setcond_tl(TCG_COND_LT, temp2, r1, t_min);
1905 tcg_gen_or_tl(cpu_PSW_V, temp, temp2);
1906 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1907 /* calc sv */
1908 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_V, cpu_PSW_SV);
1909 /* do shift */
1910 tcg_gen_shli_tl(ret, r1, shift_count);
1911
1912 tcg_temp_free(t_max);
1913 tcg_temp_free(t_min);
1914 } else {
1915 /* clear PSW.V */
1916 tcg_gen_movi_tl(cpu_PSW_V, 0);
1917 /* calc carry */
1918 msk = (1 << -shift_count) - 1;
1919 tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
1920 /* do shift */
1921 tcg_gen_sari_tl(ret, r1, -shift_count);
1922 }
1923 /* calc av overflow bit */
1924 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
1925 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
1926 /* calc sav overflow bit */
1927 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1928
1929 tcg_temp_free(temp);
1930 tcg_temp_free(temp2);
1931 tcg_temp_free(t_0);
1932 }
1933
1934 static void gen_shas(TCGv ret, TCGv r1, TCGv r2)
1935 {
1936 gen_helper_sha_ssov(ret, cpu_env, r1, r2);
1937 }
1938
1939 static void gen_shasi(TCGv ret, TCGv r1, int32_t con)
1940 {
1941 TCGv temp = tcg_const_i32(con);
1942 gen_shas(ret, r1, temp);
1943 tcg_temp_free(temp);
1944 }
1945
1946 static void gen_sha_hi(TCGv ret, TCGv r1, int32_t shift_count)
1947 {
1948 TCGv low, high;
1949
1950 if (shift_count == 0) {
1951 tcg_gen_mov_tl(ret, r1);
1952 } else if (shift_count > 0) {
1953 low = tcg_temp_new();
1954 high = tcg_temp_new();
1955
1956 tcg_gen_andi_tl(high, r1, 0xffff0000);
1957 tcg_gen_shli_tl(low, r1, shift_count);
1958 tcg_gen_shli_tl(ret, high, shift_count);
1959 tcg_gen_deposit_tl(ret, ret, low, 0, 16);
1960
1961 tcg_temp_free(low);
1962 tcg_temp_free(high);
1963 } else {
1964 low = tcg_temp_new();
1965 high = tcg_temp_new();
1966
1967 tcg_gen_ext16s_tl(low, r1);
1968 tcg_gen_sari_tl(low, low, -shift_count);
1969 tcg_gen_sari_tl(ret, r1, -shift_count);
1970 tcg_gen_deposit_tl(ret, ret, low, 0, 16);
1971
1972 tcg_temp_free(low);
1973 tcg_temp_free(high);
1974 }
1975
1976 }
1977
1978 /* ret = {ret[30:0], (r1 cond r2)}; */
1979 static void gen_sh_cond(int cond, TCGv ret, TCGv r1, TCGv r2)
1980 {
1981 TCGv temp = tcg_temp_new();
1982 TCGv temp2 = tcg_temp_new();
1983
1984 tcg_gen_shli_tl(temp, ret, 1);
1985 tcg_gen_setcond_tl(cond, temp2, r1, r2);
1986 tcg_gen_or_tl(ret, temp, temp2);
1987
1988 tcg_temp_free(temp);
1989 tcg_temp_free(temp2);
1990 }
1991
1992 static void gen_sh_condi(int cond, TCGv ret, TCGv r1, int32_t con)
1993 {
1994 TCGv temp = tcg_const_i32(con);
1995 gen_sh_cond(cond, ret, r1, temp);
1996 tcg_temp_free(temp);
1997 }
1998
1999 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2)
2000 {
2001 gen_helper_add_ssov(ret, cpu_env, r1, r2);
2002 }
2003
2004 static inline void gen_addsi(TCGv ret, TCGv r1, int32_t con)
2005 {
2006 TCGv temp = tcg_const_i32(con);
2007 gen_helper_add_ssov(ret, cpu_env, r1, temp);
2008 tcg_temp_free(temp);
2009 }
2010
2011 static inline void gen_addsui(TCGv ret, TCGv r1, int32_t con)
2012 {
2013 TCGv temp = tcg_const_i32(con);
2014 gen_helper_add_suov(ret, cpu_env, r1, temp);
2015 tcg_temp_free(temp);
2016 }
2017
2018 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2)
2019 {
2020 gen_helper_sub_ssov(ret, cpu_env, r1, r2);
2021 }
2022
2023 static inline void gen_subsu(TCGv ret, TCGv r1, TCGv r2)
2024 {
2025 gen_helper_sub_suov(ret, cpu_env, r1, r2);
2026 }
2027
2028 static inline void gen_bit_2op(TCGv ret, TCGv r1, TCGv r2,
2029 int pos1, int pos2,
2030 void(*op1)(TCGv, TCGv, TCGv),
2031 void(*op2)(TCGv, TCGv, TCGv))
2032 {
2033 TCGv temp1, temp2;
2034
2035 temp1 = tcg_temp_new();
2036 temp2 = tcg_temp_new();
2037
2038 tcg_gen_shri_tl(temp2, r2, pos2);
2039 tcg_gen_shri_tl(temp1, r1, pos1);
2040
2041 (*op1)(temp1, temp1, temp2);
2042 (*op2)(temp1 , ret, temp1);
2043
2044 tcg_gen_deposit_tl(ret, ret, temp1, 0, 1);
2045
2046 tcg_temp_free(temp1);
2047 tcg_temp_free(temp2);
2048 }
2049
2050 /* ret = r1[pos1] op1 r2[pos2]; */
2051 static inline void gen_bit_1op(TCGv ret, TCGv r1, TCGv r2,
2052 int pos1, int pos2,
2053 void(*op1)(TCGv, TCGv, TCGv))
2054 {
2055 TCGv temp1, temp2;
2056
2057 temp1 = tcg_temp_new();
2058 temp2 = tcg_temp_new();
2059
2060 tcg_gen_shri_tl(temp2, r2, pos2);
2061 tcg_gen_shri_tl(temp1, r1, pos1);
2062
2063 (*op1)(ret, temp1, temp2);
2064
2065 tcg_gen_andi_tl(ret, ret, 0x1);
2066
2067 tcg_temp_free(temp1);
2068 tcg_temp_free(temp2);
2069 }
2070
2071 static inline void gen_accumulating_cond(int cond, TCGv ret, TCGv r1, TCGv r2,
2072 void(*op)(TCGv, TCGv, TCGv))
2073 {
2074 TCGv temp = tcg_temp_new();
2075 TCGv temp2 = tcg_temp_new();
2076 /* temp = (arg1 cond arg2 )*/
2077 tcg_gen_setcond_tl(cond, temp, r1, r2);
2078 /* temp2 = ret[0]*/
2079 tcg_gen_andi_tl(temp2, ret, 0x1);
2080 /* temp = temp insn temp2 */
2081 (*op)(temp, temp, temp2);
2082 /* ret = {ret[31:1], temp} */
2083 tcg_gen_deposit_tl(ret, ret, temp, 0, 1);
2084
2085 tcg_temp_free(temp);
2086 tcg_temp_free(temp2);
2087 }
2088
2089 static inline void
2090 gen_accumulating_condi(int cond, TCGv ret, TCGv r1, int32_t con,
2091 void(*op)(TCGv, TCGv, TCGv))
2092 {
2093 TCGv temp = tcg_const_i32(con);
2094 gen_accumulating_cond(cond, ret, r1, temp, op);
2095 tcg_temp_free(temp);
2096 }
2097
2098 /* ret = (r1 cond r2) ? 0xFFFFFFFF ? 0x00000000;*/
2099 static inline void gen_cond_w(TCGCond cond, TCGv ret, TCGv r1, TCGv r2)
2100 {
2101 tcg_gen_setcond_tl(cond, ret, r1, r2);
2102 tcg_gen_neg_tl(ret, ret);
2103 }
2104
2105 static inline void gen_eqany_bi(TCGv ret, TCGv r1, int32_t con)
2106 {
2107 TCGv b0 = tcg_temp_new();
2108 TCGv b1 = tcg_temp_new();
2109 TCGv b2 = tcg_temp_new();
2110 TCGv b3 = tcg_temp_new();
2111
2112 /* byte 0 */
2113 tcg_gen_andi_tl(b0, r1, 0xff);
2114 tcg_gen_setcondi_tl(TCG_COND_EQ, b0, b0, con & 0xff);
2115
2116 /* byte 1 */
2117 tcg_gen_andi_tl(b1, r1, 0xff00);
2118 tcg_gen_setcondi_tl(TCG_COND_EQ, b1, b1, con & 0xff00);
2119
2120 /* byte 2 */
2121 tcg_gen_andi_tl(b2, r1, 0xff0000);
2122 tcg_gen_setcondi_tl(TCG_COND_EQ, b2, b2, con & 0xff0000);
2123
2124 /* byte 3 */
2125 tcg_gen_andi_tl(b3, r1, 0xff000000);
2126 tcg_gen_setcondi_tl(TCG_COND_EQ, b3, b3, con & 0xff000000);
2127
2128 /* combine them */
2129 tcg_gen_or_tl(ret, b0, b1);
2130 tcg_gen_or_tl(ret, ret, b2);
2131 tcg_gen_or_tl(ret, ret, b3);
2132
2133 tcg_temp_free(b0);
2134 tcg_temp_free(b1);
2135 tcg_temp_free(b2);
2136 tcg_temp_free(b3);
2137 }
2138
2139 static inline void gen_eqany_hi(TCGv ret, TCGv r1, int32_t con)
2140 {
2141 TCGv h0 = tcg_temp_new();
2142 TCGv h1 = tcg_temp_new();
2143
2144 /* halfword 0 */
2145 tcg_gen_andi_tl(h0, r1, 0xffff);
2146 tcg_gen_setcondi_tl(TCG_COND_EQ, h0, h0, con & 0xffff);
2147
2148 /* halfword 1 */
2149 tcg_gen_andi_tl(h1, r1, 0xffff0000);
2150 tcg_gen_setcondi_tl(TCG_COND_EQ, h1, h1, con & 0xffff0000);
2151
2152 /* combine them */
2153 tcg_gen_or_tl(ret, h0, h1);
2154
2155 tcg_temp_free(h0);
2156 tcg_temp_free(h1);
2157 }
2158 /* mask = ((1 << width) -1) << pos;
2159 ret = (r1 & ~mask) | (r2 << pos) & mask); */
2160 static inline void gen_insert(TCGv ret, TCGv r1, TCGv r2, TCGv width, TCGv pos)
2161 {
2162 TCGv mask = tcg_temp_new();
2163 TCGv temp = tcg_temp_new();
2164 TCGv temp2 = tcg_temp_new();
2165
2166 tcg_gen_movi_tl(mask, 1);
2167 tcg_gen_shl_tl(mask, mask, width);
2168 tcg_gen_subi_tl(mask, mask, 1);
2169 tcg_gen_shl_tl(mask, mask, pos);
2170
2171 tcg_gen_shl_tl(temp, r2, pos);
2172 tcg_gen_and_tl(temp, temp, mask);
2173 tcg_gen_andc_tl(temp2, r1, mask);
2174 tcg_gen_or_tl(ret, temp, temp2);
2175
2176 tcg_temp_free(mask);
2177 tcg_temp_free(temp);
2178 tcg_temp_free(temp2);
2179 }
2180
2181 static inline void gen_bsplit(TCGv rl, TCGv rh, TCGv r1)
2182 {
2183 TCGv_i64 temp = tcg_temp_new_i64();
2184
2185 gen_helper_bsplit(temp, r1);
2186 tcg_gen_extr_i64_i32(rl, rh, temp);
2187
2188 tcg_temp_free_i64(temp);
2189 }
2190
2191 static inline void gen_unpack(TCGv rl, TCGv rh, TCGv r1)
2192 {
2193 TCGv_i64 temp = tcg_temp_new_i64();
2194
2195 gen_helper_unpack(temp, r1);
2196 tcg_gen_extr_i64_i32(rl, rh, temp);
2197
2198 tcg_temp_free_i64(temp);
2199 }
2200
2201 static inline void
2202 gen_dvinit_b(CPUTriCoreState *env, TCGv rl, TCGv rh, TCGv r1, TCGv r2)
2203 {
2204 TCGv_i64 ret = tcg_temp_new_i64();
2205
2206 if (!tricore_feature(env, TRICORE_FEATURE_131)) {
2207 gen_helper_dvinit_b_13(ret, cpu_env, r1, r2);
2208 } else {
2209 gen_helper_dvinit_b_131(ret, cpu_env, r1, r2);
2210 }
2211 tcg_gen_extr_i64_i32(rl, rh, ret);
2212
2213 tcg_temp_free_i64(ret);
2214 }
2215
2216 static inline void
2217 gen_dvinit_h(CPUTriCoreState *env, TCGv rl, TCGv rh, TCGv r1, TCGv r2)
2218 {
2219 TCGv_i64 ret = tcg_temp_new_i64();
2220
2221 if (!tricore_feature(env, TRICORE_FEATURE_131)) {
2222 gen_helper_dvinit_h_13(ret, cpu_env, r1, r2);
2223 } else {
2224 gen_helper_dvinit_h_131(ret, cpu_env, r1, r2);
2225 }
2226 tcg_gen_extr_i64_i32(rl, rh, ret);
2227
2228 tcg_temp_free_i64(ret);
2229 }
2230
2231 static void gen_calc_usb_mul_h(TCGv arg_low, TCGv arg_high)
2232 {
2233 TCGv temp = tcg_temp_new();
2234 /* calc AV bit */
2235 tcg_gen_add_tl(temp, arg_low, arg_low);
2236 tcg_gen_xor_tl(temp, temp, arg_low);
2237 tcg_gen_add_tl(cpu_PSW_AV, arg_high, arg_high);
2238 tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, arg_high);
2239 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp);
2240 /* calc SAV bit */
2241 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2242 tcg_gen_movi_tl(cpu_PSW_V, 0);
2243 tcg_temp_free(temp);
2244 }
2245
2246 static void gen_calc_usb_mulr_h(TCGv arg)
2247 {
2248 TCGv temp = tcg_temp_new();
2249 /* calc AV bit */
2250 tcg_gen_add_tl(temp, arg, arg);
2251 tcg_gen_xor_tl(temp, temp, arg);
2252 tcg_gen_shli_tl(cpu_PSW_AV, temp, 16);
2253 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp);
2254 /* calc SAV bit */
2255 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2256 /* clear V bit */
2257 tcg_gen_movi_tl(cpu_PSW_V, 0);
2258 tcg_temp_free(temp);
2259 }
2260
2261 /* helpers for generating program flow micro-ops */
2262
2263 static inline void gen_save_pc(target_ulong pc)
2264 {
2265 tcg_gen_movi_tl(cpu_PC, pc);
2266 }
2267
2268 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
2269 {
2270 TranslationBlock *tb;
2271 tb = ctx->tb;
2272 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
2273 likely(!ctx->singlestep_enabled)) {
2274 tcg_gen_goto_tb(n);
2275 gen_save_pc(dest);
2276 tcg_gen_exit_tb((uintptr_t)tb + n);
2277 } else {
2278 gen_save_pc(dest);
2279 if (ctx->singlestep_enabled) {
2280 /* raise exception debug */
2281 }
2282 tcg_gen_exit_tb(0);
2283 }
2284 }
2285
2286 static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1,
2287 TCGv r2, int16_t address)
2288 {
2289 int jumpLabel;
2290 jumpLabel = gen_new_label();
2291 tcg_gen_brcond_tl(cond, r1, r2, jumpLabel);
2292
2293 gen_goto_tb(ctx, 1, ctx->next_pc);
2294
2295 gen_set_label(jumpLabel);
2296 gen_goto_tb(ctx, 0, ctx->pc + address * 2);
2297 }
2298
2299 static inline void gen_branch_condi(DisasContext *ctx, TCGCond cond, TCGv r1,
2300 int r2, int16_t address)
2301 {
2302 TCGv temp = tcg_const_i32(r2);
2303 gen_branch_cond(ctx, cond, r1, temp, address);
2304 tcg_temp_free(temp);
2305 }
2306
2307 static void gen_loop(DisasContext *ctx, int r1, int32_t offset)
2308 {
2309 int l1;
2310 l1 = gen_new_label();
2311
2312 tcg_gen_subi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], 1);
2313 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr_a[r1], -1, l1);
2314 gen_goto_tb(ctx, 1, ctx->pc + offset);
2315 gen_set_label(l1);
2316 gen_goto_tb(ctx, 0, ctx->next_pc);
2317 }
2318
2319 static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
2320 int r2 , int32_t constant , int32_t offset)
2321 {
2322 TCGv temp, temp2;
2323 int n;
2324
2325 switch (opc) {
2326 /* SB-format jumps */
2327 case OPC1_16_SB_J:
2328 case OPC1_32_B_J:
2329 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
2330 break;
2331 case OPC1_32_B_CALL:
2332 case OPC1_16_SB_CALL:
2333 gen_helper_1arg(call, ctx->next_pc);
2334 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
2335 break;
2336 case OPC1_16_SB_JZ:
2337 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], 0, offset);
2338 break;
2339 case OPC1_16_SB_JNZ:
2340 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 0, offset);
2341 break;
2342 /* SBC-format jumps */
2343 case OPC1_16_SBC_JEQ:
2344 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, offset);
2345 break;
2346 case OPC1_16_SBC_JNE:
2347 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset);
2348 break;
2349 /* SBRN-format jumps */
2350 case OPC1_16_SBRN_JZ_T:
2351 temp = tcg_temp_new();
2352 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
2353 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset);
2354 tcg_temp_free(temp);
2355 break;
2356 case OPC1_16_SBRN_JNZ_T:
2357 temp = tcg_temp_new();
2358 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
2359 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset);
2360 tcg_temp_free(temp);
2361 break;
2362 /* SBR-format jumps */
2363 case OPC1_16_SBR_JEQ:
2364 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15],
2365 offset);
2366 break;
2367 case OPC1_16_SBR_JNE:
2368 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15],
2369 offset);
2370 break;
2371 case OPC1_16_SBR_JNZ:
2372 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], 0, offset);
2373 break;
2374 case OPC1_16_SBR_JNZ_A:
2375 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset);
2376 break;
2377 case OPC1_16_SBR_JGEZ:
2378 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], 0, offset);
2379 break;
2380 case OPC1_16_SBR_JGTZ:
2381 gen_branch_condi(ctx, TCG_COND_GT, cpu_gpr_d[r1], 0, offset);
2382 break;
2383 case OPC1_16_SBR_JLEZ:
2384 gen_branch_condi(ctx, TCG_COND_LE, cpu_gpr_d[r1], 0, offset);
2385 break;
2386 case OPC1_16_SBR_JLTZ:
2387 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], 0, offset);
2388 break;
2389 case OPC1_16_SBR_JZ:
2390 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], 0, offset);
2391 break;
2392 case OPC1_16_SBR_JZ_A:
2393 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset);
2394 break;
2395 case OPC1_16_SBR_LOOP:
2396 gen_loop(ctx, r1, offset * 2 - 32);
2397 break;
2398 /* SR-format jumps */
2399 case OPC1_16_SR_JI:
2400 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], 0xfffffffe);
2401 tcg_gen_exit_tb(0);
2402 break;
2403 case OPC2_16_SR_RET:
2404 gen_helper_ret(cpu_env);
2405 tcg_gen_exit_tb(0);
2406 break;
2407 /* B-format */
2408 case OPC1_32_B_CALLA:
2409 gen_helper_1arg(call, ctx->next_pc);
2410 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
2411 break;
2412 case OPC1_32_B_JLA:
2413 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc);
2414 /* fall through */
2415 case OPC1_32_B_JA:
2416 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
2417 break;
2418 case OPC1_32_B_JL:
2419 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc);
2420 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
2421 break;
2422 /* BOL format */
2423 case OPCM_32_BRC_EQ_NEQ:
2424 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JEQ) {
2425 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], constant, offset);
2426 } else {
2427 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], constant, offset);
2428 }
2429 break;
2430 case OPCM_32_BRC_GE:
2431 if (MASK_OP_BRC_OP2(ctx->opcode) == OP2_32_BRC_JGE) {
2432 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], constant, offset);
2433 } else {
2434 constant = MASK_OP_BRC_CONST4(ctx->opcode);
2435 gen_branch_condi(ctx, TCG_COND_GEU, cpu_gpr_d[r1], constant,
2436 offset);
2437 }
2438 break;
2439 case OPCM_32_BRC_JLT:
2440 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JLT) {
2441 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], constant, offset);
2442 } else {
2443 constant = MASK_OP_BRC_CONST4(ctx->opcode);
2444 gen_branch_condi(ctx, TCG_COND_LTU, cpu_gpr_d[r1], constant,
2445 offset);
2446 }
2447 break;
2448 case OPCM_32_BRC_JNE:
2449 temp = tcg_temp_new();
2450 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JNED) {
2451 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
2452 /* subi is unconditional */
2453 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
2454 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset);
2455 } else {
2456 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
2457 /* addi is unconditional */
2458 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
2459 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset);
2460 }
2461 tcg_temp_free(temp);
2462 break;
2463 /* BRN format */
2464 case OPCM_32_BRN_JTT:
2465 n = MASK_OP_BRN_N(ctx->opcode);
2466
2467 temp = tcg_temp_new();
2468 tcg_gen_andi_tl(temp, cpu_gpr_d[r1], (1 << n));
2469
2470 if (MASK_OP_BRN_OP2(ctx->opcode) == OPC2_32_BRN_JNZ_T) {
2471 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset);
2472 } else {
2473 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset);
2474 }
2475 tcg_temp_free(temp);
2476 break;
2477 /* BRR Format */
2478 case OPCM_32_BRR_EQ_NEQ:
2479 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ) {
2480 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2],
2481 offset);
2482 } else {
2483 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2],
2484 offset);
2485 }
2486 break;
2487 case OPCM_32_BRR_ADDR_EQ_NEQ:
2488 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ_A) {
2489 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_a[r1], cpu_gpr_a[r2],
2490 offset);
2491 } else {
2492 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_a[r1], cpu_gpr_a[r2],
2493 offset);
2494 }
2495 break;
2496 case OPCM_32_BRR_GE:
2497 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JGE) {
2498 gen_branch_cond(ctx, TCG_COND_GE, cpu_gpr_d[r1], cpu_gpr_d[r2],
2499 offset);
2500 } else {
2501 gen_branch_cond(ctx, TCG_COND_GEU, cpu_gpr_d[r1], cpu_gpr_d[r2],
2502 offset);
2503 }
2504 break;
2505 case OPCM_32_BRR_JLT:
2506 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JLT) {
2507 gen_branch_cond(ctx, TCG_COND_LT, cpu_gpr_d[r1], cpu_gpr_d[r2],
2508 offset);
2509 } else {
2510 gen_branch_cond(ctx, TCG_COND_LTU, cpu_gpr_d[r1], cpu_gpr_d[r2],
2511 offset);
2512 }
2513 break;
2514 case OPCM_32_BRR_LOOP:
2515 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_LOOP) {
2516 gen_loop(ctx, r1, offset * 2);
2517 } else {
2518 /* OPC2_32_BRR_LOOPU */
2519 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
2520 }
2521 break;
2522 case OPCM_32_BRR_JNE:
2523 temp = tcg_temp_new();
2524 temp2 = tcg_temp_new();
2525 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRR_JNED) {
2526 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
2527 /* also save r2, in case of r1 == r2, so r2 is not decremented */
2528 tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]);
2529 /* subi is unconditional */
2530 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
2531 gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset);
2532 } else {
2533 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
2534 /* also save r2, in case of r1 == r2, so r2 is not decremented */
2535 tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]);
2536 /* addi is unconditional */
2537 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
2538 gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset);
2539 }
2540 tcg_temp_free(temp);
2541 tcg_temp_free(temp2);
2542 break;
2543 case OPCM_32_BRR_JNZ:
2544 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JNZ_A) {
2545 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset);
2546 } else {
2547 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset);
2548 }
2549 break;
2550 default:
2551 printf("Branch Error at %x\n", ctx->pc);
2552 }
2553 ctx->bstate = BS_BRANCH;
2554 }
2555
2556
2557 /*
2558 * Functions for decoding instructions
2559 */
2560
2561 static void decode_src_opc(DisasContext *ctx, int op1)
2562 {
2563 int r1;
2564 int32_t const4;
2565 TCGv temp, temp2;
2566
2567 r1 = MASK_OP_SRC_S1D(ctx->opcode);
2568 const4 = MASK_OP_SRC_CONST4_SEXT(ctx->opcode);
2569
2570 switch (op1) {
2571 case OPC1_16_SRC_ADD:
2572 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
2573 break;
2574 case OPC1_16_SRC_ADD_A15:
2575 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[15], const4);
2576 break;
2577 case OPC1_16_SRC_ADD_15A:
2578 gen_addi_d(cpu_gpr_d[15], cpu_gpr_d[r1], const4);
2579 break;
2580 case OPC1_16_SRC_ADD_A:
2581 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], const4);
2582 break;
2583 case OPC1_16_SRC_CADD:
2584 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const4, cpu_gpr_d[r1],
2585 cpu_gpr_d[15]);
2586 break;
2587 case OPC1_16_SRC_CADDN:
2588 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const4, cpu_gpr_d[r1],
2589 cpu_gpr_d[15]);
2590 break;
2591 case OPC1_16_SRC_CMOV:
2592 temp = tcg_const_tl(0);
2593 temp2 = tcg_const_tl(const4);
2594 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
2595 temp2, cpu_gpr_d[r1]);
2596 tcg_temp_free(temp);
2597 tcg_temp_free(temp2);
2598 break;
2599 case OPC1_16_SRC_CMOVN:
2600 temp = tcg_const_tl(0);
2601 temp2 = tcg_const_tl(const4);
2602 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
2603 temp2, cpu_gpr_d[r1]);
2604 tcg_temp_free(temp);
2605 tcg_temp_free(temp2);
2606 break;
2607 case OPC1_16_SRC_EQ:
2608 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
2609 const4);
2610 break;
2611 case OPC1_16_SRC_LT:
2612 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
2613 const4);
2614 break;
2615 case OPC1_16_SRC_MOV:
2616 tcg_gen_movi_tl(cpu_gpr_d[r1], const4);
2617 break;
2618 case OPC1_16_SRC_MOV_A:
2619 const4 = MASK_OP_SRC_CONST4(ctx->opcode);
2620 tcg_gen_movi_tl(cpu_gpr_a[r1], const4);
2621 break;
2622 case OPC1_16_SRC_SH:
2623 gen_shi(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
2624 break;
2625 case OPC1_16_SRC_SHA:
2626 gen_shaci(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
2627 break;
2628 }
2629 }
2630
2631 static void decode_srr_opc(DisasContext *ctx, int op1)
2632 {
2633 int r1, r2;
2634 TCGv temp;
2635
2636 r1 = MASK_OP_SRR_S1D(ctx->opcode);
2637 r2 = MASK_OP_SRR_S2(ctx->opcode);
2638
2639 switch (op1) {
2640 case OPC1_16_SRR_ADD:
2641 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
2642 break;
2643 case OPC1_16_SRR_ADD_A15:
2644 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]);
2645 break;
2646 case OPC1_16_SRR_ADD_15A:
2647 gen_add_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
2648 break;
2649 case OPC1_16_SRR_ADD_A:
2650 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], cpu_gpr_a[r2]);
2651 break;
2652 case OPC1_16_SRR_ADDS:
2653 gen_adds(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
2654 break;
2655 case OPC1_16_SRR_AND:
2656 tcg_gen_and_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
2657 break;
2658 case OPC1_16_SRR_CMOV:
2659 temp = tcg_const_tl(0);
2660 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
2661 cpu_gpr_d[r2], cpu_gpr_d[r1]);
2662 tcg_temp_free(temp);
2663 break;
2664 case OPC1_16_SRR_CMOVN:
2665 temp = tcg_const_tl(0);
2666 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
2667 cpu_gpr_d[r2], cpu_gpr_d[r1]);
2668 tcg_temp_free(temp);
2669 break;
2670 case OPC1_16_SRR_EQ:
2671 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
2672 cpu_gpr_d[r2]);
2673 break;
2674 case OPC1_16_SRR_LT:
2675 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
2676 cpu_gpr_d[r2]);
2677 break;
2678 case OPC1_16_SRR_MOV:
2679 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_d[r2]);
2680 break;
2681 case OPC1_16_SRR_MOV_A:
2682 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_d[r2]);
2683 break;
2684 case OPC1_16_SRR_MOV_AA:
2685 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_a[r2]);
2686 break;
2687 case OPC1_16_SRR_MOV_D:
2688 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_a[r2]);
2689 break;
2690 case OPC1_16_SRR_MUL:
2691 gen_mul_i32s(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
2692 break;
2693 case OPC1_16_SRR_OR:
2694 tcg_gen_or_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
2695 break;
2696 case OPC1_16_SRR_SUB:
2697 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
2698 break;
2699 case OPC1_16_SRR_SUB_A15B:
2700 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]);
2701 break;
2702 case OPC1_16_SRR_SUB_15AB:
2703 gen_sub_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
2704 break;
2705 case OPC1_16_SRR_SUBS:
2706 gen_subs(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
2707 break;
2708 case OPC1_16_SRR_XOR:
2709 tcg_gen_xor_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
2710 break;
2711 }
2712 }
2713
2714 static void decode_ssr_opc(DisasContext *ctx, int op1)
2715 {
2716 int r1, r2;
2717
2718 r1 = MASK_OP_SSR_S1(ctx->opcode);
2719 r2 = MASK_OP_SSR_S2(ctx->opcode);
2720
2721 switch (op1) {
2722 case OPC1_16_SSR_ST_A:
2723 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
2724 break;
2725 case OPC1_16_SSR_ST_A_POSTINC:
2726 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
2727 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
2728 break;
2729 case OPC1_16_SSR_ST_B:
2730 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
2731 break;
2732 case OPC1_16_SSR_ST_B_POSTINC:
2733 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
2734 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
2735 break;
2736 case OPC1_16_SSR_ST_H:
2737 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
2738 break;
2739 case OPC1_16_SSR_ST_H_POSTINC:
2740 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
2741 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
2742 break;
2743 case OPC1_16_SSR_ST_W:
2744 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
2745 break;
2746 case OPC1_16_SSR_ST_W_POSTINC:
2747 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
2748 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
2749 break;
2750 }
2751 }
2752
2753 static void decode_sc_opc(DisasContext *ctx, int op1)
2754 {
2755 int32_t const16;
2756
2757 const16 = MASK_OP_SC_CONST8(ctx->opcode);
2758
2759 switch (op1) {
2760 case OPC1_16_SC_AND:
2761 tcg_gen_andi_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
2762 break;
2763 case OPC1_16_SC_BISR:
2764 gen_helper_1arg(bisr, const16 & 0xff);
2765 break;
2766 case OPC1_16_SC_LD_A:
2767 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
2768 break;
2769 case OPC1_16_SC_LD_W:
2770 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
2771 break;
2772 case OPC1_16_SC_MOV:
2773 tcg_gen_movi_tl(cpu_gpr_d[15], const16);
2774 break;
2775 case OPC1_16_SC_OR:
2776 tcg_gen_ori_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
2777 break;
2778 case OPC1_16_SC_ST_A:
2779 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
2780 break;
2781 case OPC1_16_SC_ST_W:
2782 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
2783 break;
2784 case OPC1_16_SC_SUB_A:
2785 tcg_gen_subi_tl(cpu_gpr_a[10], cpu_gpr_a[10], const16);
2786 break;
2787 }
2788 }
2789
2790 static void decode_slr_opc(DisasContext *ctx, int op1)
2791 {
2792 int r1, r2;
2793
2794 r1 = MASK_OP_SLR_D(ctx->opcode);
2795 r2 = MASK_OP_SLR_S2(ctx->opcode);
2796
2797 switch (op1) {
2798 /* SLR-format */
2799 case OPC1_16_SLR_LD_A:
2800 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
2801 break;
2802 case OPC1_16_SLR_LD_A_POSTINC:
2803 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
2804 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
2805 break;
2806 case OPC1_16_SLR_LD_BU:
2807 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
2808 break;
2809 case OPC1_16_SLR_LD_BU_POSTINC:
2810 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
2811 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
2812 break;
2813 case OPC1_16_SLR_LD_H:
2814 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
2815 break;
2816 case OPC1_16_SLR_LD_H_POSTINC:
2817 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
2818 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
2819 break;
2820 case OPC1_16_SLR_LD_W:
2821 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
2822 break;
2823 case OPC1_16_SLR_LD_W_POSTINC:
2824 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
2825 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
2826 break;
2827 }
2828 }
2829
2830 static void decode_sro_opc(DisasContext *ctx, int op1)
2831 {
2832 int r2;
2833 int32_t address;
2834
2835 r2 = MASK_OP_SRO_S2(ctx->opcode);
2836 address = MASK_OP_SRO_OFF4(ctx->opcode);
2837
2838 /* SRO-format */
2839 switch (op1) {
2840 case OPC1_16_SRO_LD_A:
2841 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL);
2842 break;
2843 case OPC1_16_SRO_LD_BU:
2844 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
2845 break;
2846 case OPC1_16_SRO_LD_H:
2847 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_LESW);
2848 break;
2849 case OPC1_16_SRO_LD_W:
2850 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
2851 break;
2852 case OPC1_16_SRO_ST_A:
2853 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL);
2854 break;
2855 case OPC1_16_SRO_ST_B:
2856 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
2857 break;
2858 case OPC1_16_SRO_ST_H:
2859 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW);
2860 break;
2861 case OPC1_16_SRO_ST_W:
2862 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
2863 break;
2864 }
2865 }
2866
2867 static void decode_sr_system(CPUTriCoreState *env, DisasContext *ctx)
2868 {
2869 uint32_t op2;
2870 op2 = MASK_OP_SR_OP2(ctx->opcode);
2871
2872 switch (op2) {
2873 case OPC2_16_SR_NOP:
2874 break;
2875 case OPC2_16_SR_RET:
2876 gen_compute_branch(ctx, op2, 0, 0, 0, 0);
2877 break;
2878 case OPC2_16_SR_RFE:
2879 gen_helper_rfe(cpu_env);
2880 tcg_gen_exit_tb(0);
2881 ctx->bstate = BS_BRANCH;
2882 break;
2883 case OPC2_16_SR_DEBUG:
2884 /* raise EXCP_DEBUG */
2885 break;
2886 }
2887 }
2888
2889 static void decode_sr_accu(CPUTriCoreState *env, DisasContext *ctx)
2890 {
2891 uint32_t op2;
2892 uint32_t r1;
2893 TCGv temp;
2894
2895 r1 = MASK_OP_SR_S1D(ctx->opcode);
2896 op2 = MASK_OP_SR_OP2(ctx->opcode);
2897
2898 switch (op2) {
2899 case OPC2_16_SR_RSUB:
2900 /* overflow only if r1 = -0x80000000 */
2901 temp = tcg_const_i32(-0x80000000);
2902 /* calc V bit */
2903 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r1], temp);
2904 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
2905 /* calc SV bit */
2906 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2907 /* sub */
2908 tcg_gen_neg_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]);
2909 /* calc av */
2910 tcg_gen_add_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_gpr_d[r1]);
2911 tcg_gen_xor_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_PSW_AV);
2912 /* calc sav */
2913 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2914 tcg_temp_free(temp);
2915 break;
2916 case OPC2_16_SR_SAT_B:
2917 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7f, -0x80);
2918 break;
2919 case OPC2_16_SR_SAT_BU:
2920 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xff);
2921 break;
2922 case OPC2_16_SR_SAT_H:
2923 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7fff, -0x8000);
2924 break;
2925 case OPC2_16_SR_SAT_HU:
2926 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xffff);
2927 break;
2928 }
2929 }
2930
2931 static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
2932 {
2933 int op1;
2934 int r1, r2;
2935 int32_t const16;
2936 int32_t address;
2937 TCGv temp;
2938
2939 op1 = MASK_OP_MAJOR(ctx->opcode);
2940
2941 /* handle ADDSC.A opcode only being 6 bit long */
2942 if (unlikely((op1 & 0x3f) == OPC1_16_SRRS_ADDSC_A)) {
2943 op1 = OPC1_16_SRRS_ADDSC_A;
2944 }
2945
2946 switch (op1) {
2947 case OPC1_16_SRC_ADD:
2948 case OPC1_16_SRC_ADD_A15:
2949 case OPC1_16_SRC_ADD_15A:
2950 case OPC1_16_SRC_ADD_A:
2951 case OPC1_16_SRC_CADD:
2952 case OPC1_16_SRC_CADDN:
2953 case OPC1_16_SRC_CMOV:
2954 case OPC1_16_SRC_CMOVN:
2955 case OPC1_16_SRC_EQ:
2956 case OPC1_16_SRC_LT:
2957 case OPC1_16_SRC_MOV:
2958 case OPC1_16_SRC_MOV_A:
2959 case OPC1_16_SRC_SH:
2960 case OPC1_16_SRC_SHA:
2961 decode_src_opc(ctx, op1);
2962 break;
2963 /* SRR-format */
2964 case OPC1_16_SRR_ADD:
2965 case OPC1_16_SRR_ADD_A15:
2966 case OPC1_16_SRR_ADD_15A:
2967 case OPC1_16_SRR_ADD_A:
2968 case OPC1_16_SRR_ADDS:
2969 case OPC1_16_SRR_AND:
2970 case OPC1_16_SRR_CMOV:
2971 case OPC1_16_SRR_CMOVN:
2972 case OPC1_16_SRR_EQ:
2973 case OPC1_16_SRR_LT:
2974 case OPC1_16_SRR_MOV:
2975 case OPC1_16_SRR_MOV_A:
2976 case OPC1_16_SRR_MOV_AA:
2977 case OPC1_16_SRR_MOV_D:
2978 case OPC1_16_SRR_MUL:
2979 case OPC1_16_SRR_OR:
2980 case OPC1_16_SRR_SUB:
2981 case OPC1_16_SRR_SUB_A15B:
2982 case OPC1_16_SRR_SUB_15AB:
2983 case OPC1_16_SRR_SUBS:
2984 case OPC1_16_SRR_XOR:
2985 decode_srr_opc(ctx, op1);
2986 break;
2987 /* SSR-format */
2988 case OPC1_16_SSR_ST_A:
2989 case OPC1_16_SSR_ST_A_POSTINC:
2990 case OPC1_16_SSR_ST_B:
2991 case OPC1_16_SSR_ST_B_POSTINC:
2992 case OPC1_16_SSR_ST_H:
2993 case OPC1_16_SSR_ST_H_POSTINC:
2994 case OPC1_16_SSR_ST_W:
2995 case OPC1_16_SSR_ST_W_POSTINC:
2996 decode_ssr_opc(ctx, op1);
2997 break;
2998 /* SRRS-format */
2999 case OPC1_16_SRRS_ADDSC_A:
3000 r2 = MASK_OP_SRRS_S2(ctx->opcode);
3001 r1 = MASK_OP_SRRS_S1D(ctx->opcode);
3002 const16 = MASK_OP_SRRS_N(ctx->opcode);
3003 temp = tcg_temp_new();
3004 tcg_gen_shli_tl(temp, cpu_gpr_d[15], const16);
3005 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], temp);
3006 tcg_temp_free(temp);
3007 break;
3008 /* SLRO-format */
3009 case OPC1_16_SLRO_LD_A:
3010 r1 = MASK_OP_SLRO_D(ctx->opcode);
3011 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
3012 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
3013 break;
3014 case OPC1_16_SLRO_LD_BU:
3015 r1 = MASK_OP_SLRO_D(ctx->opcode);
3016 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
3017 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB);
3018 break;
3019 case OPC1_16_SLRO_LD_H:
3020 r1 = MASK_OP_SLRO_D(ctx->opcode);
3021 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
3022 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW);
3023 break;
3024 case OPC1_16_SLRO_LD_W:
3025 r1 = MASK_OP_SLRO_D(ctx->opcode);
3026 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
3027 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
3028 break;
3029 /* SB-format */
3030 case OPC1_16_SB_CALL:
3031 case OPC1_16_SB_J:
3032 case OPC1_16_SB_JNZ:
3033 case OPC1_16_SB_JZ:
3034 address = MASK_OP_SB_DISP8_SEXT(ctx->opcode);
3035 gen_compute_branch(ctx, op1, 0, 0, 0, address);
3036 break;
3037 /* SBC-format */
3038 case OPC1_16_SBC_JEQ:
3039 case OPC1_16_SBC_JNE:
3040 address = MASK_OP_SBC_DISP4(ctx->opcode);
3041 const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode);
3042 gen_compute_branch(ctx, op1, 0, 0, const16, address);
3043 break;
3044 /* SBRN-format */
3045 case OPC1_16_SBRN_JNZ_T:
3046 case OPC1_16_SBRN_JZ_T:
3047 address = MASK_OP_SBRN_DISP4(ctx->opcode);
3048 const16 = MASK_OP_SBRN_N(ctx->opcode);
3049 gen_compute_branch(ctx, op1, 0, 0, const16, address);
3050 break;
3051 /* SBR-format */
3052 case OPC1_16_SBR_JEQ:
3053 case OPC1_16_SBR_JGEZ:
3054 case OPC1_16_SBR_JGTZ:
3055 case OPC1_16_SBR_JLEZ:
3056 case OPC1_16_SBR_JLTZ:
3057 case OPC1_16_SBR_JNE:
3058 case OPC1_16_SBR_JNZ:
3059 case OPC1_16_SBR_JNZ_A:
3060 case OPC1_16_SBR_JZ:
3061 case OPC1_16_SBR_JZ_A:
3062 case OPC1_16_SBR_LOOP:
3063 r1 = MASK_OP_SBR_S2(ctx->opcode);
3064 address = MASK_OP_SBR_DISP4(ctx->opcode);
3065 gen_compute_branch(ctx, op1, r1, 0, 0, address);
3066 break;
3067 /* SC-format */
3068 case OPC1_16_SC_AND:
3069 case OPC1_16_SC_BISR:
3070 case OPC1_16_SC_LD_A:
3071 case OPC1_16_SC_LD_W:
3072 case OPC1_16_SC_MOV:
3073 case OPC1_16_SC_OR:
3074 case OPC1_16_SC_ST_A:
3075 case OPC1_16_SC_ST_W:
3076 case OPC1_16_SC_SUB_A:
3077 decode_sc_opc(ctx, op1);
3078 break;
3079 /* SLR-format */
3080 case OPC1_16_SLR_LD_A:
3081 case OPC1_16_SLR_LD_A_POSTINC:
3082 case OPC1_16_SLR_LD_BU:
3083 case OPC1_16_SLR_LD_BU_POSTINC:
3084 case OPC1_16_SLR_LD_H:
3085 case OPC1_16_SLR_LD_H_POSTINC:
3086 case OPC1_16_SLR_LD_W:
3087 case OPC1_16_SLR_LD_W_POSTINC:
3088 decode_slr_opc(ctx, op1);
3089 break;
3090 /* SRO-format */
3091 case OPC1_16_SRO_LD_A:
3092 case OPC1_16_SRO_LD_BU:
3093 case OPC1_16_SRO_LD_H:
3094 case OPC1_16_SRO_LD_W:
3095 case OPC1_16_SRO_ST_A:
3096 case OPC1_16_SRO_ST_B:
3097 case OPC1_16_SRO_ST_H:
3098 case OPC1_16_SRO_ST_W:
3099 decode_sro_opc(ctx, op1);
3100 break;
3101 /* SSRO-format */
3102 case OPC1_16_SSRO_ST_A:
3103 r1 = MASK_OP_SSRO_S1(ctx->opcode);
3104 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
3105 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
3106 break;
3107 case OPC1_16_SSRO_ST_B:
3108 r1 = MASK_OP_SSRO_S1(ctx->opcode);
3109 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
3110 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB);
3111 break;
3112 case OPC1_16_SSRO_ST_H:
3113 r1 = MASK_OP_SSRO_S1(ctx->opcode);
3114 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
3115 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW);
3116 break;
3117 case OPC1_16_SSRO_ST_W:
3118 r1 = MASK_OP_SSRO_S1(ctx->opcode);
3119 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
3120 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
3121 break;
3122 /* SR-format */
3123 case OPCM_16_SR_SYSTEM:
3124 decode_sr_system(env, ctx);
3125 break;
3126 case OPCM_16_SR_ACCU:
3127 decode_sr_accu(env, ctx);
3128 break;
3129 case OPC1_16_SR_JI:
3130 r1 = MASK_OP_SR_S1D(ctx->opcode);
3131 gen_compute_branch(ctx, op1, r1, 0, 0, 0);
3132 break;
3133 case OPC1_16_SR_NOT:
3134 r1 = MASK_OP_SR_S1D(ctx->opcode);
3135 tcg_gen_not_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]);
3136 break;
3137 }
3138 }
3139
3140 /*
3141 * 32 bit instructions
3142 */
3143
3144 /* ABS-format */
3145 static void decode_abs_ldw(CPUTriCoreState *env, DisasContext *ctx)
3146 {
3147 int32_t op2;
3148 int32_t r1;
3149 uint32_t address;
3150 TCGv temp;
3151
3152 r1 = MASK_OP_ABS_S1D(ctx->opcode);
3153 address = MASK_OP_ABS_OFF18(ctx->opcode);
3154 op2 = MASK_OP_ABS_OP2(ctx->opcode);
3155
3156 temp = tcg_const_i32(EA_ABS_FORMAT(address));
3157
3158 switch (op2) {
3159 case OPC2_32_ABS_LD_A:
3160 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL);
3161 break;
3162 case OPC2_32_ABS_LD_D:
3163 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
3164 break;
3165 case OPC2_32_ABS_LD_DA:
3166 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
3167 break;
3168 case OPC2_32_ABS_LD_W:
3169 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
3170 break;
3171 }
3172
3173 tcg_temp_free(temp);
3174 }
3175
3176 static void decode_abs_ldb(CPUTriCoreState *env, DisasContext *ctx)
3177 {
3178 int32_t op2;
3179 int32_t r1;
3180 uint32_t address;
3181 TCGv temp;
3182
3183 r1 = MASK_OP_ABS_S1D(ctx->opcode);
3184 address = MASK_OP_ABS_OFF18(ctx->opcode);
3185 op2 = MASK_OP_ABS_OP2(ctx->opcode);
3186
3187 temp = tcg_const_i32(EA_ABS_FORMAT(address));
3188
3189 switch (op2) {
3190 case OPC2_32_ABS_LD_B:
3191 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_SB);
3192 break;
3193 case OPC2_32_ABS_LD_BU:
3194 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB);
3195 break;
3196 case OPC2_32_ABS_LD_H:
3197 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESW);
3198 break;
3199 case OPC2_32_ABS_LD_HU:
3200 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
3201 break;
3202 }
3203
3204 tcg_temp_free(temp);
3205 }
3206
3207 static void decode_abs_ldst_swap(CPUTriCoreState *env, DisasContext *ctx)
3208 {
3209 int32_t op2;
3210 int32_t r1;
3211 uint32_t address;
3212 TCGv temp;
3213
3214 r1 = MASK_OP_ABS_S1D(ctx->opcode);
3215 address = MASK_OP_ABS_OFF18(ctx->opcode);
3216 op2 = MASK_OP_ABS_OP2(ctx->opcode);
3217
3218 temp = tcg_const_i32(EA_ABS_FORMAT(address));
3219
3220 switch (op2) {
3221 case OPC2_32_ABS_LDMST:
3222 gen_ldmst(ctx, r1, temp);
3223 break;
3224 case OPC2_32_ABS_SWAP_W:
3225 gen_swap(ctx, r1, temp);
3226 break;
3227 }
3228
3229 tcg_temp_free(temp);
3230 }
3231
3232 static void decode_abs_ldst_context(CPUTriCoreState *env, DisasContext *ctx)
3233 {
3234 uint32_t op2;
3235 int32_t off18;
3236
3237 off18 = MASK_OP_ABS_OFF18(ctx->opcode);
3238 op2 = MASK_OP_ABS_OP2(ctx->opcode);
3239
3240 switch (op2) {
3241 case OPC2_32_ABS_LDLCX:
3242 gen_helper_1arg(ldlcx, EA_ABS_FORMAT(off18));
3243 break;
3244 case OPC2_32_ABS_LDUCX:
3245 gen_helper_1arg(lducx, EA_ABS_FORMAT(off18));
3246 break;
3247 case OPC2_32_ABS_STLCX:
3248 gen_helper_1arg(stlcx, EA_ABS_FORMAT(off18));
3249 break;
3250 case OPC2_32_ABS_STUCX:
3251 gen_helper_1arg(stucx, EA_ABS_FORMAT(off18));
3252 break;
3253 }
3254 }
3255
3256 static void decode_abs_store(CPUTriCoreState *env, DisasContext *ctx)
3257 {
3258 int32_t op2;
3259 int32_t r1;
3260 uint32_t address;
3261 TCGv temp;
3262
3263 r1 = MASK_OP_ABS_S1D(ctx->opcode);
3264 address = MASK_OP_ABS_OFF18(ctx->opcode);
3265 op2 = MASK_OP_ABS_OP2(ctx->opcode);
3266
3267 temp = tcg_const_i32(EA_ABS_FORMAT(address));
3268
3269 switch (op2) {
3270 case OPC2_32_ABS_ST_A:
3271 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL);
3272 break;
3273 case OPC2_32_ABS_ST_D:
3274 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
3275 break;
3276 case OPC2_32_ABS_ST_DA:
3277 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
3278 break;
3279 case OPC2_32_ABS_ST_W:
3280 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
3281 break;
3282
3283 }
3284 tcg_temp_free(temp);
3285 }
3286
3287 static void decode_abs_storeb_h(CPUTriCoreState *env, DisasContext *ctx)
3288 {
3289 int32_t op2;
3290 int32_t r1;
3291 uint32_t address;
3292 TCGv temp;
3293
3294 r1 = MASK_OP_ABS_S1D(ctx->opcode);
3295 address = MASK_OP_ABS_OFF18(ctx->opcode);
3296 op2 = MASK_OP_ABS_OP2(ctx->opcode);
3297
3298 temp = tcg_const_i32(EA_ABS_FORMAT(address));
3299
3300 switch (op2) {
3301 case OPC2_32_ABS_ST_B:
3302 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB);
3303 break;
3304 case OPC2_32_ABS_ST_H:
3305 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
3306 break;
3307 }
3308 tcg_temp_free(temp);
3309 }
3310
3311 /* Bit-format */
3312
3313 static void decode_bit_andacc(CPUTriCoreState *env, DisasContext *ctx)
3314 {
3315 uint32_t op2;
3316 int r1, r2, r3;
3317 int pos1, pos2;
3318
3319 r1 = MASK_OP_BIT_S1(ctx->opcode);
3320 r2 = MASK_OP_BIT_S2(ctx->opcode);
3321 r3 = MASK_OP_BIT_D(ctx->opcode);
3322 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
3323 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
3324 op2 = MASK_OP_BIT_OP2(ctx->opcode);
3325
3326
3327 switch (op2) {
3328 case OPC2_32_BIT_AND_AND_T:
3329 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3330 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_and_tl);
3331 break;
3332 case OPC2_32_BIT_AND_ANDN_T:
3333 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3334 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_and_tl);
3335 break;
3336 case OPC2_32_BIT_AND_NOR_T:
3337 if (TCG_TARGET_HAS_andc_i32) {
3338 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3339 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_andc_tl);
3340 } else {
3341 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3342 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_and_tl);
3343 }
3344 break;
3345 case OPC2_32_BIT_AND_OR_T:
3346 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3347 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_and_tl);
3348 break;
3349 }
3350 }
3351
3352 static void decode_bit_logical_t(CPUTriCoreState *env, DisasContext *ctx)
3353 {
3354 uint32_t op2;
3355 int r1, r2, r3;
3356 int pos1, pos2;
3357 r1 = MASK_OP_BIT_S1(ctx->opcode);
3358 r2 = MASK_OP_BIT_S2(ctx->opcode);
3359 r3 = MASK_OP_BIT_D(ctx->opcode);
3360 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
3361 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
3362 op2 = MASK_OP_BIT_OP2(ctx->opcode);
3363
3364 switch (op2) {
3365 case OPC2_32_BIT_AND_T:
3366 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3367 pos1, pos2, &tcg_gen_and_tl);
3368 break;
3369 case OPC2_32_BIT_ANDN_T:
3370 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3371 pos1, pos2, &tcg_gen_andc_tl);
3372 break;
3373 case OPC2_32_BIT_NOR_T:
3374 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3375 pos1, pos2, &tcg_gen_nor_tl);
3376 break;
3377 case OPC2_32_BIT_OR_T:
3378 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3379 pos1, pos2, &tcg_gen_or_tl);
3380 break;
3381 }
3382 }
3383
3384 static void decode_bit_insert(CPUTriCoreState *env, DisasContext *ctx)
3385 {
3386 uint32_t op2;
3387 int r1, r2, r3;
3388 int pos1, pos2;
3389 TCGv temp;
3390 op2 = MASK_OP_BIT_OP2(ctx->opcode);
3391 r1 = MASK_OP_BIT_S1(ctx->opcode);
3392 r2 = MASK_OP_BIT_S2(ctx->opcode);
3393 r3 = MASK_OP_BIT_D(ctx->opcode);
3394 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
3395 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
3396
3397 temp = tcg_temp_new();
3398
3399 tcg_gen_shri_tl(temp, cpu_gpr_d[r2], pos2);
3400 if (op2 == OPC2_32_BIT_INSN_T) {
3401 tcg_gen_not_tl(temp, temp);
3402 }
3403 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, pos1, 1);
3404 tcg_temp_free(temp);
3405 }
3406
3407 static void decode_bit_logical_t2(CPUTriCoreState *env, DisasContext *ctx)
3408 {
3409 uint32_t op2;
3410
3411 int r1, r2, r3;
3412 int pos1, pos2;
3413
3414 op2 = MASK_OP_BIT_OP2(ctx->opcode);
3415 r1 = MASK_OP_BIT_S1(ctx->opcode);
3416 r2 = MASK_OP_BIT_S2(ctx->opcode);
3417 r3 = MASK_OP_BIT_D(ctx->opcode);
3418 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
3419 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
3420
3421 switch (op2) {
3422 case OPC2_32_BIT_NAND_T:
3423 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3424 pos1, pos2, &tcg_gen_nand_tl);
3425 break;
3426 case OPC2_32_BIT_ORN_T:
3427 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3428 pos1, pos2, &tcg_gen_orc_tl);
3429 break;
3430 case OPC2_32_BIT_XNOR_T:
3431 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3432 pos1, pos2, &tcg_gen_eqv_tl);
3433 break;
3434 case OPC2_32_BIT_XOR_T:
3435 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3436 pos1, pos2, &tcg_gen_xor_tl);
3437 break;
3438 }
3439 }
3440
3441 static void decode_bit_orand(CPUTriCoreState *env, DisasContext *ctx)
3442 {
3443 uint32_t op2;
3444
3445 int r1, r2, r3;
3446 int pos1, pos2;
3447
3448 op2 = MASK_OP_BIT_OP2(ctx->opcode);
3449 r1 = MASK_OP_BIT_S1(ctx->opcode);
3450 r2 = MASK_OP_BIT_S2(ctx->opcode);
3451 r3 = MASK_OP_BIT_D(ctx->opcode);
3452 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
3453 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
3454
3455 switch (op2) {
3456 case OPC2_32_BIT_OR_AND_T:
3457 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3458 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_or_tl);
3459 break;
3460 case OPC2_32_BIT_OR_ANDN_T:
3461 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3462 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_or_tl);
3463 break;
3464 case OPC2_32_BIT_OR_NOR_T:
3465 if (TCG_TARGET_HAS_orc_i32) {
3466 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3467 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_orc_tl);
3468 } else {
3469 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3470 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_or_tl);
3471 }
3472 break;
3473 case OPC2_32_BIT_OR_OR_T:
3474 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3475 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_or_tl);
3476 break;
3477 }
3478 }
3479
3480 static void decode_bit_sh_logic1(CPUTriCoreState *env, DisasContext *ctx)
3481 {
3482 uint32_t op2;
3483 int r1, r2, r3;
3484 int pos1, pos2;
3485 TCGv temp;
3486
3487 op2 = MASK_OP_BIT_OP2(ctx->opcode);
3488 r1 = MASK_OP_BIT_S1(ctx->opcode);
3489 r2 = MASK_OP_BIT_S2(ctx->opcode);
3490 r3 = MASK_OP_BIT_D(ctx->opcode);
3491 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
3492 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
3493
3494 temp = tcg_temp_new();
3495
3496 switch (op2) {
3497 case OPC2_32_BIT_SH_AND_T:
3498 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
3499 pos1, pos2, &tcg_gen_and_tl);
3500 break;
3501 case OPC2_32_BIT_SH_ANDN_T:
3502 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
3503 pos1, pos2, &tcg_gen_andc_tl);
3504 break;
3505 case OPC2_32_BIT_SH_NOR_T:
3506 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
3507 pos1, pos2, &tcg_gen_nor_tl);
3508 break;
3509 case OPC2_32_BIT_SH_OR_T:
3510 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
3511 pos1, pos2, &tcg_gen_or_tl);
3512 break;
3513 }
3514 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1);
3515 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
3516 tcg_temp_free(temp);
3517 }
3518
3519 static void decode_bit_sh_logic2(CPUTriCoreState *env, DisasContext *ctx)
3520 {
3521 uint32_t op2;
3522 int r1, r2, r3;
3523 int pos1, pos2;
3524 TCGv temp;
3525
3526 op2 = MASK_OP_BIT_OP2(ctx->opcode);
3527 r1 = MASK_OP_BIT_S1(ctx->opcode);
3528 r2 = MASK_OP_BIT_S2(ctx->opcode);
3529 r3 = MASK_OP_BIT_D(ctx->opcode);
3530 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
3531 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
3532
3533 temp = tcg_temp_new();
3534
3535 switch (op2) {
3536 case OPC2_32_BIT_SH_NAND_T:
3537 gen_bit_1op(temp, cpu_gpr_d[r1] , cpu_gpr_d[r2] ,
3538 pos1, pos2, &tcg_gen_nand_tl);
3539 break;
3540 case OPC2_32_BIT_SH_ORN_T:
3541 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
3542 pos1, pos2, &tcg_gen_orc_tl);
3543 break;
3544 case OPC2_32_BIT_SH_XNOR_T:
3545 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
3546 pos1, pos2, &tcg_gen_eqv_tl);
3547 break;
3548 case OPC2_32_BIT_SH_XOR_T:
3549 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
3550 pos1, pos2, &tcg_gen_xor_tl);
3551 break;
3552 }
3553 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1);
3554 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
3555 tcg_temp_free(temp);
3556 }
3557
3558 /* BO-format */
3559
3560
3561 static void decode_bo_addrmode_post_pre_base(CPUTriCoreState *env,
3562 DisasContext *ctx)
3563 {
3564 uint32_t op2;
3565 uint32_t off10;
3566 int32_t r1, r2;
3567 TCGv temp;
3568
3569 r1 = MASK_OP_BO_S1D(ctx->opcode);
3570 r2 = MASK_OP_BO_S2(ctx->opcode);
3571 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
3572 op2 = MASK_OP_BO_OP2(ctx->opcode);
3573
3574 switch (op2) {
3575 case OPC2_32_BO_CACHEA_WI_SHORTOFF:
3576 case OPC2_32_BO_CACHEA_W_SHORTOFF:
3577 case OPC2_32_BO_CACHEA_I_SHORTOFF:
3578 /* instruction to access the cache */
3579 break;
3580 case OPC2_32_BO_CACHEA_WI_POSTINC:
3581 case OPC2_32_BO_CACHEA_W_POSTINC:
3582 case OPC2_32_BO_CACHEA_I_POSTINC:
3583 /* instruction to access the cache, but we still need to handle
3584 the addressing mode */
3585 tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10);
3586 break;
3587 case OPC2_32_BO_CACHEA_WI_PREINC:
3588 case OPC2_32_BO_CACHEA_W_PREINC:
3589 case OPC2_32_BO_CACHEA_I_PREINC:
3590 /* instruction to access the cache, but we still need to handle
3591 the addressing mode */
3592 tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10);
3593 break;
3594 case OPC2_32_BO_CACHEI_WI_SHORTOFF:
3595 case OPC2_32_BO_CACHEI_W_SHORTOFF:
3596 /* TODO: Raise illegal opcode trap,
3597 if !tricore_feature(TRICORE_FEATURE_131) */
3598 break;
3599 case OPC2_32_BO_CACHEI_W_POSTINC:
3600 case OPC2_32_BO_CACHEI_WI_POSTINC:
3601 if (tricore_feature(env, TRICORE_FEATURE_131)) {
3602 tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10);
3603 } /* TODO: else raise illegal opcode trap */
3604 break;
3605 case OPC2_32_BO_CACHEI_W_PREINC:
3606 case OPC2_32_BO_CACHEI_WI_PREINC:
3607 if (tricore_feature(env, TRICORE_FEATURE_131)) {
3608 tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10);
3609 } /* TODO: else raise illegal opcode trap */
3610 break;
3611 case OPC2_32_BO_ST_A_SHORTOFF:
3612 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL);
3613 break;
3614 case OPC2_32_BO_ST_A_POSTINC:
3615 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx,
3616 MO_LESL);
3617 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
3618 break;
3619 case OPC2_32_BO_ST_A_PREINC:
3620 gen_st_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL);
3621 break;
3622 case OPC2_32_BO_ST_B_SHORTOFF:
3623 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
3624 break;
3625 case OPC2_32_BO_ST_B_POSTINC:
3626 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
3627 MO_UB);
3628 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
3629 break;
3630 case OPC2_32_BO_ST_B_PREINC:
3631 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
3632 break;
3633 case OPC2_32_BO_ST_D_SHORTOFF:
3634 gen_offset_st_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2],
3635 off10, ctx);
3636 break;
3637 case OPC2_32_BO_ST_D_POSTINC:
3638 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx);
3639 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
3640 break;
3641 case OPC2_32_BO_ST_D_PREINC:
3642 temp = tcg_temp_new();
3643 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
3644 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
3645 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
3646 tcg_temp_free(temp);
3647 break;
3648 case OPC2_32_BO_ST_DA_SHORTOFF:
3649 gen_offset_st_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2],
3650 off10, ctx);
3651 break;
3652 case OPC2_32_BO_ST_DA_POSTINC:
3653 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx);
3654 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
3655 break;
3656 case OPC2_32_BO_ST_DA_PREINC:
3657 temp = tcg_temp_new();
3658 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
3659 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
3660 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
3661 tcg_temp_free(temp);
3662 break;
3663 case OPC2_32_BO_ST_H_SHORTOFF:
3664 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
3665 break;
3666 case OPC2_32_BO_ST_H_POSTINC:
3667 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
3668 MO_LEUW);
3669 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
3670 break;
3671 case OPC2_32_BO_ST_H_PREINC:
3672 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
3673 break;
3674 case OPC2_32_BO_ST_Q_SHORTOFF:
3675 temp = tcg_temp_new();
3676 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
3677 gen_offset_st(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW);
3678 tcg_temp_free(temp);
3679 break;
3680 case OPC2_32_BO_ST_Q_POSTINC:
3681 temp = tcg_temp_new();
3682 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
3683 tcg_gen_qemu_st_tl(temp, cpu_gpr_a[r2], ctx->mem_idx,
3684 MO_LEUW);
3685 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
3686 tcg_temp_free(temp);
3687 break;
3688 case OPC2_32_BO_ST_Q_PREINC:
3689 temp = tcg_temp_new();
3690 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
3691 gen_st_preincr(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW);
3692 tcg_temp_free(temp);
3693 break;
3694 case OPC2_32_BO_ST_W_SHORTOFF:
3695 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
3696 break;
3697 case OPC2_32_BO_ST_W_POSTINC:
3698 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
3699 MO_LEUL);
3700 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
3701 break;
3702 case OPC2_32_BO_ST_W_PREINC:
3703 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
3704 break;
3705 }
3706 }
3707
3708 static void decode_bo_addrmode_bitreverse_circular(CPUTriCoreState *env,
3709 DisasContext *ctx)
3710 {
3711 uint32_t op2;
3712 uint32_t off10;
3713 int32_t r1, r2;
3714 TCGv temp, temp2, temp3;
3715
3716 r1 = MASK_OP_BO_S1D(ctx->opcode);
3717 r2 = MASK_OP_BO_S2(ctx->opcode);
3718 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
3719 op2 = MASK_OP_BO_OP2(ctx->opcode);
3720
3721 temp = tcg_temp_new();
3722 temp2 = tcg_temp_new();
3723 temp3 = tcg_const_i32(off10);
3724
3725 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
3726 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
3727
3728 switch (op2) {
3729 case OPC2_32_BO_CACHEA_WI_BR:
3730 case OPC2_32_BO_CACHEA_W_BR:
3731 case OPC2_32_BO_CACHEA_I_BR:
3732 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
3733 break;
3734 case OPC2_32_BO_CACHEA_WI_CIRC:
3735 case OPC2_32_BO_CACHEA_W_CIRC:
3736 case OPC2_32_BO_CACHEA_I_CIRC:
3737 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
3738 break;
3739 case OPC2_32_BO_ST_A_BR:
3740 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
3741 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
3742 break;
3743 case OPC2_32_BO_ST_A_CIRC:
3744 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
3745 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
3746 break;
3747 case OPC2_32_BO_ST_B_BR:
3748 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
3749 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
3750 break;
3751 case OPC2_32_BO_ST_B_CIRC:
3752 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
3753 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
3754 break;
3755 case OPC2_32_BO_ST_D_BR:
3756 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx);
3757 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
3758 break;
3759 case OPC2_32_BO_ST_D_CIRC:
3760 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
3761 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
3762 tcg_gen_addi_tl(temp, temp, 4);
3763 tcg_gen_rem_tl(temp, temp, temp2);
3764 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
3765 tcg_gen_qemu_st_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL);
3766 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
3767 break;
3768 case OPC2_32_BO_ST_DA_BR:
3769 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx);
3770 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
3771 break;
3772 case OPC2_32_BO_ST_DA_CIRC:
3773 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
3774 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
3775 tcg_gen_addi_tl(temp, temp, 4);
3776 tcg_gen_rem_tl(temp, temp, temp2);
3777 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
3778 tcg_gen_qemu_st_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL);
3779 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
3780 break;
3781 case OPC2_32_BO_ST_H_BR:
3782 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
3783 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
3784 break;
3785 case OPC2_32_BO_ST_H_CIRC:
3786 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
3787 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
3788 break;
3789 case OPC2_32_BO_ST_Q_BR:
3790 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
3791 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW);
3792 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
3793 break;
3794 case OPC2_32_BO_ST_Q_CIRC:
3795 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
3796 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW);
3797 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
3798 break;
3799 case OPC2_32_BO_ST_W_BR:
3800 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
3801 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
3802 break;
3803 case OPC2_32_BO_ST_W_CIRC:
3804 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
3805 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
3806 break;
3807 }
3808 tcg_temp_free(temp);
3809 tcg_temp_free(temp2);
3810 tcg_temp_free(temp3);
3811 }
3812
3813 static void decode_bo_addrmode_ld_post_pre_base(CPUTriCoreState *env,
3814 DisasContext *ctx)
3815 {
3816 uint32_t op2;
3817 uint32_t off10;
3818 int32_t r1, r2;
3819 TCGv temp;
3820
3821 r1 = MASK_OP_BO_S1D(ctx->opcode);
3822 r2 = MASK_OP_BO_S2(ctx->opcode);
3823 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
3824 op2 = MASK_OP_BO_OP2(ctx->opcode);
3825
3826 switch (op2) {
3827 case OPC2_32_BO_LD_A_SHORTOFF:
3828 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL);
3829 break;
3830 case OPC2_32_BO_LD_A_POSTINC:
3831 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx,
3832 MO_LEUL);
3833 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
3834 break;
3835 case OPC2_32_BO_LD_A_PREINC:
3836 gen_ld_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL);
3837 break;
3838 case OPC2_32_BO_LD_B_SHORTOFF:
3839 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
3840 break;
3841 case OPC2_32_BO_LD_B_POSTINC:
3842 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
3843 MO_SB);
3844 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
3845 break;
3846 case OPC2_32_BO_LD_B_PREINC:
3847 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
3848 break;
3849 case OPC2_32_BO_LD_BU_SHORTOFF:
3850 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
3851 break;
3852 case OPC2_32_BO_LD_BU_POSTINC:
3853 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
3854 MO_UB);
3855 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
3856 break;
3857 case OPC2_32_BO_LD_BU_PREINC:
3858 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
3859 break;
3860 case OPC2_32_BO_LD_D_SHORTOFF:
3861 gen_offset_ld_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2],
3862 off10, ctx);
3863 break;
3864 case OPC2_32_BO_LD_D_POSTINC:
3865 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx);
3866 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
3867 break;
3868 case OPC2_32_BO_LD_D_PREINC:
3869 temp = tcg_temp_new();
3870 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
3871 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
3872 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
3873 tcg_temp_free(temp);
3874 break;
3875 case OPC2_32_BO_LD_DA_SHORTOFF:
3876 gen_offset_ld_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2],
3877 off10, ctx);
3878 break;
3879 case OPC2_32_BO_LD_DA_POSTINC:
3880 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx);
3881 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
3882 break;
3883 case OPC2_32_BO_LD_DA_PREINC:
3884 temp = tcg_temp_new();
3885 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
3886 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
3887 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
3888 tcg_temp_free(temp);
3889 break;
3890 case OPC2_32_BO_LD_H_SHORTOFF:
3891 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW);
3892 break;
3893 case OPC2_32_BO_LD_H_POSTINC:
3894 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
3895 MO_LESW);
3896 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
3897 break;
3898 case OPC2_32_BO_LD_H_PREINC:
3899 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW);
3900 break;
3901 case OPC2_32_BO_LD_HU_SHORTOFF:
3902 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
3903 break;
3904 case OPC2_32_BO_LD_HU_POSTINC:
3905 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
3906 MO_LEUW);
3907 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
3908 break;
3909 case OPC2_32_BO_LD_HU_PREINC:
3910 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
3911 break;
3912 case OPC2_32_BO_LD_Q_SHORTOFF:
3913 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
3914 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
3915 break;
3916 case OPC2_32_BO_LD_Q_POSTINC:
3917 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
3918 MO_LEUW);
3919 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
3920 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
3921 break;
3922 case OPC2_32_BO_LD_Q_PREINC:
3923 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
3924 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
3925 break;
3926 case OPC2_32_BO_LD_W_SHORTOFF:
3927 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
3928 break;
3929 case OPC2_32_BO_LD_W_POSTINC:
3930 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
3931 MO_LEUL);
3932 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
3933 break;
3934 case OPC2_32_BO_LD_W_PREINC:
3935 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
3936 break;
3937 }
3938 }
3939
3940 static void decode_bo_addrmode_ld_bitreverse_circular(CPUTriCoreState *env,
3941 DisasContext *ctx)
3942 {
3943 uint32_t op2;
3944 uint32_t off10;
3945 int r1, r2;
3946
3947 TCGv temp, temp2, temp3;
3948
3949 r1 = MASK_OP_BO_S1D(ctx->opcode);
3950 r2 = MASK_OP_BO_S2(ctx->opcode);
3951 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
3952 op2 = MASK_OP_BO_OP2(ctx->opcode);
3953
3954 temp = tcg_temp_new();
3955 temp2 = tcg_temp_new();
3956 temp3 = tcg_const_i32(off10);
3957
3958 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
3959 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
3960
3961
3962 switch (op2) {
3963 case OPC2_32_BO_LD_A_BR:
3964 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
3965 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
3966 break;
3967 case OPC2_32_BO_LD_A_CIRC:
3968 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
3969 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
3970 break;
3971 case OPC2_32_BO_LD_B_BR:
3972 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB);
3973 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
3974 break;
3975 case OPC2_32_BO_LD_B_CIRC:
3976 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB);
3977 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
3978 break;
3979 case OPC2_32_BO_LD_BU_BR:
3980 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
3981 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
3982 break;
3983 case OPC2_32_BO_LD_BU_CIRC:
3984 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
3985 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
3986 break;
3987 case OPC2_32_BO_LD_D_BR:
3988 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx);
3989 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
3990 break;
3991 case OPC2_32_BO_LD_D_CIRC:
3992 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
3993 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
3994 tcg_gen_addi_tl(temp, temp, 4);
3995 tcg_gen_rem_tl(temp, temp, temp2);
3996 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
3997 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL);
3998 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
3999 break;
4000 case OPC2_32_BO_LD_DA_BR:
4001 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx);
4002 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4003 break;
4004 case OPC2_32_BO_LD_DA_CIRC:
4005 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4006 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
4007 tcg_gen_addi_tl(temp, temp, 4);
4008 tcg_gen_rem_tl(temp, temp, temp2);
4009 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4010 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL);
4011 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4012 break;
4013 case OPC2_32_BO_LD_H_BR:
4014 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW);
4015 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4016 break;
4017 case OPC2_32_BO_LD_H_CIRC:
4018 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW);
4019 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4020 break;
4021 case OPC2_32_BO_LD_HU_BR:
4022 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4023 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4024 break;
4025 case OPC2_32_BO_LD_HU_CIRC:
4026 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4027 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4028 break;
4029 case OPC2_32_BO_LD_Q_BR:
4030 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4031 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
4032 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4033 break;
4034 case OPC2_32_BO_LD_Q_CIRC:
4035 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4036 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
4037 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4038 break;
4039 case OPC2_32_BO_LD_W_BR:
4040 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4041 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4042 break;
4043 case OPC2_32_BO_LD_W_CIRC:
4044 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4045 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4046 break;
4047 }
4048 tcg_temp_free(temp);
4049 tcg_temp_free(temp2);
4050 tcg_temp_free(temp3);
4051 }
4052
4053 static void decode_bo_addrmode_stctx_post_pre_base(CPUTriCoreState *env,
4054 DisasContext *ctx)
4055 {
4056 uint32_t op2;
4057 uint32_t off10;
4058 int r1, r2;
4059
4060 TCGv temp, temp2;
4061
4062 r1 = MASK_OP_BO_S1D(ctx->opcode);
4063 r2 = MASK_OP_BO_S2(ctx->opcode);
4064 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4065 op2 = MASK_OP_BO_OP2(ctx->opcode);
4066
4067
4068 temp = tcg_temp_new();
4069 temp2 = tcg_temp_new();
4070
4071 switch (op2) {
4072 case OPC2_32_BO_LDLCX_SHORTOFF:
4073 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4074 gen_helper_ldlcx(cpu_env, temp);
4075 break;
4076 case OPC2_32_BO_LDMST_SHORTOFF:
4077 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4078 gen_ldmst(ctx, r1, temp);
4079 break;
4080 case OPC2_32_BO_LDMST_POSTINC:
4081 gen_ldmst(ctx, r1, cpu_gpr_a[r2]);
4082 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4083 break;
4084 case OPC2_32_BO_LDMST_PREINC:
4085 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4086 gen_ldmst(ctx, r1, cpu_gpr_a[r2]);
4087 break;
4088 case OPC2_32_BO_LDUCX_SHORTOFF:
4089 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4090 gen_helper_lducx(cpu_env, temp);
4091 break;
4092 case OPC2_32_BO_LEA_SHORTOFF:
4093 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], off10);
4094 break;
4095 case OPC2_32_BO_STLCX_SHORTOFF:
4096 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4097 gen_helper_stlcx(cpu_env, temp);
4098 break;
4099 case OPC2_32_BO_STUCX_SHORTOFF:
4100 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4101 gen_helper_stucx(cpu_env, temp);
4102 break;
4103 case OPC2_32_BO_SWAP_W_SHORTOFF:
4104 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4105 gen_swap(ctx, r1, temp);
4106 break;
4107 case OPC2_32_BO_SWAP_W_POSTINC:
4108 gen_swap(ctx, r1, cpu_gpr_a[r2]);
4109 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4110 break;
4111 case OPC2_32_BO_SWAP_W_PREINC:
4112 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4113 gen_swap(ctx, r1, cpu_gpr_a[r2]);
4114 break;
4115 }
4116 tcg_temp_free(temp);
4117 tcg_temp_free(temp2);
4118 }
4119
4120 static void decode_bo_addrmode_ldmst_bitreverse_circular(CPUTriCoreState *env,
4121 DisasContext *ctx)
4122 {
4123 uint32_t op2;
4124 uint32_t off10;
4125 int r1, r2;
4126
4127 TCGv temp, temp2, temp3;
4128
4129 r1 = MASK_OP_BO_S1D(ctx->opcode);
4130 r2 = MASK_OP_BO_S2(ctx->opcode);
4131 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4132 op2 = MASK_OP_BO_OP2(ctx->opcode);
4133
4134 temp = tcg_temp_new();
4135 temp2 = tcg_temp_new();
4136 temp3 = tcg_const_i32(off10);
4137
4138 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
4139 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4140
4141 switch (op2) {
4142 case OPC2_32_BO_LDMST_BR:
4143 gen_ldmst(ctx, r1, temp2);
4144 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4145 break;
4146 case OPC2_32_BO_LDMST_CIRC:
4147 gen_ldmst(ctx, r1, temp2);
4148 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4149 break;
4150 case OPC2_32_BO_SWAP_W_BR:
4151 gen_swap(ctx, r1, temp2);
4152 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4153 break;
4154 case OPC2_32_BO_SWAP_W_CIRC:
4155 gen_swap(ctx, r1, temp2);
4156 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4157 break;
4158 }
4159 tcg_temp_free(temp);
4160 tcg_temp_free(temp2);
4161 tcg_temp_free(temp3);
4162 }
4163
4164 static void decode_bol_opc(CPUTriCoreState *env, DisasContext *ctx, int32_t op1)
4165 {
4166 int r1, r2;
4167 int32_t address;
4168 TCGv temp;
4169
4170 r1 = MASK_OP_BOL_S1D(ctx->opcode);
4171 r2 = MASK_OP_BOL_S2(ctx->opcode);
4172 address = MASK_OP_BOL_OFF16_SEXT(ctx->opcode);
4173
4174 switch (op1) {
4175 case OPC1_32_BOL_LD_A_LONGOFF:
4176 temp = tcg_temp_new();
4177 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address);
4178 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LEUL);
4179 tcg_temp_free(temp);
4180 break;
4181 case OPC1_32_BOL_LD_W_LONGOFF:
4182 temp = tcg_temp_new();
4183 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address);
4184 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUL);
4185 tcg_temp_free(temp);
4186 break;
4187 case OPC1_32_BOL_LEA_LONGOFF:
4188 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], address);
4189 break;
4190 case OPC1_32_BOL_ST_A_LONGOFF:
4191 if (tricore_feature(env, TRICORE_FEATURE_16)) {
4192 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], address, MO_LEUL);
4193 } else {
4194 /* raise illegal opcode trap */
4195 }
4196 break;
4197 case OPC1_32_BOL_ST_W_LONGOFF:
4198 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUL);
4199 break;
4200 case OPC1_32_BOL_LD_B_LONGOFF:
4201 if (tricore_feature(env, TRICORE_FEATURE_16)) {
4202 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB);
4203 } else {
4204 /* raise illegal opcode trap */
4205 }
4206 break;
4207 case OPC1_32_BOL_LD_BU_LONGOFF:
4208 if (tricore_feature(env, TRICORE_FEATURE_16)) {
4209 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_UB);
4210 } else {
4211 /* raise illegal opcode trap */
4212 }
4213 break;
4214 case OPC1_32_BOL_LD_H_LONGOFF:
4215 if (tricore_feature(env, TRICORE_FEATURE_16)) {
4216 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW);
4217 } else {
4218 /* raise illegal opcode trap */
4219 }
4220 break;
4221 case OPC1_32_BOL_LD_HU_LONGOFF:
4222 if (tricore_feature(env, TRICORE_FEATURE_16)) {
4223 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUW);
4224 } else {
4225 /* raise illegal opcode trap */
4226 }
4227 break;
4228 case OPC1_32_BOL_ST_B_LONGOFF:
4229 if (tricore_feature(env, TRICORE_FEATURE_16)) {
4230 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB);
4231 } else {
4232 /* raise illegal opcode trap */
4233 }
4234 break;
4235 case OPC1_32_BOL_ST_H_LONGOFF:
4236 if (tricore_feature(env, TRICORE_FEATURE_16)) {
4237 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW);
4238 } else {
4239 /* raise illegal opcode trap */
4240 }
4241 break;
4242 }
4243 }
4244
4245 /* RC format */
4246 static void decode_rc_logical_shift(CPUTriCoreState *env, DisasContext *ctx)
4247 {
4248 uint32_t op2;
4249 int r1, r2;
4250 int32_t const9;
4251 TCGv temp;
4252
4253 r2 = MASK_OP_RC_D(ctx->opcode);
4254 r1 = MASK_OP_RC_S1(ctx->opcode);
4255 const9 = MASK_OP_RC_CONST9(ctx->opcode);
4256 op2 = MASK_OP_RC_OP2(ctx->opcode);
4257
4258 temp = tcg_temp_new();
4259
4260 switch (op2) {
4261 case OPC2_32_RC_AND:
4262 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4263 break;
4264 case OPC2_32_RC_ANDN:
4265 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9);
4266 break;
4267 case OPC2_32_RC_NAND:
4268 tcg_gen_movi_tl(temp, const9);
4269 tcg_gen_nand_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp);
4270 break;
4271 case OPC2_32_RC_NOR:
4272 tcg_gen_movi_tl(temp, const9);
4273 tcg_gen_nor_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp);
4274 break;
4275 case OPC2_32_RC_OR:
4276 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4277 break;
4278 case OPC2_32_RC_ORN:
4279 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9);
4280 break;
4281 case OPC2_32_RC_SH:
4282 const9 = sextract32(const9, 0, 6);
4283 gen_shi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4284 break;
4285 case OPC2_32_RC_SH_H:
4286 const9 = sextract32(const9, 0, 5);
4287 gen_sh_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4288 break;
4289 case OPC2_32_RC_SHA:
4290 const9 = sextract32(const9, 0, 6);
4291 gen_shaci(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4292 break;
4293 case OPC2_32_RC_SHA_H:
4294 const9 = sextract32(const9, 0, 5);
4295 gen_sha_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4296 break;
4297 case OPC2_32_RC_SHAS:
4298 gen_shasi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4299 break;
4300 case OPC2_32_RC_XNOR:
4301 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4302 tcg_gen_not_tl(cpu_gpr_d[r2], cpu_gpr_d[r2]);
4303 break;
4304 case OPC2_32_RC_XOR:
4305 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4306 break;
4307 }
4308 tcg_temp_free(temp);
4309 }
4310
4311 static void decode_rc_accumulator(CPUTriCoreState *env, DisasContext *ctx)
4312 {
4313 uint32_t op2;
4314 int r1, r2;
4315 int16_t const9;
4316
4317 TCGv temp;
4318
4319 r2 = MASK_OP_RC_D(ctx->opcode);
4320 r1 = MASK_OP_RC_S1(ctx->opcode);
4321 const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode);
4322
4323 op2 = MASK_OP_RC_OP2(ctx->opcode);
4324
4325 temp = tcg_temp_new();
4326
4327 switch (op2) {
4328 case OPC2_32_RC_ABSDIF:
4329 gen_absdifi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4330 break;
4331 case OPC2_32_RC_ABSDIFS:
4332 gen_absdifsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4333 break;
4334 case OPC2_32_RC_ADD:
4335 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4336 break;
4337 case OPC2_32_RC_ADDC:
4338 gen_addci_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4339 break;
4340 case OPC2_32_RC_ADDS:
4341 gen_addsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4342 break;
4343 case OPC2_32_RC_ADDS_U:
4344 gen_addsui(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4345 break;
4346 case OPC2_32_RC_ADDX:
4347 gen_addi_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4348 break;
4349 case OPC2_32_RC_AND_EQ:
4350 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1],
4351 const9, &tcg_gen_and_tl);
4352 break;
4353 case OPC2_32_RC_AND_GE:
4354 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1],
4355 const9, &tcg_gen_and_tl);
4356 break;
4357 case OPC2_32_RC_AND_GE_U:
4358 const9 = MASK_OP_RC_CONST9(ctx->opcode);
4359 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1],
4360 const9, &tcg_gen_and_tl);
4361 break;
4362 case OPC2_32_RC_AND_LT:
4363 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1],
4364 const9, &tcg_gen_and_tl);
4365 break;
4366 case OPC2_32_RC_AND_LT_U:
4367 const9 = MASK_OP_RC_CONST9(ctx->opcode);
4368 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1],
4369 const9, &tcg_gen_and_tl);
4370 break;
4371 case OPC2_32_RC_AND_NE:
4372 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1],
4373 const9, &tcg_gen_and_tl);
4374 break;
4375 case OPC2_32_RC_EQ:
4376 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4377 break;
4378 case OPC2_32_RC_EQANY_B:
4379 gen_eqany_bi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4380 break;
4381 case OPC2_32_RC_EQANY_H:
4382 gen_eqany_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4383 break;
4384 case OPC2_32_RC_GE:
4385 tcg_gen_setcondi_tl(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4386 break;
4387 case OPC2_32_RC_GE_U:
4388 const9 = MASK_OP_RC_CONST9(ctx->opcode);
4389 tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4390 break;
4391 case OPC2_32_RC_LT:
4392 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4393 break;
4394 case OPC2_32_RC_LT_U:
4395 const9 = MASK_OP_RC_CONST9(ctx->opcode);
4396 tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4397 break;
4398 case OPC2_32_RC_MAX:
4399 tcg_gen_movi_tl(temp, const9);
4400 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
4401 cpu_gpr_d[r1], temp);
4402 break;
4403 case OPC2_32_RC_MAX_U:
4404 tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode));
4405 tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
4406 cpu_gpr_d[r1], temp);
4407 break;
4408 case OPC2_32_RC_MIN:
4409 tcg_gen_movi_tl(temp, const9);
4410 tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
4411 cpu_gpr_d[r1], temp);
4412 break;
4413 case OPC2_32_RC_MIN_U:
4414 tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode));
4415 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
4416 cpu_gpr_d[r1], temp);
4417 break;
4418 case OPC2_32_RC_NE:
4419 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4420 break;
4421 case OPC2_32_RC_OR_EQ:
4422 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1],
4423 const9, &tcg_gen_or_tl);
4424 break;
4425 case OPC2_32_RC_OR_GE:
4426 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1],
4427 const9, &tcg_gen_or_tl);
4428 break;
4429 case OPC2_32_RC_OR_GE_U:
4430 const9 = MASK_OP_RC_CONST9(ctx->opcode);
4431 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1],
4432 const9, &tcg_gen_or_tl);
4433 break;
4434 case OPC2_32_RC_OR_LT:
4435 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1],
4436 const9, &tcg_gen_or_tl);
4437 break;
4438 case OPC2_32_RC_OR_LT_U:
4439 const9 = MASK_OP_RC_CONST9(ctx->opcode);
4440 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1],
4441 const9, &tcg_gen_or_tl);
4442 break;
4443 case OPC2_32_RC_OR_NE:
4444 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1],
4445 const9, &tcg_gen_or_tl);
4446 break;
4447 case OPC2_32_RC_RSUB:
4448 tcg_gen_movi_tl(temp, const9);
4449 gen_sub_d(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
4450 break;
4451 case OPC2_32_RC_RSUBS:
4452 tcg_gen_movi_tl(temp, const9);
4453 gen_subs(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
4454 break;
4455 case OPC2_32_RC_RSUBS_U:
4456 tcg_gen_movi_tl(temp, const9);
4457 gen_subsu(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
4458 break;
4459 case OPC2_32_RC_SH_EQ:
4460 gen_sh_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4461 break;
4462 case OPC2_32_RC_SH_GE:
4463 gen_sh_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4464 break;
4465 case OPC2_32_RC_SH_GE_U:
4466 const9 = MASK_OP_RC_CONST9(ctx->opcode);
4467 gen_sh_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4468 break;
4469 case OPC2_32_RC_SH_LT:
4470 gen_sh_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4471 break;
4472 case OPC2_32_RC_SH_LT_U:
4473 const9 = MASK_OP_RC_CONST9(ctx->opcode);
4474 gen_sh_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4475 break;
4476 case OPC2_32_RC_SH_NE:
4477 gen_sh_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4478 break;
4479 case OPC2_32_RC_XOR_EQ:
4480 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1],
4481 const9, &tcg_gen_xor_tl);
4482 break;
4483 case OPC2_32_RC_XOR_GE:
4484 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1],
4485 const9, &tcg_gen_xor_tl);
4486 break;
4487 case OPC2_32_RC_XOR_GE_U:
4488 const9 = MASK_OP_RC_CONST9(ctx->opcode);
4489 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1],
4490 const9, &tcg_gen_xor_tl);
4491 break;
4492 case OPC2_32_RC_XOR_LT:
4493 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1],
4494 const9, &tcg_gen_xor_tl);
4495 break;
4496 case OPC2_32_RC_XOR_LT_U:
4497 const9 = MASK_OP_RC_CONST9(ctx->opcode);
4498 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1],
4499 const9, &tcg_gen_xor_tl);
4500 break;
4501 case OPC2_32_RC_XOR_NE:
4502 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1],
4503 const9, &tcg_gen_xor_tl);
4504 break;
4505 }
4506 tcg_temp_free(temp);
4507 }
4508
4509 static void decode_rc_serviceroutine(CPUTriCoreState *env, DisasContext *ctx)
4510 {
4511 uint32_t op2;
4512 uint32_t const9;
4513
4514 op2 = MASK_OP_RC_OP2(ctx->opcode);
4515 const9 = MASK_OP_RC_CONST9(ctx->opcode);
4516
4517 switch (op2) {
4518 case OPC2_32_RC_BISR:
4519 gen_helper_1arg(bisr, const9);
4520 break;
4521 case OPC2_32_RC_SYSCALL:
4522 /* TODO: Add exception generation */
4523 break;
4524 }
4525 }
4526
4527 static void decode_rc_mul(CPUTriCoreState *env, DisasContext *ctx)
4528 {
4529 uint32_t op2;
4530 int r1, r2;
4531 int16_t const9;
4532
4533 r2 = MASK_OP_RC_D(ctx->opcode);
4534 r1 = MASK_OP_RC_S1(ctx->opcode);
4535 const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode);
4536
4537 op2 = MASK_OP_RC_OP2(ctx->opcode);
4538
4539 switch (op2) {
4540 case OPC2_32_RC_MUL_32:
4541 gen_muli_i32s(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4542 break;
4543 case OPC2_32_RC_MUL_64:
4544 gen_muli_i64s(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9);
4545 break;
4546 case OPC2_32_RC_MULS_32:
4547 gen_mulsi_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4548 break;
4549 case OPC2_32_RC_MUL_U_64:
4550 const9 = MASK_OP_RC_CONST9(ctx->opcode);
4551 gen_muli_i64u(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9);
4552 break;
4553 case OPC2_32_RC_MULS_U_32:
4554 const9 = MASK_OP_RC_CONST9(ctx->opcode);
4555 gen_mulsui_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4556 break;
4557 }
4558 }
4559
4560 /* RCPW format */
4561 static void decode_rcpw_insert(CPUTriCoreState *env, DisasContext *ctx)
4562 {
4563 uint32_t op2;
4564 int r1, r2;
4565 int32_t pos, width, const4;
4566
4567 TCGv temp;
4568
4569 op2 = MASK_OP_RCPW_OP2(ctx->opcode);
4570 r1 = MASK_OP_RCPW_S1(ctx->opcode);
4571 r2 = MASK_OP_RCPW_D(ctx->opcode);
4572 const4 = MASK_OP_RCPW_CONST4(ctx->opcode);
4573 width = MASK_OP_RCPW_WIDTH(ctx->opcode);
4574 pos = MASK_OP_RCPW_POS(ctx->opcode);
4575
4576 switch (op2) {
4577 case OPC2_32_RCPW_IMASK:
4578 /* if pos + width > 31 undefined result */
4579 if (pos + width <= 31) {
4580 tcg_gen_movi_tl(cpu_gpr_d[r2+1], ((1u << width) - 1) << pos);
4581 tcg_gen_movi_tl(cpu_gpr_d[r2], (const4 << pos));
4582 }
4583 break;
4584 case OPC2_32_RCPW_INSERT:
4585 /* if pos + width > 32 undefined result */
4586 if (pos + width <= 32) {
4587 temp = tcg_const_i32(const4);
4588 tcg_gen_deposit_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, pos, width);
4589 tcg_temp_free(temp);
4590 }
4591 break;
4592 }
4593 }
4594
4595 /* RCRW format */
4596
4597 static void decode_rcrw_insert(CPUTriCoreState *env, DisasContext *ctx)
4598 {
4599 uint32_t op2;
4600 int r1, r3, r4;
4601 int32_t width, const4;
4602
4603 TCGv temp, temp2, temp3;
4604
4605 op2 = MASK_OP_RCRW_OP2(ctx->opcode);
4606 r1 = MASK_OP_RCRW_S1(ctx->opcode);
4607 r3 = MASK_OP_RCRW_S3(ctx->opcode);
4608 r4 = MASK_OP_RCRW_D(ctx->opcode);
4609 width = MASK_OP_RCRW_WIDTH(ctx->opcode);
4610 const4 = MASK_OP_RCRW_CONST4(ctx->opcode);
4611
4612 temp = tcg_temp_new();
4613 temp2 = tcg_temp_new();
4614
4615 switch (op2) {
4616 case OPC2_32_RCRW_IMASK:
4617 tcg_gen_andi_tl(temp, cpu_gpr_d[r4], 0x1f);
4618 tcg_gen_movi_tl(temp2, (1 << width) - 1);
4619 tcg_gen_shl_tl(cpu_gpr_d[r3 + 1], temp2, temp);
4620 tcg_gen_movi_tl(temp2, const4);
4621 tcg_gen_shl_tl(cpu_gpr_d[r3], temp2, temp);
4622 break;
4623 case OPC2_32_RCRW_INSERT:
4624 temp3 = tcg_temp_new();
4625
4626 tcg_gen_movi_tl(temp, width);
4627 tcg_gen_movi_tl(temp2, const4);
4628 tcg_gen_andi_tl(temp3, cpu_gpr_d[r4], 0x1f);
4629 gen_insert(cpu_gpr_d[r3], cpu_gpr_d[r1], temp2, temp, temp3);
4630
4631 tcg_temp_free(temp3);
4632 break;
4633 }
4634 tcg_temp_free(temp);
4635 tcg_temp_free(temp2);
4636 }
4637
4638 /* RCR format */
4639
4640 static void decode_rcr_cond_select(CPUTriCoreState *env, DisasContext *ctx)
4641 {
4642 uint32_t op2;
4643 int r1, r3, r4;
4644 int32_t const9;
4645
4646 TCGv temp, temp2;
4647
4648 op2 = MASK_OP_RCR_OP2(ctx->opcode);
4649 r1 = MASK_OP_RCR_S1(ctx->opcode);
4650 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode);
4651 r3 = MASK_OP_RCR_S3(ctx->opcode);
4652 r4 = MASK_OP_RCR_D(ctx->opcode);
4653
4654 switch (op2) {
4655 case OPC2_32_RCR_CADD:
4656 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const9, cpu_gpr_d[r3],
4657 cpu_gpr_d[r4]);
4658 break;
4659 case OPC2_32_RCR_CADDN:
4660 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const9, cpu_gpr_d[r3],
4661 cpu_gpr_d[r4]);
4662 break;
4663 case OPC2_32_RCR_SEL:
4664 temp = tcg_const_i32(0);
4665 temp2 = tcg_const_i32(const9);
4666 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
4667 cpu_gpr_d[r1], temp2);
4668 tcg_temp_free(temp);
4669 tcg_temp_free(temp2);
4670 break;
4671 case OPC2_32_RCR_SELN:
4672 temp = tcg_const_i32(0);
4673 temp2 = tcg_const_i32(const9);
4674 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
4675 cpu_gpr_d[r1], temp2);
4676 tcg_temp_free(temp);
4677 tcg_temp_free(temp2);
4678 break;
4679 }
4680 }
4681
4682 static void decode_rcr_madd(CPUTriCoreState *env, DisasContext *ctx)
4683 {
4684 uint32_t op2;
4685 int r1, r3, r4;
4686 int32_t const9;
4687
4688
4689 op2 = MASK_OP_RCR_OP2(ctx->opcode);
4690 r1 = MASK_OP_RCR_S1(ctx->opcode);
4691 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode);
4692 r3 = MASK_OP_RCR_S3(ctx->opcode);
4693 r4 = MASK_OP_RCR_D(ctx->opcode);
4694
4695 switch (op2) {
4696 case OPC2_32_RCR_MADD_32:
4697 gen_maddi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
4698 break;
4699 case OPC2_32_RCR_MADD_64:
4700 gen_maddi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
4701 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
4702 break;
4703 case OPC2_32_RCR_MADDS_32:
4704 gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
4705 break;
4706 case OPC2_32_RCR_MADDS_64:
4707 gen_maddsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
4708 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
4709 break;
4710 case OPC2_32_RCR_MADD_U_64:
4711 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
4712 gen_maddui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
4713 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
4714 break;
4715 case OPC2_32_RCR_MADDS_U_32:
4716 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
4717 gen_maddsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
4718 break;
4719 case OPC2_32_RCR_MADDS_U_64:
4720 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
4721 gen_maddsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
4722 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
4723 break;
4724 }
4725 }
4726
4727 static void decode_rcr_msub(CPUTriCoreState *env, DisasContext *ctx)
4728 {
4729 uint32_t op2;
4730 int r1, r3, r4;
4731 int32_t const9;
4732
4733
4734 op2 = MASK_OP_RCR_OP2(ctx->opcode);
4735 r1 = MASK_OP_RCR_S1(ctx->opcode);
4736 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode);
4737 r3 = MASK_OP_RCR_S3(ctx->opcode);
4738 r4 = MASK_OP_RCR_D(ctx->opcode);
4739
4740 switch (op2) {
4741 case OPC2_32_RCR_MSUB_32:
4742 gen_msubi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
4743 break;
4744 case OPC2_32_RCR_MSUB_64:
4745 gen_msubi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
4746 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
4747 break;
4748 case OPC2_32_RCR_MSUBS_32:
4749 gen_msubsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
4750 break;
4751 case OPC2_32_RCR_MSUBS_64:
4752 gen_msubsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
4753 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
4754 break;
4755 case OPC2_32_RCR_MSUB_U_64:
4756 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
4757 gen_msubui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
4758 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
4759 break;
4760 case OPC2_32_RCR_MSUBS_U_32:
4761 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
4762 gen_msubsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
4763 break;
4764 case OPC2_32_RCR_MSUBS_U_64:
4765 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
4766 gen_msubsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
4767 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
4768 break;
4769 }
4770 }
4771
4772 /* RLC format */
4773
4774 static void decode_rlc_opc(CPUTriCoreState *env, DisasContext *ctx,
4775 uint32_t op1)
4776 {
4777 int32_t const16;
4778 int r1, r2;
4779
4780 const16 = MASK_OP_RLC_CONST16_SEXT(ctx->opcode);
4781 r1 = MASK_OP_RLC_S1(ctx->opcode);
4782 r2 = MASK_OP_RLC_D(ctx->opcode);
4783
4784 switch (op1) {
4785 case OPC1_32_RLC_ADDI:
4786 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16);
4787 break;
4788 case OPC1_32_RLC_ADDIH:
4789 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16 << 16);
4790 break;
4791 case OPC1_32_RLC_ADDIH_A:
4792 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r1], const16 << 16);
4793 break;
4794 case OPC1_32_RLC_MFCR:
4795 const16 = MASK_OP_RLC_CONST16(ctx->opcode);
4796 gen_mfcr(env, cpu_gpr_d[r2], const16);
4797 break;
4798 case OPC1_32_RLC_MOV:
4799 tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
4800 break;
4801 case OPC1_32_RLC_MOV_64:
4802 if (tricore_feature(env, TRICORE_FEATURE_16)) {
4803 if ((r2 & 0x1) != 0) {
4804 /* TODO: raise OPD trap */
4805 }
4806 tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
4807 tcg_gen_movi_tl(cpu_gpr_d[r2+1], const16 >> 15);
4808 } else {
4809 /* TODO: raise illegal opcode trap */
4810 }
4811 break;
4812 case OPC1_32_RLC_MOV_U:
4813 const16 = MASK_OP_RLC_CONST16(ctx->opcode);
4814 tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
4815 break;
4816 case OPC1_32_RLC_MOV_H:
4817 tcg_gen_movi_tl(cpu_gpr_d[r2], const16 << 16);
4818 break;
4819 case OPC1_32_RLC_MOVH_A:
4820 tcg_gen_movi_tl(cpu_gpr_a[r2], const16 << 16);
4821 break;
4822 case OPC1_32_RLC_MTCR:
4823 const16 = MASK_OP_RLC_CONST16(ctx->opcode);
4824 gen_mtcr(env, ctx, cpu_gpr_d[r1], const16);
4825 break;
4826 }
4827 }
4828
4829 /* RR format */
4830 static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx)
4831 {
4832 uint32_t op2;
4833 int r3, r2, r1;
4834
4835 r3 = MASK_OP_RR_D(ctx->opcode);
4836 r2 = MASK_OP_RR_S2(ctx->opcode);
4837 r1 = MASK_OP_RR_S1(ctx->opcode);
4838 op2 = MASK_OP_RR_OP2(ctx->opcode);
4839
4840 switch (op2) {
4841 case OPC2_32_RR_ABS:
4842 gen_abs(cpu_gpr_d[r3], cpu_gpr_d[r2]);
4843 break;
4844 case OPC2_32_RR_ABS_B:
4845 gen_helper_abs_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
4846 break;
4847 case OPC2_32_RR_ABS_H:
4848 gen_helper_abs_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
4849 break;
4850 case OPC2_32_RR_ABSDIF:
4851 gen_absdif(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
4852 break;
4853 case OPC2_32_RR_ABSDIF_B:
4854 gen_helper_absdif_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
4855 cpu_gpr_d[r2]);
4856 break;
4857 case OPC2_32_RR_ABSDIF_H:
4858 gen_helper_absdif_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
4859 cpu_gpr_d[r2]);
4860 break;
4861 case OPC2_32_RR_ABSDIFS:
4862 gen_helper_absdif_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
4863 cpu_gpr_d[r2]);
4864 break;
4865 case OPC2_32_RR_ABSDIFS_H:
4866 gen_helper_absdif_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
4867 cpu_gpr_d[r2]);
4868 break;
4869 case OPC2_32_RR_ABSS:
4870 gen_helper_abs_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
4871 break;
4872 case OPC2_32_RR_ABSS_H:
4873 gen_helper_abs_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
4874 break;
4875 case OPC2_32_RR_ADD:
4876 gen_add_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
4877 break;
4878 case OPC2_32_RR_ADD_B:
4879 gen_helper_add_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
4880 break;
4881 case OPC2_32_RR_ADD_H:
4882 gen_helper_add_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
4883 break;
4884 case OPC2_32_RR_ADDC:
4885 gen_addc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
4886 break;
4887 case OPC2_32_RR_ADDS:
4888 gen_adds(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
4889 break;
4890 case OPC2_32_RR_ADDS_H:
4891 gen_helper_add_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
4892 cpu_gpr_d[r2]);
4893 break;
4894 case OPC2_32_RR_ADDS_HU:
4895 gen_helper_add_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
4896 cpu_gpr_d[r2]);
4897 break;
4898 case OPC2_32_RR_ADDS_U:
4899 gen_helper_add_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
4900 cpu_gpr_d[r2]);
4901 break;
4902 case OPC2_32_RR_ADDX:
4903 gen_add_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
4904 break;
4905 case OPC2_32_RR_AND_EQ:
4906 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
4907 cpu_gpr_d[r2], &tcg_gen_and_tl);
4908 break;
4909 case OPC2_32_RR_AND_GE:
4910 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
4911 cpu_gpr_d[r2], &tcg_gen_and_tl);
4912 break;
4913 case OPC2_32_RR_AND_GE_U:
4914 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
4915 cpu_gpr_d[r2], &tcg_gen_and_tl);
4916 break;
4917 case OPC2_32_RR_AND_LT:
4918 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
4919 cpu_gpr_d[r2], &tcg_gen_and_tl);
4920 break;
4921 case OPC2_32_RR_AND_LT_U:
4922 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
4923 cpu_gpr_d[r2], &tcg_gen_and_tl);
4924 break;
4925 case OPC2_32_RR_AND_NE:
4926 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
4927 cpu_gpr_d[r2], &tcg_gen_and_tl);
4928 break;
4929 case OPC2_32_RR_EQ:
4930 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
4931 cpu_gpr_d[r2]);
4932 break;
4933 case OPC2_32_RR_EQ_B:
4934 gen_helper_eq_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
4935 break;
4936 case OPC2_32_RR_EQ_H:
4937 gen_helper_eq_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
4938 break;
4939 case OPC2_32_RR_EQ_W:
4940 gen_cond_w(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
4941 break;
4942 case OPC2_32_RR_EQANY_B:
4943 gen_helper_eqany_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
4944 break;
4945 case OPC2_32_RR_EQANY_H:
4946 gen_helper_eqany_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
4947 break;
4948 case OPC2_32_RR_GE:
4949 tcg_gen_setcond_tl(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
4950 cpu_gpr_d[r2]);
4951 break;
4952 case OPC2_32_RR_GE_U:
4953 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
4954 cpu_gpr_d[r2]);
4955 break;
4956 case OPC2_32_RR_LT:
4957 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
4958 cpu_gpr_d[r2]);
4959 break;
4960 case OPC2_32_RR_LT_U:
4961 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
4962 cpu_gpr_d[r2]);
4963 break;
4964 case OPC2_32_RR_LT_B:
4965 gen_helper_lt_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
4966 break;
4967 case OPC2_32_RR_LT_BU:
4968 gen_helper_lt_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
4969 break;
4970 case OPC2_32_RR_LT_H:
4971 gen_helper_lt_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
4972 break;
4973 case OPC2_32_RR_LT_HU:
4974 gen_helper_lt_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
4975 break;
4976 case OPC2_32_RR_LT_W:
4977 gen_cond_w(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
4978 break;
4979 case OPC2_32_RR_LT_WU:
4980 gen_cond_w(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
4981 break;
4982 case OPC2_32_RR_MAX:
4983 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r3], cpu_gpr_d[r1],
4984 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
4985 break;
4986 case OPC2_32_RR_MAX_U:
4987 tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
4988 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
4989 break;
4990 case OPC2_32_RR_MAX_B:
4991 gen_helper_max_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
4992 break;
4993 case OPC2_32_RR_MAX_BU:
4994 gen_helper_max_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
4995 break;
4996 case OPC2_32_RR_MAX_H:
4997 gen_helper_max_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
4998 break;
4999 case OPC2_32_RR_MAX_HU:
5000 gen_helper_max_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5001 break;
5002 case OPC2_32_RR_MIN:
5003 tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
5004 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5005 break;
5006 case OPC2_32_RR_MIN_U:
5007 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5008 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5009 break;
5010 case OPC2_32_RR_MIN_B:
5011 gen_helper_min_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5012 break;
5013 case OPC2_32_RR_MIN_BU:
5014 gen_helper_min_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5015 break;
5016 case OPC2_32_RR_MIN_H:
5017 gen_helper_min_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5018 break;
5019 case OPC2_32_RR_MIN_HU:
5020 gen_helper_min_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5021 break;
5022 case OPC2_32_RR_MOV:
5023 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]);
5024 break;
5025 case OPC2_32_RR_NE:
5026 tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5027 cpu_gpr_d[r2]);
5028 break;
5029 case OPC2_32_RR_OR_EQ:
5030 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
5031 cpu_gpr_d[r2], &tcg_gen_or_tl);
5032 break;
5033 case OPC2_32_RR_OR_GE:
5034 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5035 cpu_gpr_d[r2], &tcg_gen_or_tl);
5036 break;
5037 case OPC2_32_RR_OR_GE_U:
5038 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5039 cpu_gpr_d[r2], &tcg_gen_or_tl);
5040 break;
5041 case OPC2_32_RR_OR_LT:
5042 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
5043 cpu_gpr_d[r2], &tcg_gen_or_tl);
5044 break;
5045 case OPC2_32_RR_OR_LT_U:
5046 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5047 cpu_gpr_d[r2], &tcg_gen_or_tl);
5048 break;
5049 case OPC2_32_RR_OR_NE:
5050 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5051 cpu_gpr_d[r2], &tcg_gen_or_tl);
5052 break;
5053 case OPC2_32_RR_SAT_B:
5054 gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7f, -0x80);
5055 break;
5056 case OPC2_32_RR_SAT_BU:
5057 gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xff);
5058 break;
5059 case OPC2_32_RR_SAT_H:
5060 gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7fff, -0x8000);
5061 break;
5062 case OPC2_32_RR_SAT_HU:
5063 gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xffff);
5064 break;
5065 case OPC2_32_RR_SH_EQ:
5066 gen_sh_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
5067 cpu_gpr_d[r2]);
5068 break;
5069 case OPC2_32_RR_SH_GE:
5070 gen_sh_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5071 cpu_gpr_d[r2]);
5072 break;
5073 case OPC2_32_RR_SH_GE_U:
5074 gen_sh_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5075 cpu_gpr_d[r2]);
5076 break;
5077 case OPC2_32_RR_SH_LT:
5078 gen_sh_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
5079 cpu_gpr_d[r2]);
5080 break;
5081 case OPC2_32_RR_SH_LT_U:
5082 gen_sh_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5083 cpu_gpr_d[r2]);
5084 break;
5085 case OPC2_32_RR_SH_NE:
5086 gen_sh_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5087 cpu_gpr_d[r2]);
5088 break;
5089 case OPC2_32_RR_SUB:
5090 gen_sub_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5091 break;
5092 case OPC2_32_RR_SUB_B:
5093 gen_helper_sub_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
5094 break;
5095 case OPC2_32_RR_SUB_H:
5096 gen_helper_sub_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
5097 break;
5098 case OPC2_32_RR_SUBC:
5099 gen_subc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5100 break;
5101 case OPC2_32_RR_SUBS:
5102 gen_subs(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5103 break;
5104 case OPC2_32_RR_SUBS_U:
5105 gen_subsu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5106 break;
5107 case OPC2_32_RR_SUBS_H:
5108 gen_helper_sub_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5109 cpu_gpr_d[r2]);
5110 break;
5111 case OPC2_32_RR_SUBS_HU:
5112 gen_helper_sub_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5113 cpu_gpr_d[r2]);
5114 break;
5115 case OPC2_32_RR_SUBX:
5116 gen_sub_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5117 break;
5118 case OPC2_32_RR_XOR_EQ:
5119 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
5120 cpu_gpr_d[r2], &tcg_gen_xor_tl);
5121 break;
5122 case OPC2_32_RR_XOR_GE:
5123 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5124 cpu_gpr_d[r2], &tcg_gen_xor_tl);
5125 break;
5126 case OPC2_32_RR_XOR_GE_U:
5127 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5128 cpu_gpr_d[r2], &tcg_gen_xor_tl);
5129 break;
5130 case OPC2_32_RR_XOR_LT:
5131 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
5132 cpu_gpr_d[r2], &tcg_gen_xor_tl);
5133 break;
5134 case OPC2_32_RR_XOR_LT_U:
5135 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5136 cpu_gpr_d[r2], &tcg_gen_xor_tl);
5137 break;
5138 case OPC2_32_RR_XOR_NE:
5139 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5140 cpu_gpr_d[r2], &tcg_gen_xor_tl);
5141 break;
5142 }
5143 }
5144
5145 static void decode_rr_logical_shift(CPUTriCoreState *env, DisasContext *ctx)
5146 {
5147 uint32_t op2;
5148 int r3, r2, r1;
5149 TCGv temp;
5150
5151 r3 = MASK_OP_RR_D(ctx->opcode);
5152 r2 = MASK_OP_RR_S2(ctx->opcode);
5153 r1 = MASK_OP_RR_S1(ctx->opcode);
5154
5155 temp = tcg_temp_new();
5156 op2 = MASK_OP_RR_OP2(ctx->opcode);
5157
5158 switch (op2) {
5159 case OPC2_32_RR_AND:
5160 tcg_gen_and_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5161 break;
5162 case OPC2_32_RR_ANDN:
5163 tcg_gen_andc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5164 break;
5165 case OPC2_32_RR_CLO:
5166 gen_helper_clo(cpu_gpr_d[r3], cpu_gpr_d[r1]);
5167 break;
5168 case OPC2_32_RR_CLO_H:
5169 gen_helper_clo_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
5170 break;
5171 case OPC2_32_RR_CLS:
5172 gen_helper_cls(cpu_gpr_d[r3], cpu_gpr_d[r1]);
5173 break;
5174 case OPC2_32_RR_CLS_H:
5175 gen_helper_cls_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
5176 break;
5177 case OPC2_32_RR_CLZ:
5178 gen_helper_clz(cpu_gpr_d[r3], cpu_gpr_d[r1]);
5179 break;
5180 case OPC2_32_RR_CLZ_H:
5181 gen_helper_clz_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
5182 break;
5183 case OPC2_32_RR_NAND:
5184 tcg_gen_nand_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5185 break;
5186 case OPC2_32_RR_NOR:
5187 tcg_gen_nor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5188 break;
5189 case OPC2_32_RR_OR:
5190 tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5191 break;
5192 case OPC2_32_RR_ORN:
5193 tcg_gen_orc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5194 break;
5195 case OPC2_32_RR_SH:
5196 gen_helper_sh(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5197 break;
5198 case OPC2_32_RR_SH_H:
5199 gen_helper_sh_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5200 break;
5201 case OPC2_32_RR_SHA:
5202 gen_helper_sha(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
5203 break;
5204 case OPC2_32_RR_SHA_H:
5205 gen_helper_sha_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5206 break;
5207 case OPC2_32_RR_SHAS:
5208 gen_shas(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5209 break;
5210 case OPC2_32_RR_XNOR:
5211 tcg_gen_eqv_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5212 break;
5213 case OPC2_32_RR_XOR:
5214 tcg_gen_xor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5215 break;
5216 }
5217 tcg_temp_free(temp);
5218 }
5219
5220 static void decode_rr_address(CPUTriCoreState *env, DisasContext *ctx)
5221 {
5222 uint32_t op2, n;
5223 int r1, r2, r3;
5224 TCGv temp;
5225
5226 op2 = MASK_OP_RR_OP2(ctx->opcode);
5227 r3 = MASK_OP_RR_D(ctx->opcode);
5228 r2 = MASK_OP_RR_S2(ctx->opcode);
5229 r1 = MASK_OP_RR_S1(ctx->opcode);
5230 n = MASK_OP_RR_N(ctx->opcode);
5231
5232 switch (op2) {
5233 case OPC2_32_RR_ADD_A:
5234 tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]);
5235 break;
5236 case OPC2_32_RR_ADDSC_A:
5237 temp = tcg_temp_new();
5238 tcg_gen_shli_tl(temp, cpu_gpr_d[r1], n);
5239 tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r2], temp);
5240 tcg_temp_free(temp);
5241 break;
5242 case OPC2_32_RR_ADDSC_AT:
5243 temp = tcg_temp_new();
5244 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 3);
5245 tcg_gen_add_tl(temp, cpu_gpr_a[r2], temp);
5246 tcg_gen_andi_tl(cpu_gpr_a[r3], temp, 0xFFFFFFFC);
5247 tcg_temp_free(temp);
5248 break;
5249 case OPC2_32_RR_EQ_A:
5250 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1],
5251 cpu_gpr_a[r2]);
5252 break;
5253 case OPC2_32_RR_EQZ:
5254 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1], 0);
5255 break;
5256 case OPC2_32_RR_GE_A:
5257 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_a[r1],
5258 cpu_gpr_a[r2]);
5259 break;
5260 case OPC2_32_RR_LT_A:
5261 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_a[r1],
5262 cpu_gpr_a[r2]);
5263 break;
5264 case OPC2_32_RR_MOV_A:
5265 tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_d[r2]);
5266 break;
5267 case OPC2_32_RR_MOV_AA:
5268 tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_a[r2]);
5269 break;
5270 case OPC2_32_RR_MOV_D:
5271 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_a[r2]);
5272 break;
5273 case OPC2_32_RR_NE_A:
5274 tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1],
5275 cpu_gpr_a[r2]);
5276 break;
5277 case OPC2_32_RR_NEZ_A:
5278 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1], 0);
5279 break;
5280 case OPC2_32_RR_SUB_A:
5281 tcg_gen_sub_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]);
5282 break;
5283 }
5284 }
5285
5286 static void decode_rr_idirect(CPUTriCoreState *env, DisasContext *ctx)
5287 {
5288 uint32_t op2;
5289 int r1;
5290
5291 op2 = MASK_OP_RR_OP2(ctx->opcode);
5292 r1 = MASK_OP_RR_S1(ctx->opcode);
5293
5294 switch (op2) {
5295 case OPC2_32_RR_JI:
5296 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
5297 break;
5298 case OPC2_32_RR_JLI:
5299 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc);
5300 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
5301 break;
5302 case OPC2_32_RR_CALLI:
5303 gen_helper_1arg(call, ctx->next_pc);
5304 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
5305 break;
5306 }
5307 tcg_gen_exit_tb(0);
5308 ctx->bstate = BS_BRANCH;
5309 }
5310
5311 static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx)
5312 {
5313 uint32_t op2;
5314 int r1, r2, r3;
5315
5316 TCGv temp, temp2;
5317
5318 op2 = MASK_OP_RR_OP2(ctx->opcode);
5319 r3 = MASK_OP_RR_D(ctx->opcode);
5320 r2 = MASK_OP_RR_S2(ctx->opcode);
5321 r1 = MASK_OP_RR_S1(ctx->opcode);
5322
5323 switch (op2) {
5324 case OPC2_32_RR_BMERGE:
5325 gen_helper_bmerge(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5326 break;
5327 case OPC2_32_RR_BSPLIT:
5328 gen_bsplit(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
5329 break;
5330 case OPC2_32_RR_DVINIT_B:
5331 gen_dvinit_b(env, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
5332 cpu_gpr_d[r2]);
5333 break;
5334 case OPC2_32_RR_DVINIT_BU:
5335 temp = tcg_temp_new();
5336 temp2 = tcg_temp_new();
5337 /* reset av */
5338 tcg_gen_movi_tl(cpu_PSW_AV, 0);
5339 if (!tricore_feature(env, TRICORE_FEATURE_131)) {
5340 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
5341 tcg_gen_neg_tl(temp, cpu_gpr_d[r3+1]);
5342 /* use cpu_PSW_AV to compare against 0 */
5343 tcg_gen_movcond_tl(TCG_COND_LT, temp, cpu_gpr_d[r3+1], cpu_PSW_AV,
5344 temp, cpu_gpr_d[r3+1]);
5345 tcg_gen_neg_tl(temp2, cpu_gpr_d[r2]);
5346 tcg_gen_movcond_tl(TCG_COND_LT, temp2, cpu_gpr_d[r2], cpu_PSW_AV,
5347 temp2, cpu_gpr_d[r2]);
5348 tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2);
5349 } else {
5350 /* overflow = (D[b] == 0) */
5351 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
5352 }
5353 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
5354 /* sv */
5355 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
5356 /* write result */
5357 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 8);
5358 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 24);
5359 tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp);
5360
5361 tcg_temp_free(temp);
5362 tcg_temp_free(temp2);
5363 break;
5364 case OPC2_32_RR_DVINIT_H:
5365 gen_dvinit_h(env, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
5366 cpu_gpr_d[r2]);
5367 break;
5368 case OPC2_32_RR_DVINIT_HU:
5369 temp = tcg_temp_new();
5370 temp2 = tcg_temp_new();
5371 /* reset av */
5372 tcg_gen_movi_tl(cpu_PSW_AV, 0);
5373 if (!tricore_feature(env, TRICORE_FEATURE_131)) {
5374 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
5375 tcg_gen_neg_tl(temp, cpu_gpr_d[r3+1]);
5376 /* use cpu_PSW_AV to compare against 0 */
5377 tcg_gen_movcond_tl(TCG_COND_LT, temp, cpu_gpr_d[r3+1], cpu_PSW_AV,
5378 temp, cpu_gpr_d[r3+1]);
5379 tcg_gen_neg_tl(temp2, cpu_gpr_d[r2]);
5380 tcg_gen_movcond_tl(TCG_COND_LT, temp2, cpu_gpr_d[r2], cpu_PSW_AV,
5381 temp2, cpu_gpr_d[r2]);
5382 tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2);
5383 } else {
5384 /* overflow = (D[b] == 0) */
5385 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
5386 }
5387 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
5388 /* sv */
5389 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
5390 /* write result */
5391 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
5392 tcg_gen_shri_tl(cpu_gpr_d[r3+1], temp, 16);
5393 tcg_gen_shli_tl(cpu_gpr_d[r3], temp, 16);
5394 tcg_temp_free(temp);
5395 tcg_temp_free(temp2);
5396 break;
5397 case OPC2_32_RR_DVINIT:
5398 temp = tcg_temp_new();
5399 temp2 = tcg_temp_new();
5400 /* overflow = ((D[b] == 0) ||
5401 ((D[b] == 0xFFFFFFFF) && (D[a] == 0x80000000))) */
5402 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, cpu_gpr_d[r2], 0xffffffff);
5403 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r1], 0x80000000);
5404 tcg_gen_and_tl(temp, temp, temp2);
5405 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r2], 0);
5406 tcg_gen_or_tl(cpu_PSW_V, temp, temp2);
5407 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
5408 /* sv */
5409 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
5410 /* reset av */
5411 tcg_gen_movi_tl(cpu_PSW_AV, 0);
5412 /* write result */
5413 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
5414 /* sign extend to high reg */
5415 tcg_gen_sari_tl(cpu_gpr_d[r3+1], cpu_gpr_d[r1], 31);
5416 tcg_temp_free(temp);
5417 tcg_temp_free(temp2);
5418 break;
5419 case OPC2_32_RR_DVINIT_U:
5420 /* overflow = (D[b] == 0) */
5421 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
5422 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
5423 /* sv */
5424 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
5425 /* reset av */
5426 tcg_gen_movi_tl(cpu_PSW_AV, 0);
5427 /* write result */
5428 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
5429 /* zero extend to high reg*/
5430 tcg_gen_movi_tl(cpu_gpr_d[r3+1], 0);
5431 break;
5432 case OPC2_32_RR_PARITY:
5433 gen_helper_parity(cpu_gpr_d[r3], cpu_gpr_d[r1]);
5434 break;
5435 case OPC2_32_RR_UNPACK:
5436 gen_unpack(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
5437 break;
5438 }
5439 }
5440
5441 /* RR1 Format */
5442 static void decode_rr1_mul(CPUTriCoreState *env, DisasContext *ctx)
5443 {
5444 uint32_t op2;
5445
5446 int r1, r2, r3;
5447 TCGv n;
5448 TCGv_i64 temp64;
5449
5450 r1 = MASK_OP_RR1_S1(ctx->opcode);
5451 r2 = MASK_OP_RR1_S2(ctx->opcode);
5452 r3 = MASK_OP_RR1_D(ctx->opcode);
5453 n = tcg_const_i32(MASK_OP_RR1_N(ctx->opcode));
5454 op2 = MASK_OP_RR1_OP2(ctx->opcode);
5455
5456 switch (op2) {
5457 case OPC2_32_RR1_MUL_H_32_LL:
5458 temp64 = tcg_temp_new_i64();
5459 GEN_HELPER_LL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
5460 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
5461 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
5462 tcg_temp_free_i64(temp64);
5463 break;
5464 case OPC2_32_RR1_MUL_H_32_LU:
5465 temp64 = tcg_temp_new_i64();
5466 GEN_HELPER_LU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
5467 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
5468 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
5469 tcg_temp_free_i64(temp64);
5470 break;
5471 case OPC2_32_RR1_MUL_H_32_UL:
5472 temp64 = tcg_temp_new_i64();
5473 GEN_HELPER_UL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
5474 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
5475 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
5476 tcg_temp_free_i64(temp64);
5477 break;
5478 case OPC2_32_RR1_MUL_H_32_UU:
5479 temp64 = tcg_temp_new_i64();
5480 GEN_HELPER_UU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
5481 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
5482 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
5483 tcg_temp_free_i64(temp64);
5484 break;
5485 case OPC2_32_RR1_MULM_H_64_LL:
5486 temp64 = tcg_temp_new_i64();
5487 GEN_HELPER_LL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
5488 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
5489 /* reset V bit */
5490 tcg_gen_movi_tl(cpu_PSW_V, 0);
5491 /* reset AV bit */
5492 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
5493 tcg_temp_free_i64(temp64);
5494 break;
5495 case OPC2_32_RR1_MULM_H_64_LU:
5496 temp64 = tcg_temp_new_i64();
5497 GEN_HELPER_LU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
5498 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
5499 /* reset V bit */
5500 tcg_gen_movi_tl(cpu_PSW_V, 0);
5501 /* reset AV bit */
5502 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
5503 tcg_temp_free_i64(temp64);
5504 break;
5505 case OPC2_32_RR1_MULM_H_64_UL:
5506 temp64 = tcg_temp_new_i64();
5507 GEN_HELPER_UL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
5508 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
5509 /* reset V bit */
5510 tcg_gen_movi_tl(cpu_PSW_V, 0);
5511 /* reset AV bit */
5512 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
5513 tcg_temp_free_i64(temp64);
5514 break;
5515 case OPC2_32_RR1_MULM_H_64_UU:
5516 temp64 = tcg_temp_new_i64();
5517 GEN_HELPER_UU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
5518 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
5519 /* reset V bit */
5520 tcg_gen_movi_tl(cpu_PSW_V, 0);
5521 /* reset AV bit */
5522 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
5523 tcg_temp_free_i64(temp64);
5524
5525 break;
5526 case OPC2_32_RR1_MULR_H_16_LL:
5527 GEN_HELPER_LL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
5528 gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
5529 break;
5530 case OPC2_32_RR1_MULR_H_16_LU:
5531 GEN_HELPER_LU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
5532 gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
5533 break;
5534 case OPC2_32_RR1_MULR_H_16_UL:
5535 GEN_HELPER_UL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
5536 gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
5537 break;
5538 case OPC2_32_RR1_MULR_H_16_UU:
5539 GEN_HELPER_UU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
5540 gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
5541 break;
5542 }
5543 tcg_temp_free(n);
5544 }
5545
5546 static void decode_rr1_mulq(CPUTriCoreState *env, DisasContext *ctx)
5547 {
5548 uint32_t op2;
5549 int r1, r2, r3;
5550 uint32_t n;
5551
5552 TCGv temp, temp2;
5553
5554 r1 = MASK_OP_RR1_S1(ctx->opcode);
5555 r2 = MASK_OP_RR1_S2(ctx->opcode);
5556 r3 = MASK_OP_RR1_D(ctx->opcode);
5557 n = MASK_OP_RR1_N(ctx->opcode);
5558 op2 = MASK_OP_RR1_OP2(ctx->opcode);
5559
5560 temp = tcg_temp_new();
5561 temp2 = tcg_temp_new();
5562
5563 switch (op2) {
5564 case OPC2_32_RR1_MUL_Q_32:
5565 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], cpu_gpr_d[r2], n, 32);
5566 break;
5567 case OPC2_32_RR1_MUL_Q_64:
5568 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
5569 n, 0);
5570 break;
5571 case OPC2_32_RR1_MUL_Q_32_L:
5572 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
5573 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16);
5574 break;
5575 case OPC2_32_RR1_MUL_Q_64_L:
5576 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
5577 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0);
5578 break;
5579 case OPC2_32_RR1_MUL_Q_32_U:
5580 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
5581 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16);
5582 break;
5583 case OPC2_32_RR1_MUL_Q_64_U:
5584 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
5585 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0);
5586 break;
5587 case OPC2_32_RR1_MUL_Q_32_LL:
5588 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
5589 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
5590 gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n);
5591 break;
5592 case OPC2_32_RR1_MUL_Q_32_UU:
5593 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
5594 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
5595 gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n);
5596 break;
5597 case OPC2_32_RR1_MULR_Q_32_L:
5598 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
5599 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
5600 gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n);
5601 break;
5602 case OPC2_32_RR1_MULR_Q_32_U:
5603 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
5604 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
5605 gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n);
5606 break;
5607 }
5608 tcg_temp_free(temp);
5609 tcg_temp_free(temp2);
5610 }
5611
5612 /* RR2 format */
5613 static void decode_rr2_mul(CPUTriCoreState *env, DisasContext *ctx)
5614 {
5615 uint32_t op2;
5616 int r1, r2, r3;
5617
5618 op2 = MASK_OP_RR2_OP2(ctx->opcode);
5619 r1 = MASK_OP_RR2_S1(ctx->opcode);
5620 r2 = MASK_OP_RR2_S2(ctx->opcode);
5621 r3 = MASK_OP_RR2_D(ctx->opcode);
5622 switch (op2) {
5623 case OPC2_32_RR2_MUL_32:
5624 gen_mul_i32s(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5625 break;
5626 case OPC2_32_RR2_MUL_64:
5627 gen_mul_i64s(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
5628 cpu_gpr_d[r2]);
5629 break;
5630 case OPC2_32_RR2_MULS_32:
5631 gen_helper_mul_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5632 cpu_gpr_d[r2]);
5633 break;
5634 case OPC2_32_RR2_MUL_U_64:
5635 gen_mul_i64u(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
5636 cpu_gpr_d[r2]);
5637 break;
5638 case OPC2_32_RR2_MULS_U_32:
5639 gen_helper_mul_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5640 cpu_gpr_d[r2]);
5641 break;
5642 }
5643 }
5644
5645 /* RRPW format */
5646 static void decode_rrpw_extract_insert(CPUTriCoreState *env, DisasContext *ctx)
5647 {
5648 uint32_t op2;
5649 int r1, r2, r3;
5650 int32_t pos, width;
5651
5652 op2 = MASK_OP_RRPW_OP2(ctx->opcode);
5653 r1 = MASK_OP_RRPW_S1(ctx->opcode);
5654 r2 = MASK_OP_RRPW_S2(ctx->opcode);
5655 r3 = MASK_OP_RRPW_D(ctx->opcode);
5656 pos = MASK_OP_RRPW_POS(ctx->opcode);
5657 width = MASK_OP_RRPW_WIDTH(ctx->opcode);
5658
5659 switch (op2) {
5660 case OPC2_32_RRPW_EXTR:
5661 if (pos + width <= 31) {
5662 /* optimize special cases */
5663 if ((pos == 0) && (width == 8)) {
5664 tcg_gen_ext8s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
5665 } else if ((pos == 0) && (width == 16)) {
5666 tcg_gen_ext16s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
5667 } else {
5668 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 32 - pos - width);
5669 tcg_gen_sari_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 32 - width);
5670 }
5671 }
5672 break;
5673 case OPC2_32_RRPW_EXTR_U:
5674 if (width == 0) {
5675 tcg_gen_movi_tl(cpu_gpr_d[r3], 0);
5676 } else {
5677 tcg_gen_shri_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], pos);
5678 tcg_gen_andi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], ~0u >> (32-width));
5679 }
5680 break;
5681 case OPC2_32_RRPW_IMASK:
5682 if (pos + width <= 31) {
5683 tcg_gen_movi_tl(cpu_gpr_d[r3+1], ((1u << width) - 1) << pos);
5684 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], pos);
5685 }
5686 break;
5687 case OPC2_32_RRPW_INSERT:
5688 if (pos + width <= 31) {
5689 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
5690 width, pos);
5691 }
5692 break;
5693 }
5694 }
5695
5696 /* RRR format */
5697 static void decode_rrr_cond_select(CPUTriCoreState *env, DisasContext *ctx)
5698 {
5699 uint32_t op2;
5700 int r1, r2, r3, r4;
5701 TCGv temp;
5702
5703 op2 = MASK_OP_RRR_OP2(ctx->opcode);
5704 r1 = MASK_OP_RRR_S1(ctx->opcode);
5705 r2 = MASK_OP_RRR_S2(ctx->opcode);
5706 r3 = MASK_OP_RRR_S3(ctx->opcode);
5707 r4 = MASK_OP_RRR_D(ctx->opcode);
5708
5709 switch (op2) {
5710 case OPC2_32_RRR_CADD:
5711 gen_cond_add(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2],
5712 cpu_gpr_d[r4], cpu_gpr_d[r3]);
5713 break;
5714 case OPC2_32_RRR_CADDN:
5715 gen_cond_add(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4],
5716 cpu_gpr_d[r3]);
5717 break;
5718 case OPC2_32_RRR_CSUB:
5719 gen_cond_sub(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4],
5720 cpu_gpr_d[r3]);
5721 break;
5722 case OPC2_32_RRR_CSUBN:
5723 gen_cond_sub(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4],
5724 cpu_gpr_d[r3]);
5725 break;
5726 case OPC2_32_RRR_SEL:
5727 temp = tcg_const_i32(0);
5728 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
5729 cpu_gpr_d[r1], cpu_gpr_d[r2]);
5730 tcg_temp_free(temp);
5731 break;
5732 case OPC2_32_RRR_SELN:
5733 temp = tcg_const_i32(0);
5734 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
5735 cpu_gpr_d[r1], cpu_gpr_d[r2]);
5736 tcg_temp_free(temp);
5737 break;
5738 }
5739 }
5740
5741 static void decode_rrr_divide(CPUTriCoreState *env, DisasContext *ctx)
5742 {
5743 uint32_t op2;
5744
5745 int r1, r2, r3, r4;
5746
5747 op2 = MASK_OP_RRR_OP2(ctx->opcode);
5748 r1 = MASK_OP_RRR_S1(ctx->opcode);
5749 r2 = MASK_OP_RRR_S2(ctx->opcode);
5750 r3 = MASK_OP_RRR_S3(ctx->opcode);
5751 r4 = MASK_OP_RRR_D(ctx->opcode);
5752
5753 switch (op2) {
5754 case OPC2_32_RRR_DVADJ:
5755 GEN_HELPER_RRR(dvadj, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
5756 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
5757 break;
5758 case OPC2_32_RRR_DVSTEP:
5759 GEN_HELPER_RRR(dvstep, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
5760 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
5761 break;
5762 case OPC2_32_RRR_DVSTEP_U:
5763 GEN_HELPER_RRR(dvstep_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
5764 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
5765 break;
5766 case OPC2_32_RRR_IXMAX:
5767 GEN_HELPER_RRR(ixmax, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
5768 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
5769 break;
5770 case OPC2_32_RRR_IXMAX_U:
5771 GEN_HELPER_RRR(ixmax_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
5772 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
5773 break;
5774 case OPC2_32_RRR_IXMIN:
5775 GEN_HELPER_RRR(ixmin, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
5776 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
5777 break;
5778 case OPC2_32_RRR_IXMIN_U:
5779 GEN_HELPER_RRR(ixmin_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
5780 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
5781 break;
5782 case OPC2_32_RRR_PACK:
5783 gen_helper_pack(cpu_gpr_d[r4], cpu_PSW_C, cpu_gpr_d[r3],
5784 cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
5785 break;
5786 }
5787 }
5788
5789 /* RRR2 format */
5790 static void decode_rrr2_madd(CPUTriCoreState *env, DisasContext *ctx)
5791 {
5792 uint32_t op2;
5793 uint32_t r1, r2, r3, r4;
5794
5795 op2 = MASK_OP_RRR2_OP2(ctx->opcode);
5796 r1 = MASK_OP_RRR2_S1(ctx->opcode);
5797 r2 = MASK_OP_RRR2_S2(ctx->opcode);
5798 r3 = MASK_OP_RRR2_S3(ctx->opcode);
5799 r4 = MASK_OP_RRR2_D(ctx->opcode);
5800 switch (op2) {
5801 case OPC2_32_RRR2_MADD_32:
5802 gen_madd32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3],
5803 cpu_gpr_d[r2]);
5804 break;
5805 case OPC2_32_RRR2_MADD_64:
5806 gen_madd64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5807 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
5808 break;
5809 case OPC2_32_RRR2_MADDS_32:
5810 gen_helper_madd32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
5811 cpu_gpr_d[r3], cpu_gpr_d[r2]);
5812 break;
5813 case OPC2_32_RRR2_MADDS_64:
5814 gen_madds_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5815 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
5816 break;
5817 case OPC2_32_RRR2_MADD_U_64:
5818 gen_maddu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5819 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
5820 break;
5821 case OPC2_32_RRR2_MADDS_U_32:
5822 gen_helper_madd32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
5823 cpu_gpr_d[r3], cpu_gpr_d[r2]);
5824 break;
5825 case OPC2_32_RRR2_MADDS_U_64:
5826 gen_maddsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5827 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
5828 break;
5829 }
5830 }
5831
5832 static void decode_rrr2_msub(CPUTriCoreState *env, DisasContext *ctx)
5833 {
5834 uint32_t op2;
5835 uint32_t r1, r2, r3, r4;
5836
5837 op2 = MASK_OP_RRR2_OP2(ctx->opcode);
5838 r1 = MASK_OP_RRR2_S1(ctx->opcode);
5839 r2 = MASK_OP_RRR2_S2(ctx->opcode);
5840 r3 = MASK_OP_RRR2_S3(ctx->opcode);
5841 r4 = MASK_OP_RRR2_D(ctx->opcode);
5842
5843 switch (op2) {
5844 case OPC2_32_RRR2_MSUB_32:
5845 gen_msub32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3],
5846 cpu_gpr_d[r2]);
5847 break;
5848 case OPC2_32_RRR2_MSUB_64:
5849 gen_msub64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5850 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
5851 break;
5852 case OPC2_32_RRR2_MSUBS_32:
5853 gen_helper_msub32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
5854 cpu_gpr_d[r3], cpu_gpr_d[r2]);
5855 break;
5856 case OPC2_32_RRR2_MSUBS_64:
5857 gen_msubs_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5858 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
5859 break;
5860 case OPC2_32_RRR2_MSUB_U_64:
5861 gen_msubu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5862 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
5863 break;
5864 case OPC2_32_RRR2_MSUBS_U_32:
5865 gen_helper_msub32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
5866 cpu_gpr_d[r3], cpu_gpr_d[r2]);
5867 break;
5868 case OPC2_32_RRR2_MSUBS_U_64:
5869 gen_msubsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5870 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
5871 break;
5872 }
5873 }
5874
5875 /* RRR1 format */
5876 static void decode_rrr1_madd(CPUTriCoreState *env, DisasContext *ctx)
5877 {
5878 uint32_t op2;
5879 uint32_t r1, r2, r3, r4, n;
5880
5881 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
5882 r1 = MASK_OP_RRR1_S1(ctx->opcode);
5883 r2 = MASK_OP_RRR1_S2(ctx->opcode);
5884 r3 = MASK_OP_RRR1_S3(ctx->opcode);
5885 r4 = MASK_OP_RRR1_D(ctx->opcode);
5886 n = MASK_OP_RRR1_N(ctx->opcode);
5887
5888 switch (op2) {
5889 case OPC2_32_RRR1_MADD_H_LL:
5890 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
5891 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
5892 break;
5893 case OPC2_32_RRR1_MADD_H_LU:
5894 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
5895 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
5896 break;
5897 case OPC2_32_RRR1_MADD_H_UL:
5898 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
5899 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
5900 break;
5901 case OPC2_32_RRR1_MADD_H_UU:
5902 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
5903 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
5904 break;
5905 case OPC2_32_RRR1_MADDS_H_LL:
5906 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
5907 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
5908 break;
5909 case OPC2_32_RRR1_MADDS_H_LU:
5910 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
5911 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
5912 break;
5913 case OPC2_32_RRR1_MADDS_H_UL:
5914 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
5915 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
5916 break;
5917 case OPC2_32_RRR1_MADDS_H_UU:
5918 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
5919 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
5920 break;
5921 case OPC2_32_RRR1_MADDM_H_LL:
5922 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
5923 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
5924 break;
5925 case OPC2_32_RRR1_MADDM_H_LU:
5926 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
5927 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
5928 break;
5929 case OPC2_32_RRR1_MADDM_H_UL:
5930 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
5931 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
5932 break;
5933 case OPC2_32_RRR1_MADDM_H_UU:
5934 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
5935 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
5936 break;
5937 case OPC2_32_RRR1_MADDMS_H_LL:
5938 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
5939 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
5940 break;
5941 case OPC2_32_RRR1_MADDMS_H_LU:
5942 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
5943 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
5944 break;
5945 case OPC2_32_RRR1_MADDMS_H_UL:
5946 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
5947 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
5948 break;
5949 case OPC2_32_RRR1_MADDMS_H_UU:
5950 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
5951 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
5952 break;
5953 case OPC2_32_RRR1_MADDR_H_LL:
5954 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
5955 cpu_gpr_d[r2], n, MODE_LL);
5956 break;
5957 case OPC2_32_RRR1_MADDR_H_LU:
5958 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
5959 cpu_gpr_d[r2], n, MODE_LU);
5960 break;
5961 case OPC2_32_RRR1_MADDR_H_UL:
5962 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
5963 cpu_gpr_d[r2], n, MODE_UL);
5964 break;
5965 case OPC2_32_RRR1_MADDR_H_UU:
5966 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
5967 cpu_gpr_d[r2], n, MODE_UU);
5968 break;
5969 case OPC2_32_RRR1_MADDRS_H_LL:
5970 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
5971 cpu_gpr_d[r2], n, MODE_LL);
5972 break;
5973 case OPC2_32_RRR1_MADDRS_H_LU:
5974 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
5975 cpu_gpr_d[r2], n, MODE_LU);
5976 break;
5977 case OPC2_32_RRR1_MADDRS_H_UL:
5978 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
5979 cpu_gpr_d[r2], n, MODE_UL);
5980 break;
5981 case OPC2_32_RRR1_MADDRS_H_UU:
5982 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
5983 cpu_gpr_d[r2], n, MODE_UU);
5984 break;
5985 }
5986 }
5987
5988 static void decode_rrr1_maddq_h(CPUTriCoreState *env, DisasContext *ctx)
5989 {
5990 uint32_t op2;
5991 uint32_t r1, r2, r3, r4, n;
5992 TCGv temp, temp2;
5993
5994 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
5995 r1 = MASK_OP_RRR1_S1(ctx->opcode);
5996 r2 = MASK_OP_RRR1_S2(ctx->opcode);
5997 r3 = MASK_OP_RRR1_S3(ctx->opcode);
5998 r4 = MASK_OP_RRR1_D(ctx->opcode);
5999 n = MASK_OP_RRR1_N(ctx->opcode);
6000
6001 temp = tcg_const_i32(n);
6002 temp2 = tcg_temp_new();
6003
6004 switch (op2) {
6005 case OPC2_32_RRR1_MADD_Q_32:
6006 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6007 cpu_gpr_d[r2], n, 32, env);
6008 break;
6009 case OPC2_32_RRR1_MADD_Q_64:
6010 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6011 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
6012 n, env);
6013 break;
6014 case OPC2_32_RRR1_MADD_Q_32_L:
6015 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
6016 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6017 temp, n, 16, env);
6018 break;
6019 case OPC2_32_RRR1_MADD_Q_64_L:
6020 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
6021 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6022 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
6023 n, env);
6024 break;
6025 case OPC2_32_RRR1_MADD_Q_32_U:
6026 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
6027 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6028 temp, n, 16, env);
6029 break;
6030 case OPC2_32_RRR1_MADD_Q_64_U:
6031 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
6032 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6033 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
6034 n, env);
6035 break;
6036 case OPC2_32_RRR1_MADD_Q_32_LL:
6037 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
6038 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
6039 gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
6040 break;
6041 case OPC2_32_RRR1_MADD_Q_64_LL:
6042 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
6043 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
6044 gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6045 cpu_gpr_d[r3+1], temp, temp2, n);
6046 break;
6047 case OPC2_32_RRR1_MADD_Q_32_UU:
6048 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
6049 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
6050 gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
6051 break;
6052 case OPC2_32_RRR1_MADD_Q_64_UU:
6053 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
6054 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
6055 gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6056 cpu_gpr_d[r3+1], temp, temp2, n);
6057 break;
6058 case OPC2_32_RRR1_MADDS_Q_32:
6059 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6060 cpu_gpr_d[r2], n, 32);
6061 break;
6062 case OPC2_32_RRR1_MADDS_Q_64:
6063 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6064 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
6065 n);
6066 break;
6067 case OPC2_32_RRR1_MADDS_Q_32_L:
6068 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
6069 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6070 temp, n, 16);
6071 break;
6072 case OPC2_32_RRR1_MADDS_Q_64_L:
6073 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
6074 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6075 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
6076 n);
6077 break;
6078 case OPC2_32_RRR1_MADDS_Q_32_U:
6079 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
6080 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6081 temp, n, 16);
6082 break;
6083 case OPC2_32_RRR1_MADDS_Q_64_U:
6084 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
6085 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6086 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
6087 n);
6088 break;
6089 case OPC2_32_RRR1_MADDS_Q_32_LL:
6090 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
6091 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
6092 gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
6093 break;
6094 case OPC2_32_RRR1_MADDS_Q_64_LL:
6095 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
6096 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
6097 gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6098 cpu_gpr_d[r3+1], temp, temp2, n);
6099 break;
6100 case OPC2_32_RRR1_MADDS_Q_32_UU:
6101 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
6102 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
6103 gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
6104 break;
6105 case OPC2_32_RRR1_MADDS_Q_64_UU:
6106 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
6107 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
6108 gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6109 cpu_gpr_d[r3+1], temp, temp2, n);
6110 break;
6111 case OPC2_32_RRR1_MADDR_H_64_UL:
6112 gen_maddr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
6113 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
6114 break;
6115 case OPC2_32_RRR1_MADDRS_H_64_UL:
6116 gen_maddr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
6117 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
6118 break;
6119 case OPC2_32_RRR1_MADDR_Q_32_LL:
6120 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
6121 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
6122 gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
6123 break;
6124 case OPC2_32_RRR1_MADDR_Q_32_UU:
6125 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
6126 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
6127 gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
6128 break;
6129 case OPC2_32_RRR1_MADDRS_Q_32_LL:
6130 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
6131 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
6132 gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
6133 break;
6134 case OPC2_32_RRR1_MADDRS_Q_32_UU:
6135 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
6136 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
6137 gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
6138 break;
6139 }
6140 tcg_temp_free(temp);
6141 tcg_temp_free(temp2);
6142 }
6143
6144 static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
6145 {
6146 int op1;
6147 int32_t r1, r2, r3;
6148 int32_t address, const16;
6149 int8_t b, const4;
6150 int32_t bpos;
6151 TCGv temp, temp2, temp3;
6152
6153 op1 = MASK_OP_MAJOR(ctx->opcode);
6154
6155 /* handle JNZ.T opcode only being 7 bit long */
6156 if (unlikely((op1 & 0x7f) == OPCM_32_BRN_JTT)) {
6157 op1 = OPCM_32_BRN_JTT;
6158 }
6159
6160 switch (op1) {
6161 /* ABS-format */
6162 case OPCM_32_ABS_LDW:
6163 decode_abs_ldw(env, ctx);
6164 break;
6165 case OPCM_32_ABS_LDB:
6166 decode_abs_ldb(env, ctx);
6167 break;
6168 case OPCM_32_ABS_LDMST_SWAP:
6169 decode_abs_ldst_swap(env, ctx);
6170 break;
6171 case OPCM_32_ABS_LDST_CONTEXT:
6172 decode_abs_ldst_context(env, ctx);
6173 break;
6174 case OPCM_32_ABS_STORE:
6175 decode_abs_store(env, ctx);
6176 break;
6177 case OPCM_32_ABS_STOREB_H:
6178 decode_abs_storeb_h(env, ctx);
6179 break;
6180 case OPC1_32_ABS_STOREQ:
6181 address = MASK_OP_ABS_OFF18(ctx->opcode);
6182 r1 = MASK_OP_ABS_S1D(ctx->opcode);
6183 temp = tcg_const_i32(EA_ABS_FORMAT(address));
6184 temp2 = tcg_temp_new();
6185
6186 tcg_gen_shri_tl(temp2, cpu_gpr_d[r1], 16);
6187 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_LEUW);
6188
6189 tcg_temp_free(temp2);
6190 tcg_temp_free(temp);
6191 break;
6192 case OPC1_32_ABS_LD_Q:
6193 address = MASK_OP_ABS_OFF18(ctx->opcode);
6194 r1 = MASK_OP_ABS_S1D(ctx->opcode);
6195 temp = tcg_const_i32(EA_ABS_FORMAT(address));
6196
6197 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
6198 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
6199
6200 tcg_temp_free(temp);
6201 break;
6202 case OPC1_32_ABS_LEA:
6203 address = MASK_OP_ABS_OFF18(ctx->opcode);
6204 r1 = MASK_OP_ABS_S1D(ctx->opcode);
6205 tcg_gen_movi_tl(cpu_gpr_a[r1], EA_ABS_FORMAT(address));
6206 break;
6207 /* ABSB-format */
6208 case OPC1_32_ABSB_ST_T:
6209 address = MASK_OP_ABS_OFF18(ctx->opcode);
6210 b = MASK_OP_ABSB_B(ctx->opcode);
6211 bpos = MASK_OP_ABSB_BPOS(ctx->opcode);
6212
6213 temp = tcg_const_i32(EA_ABS_FORMAT(address));
6214 temp2 = tcg_temp_new();
6215
6216 tcg_gen_qemu_ld_tl(temp2, temp, ctx->mem_idx, MO_UB);
6217 tcg_gen_andi_tl(temp2, temp2, ~(0x1u << bpos));
6218 tcg_gen_ori_tl(temp2, temp2, (b << bpos));
6219 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_UB);
6220
6221 tcg_temp_free(temp);
6222 tcg_temp_free(temp2);
6223 break;
6224 /* B-format */
6225 case OPC1_32_B_CALL:
6226 case OPC1_32_B_CALLA:
6227 case OPC1_32_B_J:
6228 case OPC1_32_B_JA:
6229 case OPC1_32_B_JL:
6230 case OPC1_32_B_JLA:
6231 address = MASK_OP_B_DISP24_SEXT(ctx->opcode);
6232 gen_compute_branch(ctx, op1, 0, 0, 0, address);
6233 break;
6234 /* Bit-format */
6235 case OPCM_32_BIT_ANDACC:
6236 decode_bit_andacc(env, ctx);
6237 break;
6238 case OPCM_32_BIT_LOGICAL_T1:
6239 decode_bit_logical_t(env, ctx);
6240 break;
6241 case OPCM_32_BIT_INSERT:
6242 decode_bit_insert(env, ctx);
6243 break;
6244 case OPCM_32_BIT_LOGICAL_T2:
6245 decode_bit_logical_t2(env, ctx);
6246 break;
6247 case OPCM_32_BIT_ORAND:
6248 decode_bit_orand(env, ctx);
6249 break;
6250 case OPCM_32_BIT_SH_LOGIC1:
6251 decode_bit_sh_logic1(env, ctx);
6252 break;
6253 case OPCM_32_BIT_SH_LOGIC2:
6254 decode_bit_sh_logic2(env, ctx);
6255 break;
6256 /* BO Format */
6257 case OPCM_32_BO_ADDRMODE_POST_PRE_BASE:
6258 decode_bo_addrmode_post_pre_base(env, ctx);
6259 break;
6260 case OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR:
6261 decode_bo_addrmode_bitreverse_circular(env, ctx);
6262 break;
6263 case OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE:
6264 decode_bo_addrmode_ld_post_pre_base(env, ctx);
6265 break;
6266 case OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR:
6267 decode_bo_addrmode_ld_bitreverse_circular(env, ctx);
6268 break;
6269 case OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE:
6270 decode_bo_addrmode_stctx_post_pre_base(env, ctx);
6271 break;
6272 case OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR:
6273 decode_bo_addrmode_ldmst_bitreverse_circular(env, ctx);
6274 break;
6275 /* BOL-format */
6276 case OPC1_32_BOL_LD_A_LONGOFF:
6277 case OPC1_32_BOL_LD_W_LONGOFF:
6278 case OPC1_32_BOL_LEA_LONGOFF:
6279 case OPC1_32_BOL_ST_W_LONGOFF:
6280 case OPC1_32_BOL_ST_A_LONGOFF:
6281 case OPC1_32_BOL_LD_B_LONGOFF:
6282 case OPC1_32_BOL_LD_BU_LONGOFF:
6283 case OPC1_32_BOL_LD_H_LONGOFF:
6284 case OPC1_32_BOL_LD_HU_LONGOFF:
6285 case OPC1_32_BOL_ST_B_LONGOFF:
6286 case OPC1_32_BOL_ST_H_LONGOFF:
6287 decode_bol_opc(env, ctx, op1);
6288 break;
6289 /* BRC Format */
6290 case OPCM_32_BRC_EQ_NEQ:
6291 case OPCM_32_BRC_GE:
6292 case OPCM_32_BRC_JLT:
6293 case OPCM_32_BRC_JNE:
6294 const4 = MASK_OP_BRC_CONST4_SEXT(ctx->opcode);
6295 address = MASK_OP_BRC_DISP15_SEXT(ctx->opcode);
6296 r1 = MASK_OP_BRC_S1(ctx->opcode);
6297 gen_compute_branch(ctx, op1, r1, 0, const4, address);
6298 break;
6299 /* BRN Format */
6300 case OPCM_32_BRN_JTT:
6301 address = MASK_OP_BRN_DISP15_SEXT(ctx->opcode);
6302 r1 = MASK_OP_BRN_S1(ctx->opcode);
6303 gen_compute_branch(ctx, op1, r1, 0, 0, address);
6304 break;
6305 /* BRR Format */
6306 case OPCM_32_BRR_EQ_NEQ:
6307 case OPCM_32_BRR_ADDR_EQ_NEQ:
6308 case OPCM_32_BRR_GE:
6309 case OPCM_32_BRR_JLT:
6310 case OPCM_32_BRR_JNE:
6311 case OPCM_32_BRR_JNZ:
6312 case OPCM_32_BRR_LOOP:
6313 address = MASK_OP_BRR_DISP15_SEXT(ctx->opcode);
6314 r2 = MASK_OP_BRR_S2(ctx->opcode);
6315 r1 = MASK_OP_BRR_S1(ctx->opcode);
6316 gen_compute_branch(ctx, op1, r1, r2, 0, address);
6317 break;
6318 /* RC Format */
6319 case OPCM_32_RC_LOGICAL_SHIFT:
6320 decode_rc_logical_shift(env, ctx);
6321 break;
6322 case OPCM_32_RC_ACCUMULATOR:
6323 decode_rc_accumulator(env, ctx);
6324 break;
6325 case OPCM_32_RC_SERVICEROUTINE:
6326 decode_rc_serviceroutine(env, ctx);
6327 break;
6328 case OPCM_32_RC_MUL:
6329 decode_rc_mul(env, ctx);
6330 break;
6331 /* RCPW Format */
6332 case OPCM_32_RCPW_MASK_INSERT:
6333 decode_rcpw_insert(env, ctx);
6334 break;
6335 /* RCRR Format */
6336 case OPC1_32_RCRR_INSERT:
6337 r1 = MASK_OP_RCRR_S1(ctx->opcode);
6338 r2 = MASK_OP_RCRR_S3(ctx->opcode);
6339 r3 = MASK_OP_RCRR_D(ctx->opcode);
6340 const16 = MASK_OP_RCRR_CONST4(ctx->opcode);
6341 temp = tcg_const_i32(const16);
6342 temp2 = tcg_temp_new(); /* width*/
6343 temp3 = tcg_temp_new(); /* pos */
6344
6345 tcg_gen_andi_tl(temp2, cpu_gpr_d[r3+1], 0x1f);
6346 tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f);
6347
6348 gen_insert(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, temp2, temp3);
6349
6350 tcg_temp_free(temp);
6351 tcg_temp_free(temp2);
6352 tcg_temp_free(temp3);
6353 break;
6354 /* RCRW Format */
6355 case OPCM_32_RCRW_MASK_INSERT:
6356 decode_rcrw_insert(env, ctx);
6357 break;
6358 /* RCR Format */
6359 case OPCM_32_RCR_COND_SELECT:
6360 decode_rcr_cond_select(env, ctx);
6361 break;
6362 case OPCM_32_RCR_MADD:
6363 decode_rcr_madd(env, ctx);
6364 break;
6365 case OPCM_32_RCR_MSUB:
6366 decode_rcr_msub(env, ctx);
6367 break;
6368 /* RLC Format */
6369 case OPC1_32_RLC_ADDI:
6370 case OPC1_32_RLC_ADDIH:
6371 case OPC1_32_RLC_ADDIH_A:
6372 case OPC1_32_RLC_MFCR:
6373 case OPC1_32_RLC_MOV:
6374 case OPC1_32_RLC_MOV_64:
6375 case OPC1_32_RLC_MOV_U:
6376 case OPC1_32_RLC_MOV_H:
6377 case OPC1_32_RLC_MOVH_A:
6378 case OPC1_32_RLC_MTCR:
6379 decode_rlc_opc(env, ctx, op1);
6380 break;
6381 /* RR Format */
6382 case OPCM_32_RR_ACCUMULATOR:
6383 decode_rr_accumulator(env, ctx);
6384 break;
6385 case OPCM_32_RR_LOGICAL_SHIFT:
6386 decode_rr_logical_shift(env, ctx);
6387 break;
6388 case OPCM_32_RR_ADDRESS:
6389 decode_rr_address(env, ctx);
6390 break;
6391 case OPCM_32_RR_IDIRECT:
6392 decode_rr_idirect(env, ctx);
6393 break;
6394 case OPCM_32_RR_DIVIDE:
6395 decode_rr_divide(env, ctx);
6396 break;
6397 /* RR1 Format */
6398 case OPCM_32_RR1_MUL:
6399 decode_rr1_mul(env, ctx);
6400 break;
6401 case OPCM_32_RR1_MULQ:
6402 decode_rr1_mulq(env, ctx);
6403 break;
6404 /* RR2 format */
6405 case OPCM_32_RR2_MUL:
6406 decode_rr2_mul(env, ctx);
6407 break;
6408 /* RRPW format */
6409 case OPCM_32_RRPW_EXTRACT_INSERT:
6410 decode_rrpw_extract_insert(env, ctx);
6411 break;
6412 case OPC1_32_RRPW_DEXTR:
6413 r1 = MASK_OP_RRPW_S1(ctx->opcode);
6414 r2 = MASK_OP_RRPW_S2(ctx->opcode);
6415 r3 = MASK_OP_RRPW_D(ctx->opcode);
6416 const16 = MASK_OP_RRPW_POS(ctx->opcode);
6417 if (r1 == r2) {
6418 tcg_gen_rotli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], const16);
6419 } else {
6420 temp = tcg_temp_new();
6421 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], const16);
6422 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 32 - const16);
6423 tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
6424 tcg_temp_free(temp);
6425 }
6426 break;
6427 /* RRR Format */
6428 case OPCM_32_RRR_COND_SELECT:
6429 decode_rrr_cond_select(env, ctx);
6430 break;
6431 case OPCM_32_RRR_DIVIDE:
6432 decode_rrr_divide(env, ctx);
6433 /* RRR2 Format */
6434 case OPCM_32_RRR2_MADD:
6435 decode_rrr2_madd(env, ctx);
6436 break;
6437 case OPCM_32_RRR2_MSUB:
6438 decode_rrr2_msub(env, ctx);
6439 break;
6440 /* RRR1 format */
6441 case OPCM_32_RRR1_MADD:
6442 decode_rrr1_madd(env, ctx);
6443 break;
6444 case OPCM_32_RRR1_MADDQ_H:
6445 decode_rrr1_maddq_h(env, ctx);
6446 break;
6447 }
6448 }
6449
6450 static void decode_opc(CPUTriCoreState *env, DisasContext *ctx, int *is_branch)
6451 {
6452 /* 16-Bit Instruction */
6453 if ((ctx->opcode & 0x1) == 0) {
6454 ctx->next_pc = ctx->pc + 2;
6455 decode_16Bit_opc(env, ctx);
6456 /* 32-Bit Instruction */
6457 } else {
6458 ctx->next_pc = ctx->pc + 4;
6459 decode_32Bit_opc(env, ctx);
6460 }
6461 }
6462
6463 static inline void
6464 gen_intermediate_code_internal(TriCoreCPU *cpu, struct TranslationBlock *tb,
6465 int search_pc)
6466 {
6467 CPUState *cs = CPU(cpu);
6468 CPUTriCoreState *env = &cpu->env;
6469 DisasContext ctx;
6470 target_ulong pc_start;
6471 int num_insns;
6472
6473 if (search_pc) {
6474 qemu_log("search pc %d\n", search_pc);
6475 }
6476
6477 num_insns = 0;
6478 pc_start = tb->pc;
6479 ctx.pc = pc_start;
6480 ctx.saved_pc = -1;
6481 ctx.tb = tb;
6482 ctx.singlestep_enabled = cs->singlestep_enabled;
6483 ctx.bstate = BS_NONE;
6484 ctx.mem_idx = cpu_mmu_index(env);
6485
6486 tcg_clear_temp_count();
6487 gen_tb_start(tb);
6488 while (ctx.bstate == BS_NONE) {
6489 ctx.opcode = cpu_ldl_code(env, ctx.pc);
6490 decode_opc(env, &ctx, 0);
6491
6492 num_insns++;
6493
6494 if (tcg_op_buf_full()) {
6495 gen_save_pc(ctx.next_pc);
6496 tcg_gen_exit_tb(0);
6497 break;
6498 }
6499 if (singlestep) {
6500 gen_save_pc(ctx.next_pc);
6501 tcg_gen_exit_tb(0);
6502 break;
6503 }
6504 ctx.pc = ctx.next_pc;
6505 }
6506
6507 gen_tb_end(tb, num_insns);
6508 if (search_pc) {
6509 printf("done_generating search pc\n");
6510 } else {
6511 tb->size = ctx.pc - pc_start;
6512 tb->icount = num_insns;
6513 }
6514 if (tcg_check_temp_count()) {
6515 printf("LEAK at %08x\n", env->PC);
6516 }
6517
6518 #ifdef DEBUG_DISAS
6519 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
6520 qemu_log("IN: %s\n", lookup_symbol(pc_start));
6521 log_target_disas(env, pc_start, ctx.pc - pc_start, 0);
6522 qemu_log("\n");
6523 }
6524 #endif
6525 }
6526
6527 void
6528 gen_intermediate_code(CPUTriCoreState *env, struct TranslationBlock *tb)
6529 {
6530 gen_intermediate_code_internal(tricore_env_get_cpu(env), tb, false);
6531 }
6532
6533 void
6534 gen_intermediate_code_pc(CPUTriCoreState *env, struct TranslationBlock *tb)
6535 {
6536 gen_intermediate_code_internal(tricore_env_get_cpu(env), tb, true);
6537 }
6538
6539 void
6540 restore_state_to_opc(CPUTriCoreState *env, TranslationBlock *tb, int pc_pos)
6541 {
6542 env->PC = tcg_ctx.gen_opc_pc[pc_pos];
6543 }
6544 /*
6545 *
6546 * Initialization
6547 *
6548 */
6549
6550 void cpu_state_reset(CPUTriCoreState *env)
6551 {
6552 /* Reset Regs to Default Value */
6553 env->PSW = 0xb80;
6554 }
6555
6556 static void tricore_tcg_init_csfr(void)
6557 {
6558 cpu_PCXI = tcg_global_mem_new(TCG_AREG0,
6559 offsetof(CPUTriCoreState, PCXI), "PCXI");
6560 cpu_PSW = tcg_global_mem_new(TCG_AREG0,
6561 offsetof(CPUTriCoreState, PSW), "PSW");
6562 cpu_PC = tcg_global_mem_new(TCG_AREG0,
6563 offsetof(CPUTriCoreState, PC), "PC");
6564 cpu_ICR = tcg_global_mem_new(TCG_AREG0,
6565 offsetof(CPUTriCoreState, ICR), "ICR");
6566 }
6567
6568 void tricore_tcg_init(void)
6569 {
6570 int i;
6571 static int inited;
6572 if (inited) {
6573 return;
6574 }
6575 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
6576 /* reg init */
6577 for (i = 0 ; i < 16 ; i++) {
6578 cpu_gpr_a[i] = tcg_global_mem_new(TCG_AREG0,
6579 offsetof(CPUTriCoreState, gpr_a[i]),
6580 regnames_a[i]);
6581 }
6582 for (i = 0 ; i < 16 ; i++) {
6583 cpu_gpr_d[i] = tcg_global_mem_new(TCG_AREG0,
6584 offsetof(CPUTriCoreState, gpr_d[i]),
6585 regnames_d[i]);
6586 }
6587 tricore_tcg_init_csfr();
6588 /* init PSW flag cache */
6589 cpu_PSW_C = tcg_global_mem_new(TCG_AREG0,
6590 offsetof(CPUTriCoreState, PSW_USB_C),
6591 "PSW_C");
6592 cpu_PSW_V = tcg_global_mem_new(TCG_AREG0,
6593 offsetof(CPUTriCoreState, PSW_USB_V),
6594 "PSW_V");
6595 cpu_PSW_SV = tcg_global_mem_new(TCG_AREG0,
6596 offsetof(CPUTriCoreState, PSW_USB_SV),
6597 "PSW_SV");
6598 cpu_PSW_AV = tcg_global_mem_new(TCG_AREG0,
6599 offsetof(CPUTriCoreState, PSW_USB_AV),
6600 "PSW_AV");
6601 cpu_PSW_SAV = tcg_global_mem_new(TCG_AREG0,
6602 offsetof(CPUTriCoreState, PSW_USB_SAV),
6603 "PSW_SAV");
6604 }
AR7 emulation for QEMU