4 * Copyright (c) 2005-2007 CodeSourcery, LLC
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qemu/units.h"
22 #include "qemu/main-loop.h"
24 #include "exec/helper-proto.h"
25 #include "internals.h"
26 #include "exec/exec-all.h"
27 #include "exec/cpu_ldst.h"
29 #define SIGNBIT (uint32_t)0x80000000
30 #define SIGNBIT64 ((uint64_t)1 << 63)
32 static CPUState
*do_raise_exception(CPUARMState
*env
, uint32_t excp
,
33 uint32_t syndrome
, uint32_t target_el
)
35 CPUState
*cs
= env_cpu(env
);
37 if (target_el
== 1 && (arm_hcr_el2_eff(env
) & HCR_TGE
)) {
39 * Redirect NS EL1 exceptions to NS EL2. These are reported with
40 * their original syndrome register value, with the exception of
41 * SIMD/FP access traps, which are reported as uncategorized
42 * (see DDI0478C.a D1.10.4)
45 if (syn_get_ec(syndrome
) == EC_ADVSIMDFPACCESSTRAP
) {
46 syndrome
= syn_uncategorized();
50 assert(!excp_is_internal(excp
));
51 cs
->exception_index
= excp
;
52 env
->exception
.syndrome
= syndrome
;
53 env
->exception
.target_el
= target_el
;
58 void raise_exception(CPUARMState
*env
, uint32_t excp
,
59 uint32_t syndrome
, uint32_t target_el
)
61 CPUState
*cs
= do_raise_exception(env
, excp
, syndrome
, target_el
);
65 void raise_exception_ra(CPUARMState
*env
, uint32_t excp
, uint32_t syndrome
,
66 uint32_t target_el
, uintptr_t ra
)
68 CPUState
*cs
= do_raise_exception(env
, excp
, syndrome
, target_el
);
69 cpu_loop_exit_restore(cs
, ra
);
72 uint32_t HELPER(neon_tbl
)(uint32_t ireg
, uint32_t def
, void *vn
,
79 for (shift
= 0; shift
< 32; shift
+= 8) {
80 uint32_t index
= (ireg
>> shift
) & 0xff;
81 if (index
< maxindex
) {
82 uint32_t tmp
= (table
[index
>> 3] >> ((index
& 7) << 3)) & 0xff;
85 val
|= def
& (0xff << shift
);
91 void HELPER(v8m_stackcheck
)(CPUARMState
*env
, uint32_t newvalue
)
94 * Perform the v8M stack limit check for SP updates from translated code,
95 * raising an exception if the limit is breached.
97 if (newvalue
< v7m_sp_limit(env
)) {
98 CPUState
*cs
= env_cpu(env
);
101 * Stack limit exceptions are a rare case, so rather than syncing
102 * PC/condbits before the call, we use cpu_restore_state() to
103 * get them right before raising the exception.
105 cpu_restore_state(cs
, GETPC(), true);
106 raise_exception(env
, EXCP_STKOF
, 0, 1);
110 uint32_t HELPER(add_setq
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
112 uint32_t res
= a
+ b
;
113 if (((res
^ a
) & SIGNBIT
) && !((a
^ b
) & SIGNBIT
))
118 uint32_t HELPER(add_saturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
120 uint32_t res
= a
+ b
;
121 if (((res
^ a
) & SIGNBIT
) && !((a
^ b
) & SIGNBIT
)) {
123 res
= ~(((int32_t)a
>> 31) ^ SIGNBIT
);
128 uint32_t HELPER(sub_saturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
130 uint32_t res
= a
- b
;
131 if (((res
^ a
) & SIGNBIT
) && ((a
^ b
) & SIGNBIT
)) {
133 res
= ~(((int32_t)a
>> 31) ^ SIGNBIT
);
138 uint32_t HELPER(add_usaturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
140 uint32_t res
= a
+ b
;
148 uint32_t HELPER(sub_usaturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
150 uint32_t res
= a
- b
;
158 /* Signed saturation. */
159 static inline uint32_t do_ssat(CPUARMState
*env
, int32_t val
, int shift
)
165 mask
= (1u << shift
) - 1;
169 } else if (top
< -1) {
176 /* Unsigned saturation. */
177 static inline uint32_t do_usat(CPUARMState
*env
, int32_t val
, int shift
)
181 max
= (1u << shift
) - 1;
185 } else if (val
> max
) {
192 /* Signed saturate. */
193 uint32_t HELPER(ssat
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
195 return do_ssat(env
, x
, shift
);
198 /* Dual halfword signed saturate. */
199 uint32_t HELPER(ssat16
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
203 res
= (uint16_t)do_ssat(env
, (int16_t)x
, shift
);
204 res
|= do_ssat(env
, ((int32_t)x
) >> 16, shift
) << 16;
208 /* Unsigned saturate. */
209 uint32_t HELPER(usat
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
211 return do_usat(env
, x
, shift
);
214 /* Dual halfword unsigned saturate. */
215 uint32_t HELPER(usat16
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
219 res
= (uint16_t)do_usat(env
, (int16_t)x
, shift
);
220 res
|= do_usat(env
, ((int32_t)x
) >> 16, shift
) << 16;
224 void HELPER(setend
)(CPUARMState
*env
)
226 env
->uncached_cpsr
^= CPSR_E
;
229 /* Function checks whether WFx (WFI/WFE) instructions are set up to be trapped.
230 * The function returns the target EL (1-3) if the instruction is to be trapped;
231 * otherwise it returns 0 indicating it is not trapped.
233 static inline int check_wfx_trap(CPUARMState
*env
, bool is_wfe
)
235 int cur_el
= arm_current_el(env
);
238 if (arm_feature(env
, ARM_FEATURE_M
)) {
239 /* M profile cores can never trap WFI/WFE. */
243 /* If we are currently in EL0 then we need to check if SCTLR is set up for
244 * WFx instructions being trapped to EL1. These trap bits don't exist in v7.
246 if (cur_el
< 1 && arm_feature(env
, ARM_FEATURE_V8
)) {
249 mask
= is_wfe
? SCTLR_nTWE
: SCTLR_nTWI
;
250 if (arm_is_secure_below_el3(env
) && !arm_el_is_aa64(env
, 3)) {
251 /* Secure EL0 and Secure PL1 is at EL3 */
257 if (!(env
->cp15
.sctlr_el
[target_el
] & mask
)) {
262 /* We are not trapping to EL1; trap to EL2 if HCR_EL2 requires it
263 * No need for ARM_FEATURE check as if HCR_EL2 doesn't exist the
264 * bits will be zero indicating no trap.
267 mask
= is_wfe
? HCR_TWE
: HCR_TWI
;
268 if (arm_hcr_el2_eff(env
) & mask
) {
273 /* We are not trapping to EL1 or EL2; trap to EL3 if SCR_EL3 requires it */
275 mask
= (is_wfe
) ? SCR_TWE
: SCR_TWI
;
276 if (env
->cp15
.scr_el3
& mask
) {
284 void HELPER(wfi
)(CPUARMState
*env
, uint32_t insn_len
)
286 CPUState
*cs
= env_cpu(env
);
287 int target_el
= check_wfx_trap(env
, false);
289 if (cpu_has_work(cs
)) {
290 /* Don't bother to go into our "low power state" if
291 * we would just wake up immediately.
298 raise_exception(env
, EXCP_UDEF
, syn_wfx(1, 0xe, 0, insn_len
== 2),
302 cs
->exception_index
= EXCP_HLT
;
307 void HELPER(wfe
)(CPUARMState
*env
)
309 /* This is a hint instruction that is semantically different
310 * from YIELD even though we currently implement it identically.
311 * Don't actually halt the CPU, just yield back to top
312 * level loop. This is not going into a "low power state"
313 * (ie halting until some event occurs), so we never take
314 * a configurable trap to a different exception level.
319 void HELPER(yield
)(CPUARMState
*env
)
321 CPUState
*cs
= env_cpu(env
);
323 /* This is a non-trappable hint instruction that generally indicates
324 * that the guest is currently busy-looping. Yield control back to the
325 * top level loop so that a more deserving VCPU has a chance to run.
327 cs
->exception_index
= EXCP_YIELD
;
331 /* Raise an internal-to-QEMU exception. This is limited to only
332 * those EXCP values which are special cases for QEMU to interrupt
333 * execution and not to be used for exceptions which are passed to
334 * the guest (those must all have syndrome information and thus should
335 * use exception_with_syndrome).
337 void HELPER(exception_internal
)(CPUARMState
*env
, uint32_t excp
)
339 CPUState
*cs
= env_cpu(env
);
341 assert(excp_is_internal(excp
));
342 cs
->exception_index
= excp
;
346 /* Raise an exception with the specified syndrome register value */
347 void HELPER(exception_with_syndrome
)(CPUARMState
*env
, uint32_t excp
,
348 uint32_t syndrome
, uint32_t target_el
)
350 raise_exception(env
, excp
, syndrome
, target_el
);
353 /* Raise an EXCP_BKPT with the specified syndrome register value,
354 * targeting the correct exception level for debug exceptions.
356 void HELPER(exception_bkpt_insn
)(CPUARMState
*env
, uint32_t syndrome
)
358 int debug_el
= arm_debug_target_el(env
);
359 int cur_el
= arm_current_el(env
);
361 /* FSR will only be used if the debug target EL is AArch32. */
362 env
->exception
.fsr
= arm_debug_exception_fsr(env
);
363 /* FAR is UNKNOWN: clear vaddress to avoid potentially exposing
364 * values to the guest that it shouldn't be able to see at its
365 * exception/security level.
367 env
->exception
.vaddress
= 0;
369 * Other kinds of architectural debug exception are ignored if
370 * they target an exception level below the current one (in QEMU
371 * this is checked by arm_generate_debug_exceptions()). Breakpoint
372 * instructions are special because they always generate an exception
373 * to somewhere: if they can't go to the configured debug exception
374 * level they are taken to the current exception level.
376 if (debug_el
< cur_el
) {
379 raise_exception(env
, EXCP_BKPT
, syndrome
, debug_el
);
382 uint32_t HELPER(cpsr_read
)(CPUARMState
*env
)
384 return cpsr_read(env
) & ~(CPSR_EXEC
| CPSR_RESERVED
);
387 void HELPER(cpsr_write
)(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
389 cpsr_write(env
, val
, mask
, CPSRWriteByInstr
);
392 /* Write the CPSR for a 32-bit exception return */
393 void HELPER(cpsr_write_eret
)(CPUARMState
*env
, uint32_t val
)
395 qemu_mutex_lock_iothread();
396 arm_call_pre_el_change_hook(env_archcpu(env
));
397 qemu_mutex_unlock_iothread();
399 cpsr_write(env
, val
, CPSR_ERET_MASK
, CPSRWriteExceptionReturn
);
401 /* Generated code has already stored the new PC value, but
402 * without masking out its low bits, because which bits need
403 * masking depends on whether we're returning to Thumb or ARM
404 * state. Do the masking now.
406 env
->regs
[15] &= (env
->thumb
? ~1 : ~3);
408 qemu_mutex_lock_iothread();
409 arm_call_el_change_hook(env_archcpu(env
));
410 qemu_mutex_unlock_iothread();
413 /* Access to user mode registers from privileged modes. */
414 uint32_t HELPER(get_user_reg
)(CPUARMState
*env
, uint32_t regno
)
419 val
= env
->banked_r13
[BANK_USRSYS
];
420 } else if (regno
== 14) {
421 val
= env
->banked_r14
[BANK_USRSYS
];
422 } else if (regno
>= 8
423 && (env
->uncached_cpsr
& 0x1f) == ARM_CPU_MODE_FIQ
) {
424 val
= env
->usr_regs
[regno
- 8];
426 val
= env
->regs
[regno
];
431 void HELPER(set_user_reg
)(CPUARMState
*env
, uint32_t regno
, uint32_t val
)
434 env
->banked_r13
[BANK_USRSYS
] = val
;
435 } else if (regno
== 14) {
436 env
->banked_r14
[BANK_USRSYS
] = val
;
437 } else if (regno
>= 8
438 && (env
->uncached_cpsr
& 0x1f) == ARM_CPU_MODE_FIQ
) {
439 env
->usr_regs
[regno
- 8] = val
;
441 env
->regs
[regno
] = val
;
445 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
447 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
450 env
->banked_r13
[bank_number(mode
)] = val
;
454 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
456 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_SYS
) {
457 /* SRS instruction is UNPREDICTABLE from System mode; we UNDEF.
458 * Other UNPREDICTABLE and UNDEF cases were caught at translate time.
460 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
461 exception_target_el(env
));
464 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
465 return env
->regs
[13];
467 return env
->banked_r13
[bank_number(mode
)];
471 static void msr_mrs_banked_exc_checks(CPUARMState
*env
, uint32_t tgtmode
,
474 /* Raise an exception if the requested access is one of the UNPREDICTABLE
475 * cases; otherwise return. This broadly corresponds to the pseudocode
476 * BankedRegisterAccessValid() and SPSRAccessValid(),
477 * except that we have already handled some cases at translate time.
479 int curmode
= env
->uncached_cpsr
& CPSR_M
;
482 /* ELR_Hyp: a special case because access from tgtmode is OK */
483 if (curmode
!= ARM_CPU_MODE_HYP
&& curmode
!= ARM_CPU_MODE_MON
) {
489 if (curmode
== tgtmode
) {
493 if (tgtmode
== ARM_CPU_MODE_USR
) {
496 if (curmode
!= ARM_CPU_MODE_FIQ
) {
501 if (curmode
== ARM_CPU_MODE_SYS
) {
506 if (curmode
== ARM_CPU_MODE_HYP
|| curmode
== ARM_CPU_MODE_SYS
) {
515 if (tgtmode
== ARM_CPU_MODE_HYP
) {
516 /* SPSR_Hyp, r13_hyp: accessible from Monitor mode only */
517 if (curmode
!= ARM_CPU_MODE_MON
) {
525 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
526 exception_target_el(env
));
529 void HELPER(msr_banked
)(CPUARMState
*env
, uint32_t value
, uint32_t tgtmode
,
532 msr_mrs_banked_exc_checks(env
, tgtmode
, regno
);
536 env
->banked_spsr
[bank_number(tgtmode
)] = value
;
538 case 17: /* ELR_Hyp */
539 env
->elr_el
[2] = value
;
542 env
->banked_r13
[bank_number(tgtmode
)] = value
;
545 env
->banked_r14
[r14_bank_number(tgtmode
)] = value
;
549 case ARM_CPU_MODE_USR
:
550 env
->usr_regs
[regno
- 8] = value
;
552 case ARM_CPU_MODE_FIQ
:
553 env
->fiq_regs
[regno
- 8] = value
;
556 g_assert_not_reached();
560 g_assert_not_reached();
564 uint32_t HELPER(mrs_banked
)(CPUARMState
*env
, uint32_t tgtmode
, uint32_t regno
)
566 msr_mrs_banked_exc_checks(env
, tgtmode
, regno
);
570 return env
->banked_spsr
[bank_number(tgtmode
)];
571 case 17: /* ELR_Hyp */
572 return env
->elr_el
[2];
574 return env
->banked_r13
[bank_number(tgtmode
)];
576 return env
->banked_r14
[r14_bank_number(tgtmode
)];
579 case ARM_CPU_MODE_USR
:
580 return env
->usr_regs
[regno
- 8];
581 case ARM_CPU_MODE_FIQ
:
582 return env
->fiq_regs
[regno
- 8];
584 g_assert_not_reached();
587 g_assert_not_reached();
591 void HELPER(access_check_cp_reg
)(CPUARMState
*env
, void *rip
, uint32_t syndrome
,
594 const ARMCPRegInfo
*ri
= rip
;
597 if (arm_feature(env
, ARM_FEATURE_XSCALE
) && ri
->cp
< 14
598 && extract32(env
->cp15
.c15_cpar
, ri
->cp
, 1) == 0) {
599 raise_exception(env
, EXCP_UDEF
, syndrome
, exception_target_el(env
));
606 switch (ri
->accessfn(env
, ri
, isread
)) {
610 target_el
= exception_target_el(env
);
612 case CP_ACCESS_TRAP_EL2
:
613 /* Requesting a trap to EL2 when we're in EL3 or S-EL0/1 is
614 * a bug in the access function.
616 assert(!arm_is_secure(env
) && arm_current_el(env
) != 3);
619 case CP_ACCESS_TRAP_EL3
:
622 case CP_ACCESS_TRAP_UNCATEGORIZED
:
623 target_el
= exception_target_el(env
);
624 syndrome
= syn_uncategorized();
626 case CP_ACCESS_TRAP_UNCATEGORIZED_EL2
:
628 syndrome
= syn_uncategorized();
630 case CP_ACCESS_TRAP_UNCATEGORIZED_EL3
:
632 syndrome
= syn_uncategorized();
634 case CP_ACCESS_TRAP_FP_EL2
:
636 /* Since we are an implementation that takes exceptions on a trapped
637 * conditional insn only if the insn has passed its condition code
638 * check, we take the IMPDEF choice to always report CV=1 COND=0xe
639 * (which is also the required value for AArch64 traps).
641 syndrome
= syn_fp_access_trap(1, 0xe, false);
643 case CP_ACCESS_TRAP_FP_EL3
:
645 syndrome
= syn_fp_access_trap(1, 0xe, false);
648 g_assert_not_reached();
651 raise_exception(env
, EXCP_UDEF
, syndrome
, target_el
);
654 void HELPER(set_cp_reg
)(CPUARMState
*env
, void *rip
, uint32_t value
)
656 const ARMCPRegInfo
*ri
= rip
;
658 if (ri
->type
& ARM_CP_IO
) {
659 qemu_mutex_lock_iothread();
660 ri
->writefn(env
, ri
, value
);
661 qemu_mutex_unlock_iothread();
663 ri
->writefn(env
, ri
, value
);
667 uint32_t HELPER(get_cp_reg
)(CPUARMState
*env
, void *rip
)
669 const ARMCPRegInfo
*ri
= rip
;
672 if (ri
->type
& ARM_CP_IO
) {
673 qemu_mutex_lock_iothread();
674 res
= ri
->readfn(env
, ri
);
675 qemu_mutex_unlock_iothread();
677 res
= ri
->readfn(env
, ri
);
683 void HELPER(set_cp_reg64
)(CPUARMState
*env
, void *rip
, uint64_t value
)
685 const ARMCPRegInfo
*ri
= rip
;
687 if (ri
->type
& ARM_CP_IO
) {
688 qemu_mutex_lock_iothread();
689 ri
->writefn(env
, ri
, value
);
690 qemu_mutex_unlock_iothread();
692 ri
->writefn(env
, ri
, value
);
696 uint64_t HELPER(get_cp_reg64
)(CPUARMState
*env
, void *rip
)
698 const ARMCPRegInfo
*ri
= rip
;
701 if (ri
->type
& ARM_CP_IO
) {
702 qemu_mutex_lock_iothread();
703 res
= ri
->readfn(env
, ri
);
704 qemu_mutex_unlock_iothread();
706 res
= ri
->readfn(env
, ri
);
712 void HELPER(pre_hvc
)(CPUARMState
*env
)
714 ARMCPU
*cpu
= env_archcpu(env
);
715 int cur_el
= arm_current_el(env
);
716 /* FIXME: Use actual secure state. */
720 if (arm_is_psci_call(cpu
, EXCP_HVC
)) {
721 /* If PSCI is enabled and this looks like a valid PSCI call then
722 * that overrides the architecturally mandated HVC behaviour.
727 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
728 /* If EL2 doesn't exist, HVC always UNDEFs */
730 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
731 /* EL3.HCE has priority over EL2.HCD. */
732 undef
= !(env
->cp15
.scr_el3
& SCR_HCE
);
734 undef
= env
->cp15
.hcr_el2
& HCR_HCD
;
737 /* In ARMv7 and ARMv8/AArch32, HVC is undef in secure state.
738 * For ARMv8/AArch64, HVC is allowed in EL3.
739 * Note that we've already trapped HVC from EL0 at translation
742 if (secure
&& (!is_a64(env
) || cur_el
== 1)) {
747 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
748 exception_target_el(env
));
752 void HELPER(pre_smc
)(CPUARMState
*env
, uint32_t syndrome
)
754 ARMCPU
*cpu
= env_archcpu(env
);
755 int cur_el
= arm_current_el(env
);
756 bool secure
= arm_is_secure(env
);
757 bool smd_flag
= env
->cp15
.scr_el3
& SCR_SMD
;
760 * SMC behaviour is summarized in the following table.
761 * This helper handles the "Trap to EL2" and "Undef insn" cases.
762 * The "Trap to EL3" and "PSCI call" cases are handled in the exception
765 * -> ARM_FEATURE_EL3 and !SMD
766 * HCR_TSC && NS EL1 !HCR_TSC || !NS EL1
768 * Conduit SMC, valid call Trap to EL2 PSCI Call
769 * Conduit SMC, inval call Trap to EL2 Trap to EL3
770 * Conduit not SMC Trap to EL2 Trap to EL3
773 * -> ARM_FEATURE_EL3 and SMD
774 * HCR_TSC && NS EL1 !HCR_TSC || !NS EL1
776 * Conduit SMC, valid call Trap to EL2 PSCI Call
777 * Conduit SMC, inval call Trap to EL2 Undef insn
778 * Conduit not SMC Trap to EL2 Undef insn
781 * -> !ARM_FEATURE_EL3
782 * HCR_TSC && NS EL1 !HCR_TSC || !NS EL1
784 * Conduit SMC, valid call Trap to EL2 PSCI Call
785 * Conduit SMC, inval call Trap to EL2 Undef insn
786 * Conduit not SMC Undef insn Undef insn
789 /* On ARMv8 with EL3 AArch64, SMD applies to both S and NS state.
790 * On ARMv8 with EL3 AArch32, or ARMv7 with the Virtualization
791 * extensions, SMD only applies to NS state.
792 * On ARMv7 without the Virtualization extensions, the SMD bit
793 * doesn't exist, but we forbid the guest to set it to 1 in scr_write(),
794 * so we need not special case this here.
796 bool smd
= arm_feature(env
, ARM_FEATURE_AARCH64
) ? smd_flag
797 : smd_flag
&& !secure
;
799 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
800 cpu
->psci_conduit
!= QEMU_PSCI_CONDUIT_SMC
) {
801 /* If we have no EL3 then SMC always UNDEFs and can't be
802 * trapped to EL2. PSCI-via-SMC is a sort of ersatz EL3
803 * firmware within QEMU, and we want an EL2 guest to be able
804 * to forbid its EL1 from making PSCI calls into QEMU's
805 * "firmware" via HCR.TSC, so for these purposes treat
806 * PSCI-via-SMC as implying an EL3.
807 * This handles the very last line of the previous table.
809 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
810 exception_target_el(env
));
813 if (cur_el
== 1 && (arm_hcr_el2_eff(env
) & HCR_TSC
)) {
814 /* In NS EL1, HCR controlled routing to EL2 has priority over SMD.
815 * We also want an EL2 guest to be able to forbid its EL1 from
816 * making PSCI calls into QEMU's "firmware" via HCR.TSC.
817 * This handles all the "Trap to EL2" cases of the previous table.
819 raise_exception(env
, EXCP_HYP_TRAP
, syndrome
, 2);
822 /* Catch the two remaining "Undef insn" cases of the previous table:
823 * - PSCI conduit is SMC but we don't have a valid PCSI call,
824 * - We don't have EL3 or SMD is set.
826 if (!arm_is_psci_call(cpu
, EXCP_SMC
) &&
827 (smd
|| !arm_feature(env
, ARM_FEATURE_EL3
))) {
828 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
829 exception_target_el(env
));
833 /* ??? Flag setting arithmetic is awkward because we need to do comparisons.
834 The only way to do that in TCG is a conditional branch, which clobbers
835 all our temporaries. For now implement these as helper functions. */
837 /* Similarly for variable shift instructions. */
839 uint32_t HELPER(shl_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
841 int shift
= i
& 0xff;
848 } else if (shift
!= 0) {
849 env
->CF
= (x
>> (32 - shift
)) & 1;
855 uint32_t HELPER(shr_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
857 int shift
= i
& 0xff;
860 env
->CF
= (x
>> 31) & 1;
864 } else if (shift
!= 0) {
865 env
->CF
= (x
>> (shift
- 1)) & 1;
871 uint32_t HELPER(sar_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
873 int shift
= i
& 0xff;
875 env
->CF
= (x
>> 31) & 1;
876 return (int32_t)x
>> 31;
877 } else if (shift
!= 0) {
878 env
->CF
= (x
>> (shift
- 1)) & 1;
879 return (int32_t)x
>> shift
;
884 uint32_t HELPER(ror_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
888 shift
= shift1
& 0x1f;
891 env
->CF
= (x
>> 31) & 1;
894 env
->CF
= (x
>> (shift
- 1)) & 1;
895 return ((uint32_t)x
>> shift
) | (x
<< (32 - shift
));
899 void HELPER(dc_zva
)(CPUARMState
*env
, uint64_t vaddr_in
)
902 * Implement DC ZVA, which zeroes a fixed-length block of memory.
903 * Note that we do not implement the (architecturally mandated)
904 * alignment fault for attempts to use this on Device memory
905 * (which matches the usual QEMU behaviour of not implementing either
906 * alignment faults or any memory attribute handling).
909 ARMCPU
*cpu
= env_archcpu(env
);
910 uint64_t blocklen
= 4 << cpu
->dcz_blocksize
;
911 uint64_t vaddr
= vaddr_in
& ~(blocklen
- 1);
913 #ifndef CONFIG_USER_ONLY
916 * Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
917 * the block size so we might have to do more than one TLB lookup.
918 * We know that in fact for any v8 CPU the page size is at least 4K
919 * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
920 * 1K as an artefact of legacy v5 subpage support being present in the
921 * same QEMU executable. So in practice the hostaddr[] array has
922 * two entries, given the current setting of TARGET_PAGE_BITS_MIN.
924 int maxidx
= DIV_ROUND_UP(blocklen
, TARGET_PAGE_SIZE
);
925 void *hostaddr
[DIV_ROUND_UP(2 * KiB
, 1 << TARGET_PAGE_BITS_MIN
)];
927 unsigned mmu_idx
= cpu_mmu_index(env
, false);
928 TCGMemOpIdx oi
= make_memop_idx(MO_UB
, mmu_idx
);
930 assert(maxidx
<= ARRAY_SIZE(hostaddr
));
932 for (try = 0; try < 2; try++) {
934 for (i
= 0; i
< maxidx
; i
++) {
935 hostaddr
[i
] = tlb_vaddr_to_host(env
,
936 vaddr
+ TARGET_PAGE_SIZE
* i
,
944 * If it's all in the TLB it's fair game for just writing to;
945 * we know we don't need to update dirty status, etc.
947 for (i
= 0; i
< maxidx
- 1; i
++) {
948 memset(hostaddr
[i
], 0, TARGET_PAGE_SIZE
);
950 memset(hostaddr
[i
], 0, blocklen
- (i
* TARGET_PAGE_SIZE
));
954 * OK, try a store and see if we can populate the tlb. This
955 * might cause an exception if the memory isn't writable,
956 * in which case we will longjmp out of here. We must for
957 * this purpose use the actual register value passed to us
958 * so that we get the fault address right.
960 helper_ret_stb_mmu(env
, vaddr_in
, 0, oi
, GETPC());
961 /* Now we can populate the other TLB entries, if any */
962 for (i
= 0; i
< maxidx
; i
++) {
963 uint64_t va
= vaddr
+ TARGET_PAGE_SIZE
* i
;
964 if (va
!= (vaddr_in
& TARGET_PAGE_MASK
)) {
965 helper_ret_stb_mmu(env
, va
, 0, oi
, GETPC());
971 * Slow path (probably attempt to do this to an I/O device or
972 * similar, or clearing of a block of code we have translations
973 * cached for). Just do a series of byte writes as the architecture
974 * demands. It's not worth trying to use a cpu_physical_memory_map(),
975 * memset(), unmap() sequence here because:
976 * + we'd need to account for the blocksize being larger than a page
977 * + the direct-RAM access case is almost always going to be dealt
978 * with in the fastpath code above, so there's no speed benefit
979 * + we would have to deal with the map returning NULL because the
980 * bounce buffer was in use
982 for (i
= 0; i
< blocklen
; i
++) {
983 helper_ret_stb_mmu(env
, vaddr
+ i
, 0, oi
, GETPC());
987 memset(g2h(vaddr
), 0, blocklen
);