hw/misc/mips_itu.c

   1 /*
   2  * Inter-Thread Communication Unit emulation.
   3  *
   4  * Copyright (c) 2016 Imagination Technologies
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qapi/error.h"
  22 #include "cpu.h"
  23 #include "qemu/log.h"
  24 #include "exec/exec-all.h"
  25 #include "hw/hw.h"
  26 #include "hw/sysbus.h"
  27 #include "sysemu/sysemu.h"
  28 #include "hw/misc/mips_itu.h"
  29
  30 #define ITC_TAG_ADDRSPACE_SZ (ITC_ADDRESSMAP_NUM * 8)
  31 /* Initialize as 4kB area to fit all 32 cells with default 128B grain.
  32    Storage may be resized by the software. */
  33 #define ITC_STORAGE_ADDRSPACE_SZ 0x1000
  34
  35 #define ITC_FIFO_NUM_MAX 16
  36 #define ITC_SEMAPH_NUM_MAX 16
  37 #define ITC_AM1_NUMENTRIES_OFS 20
  38
  39 #define ITC_CELL_PV_MAX_VAL 0xFFFF
  40
  41 #define ITC_CELL_TAG_FIFO_DEPTH 28
  42 #define ITC_CELL_TAG_FIFO_PTR 18
  43 #define ITC_CELL_TAG_FIFO 17
  44 #define ITC_CELL_TAG_T 16
  45 #define ITC_CELL_TAG_F 1
  46 #define ITC_CELL_TAG_E 0
  47
  48 #define ITC_AM0_BASE_ADDRESS_MASK 0xFFFFFC00ULL
  49 #define ITC_AM0_EN_MASK 0x1
  50
  51 #define ITC_AM1_ADDR_MASK_MASK 0x1FC00
  52 #define ITC_AM1_ENTRY_GRAIN_MASK 0x7
  53
  54 typedef enum ITCView {
  55     ITCVIEW_BYPASS  = 0,
  56     ITCVIEW_CONTROL = 1,
  57     ITCVIEW_EF_SYNC = 2,
  58     ITCVIEW_EF_TRY  = 3,
  59     ITCVIEW_PV_SYNC = 4,
  60     ITCVIEW_PV_TRY  = 5
  61 } ITCView;
  62
  63 MemoryRegion *mips_itu_get_tag_region(MIPSITUState *itu)
  64 {
  65     return &itu->tag_io;
  66 }
  67
  68 static uint64_t itc_tag_read(void *opaque, hwaddr addr, unsigned size)
  69 {
  70     MIPSITUState *tag = (MIPSITUState *)opaque;
  71     uint64_t index = addr >> 3;
  72
  73     if (index >= ITC_ADDRESSMAP_NUM) {
  74         qemu_log_mask(LOG_GUEST_ERROR, "Read 0x%" PRIx64 "\n", addr);
  75         return 0;
  76     }
  77
  78     return tag->ITCAddressMap[index];
  79 }
  80
  81 static void itc_reconfigure(MIPSITUState *tag)
  82 {
  83     uint64_t *am = &tag->ITCAddressMap[0];
  84     MemoryRegion *mr = &tag->storage_io;
  85     hwaddr address = am[0] & ITC_AM0_BASE_ADDRESS_MASK;
  86     uint64_t size = (1 << 10) + (am[1] & ITC_AM1_ADDR_MASK_MASK);
  87     bool is_enabled = (am[0] & ITC_AM0_EN_MASK) != 0;
  88
  89     memory_region_transaction_begin();
  90     if (!(size & (size - 1))) {
  91         memory_region_set_size(mr, size);
  92     }
  93     memory_region_set_address(mr, address);
  94     memory_region_set_enabled(mr, is_enabled);
  95     memory_region_transaction_commit();
  96 }
  97
  98 static void itc_tag_write(void *opaque, hwaddr addr,
  99                           uint64_t data, unsigned size)
 100 {
 101     MIPSITUState *tag = (MIPSITUState *)opaque;
 102     uint64_t *am = &tag->ITCAddressMap[0];
 103     uint64_t am_old, mask;
 104     uint64_t index = addr >> 3;
 105
 106     switch (index) {
 107     case 0:
 108         mask = ITC_AM0_BASE_ADDRESS_MASK | ITC_AM0_EN_MASK;
 109         break;
 110     case 1:
 111         mask = ITC_AM1_ADDR_MASK_MASK | ITC_AM1_ENTRY_GRAIN_MASK;
 112         break;
 113     default:
 114         qemu_log_mask(LOG_GUEST_ERROR, "Bad write 0x%" PRIx64 "\n", addr);
 115         return;
 116     }
 117
 118     am_old = am[index];
 119     am[index] = (data & mask) | (am_old & ~mask);
 120     if (am_old != am[index]) {
 121         itc_reconfigure(tag);
 122     }
 123 }
 124
 125 static const MemoryRegionOps itc_tag_ops = {
 126     .read = itc_tag_read,
 127     .write = itc_tag_write,
 128     .impl = {
 129         .max_access_size = 8,
 130     },
 131     .endianness = DEVICE_NATIVE_ENDIAN,
 132 };
 133
 134 static inline uint32_t get_num_cells(MIPSITUState *s)
 135 {
 136     return s->num_fifo + s->num_semaphores;
 137 }
 138
 139 static inline ITCView get_itc_view(hwaddr addr)
 140 {
 141     return (addr >> 3) & 0xf;
 142 }
 143
 144 static inline int get_cell_stride_shift(const MIPSITUState *s)
 145 {
 146     /* Minimum interval (for EntryGain = 0) is 128 B */
 147     return 7 + (s->ITCAddressMap[1] & ITC_AM1_ENTRY_GRAIN_MASK);
 148 }
 149
 150 static inline ITCStorageCell *get_cell(MIPSITUState *s,
 151                                        hwaddr addr)
 152 {
 153     uint32_t cell_idx = addr >> get_cell_stride_shift(s);
 154     uint32_t num_cells = get_num_cells(s);
 155
 156     if (cell_idx >= num_cells) {
 157         cell_idx = num_cells - 1;
 158     }
 159
 160     return &s->cell[cell_idx];
 161 }
 162
 163 static void wake_blocked_threads(ITCStorageCell *c)
 164 {
 165     CPUState *cs;
 166     CPU_FOREACH(cs) {
 167         if (cs->halted && (c->blocked_threads & (1ULL << cs->cpu_index))) {
 168             cpu_interrupt(cs, CPU_INTERRUPT_WAKE);
 169         }
 170     }
 171     c->blocked_threads = 0;
 172 }
 173
 174 static void QEMU_NORETURN block_thread_and_exit(ITCStorageCell *c)
 175 {
 176     c->blocked_threads |= 1ULL << current_cpu->cpu_index;
 177     current_cpu->halted = 1;
 178     current_cpu->exception_index = EXCP_HLT;
 179     cpu_loop_exit_restore(current_cpu, current_cpu->mem_io_pc);
 180 }
 181
 182 /* ITC Bypass View */
 183
 184 static inline uint64_t view_bypass_read(ITCStorageCell *c)
 185 {
 186     if (c->tag.FIFO) {
 187         return c->data[c->fifo_out];
 188     } else {
 189         return c->data[0];
 190     }
 191 }
 192
 193 static inline void view_bypass_write(ITCStorageCell *c, uint64_t val)
 194 {
 195     if (c->tag.FIFO && (c->tag.FIFOPtr > 0)) {
 196         int idx = (c->fifo_out + c->tag.FIFOPtr - 1) % ITC_CELL_DEPTH;
 197         c->data[idx] = val;
 198     }
 199
 200     /* ignore a write to the semaphore cell */
 201 }
 202
 203 /* ITC Control View */
 204
 205 static inline uint64_t view_control_read(ITCStorageCell *c)
 206 {
 207     return ((uint64_t)c->tag.FIFODepth << ITC_CELL_TAG_FIFO_DEPTH) |
 208            (c->tag.FIFOPtr << ITC_CELL_TAG_FIFO_PTR) |
 209            (c->tag.FIFO << ITC_CELL_TAG_FIFO) |
 210            (c->tag.T << ITC_CELL_TAG_T) |
 211            (c->tag.E << ITC_CELL_TAG_E) |
 212            (c->tag.F << ITC_CELL_TAG_F);
 213 }
 214
 215 static inline void view_control_write(ITCStorageCell *c, uint64_t val)
 216 {
 217     c->tag.T = (val >> ITC_CELL_TAG_T) & 1;
 218     c->tag.E = (val >> ITC_CELL_TAG_E) & 1;
 219     c->tag.F = (val >> ITC_CELL_TAG_F) & 1;
 220
 221     if (c->tag.E) {
 222         c->tag.FIFOPtr = 0;
 223     }
 224 }
 225
 226 /* ITC Empty/Full View */
 227
 228 static uint64_t view_ef_common_read(ITCStorageCell *c, bool blocking)
 229 {
 230     uint64_t ret = 0;
 231
 232     if (!c->tag.FIFO) {
 233         return 0;
 234     }
 235
 236     c->tag.F = 0;
 237
 238     if (blocking && c->tag.E) {
 239         block_thread_and_exit(c);
 240     }
 241
 242     if (c->blocked_threads) {
 243         wake_blocked_threads(c);
 244     }
 245
 246     if (c->tag.FIFOPtr > 0) {
 247         ret = c->data[c->fifo_out];
 248         c->fifo_out = (c->fifo_out + 1) % ITC_CELL_DEPTH;
 249         c->tag.FIFOPtr--;
 250     }
 251
 252     if (c->tag.FIFOPtr == 0) {
 253         c->tag.E = 1;
 254     }
 255
 256     return ret;
 257 }
 258
 259 static uint64_t view_ef_sync_read(ITCStorageCell *c)
 260 {
 261     return view_ef_common_read(c, true);
 262 }
 263
 264 static uint64_t view_ef_try_read(ITCStorageCell *c)
 265 {
 266     return view_ef_common_read(c, false);
 267 }
 268
 269 static inline void view_ef_common_write(ITCStorageCell *c, uint64_t val,
 270                                         bool blocking)
 271 {
 272     if (!c->tag.FIFO) {
 273         return;
 274     }
 275
 276     c->tag.E = 0;
 277
 278     if (blocking && c->tag.F) {
 279         block_thread_and_exit(c);
 280     }
 281
 282     if (c->blocked_threads) {
 283         wake_blocked_threads(c);
 284     }
 285
 286     if (c->tag.FIFOPtr < ITC_CELL_DEPTH) {
 287         int idx = (c->fifo_out + c->tag.FIFOPtr) % ITC_CELL_DEPTH;
 288         c->data[idx] = val;
 289         c->tag.FIFOPtr++;
 290     }
 291
 292     if (c->tag.FIFOPtr == ITC_CELL_DEPTH) {
 293         c->tag.F = 1;
 294     }
 295 }
 296
 297 static void view_ef_sync_write(ITCStorageCell *c, uint64_t val)
 298 {
 299     view_ef_common_write(c, val, true);
 300 }
 301
 302 static void view_ef_try_write(ITCStorageCell *c, uint64_t val)
 303 {
 304     view_ef_common_write(c, val, false);
 305 }
 306
 307 /* ITC P/V View */
 308
 309 static uint64_t view_pv_common_read(ITCStorageCell *c, bool blocking)
 310 {
 311     uint64_t ret = c->data[0];
 312
 313     if (c->tag.FIFO) {
 314         return 0;
 315     }
 316
 317     if (c->data[0] > 0) {
 318         c->data[0]--;
 319     } else if (blocking) {
 320         block_thread_and_exit(c);
 321     }
 322
 323     return ret;
 324 }
 325
 326 static uint64_t view_pv_sync_read(ITCStorageCell *c)
 327 {
 328     return view_pv_common_read(c, true);
 329 }
 330
 331 static uint64_t view_pv_try_read(ITCStorageCell *c)
 332 {
 333     return view_pv_common_read(c, false);
 334 }
 335
 336 static inline void view_pv_common_write(ITCStorageCell *c)
 337 {
 338     if (c->tag.FIFO) {
 339         return;
 340     }
 341
 342     if (c->data[0] < ITC_CELL_PV_MAX_VAL) {
 343         c->data[0]++;
 344     }
 345
 346     if (c->blocked_threads) {
 347         wake_blocked_threads(c);
 348     }
 349 }
 350
 351 static void view_pv_sync_write(ITCStorageCell *c)
 352 {
 353     view_pv_common_write(c);
 354 }
 355
 356 static void view_pv_try_write(ITCStorageCell *c)
 357 {
 358     view_pv_common_write(c);
 359 }
 360
 361 static uint64_t itc_storage_read(void *opaque, hwaddr addr, unsigned size)
 362 {
 363     MIPSITUState *s = (MIPSITUState *)opaque;
 364     ITCStorageCell *cell = get_cell(s, addr);
 365     ITCView view = get_itc_view(addr);
 366     uint64_t ret = -1;
 367
 368     switch (view) {
 369     case ITCVIEW_BYPASS:
 370         ret = view_bypass_read(cell);
 371         break;
 372     case ITCVIEW_CONTROL:
 373         ret = view_control_read(cell);
 374         break;
 375     case ITCVIEW_EF_SYNC:
 376         ret = view_ef_sync_read(cell);
 377         break;
 378     case ITCVIEW_EF_TRY:
 379         ret = view_ef_try_read(cell);
 380         break;
 381     case ITCVIEW_PV_SYNC:
 382         ret = view_pv_sync_read(cell);
 383         break;
 384     case ITCVIEW_PV_TRY:
 385         ret = view_pv_try_read(cell);
 386         break;
 387     default:
 388         qemu_log_mask(LOG_GUEST_ERROR,
 389                       "itc_storage_read: Bad ITC View %d\n", (int)view);
 390         break;
 391     }
 392
 393     return ret;
 394 }
 395
 396 static void itc_storage_write(void *opaque, hwaddr addr, uint64_t data,
 397                               unsigned size)
 398 {
 399     MIPSITUState *s = (MIPSITUState *)opaque;
 400     ITCStorageCell *cell = get_cell(s, addr);
 401     ITCView view = get_itc_view(addr);
 402
 403     switch (view) {
 404     case ITCVIEW_BYPASS:
 405         view_bypass_write(cell, data);
 406         break;
 407     case ITCVIEW_CONTROL:
 408         view_control_write(cell, data);
 409         break;
 410     case ITCVIEW_EF_SYNC:
 411         view_ef_sync_write(cell, data);
 412         break;
 413     case ITCVIEW_EF_TRY:
 414         view_ef_try_write(cell, data);
 415         break;
 416     case ITCVIEW_PV_SYNC:
 417         view_pv_sync_write(cell);
 418         break;
 419     case ITCVIEW_PV_TRY:
 420         view_pv_try_write(cell);
 421         break;
 422     default:
 423         qemu_log_mask(LOG_GUEST_ERROR,
 424                       "itc_storage_write: Bad ITC View %d\n", (int)view);
 425         break;
 426     }
 427
 428 }
 429
 430 static const MemoryRegionOps itc_storage_ops = {
 431     .read = itc_storage_read,
 432     .write = itc_storage_write,
 433     .endianness = DEVICE_NATIVE_ENDIAN,
 434 };
 435
 436 static void itc_reset_cells(MIPSITUState *s)
 437 {
 438     int i;
 439
 440     memset(s->cell, 0, get_num_cells(s) * sizeof(s->cell[0]));
 441
 442     for (i = 0; i < s->num_fifo; i++) {
 443         s->cell[i].tag.E = 1;
 444         s->cell[i].tag.FIFO = 1;
 445         s->cell[i].tag.FIFODepth = ITC_CELL_DEPTH_SHIFT;
 446     }
 447 }
 448
 449 static void mips_itu_init(Object *obj)
 450 {
 451     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 452     MIPSITUState *s = MIPS_ITU(obj);
 453
 454     memory_region_init_io(&s->storage_io, OBJECT(s), &itc_storage_ops, s,
 455                           "mips-itc-storage", ITC_STORAGE_ADDRSPACE_SZ);
 456     sysbus_init_mmio(sbd, &s->storage_io);
 457
 458     memory_region_init_io(&s->tag_io, OBJECT(s), &itc_tag_ops, s,
 459                           "mips-itc-tag", ITC_TAG_ADDRSPACE_SZ);
 460 }
 461
 462 static void mips_itu_realize(DeviceState *dev, Error **errp)
 463 {
 464     MIPSITUState *s = MIPS_ITU(dev);
 465
 466     if (s->num_fifo > ITC_FIFO_NUM_MAX) {
 467         error_setg(errp, "Exceed maximum number of FIFO cells: %d",
 468                    s->num_fifo);
 469         return;
 470     }
 471     if (s->num_semaphores > ITC_SEMAPH_NUM_MAX) {
 472         error_setg(errp, "Exceed maximum number of Semaphore cells: %d",
 473                    s->num_semaphores);
 474         return;
 475     }
 476
 477     s->cell = g_new(ITCStorageCell, get_num_cells(s));
 478 }
 479
 480 static void mips_itu_reset(DeviceState *dev)
 481 {
 482     MIPSITUState *s = MIPS_ITU(dev);
 483
 484     s->ITCAddressMap[0] = 0;
 485     s->ITCAddressMap[1] =
 486         ((ITC_STORAGE_ADDRSPACE_SZ - 1) & ITC_AM1_ADDR_MASK_MASK) |
 487         (get_num_cells(s) << ITC_AM1_NUMENTRIES_OFS);
 488     itc_reconfigure(s);
 489
 490     itc_reset_cells(s);
 491 }
 492
 493 static Property mips_itu_properties[] = {
 494     DEFINE_PROP_INT32("num-fifo", MIPSITUState, num_fifo,
 495                       ITC_FIFO_NUM_MAX),
 496     DEFINE_PROP_INT32("num-semaphores", MIPSITUState, num_semaphores,
 497                       ITC_SEMAPH_NUM_MAX),
 498     DEFINE_PROP_END_OF_LIST(),
 499 };
 500
 501 static void mips_itu_class_init(ObjectClass *klass, void *data)
 502 {
 503     DeviceClass *dc = DEVICE_CLASS(klass);
 504
 505     dc->props = mips_itu_properties;
 506     dc->realize = mips_itu_realize;
 507     dc->reset = mips_itu_reset;
 508 }
 509
 510 static const TypeInfo mips_itu_info = {
 511     .name          = TYPE_MIPS_ITU,
 512     .parent        = TYPE_SYS_BUS_DEVICE,
 513     .instance_size = sizeof(MIPSITUState),
 514     .instance_init = mips_itu_init,
 515     .class_init    = mips_itu_class_init,
 516 };
 517
 518 static void mips_itu_register_types(void)
 519 {
 520     type_register_static(&mips_itu_info);
 521 }
 522
 523 type_init(mips_itu_register_types)