2 * VT82C686B south bridge support
4 * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
5 * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn)
6 * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
7 * This code is licensed under the GNU GPL v2.
9 * Contributions after 2012-01-13 are licensed under the terms of the
10 * GNU GPL, version 2 or (at your option) any later version.
26 #include "qemu-timer.h"
27 #include "exec-memory.h"
29 typedef uint32_t pci_addr_t
;
31 //#define DEBUG_VT82C686B
33 #ifdef DEBUG_VT82C686B
34 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
36 #define DPRINTF(fmt, ...)
39 typedef struct SuperIOConfig
46 typedef struct VT82C686BState
{
48 SuperIOConfig superio_conf
;
51 static void superio_ioport_writeb(void *opaque
, uint32_t addr
, uint32_t data
)
54 SuperIOConfig
*superio_conf
= opaque
;
56 DPRINTF("superio_ioport_writeb address 0x%x val 0x%x\n", addr
, data
);
58 superio_conf
->index
= data
& 0xff;
61 switch (superio_conf
->index
) {
77 switch (superio_conf
->index
) {
79 if ((data
& 0xff) != 0xfe) {
80 DPRINTF("chage uart 1 base. unsupported yet\n");
84 if ((data
& 0xff) != 0xbe) {
85 DPRINTF("chage uart 2 base. unsupported yet\n");
90 superio_conf
->config
[superio_conf
->index
] = data
& 0xff;
94 superio_conf
->config
[superio_conf
->index
] = data
& 0xff;
98 static uint32_t superio_ioport_readb(void *opaque
, uint32_t addr
)
100 SuperIOConfig
*superio_conf
= opaque
;
102 DPRINTF("superio_ioport_readb address 0x%x\n", addr
);
103 return (superio_conf
->config
[superio_conf
->index
]);
106 static void vt82c686b_reset(void * opaque
)
108 PCIDevice
*d
= opaque
;
109 uint8_t *pci_conf
= d
->config
;
110 VT82C686BState
*vt82c
= DO_UPCAST(VT82C686BState
, dev
, d
);
112 pci_set_long(pci_conf
+ PCI_CAPABILITY_LIST
, 0x000000c0);
113 pci_set_word(pci_conf
+ PCI_COMMAND
, PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
|
114 PCI_COMMAND_MASTER
| PCI_COMMAND_SPECIAL
);
115 pci_set_word(pci_conf
+ PCI_STATUS
, PCI_STATUS_DEVSEL_MEDIUM
);
117 pci_conf
[0x48] = 0x01; /* Miscellaneous Control 3 */
118 pci_conf
[0x4a] = 0x04; /* IDE interrupt Routing */
119 pci_conf
[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */
120 pci_conf
[0x50] = 0x2d; /* PnP DMA Request Control */
121 pci_conf
[0x59] = 0x04;
122 pci_conf
[0x5a] = 0x04; /* KBC/RTC Control*/
123 pci_conf
[0x5f] = 0x04;
124 pci_conf
[0x77] = 0x10; /* GPIO Control 1/2/3/4 */
126 vt82c
->superio_conf
.config
[0xe0] = 0x3c;
127 vt82c
->superio_conf
.config
[0xe2] = 0x03;
128 vt82c
->superio_conf
.config
[0xe3] = 0xfc;
129 vt82c
->superio_conf
.config
[0xe6] = 0xde;
130 vt82c
->superio_conf
.config
[0xe7] = 0xfe;
131 vt82c
->superio_conf
.config
[0xe8] = 0xbe;
134 /* write config pci function0 registers. PCI-ISA bridge */
135 static void vt82c686b_write_config(PCIDevice
* d
, uint32_t address
,
136 uint32_t val
, int len
)
138 VT82C686BState
*vt686
= DO_UPCAST(VT82C686BState
, dev
, d
);
140 DPRINTF("vt82c686b_write_config address 0x%x val 0x%x len 0x%x\n",
143 pci_default_write_config(d
, address
, val
, len
);
144 if (address
== 0x85) { /* enable or disable super IO configure */
146 /* floppy also uses 0x3f0 and 0x3f1.
147 * But we do not emulate flopy,so just set it here. */
148 isa_unassign_ioport(0x3f0, 2);
149 register_ioport_read(0x3f0, 2, 1, superio_ioport_readb
,
150 &vt686
->superio_conf
);
151 register_ioport_write(0x3f0, 2, 1, superio_ioport_writeb
,
152 &vt686
->superio_conf
);
154 isa_unassign_ioport(0x3f0, 2);
159 #define ACPI_DBG_IO_ADDR 0xb044
161 typedef struct VT686PMState
{
167 uint32_t smb_io_base
;
170 typedef struct VT686AC97State
{
174 typedef struct VT686MC97State
{
178 static void pm_update_sci(VT686PMState
*s
)
180 int sci_level
, pmsts
;
182 pmsts
= acpi_pm1_evt_get_sts(&s
->ar
);
183 sci_level
= (((pmsts
& s
->ar
.pm1
.evt
.en
) &
184 (ACPI_BITMASK_RT_CLOCK_ENABLE
|
185 ACPI_BITMASK_POWER_BUTTON_ENABLE
|
186 ACPI_BITMASK_GLOBAL_LOCK_ENABLE
|
187 ACPI_BITMASK_TIMER_ENABLE
)) != 0);
188 qemu_set_irq(s
->dev
.irq
[0], sci_level
);
189 /* schedule a timer interruption if needed */
190 acpi_pm_tmr_update(&s
->ar
, (s
->ar
.pm1
.evt
.en
& ACPI_BITMASK_TIMER_ENABLE
) &&
191 !(pmsts
& ACPI_BITMASK_TIMER_STATUS
));
194 static void pm_tmr_timer(ACPIREGS
*ar
)
196 VT686PMState
*s
= container_of(ar
, VT686PMState
, ar
);
200 static void pm_ioport_writew(void *opaque
, uint32_t addr
, uint32_t val
)
202 VT686PMState
*s
= opaque
;
207 acpi_pm1_evt_write_sts(&s
->ar
, val
);
211 acpi_pm1_evt_write_en(&s
->ar
, val
);
217 DPRINTF("PM writew port=0x%04x val=0x%02x\n", addr
, val
);
220 static uint32_t pm_ioport_readw(void *opaque
, uint32_t addr
)
222 VT686PMState
*s
= opaque
;
228 val
= acpi_pm1_evt_get_sts(&s
->ar
);
231 val
= s
->ar
.pm1
.evt
.en
;
237 DPRINTF("PM readw port=0x%04x val=0x%02x\n", addr
, val
);
241 static void pm_ioport_writel(void *opaque
, uint32_t addr
, uint32_t val
)
244 DPRINTF("PM writel port=0x%04x val=0x%08x\n", addr
, val
);
247 static uint32_t pm_ioport_readl(void *opaque
, uint32_t addr
)
257 DPRINTF("PM readl port=0x%04x val=0x%08x\n", addr
, val
);
261 static const MemoryRegionOps pm_io_ops
= {
262 .old_portio
= (MemoryRegionPortio
[]) {
263 { .offset
= 0, .len
= 64, .size
= 2,
264 .read
= pm_ioport_readw
, .write
= pm_ioport_writew
},
265 { .offset
= 0, .len
= 64, .size
= 4,
266 .read
= pm_ioport_readl
, .write
= pm_ioport_writel
},
267 PORTIO_END_OF_LIST(),
269 .valid
.min_access_size
= 1,
270 .valid
.max_access_size
= 4,
271 .impl
.min_access_size
= 1,
272 .impl
.max_access_size
= 4,
273 .endianness
= DEVICE_LITTLE_ENDIAN
,
276 static void pm_io_space_update(VT686PMState
*s
)
280 pm_io_base
= pci_get_long(s
->dev
.config
+ 0x40);
281 pm_io_base
&= 0xffc0;
283 memory_region_transaction_begin();
284 memory_region_set_enabled(&s
->io
, s
->dev
.config
[0x80] & 1);
285 memory_region_set_address(&s
->io
, pm_io_base
);
286 memory_region_transaction_commit();
289 static void pm_write_config(PCIDevice
*d
,
290 uint32_t address
, uint32_t val
, int len
)
292 DPRINTF("pm_write_config address 0x%x val 0x%x len 0x%x\n",
294 pci_default_write_config(d
, address
, val
, len
);
297 static int vmstate_acpi_post_load(void *opaque
, int version_id
)
299 VT686PMState
*s
= opaque
;
301 pm_io_space_update(s
);
305 static const VMStateDescription vmstate_acpi
= {
306 .name
= "vt82c686b_pm",
308 .minimum_version_id
= 1,
309 .minimum_version_id_old
= 1,
310 .post_load
= vmstate_acpi_post_load
,
311 .fields
= (VMStateField
[]) {
312 VMSTATE_PCI_DEVICE(dev
, VT686PMState
),
313 VMSTATE_UINT16(ar
.pm1
.evt
.sts
, VT686PMState
),
314 VMSTATE_UINT16(ar
.pm1
.evt
.en
, VT686PMState
),
315 VMSTATE_UINT16(ar
.pm1
.cnt
.cnt
, VT686PMState
),
316 VMSTATE_STRUCT(apm
, VT686PMState
, 0, vmstate_apm
, APMState
),
317 VMSTATE_TIMER(ar
.tmr
.timer
, VT686PMState
),
318 VMSTATE_INT64(ar
.tmr
.overflow_time
, VT686PMState
),
319 VMSTATE_END_OF_LIST()
324 * TODO: vt82c686b_ac97_init() and vt82c686b_mc97_init()
325 * just register a PCI device now, functionalities will be implemented later.
328 static int vt82c686b_ac97_initfn(PCIDevice
*dev
)
330 VT686AC97State
*s
= DO_UPCAST(VT686AC97State
, dev
, dev
);
331 uint8_t *pci_conf
= s
->dev
.config
;
333 pci_set_word(pci_conf
+ PCI_COMMAND
, PCI_COMMAND_INVALIDATE
|
335 pci_set_word(pci_conf
+ PCI_STATUS
, PCI_STATUS_CAP_LIST
|
336 PCI_STATUS_DEVSEL_MEDIUM
);
337 pci_set_long(pci_conf
+ PCI_INTERRUPT_PIN
, 0x03);
342 void vt82c686b_ac97_init(PCIBus
*bus
, int devfn
)
346 dev
= pci_create(bus
, devfn
, "VT82C686B_AC97");
347 qdev_init_nofail(&dev
->qdev
);
350 static void via_ac97_class_init(ObjectClass
*klass
, void *data
)
352 DeviceClass
*dc
= DEVICE_CLASS(klass
);
353 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
355 k
->init
= vt82c686b_ac97_initfn
;
356 k
->vendor_id
= PCI_VENDOR_ID_VIA
;
357 k
->device_id
= PCI_DEVICE_ID_VIA_AC97
;
359 k
->class_id
= PCI_CLASS_MULTIMEDIA_AUDIO
;
363 static TypeInfo via_ac97_info
= {
364 .name
= "VT82C686B_AC97",
365 .parent
= TYPE_PCI_DEVICE
,
366 .instance_size
= sizeof(VT686AC97State
),
367 .class_init
= via_ac97_class_init
,
370 static int vt82c686b_mc97_initfn(PCIDevice
*dev
)
372 VT686MC97State
*s
= DO_UPCAST(VT686MC97State
, dev
, dev
);
373 uint8_t *pci_conf
= s
->dev
.config
;
375 pci_set_word(pci_conf
+ PCI_COMMAND
, PCI_COMMAND_INVALIDATE
|
376 PCI_COMMAND_VGA_PALETTE
);
377 pci_set_word(pci_conf
+ PCI_STATUS
, PCI_STATUS_DEVSEL_MEDIUM
);
378 pci_set_long(pci_conf
+ PCI_INTERRUPT_PIN
, 0x03);
383 void vt82c686b_mc97_init(PCIBus
*bus
, int devfn
)
387 dev
= pci_create(bus
, devfn
, "VT82C686B_MC97");
388 qdev_init_nofail(&dev
->qdev
);
391 static void via_mc97_class_init(ObjectClass
*klass
, void *data
)
393 DeviceClass
*dc
= DEVICE_CLASS(klass
);
394 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
396 k
->init
= vt82c686b_mc97_initfn
;
397 k
->vendor_id
= PCI_VENDOR_ID_VIA
;
398 k
->device_id
= PCI_DEVICE_ID_VIA_MC97
;
399 k
->class_id
= PCI_CLASS_COMMUNICATION_OTHER
;
404 static TypeInfo via_mc97_info
= {
405 .name
= "VT82C686B_MC97",
406 .parent
= TYPE_PCI_DEVICE
,
407 .instance_size
= sizeof(VT686MC97State
),
408 .class_init
= via_mc97_class_init
,
411 /* vt82c686 pm init */
412 static int vt82c686b_pm_initfn(PCIDevice
*dev
)
414 VT686PMState
*s
= DO_UPCAST(VT686PMState
, dev
, dev
);
417 pci_conf
= s
->dev
.config
;
418 pci_set_word(pci_conf
+ PCI_COMMAND
, 0);
419 pci_set_word(pci_conf
+ PCI_STATUS
, PCI_STATUS_FAST_BACK
|
420 PCI_STATUS_DEVSEL_MEDIUM
);
422 /* 0x48-0x4B is Power Management I/O Base */
423 pci_set_long(pci_conf
+ 0x48, 0x00000001);
425 /* SMB ports:0xeee0~0xeeef */
426 s
->smb_io_base
=((s
->smb_io_base
& 0xfff0) + 0x0);
427 pci_conf
[0x90] = s
->smb_io_base
| 1;
428 pci_conf
[0x91] = s
->smb_io_base
>> 8;
429 pci_conf
[0xd2] = 0x90;
430 register_ioport_write(s
->smb_io_base
, 0xf, 1, smb_ioport_writeb
, &s
->smb
);
431 register_ioport_read(s
->smb_io_base
, 0xf, 1, smb_ioport_readb
, &s
->smb
);
433 apm_init(&s
->apm
, NULL
, s
);
435 memory_region_init_io(&s
->io
, &pm_io_ops
, s
, "vt82c686-pm", 64);
436 memory_region_set_enabled(&s
->io
, false);
437 memory_region_add_subregion(get_system_io(), 0, &s
->io
);
439 acpi_pm_tmr_init(&s
->ar
, pm_tmr_timer
, &s
->io
);
440 acpi_pm1_cnt_init(&s
->ar
, &s
->io
);
442 pm_smbus_init(&s
->dev
.qdev
, &s
->smb
);
447 i2c_bus
*vt82c686b_pm_init(PCIBus
*bus
, int devfn
, uint32_t smb_io_base
,
453 dev
= pci_create(bus
, devfn
, "VT82C686B_PM");
454 qdev_prop_set_uint32(&dev
->qdev
, "smb_io_base", smb_io_base
);
456 s
= DO_UPCAST(VT686PMState
, dev
, dev
);
458 qdev_init_nofail(&dev
->qdev
);
463 static Property via_pm_properties
[] = {
464 DEFINE_PROP_UINT32("smb_io_base", VT686PMState
, smb_io_base
, 0),
465 DEFINE_PROP_END_OF_LIST(),
468 static void via_pm_class_init(ObjectClass
*klass
, void *data
)
470 DeviceClass
*dc
= DEVICE_CLASS(klass
);
471 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
473 k
->init
= vt82c686b_pm_initfn
;
474 k
->config_write
= pm_write_config
;
475 k
->vendor_id
= PCI_VENDOR_ID_VIA
;
476 k
->device_id
= PCI_DEVICE_ID_VIA_ACPI
;
477 k
->class_id
= PCI_CLASS_BRIDGE_OTHER
;
480 dc
->vmsd
= &vmstate_acpi
;
481 dc
->props
= via_pm_properties
;
484 static TypeInfo via_pm_info
= {
485 .name
= "VT82C686B_PM",
486 .parent
= TYPE_PCI_DEVICE
,
487 .instance_size
= sizeof(VT686PMState
),
488 .class_init
= via_pm_class_init
,
491 static const VMStateDescription vmstate_via
= {
494 .minimum_version_id
= 1,
495 .minimum_version_id_old
= 1,
496 .fields
= (VMStateField
[]) {
497 VMSTATE_PCI_DEVICE(dev
, VT82C686BState
),
498 VMSTATE_END_OF_LIST()
502 /* init the PCI-to-ISA bridge */
503 static int vt82c686b_initfn(PCIDevice
*d
)
509 isa_bus_new(&d
->qdev
, pci_address_space_io(d
));
511 pci_conf
= d
->config
;
512 pci_config_set_prog_interface(pci_conf
, 0x0);
515 for (i
= 0x00; i
< 0xff; i
++) {
516 if (i
<=0x03 || (i
>=0x08 && i
<=0x3f)) {
521 qemu_register_reset(vt82c686b_reset
, d
);
526 ISABus
*vt82c686b_init(PCIBus
*bus
, int devfn
)
530 d
= pci_create_simple_multifunction(bus
, devfn
, true, "VT82C686B");
532 return DO_UPCAST(ISABus
, qbus
, qdev_get_child_bus(&d
->qdev
, "isa.0"));
535 static void via_class_init(ObjectClass
*klass
, void *data
)
537 DeviceClass
*dc
= DEVICE_CLASS(klass
);
538 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
540 k
->init
= vt82c686b_initfn
;
541 k
->config_write
= vt82c686b_write_config
;
542 k
->vendor_id
= PCI_VENDOR_ID_VIA
;
543 k
->device_id
= PCI_DEVICE_ID_VIA_ISA_BRIDGE
;
544 k
->class_id
= PCI_CLASS_BRIDGE_ISA
;
546 dc
->desc
= "ISA bridge";
548 dc
->vmsd
= &vmstate_via
;
551 static TypeInfo via_info
= {
553 .parent
= TYPE_PCI_DEVICE
,
554 .instance_size
= sizeof(VT82C686BState
),
555 .class_init
= via_class_init
,
558 static void vt82c686b_register_types(void)
560 type_register_static(&via_ac97_info
);
561 type_register_static(&via_mc97_info
);
562 type_register_static(&via_pm_info
);
563 type_register_static(&via_info
);
566 type_init(vt82c686b_register_types
)