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fsdev: Error out when unsupported option is passed
[qemu/ar7.git] / target / ppc / translate_init.inc.c
blobad5e14b16f6956d86f0b1dac4be27ee9631dc4f6
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "disas/dis-asm.h"
22 #include "exec/gdbstub.h"
23 #include "kvm_ppc.h"
24 #include "sysemu/arch_init.h"
25 #include "sysemu/cpus.h"
26 #include "sysemu/hw_accel.h"
27 #include "cpu-models.h"
28 #include "mmu-hash32.h"
29 #include "mmu-hash64.h"
30 #include "qemu/error-report.h"
31 #include "qemu/qemu-print.h"
32 #include "qapi/error.h"
33 #include "qapi/qmp/qnull.h"
34 #include "qapi/visitor.h"
35 #include "hw/qdev-properties.h"
36 #include "hw/ppc/ppc.h"
37 #include "mmu-book3s-v3.h"
38 #include "sysemu/qtest.h"
39 #include "qemu/cutils.h"
40 #include "disas/capstone.h"
41 #include "fpu/softfloat.h"
42 #include "qapi/qapi-commands-target.h"
43
44 /* #define PPC_DUMP_CPU */
45 /* #define PPC_DEBUG_SPR */
46 /* #define PPC_DUMP_SPR_ACCESSES */
47 /* #define USE_APPLE_GDB */
48
49 /*
50 * Generic callbacks:
51 * do nothing but store/retrieve spr value
52 */
53 static void spr_load_dump_spr(int sprn)
54 {
55 #ifdef PPC_DUMP_SPR_ACCESSES
56 TCGv_i32 t0 = tcg_const_i32(sprn);
57 gen_helper_load_dump_spr(cpu_env, t0);
58 tcg_temp_free_i32(t0);
59 #endif
60 }
61
62 static void spr_read_generic(DisasContext *ctx, int gprn, int sprn)
63 {
64 gen_load_spr(cpu_gpr[gprn], sprn);
65 spr_load_dump_spr(sprn);
66 }
67
68 static void spr_store_dump_spr(int sprn)
69 {
70 #ifdef PPC_DUMP_SPR_ACCESSES
71 TCGv_i32 t0 = tcg_const_i32(sprn);
72 gen_helper_store_dump_spr(cpu_env, t0);
73 tcg_temp_free_i32(t0);
74 #endif
75 }
76
77 static void spr_write_generic(DisasContext *ctx, int sprn, int gprn)
78 {
79 gen_store_spr(sprn, cpu_gpr[gprn]);
80 spr_store_dump_spr(sprn);
81 }
82
83 #if !defined(CONFIG_USER_ONLY)
84 static void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
85 {
86 #ifdef TARGET_PPC64
87 TCGv t0 = tcg_temp_new();
88 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
89 gen_store_spr(sprn, t0);
90 tcg_temp_free(t0);
91 spr_store_dump_spr(sprn);
92 #else
93 spr_write_generic(ctx, sprn, gprn);
94 #endif
95 }
96
97 static void spr_write_clear(DisasContext *ctx, int sprn, int gprn)
98 {
99 TCGv t0 = tcg_temp_new();
100 TCGv t1 = tcg_temp_new();
101 gen_load_spr(t0, sprn);
102 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
103 tcg_gen_and_tl(t0, t0, t1);
104 gen_store_spr(sprn, t0);
105 tcg_temp_free(t0);
106 tcg_temp_free(t1);
107 }
108
109 static void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
110 {
111 }
112
113 #endif
114
115 /* SPR common to all PowerPC */
116 /* XER */
117 static void spr_read_xer(DisasContext *ctx, int gprn, int sprn)
118 {
119 gen_read_xer(ctx, cpu_gpr[gprn]);
120 }
121
122 static void spr_write_xer(DisasContext *ctx, int sprn, int gprn)
123 {
124 gen_write_xer(cpu_gpr[gprn]);
125 }
126
127 /* LR */
128 static void spr_read_lr(DisasContext *ctx, int gprn, int sprn)
129 {
130 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
131 }
132
133 static void spr_write_lr(DisasContext *ctx, int sprn, int gprn)
134 {
135 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
136 }
137
138 /* CFAR */
139 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
140 static void spr_read_cfar(DisasContext *ctx, int gprn, int sprn)
141 {
142 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
143 }
144
145 static void spr_write_cfar(DisasContext *ctx, int sprn, int gprn)
146 {
147 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
148 }
149 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
150
151 /* CTR */
152 static void spr_read_ctr(DisasContext *ctx, int gprn, int sprn)
153 {
154 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
155 }
156
157 static void spr_write_ctr(DisasContext *ctx, int sprn, int gprn)
158 {
159 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
160 }
161
162 /* User read access to SPR */
163 /* USPRx */
164 /* UMMCRx */
165 /* UPMCx */
166 /* USIA */
167 /* UDECR */
168 static void spr_read_ureg(DisasContext *ctx, int gprn, int sprn)
169 {
170 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
171 }
172
173 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
174 static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
175 {
176 gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
177 }
178 #endif
179
180 /* SPR common to all non-embedded PowerPC */
181 /* DECR */
182 #if !defined(CONFIG_USER_ONLY)
183 static void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
184 {
185 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
186 gen_io_start();
187 }
188 gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
189 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
190 gen_io_end();
191 gen_stop_exception(ctx);
192 }
193 }
194
195 static void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
196 {
197 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
198 gen_io_start();
199 }
200 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
201 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
202 gen_io_end();
203 gen_stop_exception(ctx);
204 }
205 }
206 #endif
207
208 /* SPR common to all non-embedded PowerPC, except 601 */
209 /* Time base */
210 static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
211 {
212 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
213 gen_io_start();
214 }
215 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
216 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
217 gen_io_end();
218 gen_stop_exception(ctx);
219 }
220 }
221
222 static void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
223 {
224 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
225 gen_io_start();
226 }
227 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
228 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
229 gen_io_end();
230 gen_stop_exception(ctx);
231 }
232 }
233
234 ATTRIBUTE_UNUSED
235 static void spr_read_atbl(DisasContext *ctx, int gprn, int sprn)
236 {
237 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
238 }
239
240 ATTRIBUTE_UNUSED
241 static void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
242 {
243 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
244 }
245
246 #if !defined(CONFIG_USER_ONLY)
247 static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
248 {
249 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
250 gen_io_start();
251 }
252 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
253 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
254 gen_io_end();
255 gen_stop_exception(ctx);
256 }
257 }
258
259 static void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
260 {
261 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
262 gen_io_start();
263 }
264 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
265 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
266 gen_io_end();
267 gen_stop_exception(ctx);
268 }
269 }
270
271 ATTRIBUTE_UNUSED
272 static void spr_write_atbl(DisasContext *ctx, int sprn, int gprn)
273 {
274 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
275 }
276
277 ATTRIBUTE_UNUSED
278 static void spr_write_atbu(DisasContext *ctx, int sprn, int gprn)
279 {
280 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
281 }
282
283 #if defined(TARGET_PPC64)
284 ATTRIBUTE_UNUSED
285 static void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
286 {
287 gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
288 }
289
290 /* HDECR */
291 static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
292 {
293 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
294 gen_io_start();
295 }
296 gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env);
297 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
298 gen_io_end();
299 gen_stop_exception(ctx);
300 }
301 }
302
303 static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
304 {
305 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
306 gen_io_start();
307 }
308 gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]);
309 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
310 gen_io_end();
311 gen_stop_exception(ctx);
312 }
313 }
314
315 #endif
316 #endif
317
318 #if !defined(CONFIG_USER_ONLY)
319 /* IBAT0U...IBAT0U */
320 /* IBAT0L...IBAT7L */
321 static void spr_read_ibat(DisasContext *ctx, int gprn, int sprn)
322 {
323 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
324 offsetof(CPUPPCState,
325 IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
326 }
327
328 static void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn)
329 {
330 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
331 offsetof(CPUPPCState,
332 IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4]));
333 }
334
335 static void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn)
336 {
337 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
338 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
339 tcg_temp_free_i32(t0);
340 }
341
342 static void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn)
343 {
344 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
345 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
346 tcg_temp_free_i32(t0);
347 }
348
349 static void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn)
350 {
351 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
352 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
353 tcg_temp_free_i32(t0);
354 }
355
356 static void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn)
357 {
358 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
359 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
360 tcg_temp_free_i32(t0);
361 }
362
363 /* DBAT0U...DBAT7U */
364 /* DBAT0L...DBAT7L */
365 static void spr_read_dbat(DisasContext *ctx, int gprn, int sprn)
366 {
367 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
368 offsetof(CPUPPCState,
369 DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
370 }
371
372 static void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn)
373 {
374 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
375 offsetof(CPUPPCState,
376 DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
377 }
378
379 static void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn)
380 {
381 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
382 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
383 tcg_temp_free_i32(t0);
384 }
385
386 static void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn)
387 {
388 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
389 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
390 tcg_temp_free_i32(t0);
391 }
392
393 static void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn)
394 {
395 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
396 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
397 tcg_temp_free_i32(t0);
398 }
399
400 static void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn)
401 {
402 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
403 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
404 tcg_temp_free_i32(t0);
405 }
406
407 /* SDR1 */
408 static void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn)
409 {
410 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
411 }
412
413 #if defined(TARGET_PPC64)
414 /* 64 bits PowerPC specific SPRs */
415 /* PIDR */
416 static void spr_write_pidr(DisasContext *ctx, int sprn, int gprn)
417 {
418 gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]);
419 }
420
421 static void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn)
422 {
423 gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]);
424 }
425
426 static void spr_read_hior(DisasContext *ctx, int gprn, int sprn)
427 {
428 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
429 }
430
431 static void spr_write_hior(DisasContext *ctx, int sprn, int gprn)
432 {
433 TCGv t0 = tcg_temp_new();
434 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
435 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
436 tcg_temp_free(t0);
437 }
438 static void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
439 {
440 gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]);
441 }
442
443 static void spr_write_pcr(DisasContext *ctx, int sprn, int gprn)
444 {
445 gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]);
446 }
447 #endif
448 #endif
449
450 /* PowerPC 601 specific registers */
451 /* RTC */
452 static void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn)
453 {
454 gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
455 }
456
457 static void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn)
458 {
459 gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
460 }
461
462 #if !defined(CONFIG_USER_ONLY)
463 static void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn)
464 {
465 gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
466 }
467
468 static void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn)
469 {
470 gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
471 }
472
473 static void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn)
474 {
475 gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
476 /* Must stop the translation as endianness may have changed */
477 gen_stop_exception(ctx);
478 }
479 #endif
480
481 /* Unified bats */
482 #if !defined(CONFIG_USER_ONLY)
483 static void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn)
484 {
485 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
486 offsetof(CPUPPCState,
487 IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
488 }
489
490 static void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn)
491 {
492 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
493 gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
494 tcg_temp_free_i32(t0);
495 }
496
497 static void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn)
498 {
499 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
500 gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
501 tcg_temp_free_i32(t0);
502 }
503 #endif
504
505 /* PowerPC 40x specific registers */
506 #if !defined(CONFIG_USER_ONLY)
507 static void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn)
508 {
509 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
510 }
511
512 static void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn)
513 {
514 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
515 }
516
517 static void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
518 {
519 gen_store_spr(sprn, cpu_gpr[gprn]);
520 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
521 /* We must stop translation as we may have rebooted */
522 gen_stop_exception(ctx);
523 }
524
525 static void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
526 {
527 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
528 }
529
530 static void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
531 {
532 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
533 }
534
535 static void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
536 {
537 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
538 }
539 #endif
540
541 /* PowerPC 403 specific registers */
542 /* PBL1 / PBU1 / PBL2 / PBU2 */
543 #if !defined(CONFIG_USER_ONLY)
544 static void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn)
545 {
546 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
547 offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
548 }
549
550 static void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn)
551 {
552 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
553 gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
554 tcg_temp_free_i32(t0);
555 }
556
557 static void spr_write_pir(DisasContext *ctx, int sprn, int gprn)
558 {
559 TCGv t0 = tcg_temp_new();
560 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
561 gen_store_spr(SPR_PIR, t0);
562 tcg_temp_free(t0);
563 }
564 #endif
565
566 /* SPE specific registers */
567 static void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn)
568 {
569 TCGv_i32 t0 = tcg_temp_new_i32();
570 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
571 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
572 tcg_temp_free_i32(t0);
573 }
574
575 static void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn)
576 {
577 TCGv_i32 t0 = tcg_temp_new_i32();
578 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
579 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
580 tcg_temp_free_i32(t0);
581 }
582
583 #if !defined(CONFIG_USER_ONLY)
584 /* Callback used to write the exception vector base */
585 static void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn)
586 {
587 TCGv t0 = tcg_temp_new();
588 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
589 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
590 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
591 gen_store_spr(sprn, t0);
592 tcg_temp_free(t0);
593 }
594
595 static void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn)
596 {
597 int sprn_offs;
598
599 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
600 sprn_offs = sprn - SPR_BOOKE_IVOR0;
601 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
602 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
603 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
604 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
605 } else {
606 printf("Trying to write an unknown exception vector %d %03x\n",
607 sprn, sprn);
608 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
609 return;
610 }
611
612 TCGv t0 = tcg_temp_new();
613 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
614 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
615 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
616 gen_store_spr(sprn, t0);
617 tcg_temp_free(t0);
618 }
619 #endif
620
621 static inline void vscr_init(CPUPPCState *env, uint32_t val)
622 {
623 /* Altivec always uses round-to-nearest */
624 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
625 helper_mtvscr(env, val);
626 }
627
628 #ifdef CONFIG_USER_ONLY
629 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
630 oea_read, oea_write, one_reg_id, initial_value) \
631 _spr_register(env, num, name, uea_read, uea_write, initial_value)
632 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
633 oea_read, oea_write, hea_read, hea_write, \
634 one_reg_id, initial_value) \
635 _spr_register(env, num, name, uea_read, uea_write, initial_value)
636 #else
637 #if !defined(CONFIG_KVM)
638 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
639 oea_read, oea_write, one_reg_id, initial_value) \
640 _spr_register(env, num, name, uea_read, uea_write, \
641 oea_read, oea_write, oea_read, oea_write, initial_value)
642 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
643 oea_read, oea_write, hea_read, hea_write, \
644 one_reg_id, initial_value) \
645 _spr_register(env, num, name, uea_read, uea_write, \
646 oea_read, oea_write, hea_read, hea_write, initial_value)
647 #else
648 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
649 oea_read, oea_write, one_reg_id, initial_value) \
650 _spr_register(env, num, name, uea_read, uea_write, \
651 oea_read, oea_write, oea_read, oea_write, \
652 one_reg_id, initial_value)
653 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
654 oea_read, oea_write, hea_read, hea_write, \
655 one_reg_id, initial_value) \
656 _spr_register(env, num, name, uea_read, uea_write, \
657 oea_read, oea_write, hea_read, hea_write, \
658 one_reg_id, initial_value)
659 #endif
660 #endif
661
662 #define spr_register(env, num, name, uea_read, uea_write, \
663 oea_read, oea_write, initial_value) \
664 spr_register_kvm(env, num, name, uea_read, uea_write, \
665 oea_read, oea_write, 0, initial_value)
666
667 #define spr_register_hv(env, num, name, uea_read, uea_write, \
668 oea_read, oea_write, hea_read, hea_write, \
669 initial_value) \
670 spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
671 oea_read, oea_write, hea_read, hea_write, \
672 0, initial_value)
673
674 static inline void _spr_register(CPUPPCState *env, int num,
675 const char *name,
676 void (*uea_read)(DisasContext *ctx,
677 int gprn, int sprn),
678 void (*uea_write)(DisasContext *ctx,
679 int sprn, int gprn),
680 #if !defined(CONFIG_USER_ONLY)
681
682 void (*oea_read)(DisasContext *ctx,
683 int gprn, int sprn),
684 void (*oea_write)(DisasContext *ctx,
685 int sprn, int gprn),
686 void (*hea_read)(DisasContext *opaque,
687 int gprn, int sprn),
688 void (*hea_write)(DisasContext *opaque,
689 int sprn, int gprn),
690 #endif
691 #if defined(CONFIG_KVM)
692 uint64_t one_reg_id,
693 #endif
694 target_ulong initial_value)
695 {
696 ppc_spr_t *spr;
697
698 spr = &env->spr_cb[num];
699 if (spr->name != NULL || env->spr[num] != 0x00000000 ||
700 #if !defined(CONFIG_USER_ONLY)
701 spr->oea_read != NULL || spr->oea_write != NULL ||
702 #endif
703 spr->uea_read != NULL || spr->uea_write != NULL) {
704 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
705 exit(1);
706 }
707 #if defined(PPC_DEBUG_SPR)
708 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
709 name, initial_value);
710 #endif
711 spr->name = name;
712 spr->uea_read = uea_read;
713 spr->uea_write = uea_write;
714 #if !defined(CONFIG_USER_ONLY)
715 spr->oea_read = oea_read;
716 spr->oea_write = oea_write;
717 spr->hea_read = hea_read;
718 spr->hea_write = hea_write;
719 #endif
720 #if defined(CONFIG_KVM)
721 spr->one_reg_id = one_reg_id,
722 #endif
723 env->spr[num] = spr->default_value = initial_value;
724 }
725
726 /* Generic PowerPC SPRs */
727 static void gen_spr_generic(CPUPPCState *env)
728 {
729 /* Integer processing */
730 spr_register(env, SPR_XER, "XER",
731 &spr_read_xer, &spr_write_xer,
732 &spr_read_xer, &spr_write_xer,
733 0x00000000);
734 /* Branch contol */
735 spr_register(env, SPR_LR, "LR",
736 &spr_read_lr, &spr_write_lr,
737 &spr_read_lr, &spr_write_lr,
738 0x00000000);
739 spr_register(env, SPR_CTR, "CTR",
740 &spr_read_ctr, &spr_write_ctr,
741 &spr_read_ctr, &spr_write_ctr,
742 0x00000000);
743 /* Interrupt processing */
744 spr_register(env, SPR_SRR0, "SRR0",
745 SPR_NOACCESS, SPR_NOACCESS,
746 &spr_read_generic, &spr_write_generic,
747 0x00000000);
748 spr_register(env, SPR_SRR1, "SRR1",
749 SPR_NOACCESS, SPR_NOACCESS,
750 &spr_read_generic, &spr_write_generic,
751 0x00000000);
752 /* Processor control */
753 spr_register(env, SPR_SPRG0, "SPRG0",
754 SPR_NOACCESS, SPR_NOACCESS,
755 &spr_read_generic, &spr_write_generic,
756 0x00000000);
757 spr_register(env, SPR_SPRG1, "SPRG1",
758 SPR_NOACCESS, SPR_NOACCESS,
759 &spr_read_generic, &spr_write_generic,
760 0x00000000);
761 spr_register(env, SPR_SPRG2, "SPRG2",
762 SPR_NOACCESS, SPR_NOACCESS,
763 &spr_read_generic, &spr_write_generic,
764 0x00000000);
765 spr_register(env, SPR_SPRG3, "SPRG3",
766 SPR_NOACCESS, SPR_NOACCESS,
767 &spr_read_generic, &spr_write_generic,
768 0x00000000);
769 }
770
771 /* SPR common to all non-embedded PowerPC, including 601 */
772 static void gen_spr_ne_601(CPUPPCState *env)
773 {
774 /* Exception processing */
775 spr_register_kvm(env, SPR_DSISR, "DSISR",
776 SPR_NOACCESS, SPR_NOACCESS,
777 &spr_read_generic, &spr_write_generic,
778 KVM_REG_PPC_DSISR, 0x00000000);
779 spr_register_kvm(env, SPR_DAR, "DAR",
780 SPR_NOACCESS, SPR_NOACCESS,
781 &spr_read_generic, &spr_write_generic,
782 KVM_REG_PPC_DAR, 0x00000000);
783 /* Timer */
784 spr_register(env, SPR_DECR, "DECR",
785 SPR_NOACCESS, SPR_NOACCESS,
786 &spr_read_decr, &spr_write_decr,
787 0x00000000);
788 }
789
790 /* Storage Description Register 1 */
791 static void gen_spr_sdr1(CPUPPCState *env)
792 {
793 #ifndef CONFIG_USER_ONLY
794 if (env->has_hv_mode) {
795 /*
796 * SDR1 is a hypervisor resource on CPUs which have a
797 * hypervisor mode
798 */
799 spr_register_hv(env, SPR_SDR1, "SDR1",
800 SPR_NOACCESS, SPR_NOACCESS,
801 SPR_NOACCESS, SPR_NOACCESS,
802 &spr_read_generic, &spr_write_sdr1,
803 0x00000000);
804 } else {
805 spr_register(env, SPR_SDR1, "SDR1",
806 SPR_NOACCESS, SPR_NOACCESS,
807 &spr_read_generic, &spr_write_sdr1,
808 0x00000000);
809 }
810 #endif
811 }
812
813 /* BATs 0-3 */
814 static void gen_low_BATs(CPUPPCState *env)
815 {
816 #if !defined(CONFIG_USER_ONLY)
817 spr_register(env, SPR_IBAT0U, "IBAT0U",
818 SPR_NOACCESS, SPR_NOACCESS,
819 &spr_read_ibat, &spr_write_ibatu,
820 0x00000000);
821 spr_register(env, SPR_IBAT0L, "IBAT0L",
822 SPR_NOACCESS, SPR_NOACCESS,
823 &spr_read_ibat, &spr_write_ibatl,
824 0x00000000);
825 spr_register(env, SPR_IBAT1U, "IBAT1U",
826 SPR_NOACCESS, SPR_NOACCESS,
827 &spr_read_ibat, &spr_write_ibatu,
828 0x00000000);
829 spr_register(env, SPR_IBAT1L, "IBAT1L",
830 SPR_NOACCESS, SPR_NOACCESS,
831 &spr_read_ibat, &spr_write_ibatl,
832 0x00000000);
833 spr_register(env, SPR_IBAT2U, "IBAT2U",
834 SPR_NOACCESS, SPR_NOACCESS,
835 &spr_read_ibat, &spr_write_ibatu,
836 0x00000000);
837 spr_register(env, SPR_IBAT2L, "IBAT2L",
838 SPR_NOACCESS, SPR_NOACCESS,
839 &spr_read_ibat, &spr_write_ibatl,
840 0x00000000);
841 spr_register(env, SPR_IBAT3U, "IBAT3U",
842 SPR_NOACCESS, SPR_NOACCESS,
843 &spr_read_ibat, &spr_write_ibatu,
844 0x00000000);
845 spr_register(env, SPR_IBAT3L, "IBAT3L",
846 SPR_NOACCESS, SPR_NOACCESS,
847 &spr_read_ibat, &spr_write_ibatl,
848 0x00000000);
849 spr_register(env, SPR_DBAT0U, "DBAT0U",
850 SPR_NOACCESS, SPR_NOACCESS,
851 &spr_read_dbat, &spr_write_dbatu,
852 0x00000000);
853 spr_register(env, SPR_DBAT0L, "DBAT0L",
854 SPR_NOACCESS, SPR_NOACCESS,
855 &spr_read_dbat, &spr_write_dbatl,
856 0x00000000);
857 spr_register(env, SPR_DBAT1U, "DBAT1U",
858 SPR_NOACCESS, SPR_NOACCESS,
859 &spr_read_dbat, &spr_write_dbatu,
860 0x00000000);
861 spr_register(env, SPR_DBAT1L, "DBAT1L",
862 SPR_NOACCESS, SPR_NOACCESS,
863 &spr_read_dbat, &spr_write_dbatl,
864 0x00000000);
865 spr_register(env, SPR_DBAT2U, "DBAT2U",
866 SPR_NOACCESS, SPR_NOACCESS,
867 &spr_read_dbat, &spr_write_dbatu,
868 0x00000000);
869 spr_register(env, SPR_DBAT2L, "DBAT2L",
870 SPR_NOACCESS, SPR_NOACCESS,
871 &spr_read_dbat, &spr_write_dbatl,
872 0x00000000);
873 spr_register(env, SPR_DBAT3U, "DBAT3U",
874 SPR_NOACCESS, SPR_NOACCESS,
875 &spr_read_dbat, &spr_write_dbatu,
876 0x00000000);
877 spr_register(env, SPR_DBAT3L, "DBAT3L",
878 SPR_NOACCESS, SPR_NOACCESS,
879 &spr_read_dbat, &spr_write_dbatl,
880 0x00000000);
881 env->nb_BATs += 4;
882 #endif
883 }
884
885 /* BATs 4-7 */
886 static void gen_high_BATs(CPUPPCState *env)
887 {
888 #if !defined(CONFIG_USER_ONLY)
889 spr_register(env, SPR_IBAT4U, "IBAT4U",
890 SPR_NOACCESS, SPR_NOACCESS,
891 &spr_read_ibat_h, &spr_write_ibatu_h,
892 0x00000000);
893 spr_register(env, SPR_IBAT4L, "IBAT4L",
894 SPR_NOACCESS, SPR_NOACCESS,
895 &spr_read_ibat_h, &spr_write_ibatl_h,
896 0x00000000);
897 spr_register(env, SPR_IBAT5U, "IBAT5U",
898 SPR_NOACCESS, SPR_NOACCESS,
899 &spr_read_ibat_h, &spr_write_ibatu_h,
900 0x00000000);
901 spr_register(env, SPR_IBAT5L, "IBAT5L",
902 SPR_NOACCESS, SPR_NOACCESS,
903 &spr_read_ibat_h, &spr_write_ibatl_h,
904 0x00000000);
905 spr_register(env, SPR_IBAT6U, "IBAT6U",
906 SPR_NOACCESS, SPR_NOACCESS,
907 &spr_read_ibat_h, &spr_write_ibatu_h,
908 0x00000000);
909 spr_register(env, SPR_IBAT6L, "IBAT6L",
910 SPR_NOACCESS, SPR_NOACCESS,
911 &spr_read_ibat_h, &spr_write_ibatl_h,
912 0x00000000);
913 spr_register(env, SPR_IBAT7U, "IBAT7U",
914 SPR_NOACCESS, SPR_NOACCESS,
915 &spr_read_ibat_h, &spr_write_ibatu_h,
916 0x00000000);
917 spr_register(env, SPR_IBAT7L, "IBAT7L",
918 SPR_NOACCESS, SPR_NOACCESS,
919 &spr_read_ibat_h, &spr_write_ibatl_h,
920 0x00000000);
921 spr_register(env, SPR_DBAT4U, "DBAT4U",
922 SPR_NOACCESS, SPR_NOACCESS,
923 &spr_read_dbat_h, &spr_write_dbatu_h,
924 0x00000000);
925 spr_register(env, SPR_DBAT4L, "DBAT4L",
926 SPR_NOACCESS, SPR_NOACCESS,
927 &spr_read_dbat_h, &spr_write_dbatl_h,
928 0x00000000);
929 spr_register(env, SPR_DBAT5U, "DBAT5U",
930 SPR_NOACCESS, SPR_NOACCESS,
931 &spr_read_dbat_h, &spr_write_dbatu_h,
932 0x00000000);
933 spr_register(env, SPR_DBAT5L, "DBAT5L",
934 SPR_NOACCESS, SPR_NOACCESS,
935 &spr_read_dbat_h, &spr_write_dbatl_h,
936 0x00000000);
937 spr_register(env, SPR_DBAT6U, "DBAT6U",
938 SPR_NOACCESS, SPR_NOACCESS,
939 &spr_read_dbat_h, &spr_write_dbatu_h,
940 0x00000000);
941 spr_register(env, SPR_DBAT6L, "DBAT6L",
942 SPR_NOACCESS, SPR_NOACCESS,
943 &spr_read_dbat_h, &spr_write_dbatl_h,
944 0x00000000);
945 spr_register(env, SPR_DBAT7U, "DBAT7U",
946 SPR_NOACCESS, SPR_NOACCESS,
947 &spr_read_dbat_h, &spr_write_dbatu_h,
948 0x00000000);
949 spr_register(env, SPR_DBAT7L, "DBAT7L",
950 SPR_NOACCESS, SPR_NOACCESS,
951 &spr_read_dbat_h, &spr_write_dbatl_h,
952 0x00000000);
953 env->nb_BATs += 4;
954 #endif
955 }
956
957 /* Generic PowerPC time base */
958 static void gen_tbl(CPUPPCState *env)
959 {
960 spr_register(env, SPR_VTBL, "TBL",
961 &spr_read_tbl, SPR_NOACCESS,
962 &spr_read_tbl, SPR_NOACCESS,
963 0x00000000);
964 spr_register(env, SPR_TBL, "TBL",
965 &spr_read_tbl, SPR_NOACCESS,
966 &spr_read_tbl, &spr_write_tbl,
967 0x00000000);
968 spr_register(env, SPR_VTBU, "TBU",
969 &spr_read_tbu, SPR_NOACCESS,
970 &spr_read_tbu, SPR_NOACCESS,
971 0x00000000);
972 spr_register(env, SPR_TBU, "TBU",
973 &spr_read_tbu, SPR_NOACCESS,
974 &spr_read_tbu, &spr_write_tbu,
975 0x00000000);
976 }
977
978 /* Softare table search registers */
979 static void gen_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
980 {
981 #if !defined(CONFIG_USER_ONLY)
982 env->nb_tlb = nb_tlbs;
983 env->nb_ways = nb_ways;
984 env->id_tlbs = 1;
985 env->tlb_type = TLB_6XX;
986 spr_register(env, SPR_DMISS, "DMISS",
987 SPR_NOACCESS, SPR_NOACCESS,
988 &spr_read_generic, SPR_NOACCESS,
989 0x00000000);
990 spr_register(env, SPR_DCMP, "DCMP",
991 SPR_NOACCESS, SPR_NOACCESS,
992 &spr_read_generic, SPR_NOACCESS,
993 0x00000000);
994 spr_register(env, SPR_HASH1, "HASH1",
995 SPR_NOACCESS, SPR_NOACCESS,
996 &spr_read_generic, SPR_NOACCESS,
997 0x00000000);
998 spr_register(env, SPR_HASH2, "HASH2",
999 SPR_NOACCESS, SPR_NOACCESS,
1000 &spr_read_generic, SPR_NOACCESS,
1001 0x00000000);
1002 spr_register(env, SPR_IMISS, "IMISS",
1003 SPR_NOACCESS, SPR_NOACCESS,
1004 &spr_read_generic, SPR_NOACCESS,
1005 0x00000000);
1006 spr_register(env, SPR_ICMP, "ICMP",
1007 SPR_NOACCESS, SPR_NOACCESS,
1008 &spr_read_generic, SPR_NOACCESS,
1009 0x00000000);
1010 spr_register(env, SPR_RPA, "RPA",
1011 SPR_NOACCESS, SPR_NOACCESS,
1012 &spr_read_generic, &spr_write_generic,
1013 0x00000000);
1014 #endif
1015 }
1016
1017 /* SPR common to MPC755 and G2 */
1018 static void gen_spr_G2_755(CPUPPCState *env)
1019 {
1020 /* SGPRs */
1021 spr_register(env, SPR_SPRG4, "SPRG4",
1022 SPR_NOACCESS, SPR_NOACCESS,
1023 &spr_read_generic, &spr_write_generic,
1024 0x00000000);
1025 spr_register(env, SPR_SPRG5, "SPRG5",
1026 SPR_NOACCESS, SPR_NOACCESS,
1027 &spr_read_generic, &spr_write_generic,
1028 0x00000000);
1029 spr_register(env, SPR_SPRG6, "SPRG6",
1030 SPR_NOACCESS, SPR_NOACCESS,
1031 &spr_read_generic, &spr_write_generic,
1032 0x00000000);
1033 spr_register(env, SPR_SPRG7, "SPRG7",
1034 SPR_NOACCESS, SPR_NOACCESS,
1035 &spr_read_generic, &spr_write_generic,
1036 0x00000000);
1037 }
1038
1039 /* SPR common to all 7xx PowerPC implementations */
1040 static void gen_spr_7xx(CPUPPCState *env)
1041 {
1042 /* Breakpoints */
1043 /* XXX : not implemented */
1044 spr_register_kvm(env, SPR_DABR, "DABR",
1045 SPR_NOACCESS, SPR_NOACCESS,
1046 &spr_read_generic, &spr_write_generic,
1047 KVM_REG_PPC_DABR, 0x00000000);
1048 /* XXX : not implemented */
1049 spr_register(env, SPR_IABR, "IABR",
1050 SPR_NOACCESS, SPR_NOACCESS,
1051 &spr_read_generic, &spr_write_generic,
1052 0x00000000);
1053 /* Cache management */
1054 /* XXX : not implemented */
1055 spr_register(env, SPR_ICTC, "ICTC",
1056 SPR_NOACCESS, SPR_NOACCESS,
1057 &spr_read_generic, &spr_write_generic,
1058 0x00000000);
1059 /* Performance monitors */
1060 /* XXX : not implemented */
1061 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
1062 SPR_NOACCESS, SPR_NOACCESS,
1063 &spr_read_generic, &spr_write_generic,
1064 0x00000000);
1065 /* XXX : not implemented */
1066 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
1067 SPR_NOACCESS, SPR_NOACCESS,
1068 &spr_read_generic, &spr_write_generic,
1069 0x00000000);
1070 /* XXX : not implemented */
1071 spr_register(env, SPR_7XX_PMC1, "PMC1",
1072 SPR_NOACCESS, SPR_NOACCESS,
1073 &spr_read_generic, &spr_write_generic,
1074 0x00000000);
1075 /* XXX : not implemented */
1076 spr_register(env, SPR_7XX_PMC2, "PMC2",
1077 SPR_NOACCESS, SPR_NOACCESS,
1078 &spr_read_generic, &spr_write_generic,
1079 0x00000000);
1080 /* XXX : not implemented */
1081 spr_register(env, SPR_7XX_PMC3, "PMC3",
1082 SPR_NOACCESS, SPR_NOACCESS,
1083 &spr_read_generic, &spr_write_generic,
1084 0x00000000);
1085 /* XXX : not implemented */
1086 spr_register(env, SPR_7XX_PMC4, "PMC4",
1087 SPR_NOACCESS, SPR_NOACCESS,
1088 &spr_read_generic, &spr_write_generic,
1089 0x00000000);
1090 /* XXX : not implemented */
1091 spr_register(env, SPR_7XX_SIAR, "SIAR",
1092 SPR_NOACCESS, SPR_NOACCESS,
1093 &spr_read_generic, SPR_NOACCESS,
1094 0x00000000);
1095 /* XXX : not implemented */
1096 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
1097 &spr_read_ureg, SPR_NOACCESS,
1098 &spr_read_ureg, SPR_NOACCESS,
1099 0x00000000);
1100 /* XXX : not implemented */
1101 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
1102 &spr_read_ureg, SPR_NOACCESS,
1103 &spr_read_ureg, SPR_NOACCESS,
1104 0x00000000);
1105 /* XXX : not implemented */
1106 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
1107 &spr_read_ureg, SPR_NOACCESS,
1108 &spr_read_ureg, SPR_NOACCESS,
1109 0x00000000);
1110 /* XXX : not implemented */
1111 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
1112 &spr_read_ureg, SPR_NOACCESS,
1113 &spr_read_ureg, SPR_NOACCESS,
1114 0x00000000);
1115 /* XXX : not implemented */
1116 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
1117 &spr_read_ureg, SPR_NOACCESS,
1118 &spr_read_ureg, SPR_NOACCESS,
1119 0x00000000);
1120 /* XXX : not implemented */
1121 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
1122 &spr_read_ureg, SPR_NOACCESS,
1123 &spr_read_ureg, SPR_NOACCESS,
1124 0x00000000);
1125 /* XXX : not implemented */
1126 spr_register(env, SPR_7XX_USIAR, "USIAR",
1127 &spr_read_ureg, SPR_NOACCESS,
1128 &spr_read_ureg, SPR_NOACCESS,
1129 0x00000000);
1130 /* External access control */
1131 /* XXX : not implemented */
1132 spr_register(env, SPR_EAR, "EAR",
1133 SPR_NOACCESS, SPR_NOACCESS,
1134 &spr_read_generic, &spr_write_generic,
1135 0x00000000);
1136 }
1137
1138 #ifdef TARGET_PPC64
1139 #ifndef CONFIG_USER_ONLY
1140 static void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
1141 {
1142 TCGv t0 = tcg_temp_new();
1143 TCGv t1 = tcg_temp_new();
1144 TCGv t2 = tcg_temp_new();
1145
1146 /*
1147 * Note, the HV=1 PR=0 case is handled earlier by simply using
1148 * spr_write_generic for HV mode in the SPR table
1149 */
1150
1151 /* Build insertion mask into t1 based on context */
1152 if (ctx->pr) {
1153 gen_load_spr(t1, SPR_UAMOR);
1154 } else {
1155 gen_load_spr(t1, SPR_AMOR);
1156 }
1157
1158 /* Mask new bits into t2 */
1159 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1160
1161 /* Load AMR and clear new bits in t0 */
1162 gen_load_spr(t0, SPR_AMR);
1163 tcg_gen_andc_tl(t0, t0, t1);
1164
1165 /* Or'in new bits and write it out */
1166 tcg_gen_or_tl(t0, t0, t2);
1167 gen_store_spr(SPR_AMR, t0);
1168 spr_store_dump_spr(SPR_AMR);
1169
1170 tcg_temp_free(t0);
1171 tcg_temp_free(t1);
1172 tcg_temp_free(t2);
1173 }
1174
1175 static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
1176 {
1177 TCGv t0 = tcg_temp_new();
1178 TCGv t1 = tcg_temp_new();
1179 TCGv t2 = tcg_temp_new();
1180
1181 /*
1182 * Note, the HV=1 case is handled earlier by simply using
1183 * spr_write_generic for HV mode in the SPR table
1184 */
1185
1186 /* Build insertion mask into t1 based on context */
1187 gen_load_spr(t1, SPR_AMOR);
1188
1189 /* Mask new bits into t2 */
1190 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1191
1192 /* Load AMR and clear new bits in t0 */
1193 gen_load_spr(t0, SPR_UAMOR);
1194 tcg_gen_andc_tl(t0, t0, t1);
1195
1196 /* Or'in new bits and write it out */
1197 tcg_gen_or_tl(t0, t0, t2);
1198 gen_store_spr(SPR_UAMOR, t0);
1199 spr_store_dump_spr(SPR_UAMOR);
1200
1201 tcg_temp_free(t0);
1202 tcg_temp_free(t1);
1203 tcg_temp_free(t2);
1204 }
1205
1206 static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
1207 {
1208 TCGv t0 = tcg_temp_new();
1209 TCGv t1 = tcg_temp_new();
1210 TCGv t2 = tcg_temp_new();
1211
1212 /*
1213 * Note, the HV=1 case is handled earlier by simply using
1214 * spr_write_generic for HV mode in the SPR table
1215 */
1216
1217 /* Build insertion mask into t1 based on context */
1218 gen_load_spr(t1, SPR_AMOR);
1219
1220 /* Mask new bits into t2 */
1221 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1222
1223 /* Load AMR and clear new bits in t0 */
1224 gen_load_spr(t0, SPR_IAMR);
1225 tcg_gen_andc_tl(t0, t0, t1);
1226
1227 /* Or'in new bits and write it out */
1228 tcg_gen_or_tl(t0, t0, t2);
1229 gen_store_spr(SPR_IAMR, t0);
1230 spr_store_dump_spr(SPR_IAMR);
1231
1232 tcg_temp_free(t0);
1233 tcg_temp_free(t1);
1234 tcg_temp_free(t2);
1235 }
1236 #endif /* CONFIG_USER_ONLY */
1237
1238 static void gen_spr_amr(CPUPPCState *env)
1239 {
1240 #ifndef CONFIG_USER_ONLY
1241 /*
1242 * Virtual Page Class Key protection
1243 *
1244 * The AMR is accessible either via SPR 13 or SPR 29. 13 is
1245 * userspace accessible, 29 is privileged. So we only need to set
1246 * the kvm ONE_REG id on one of them, we use 29
1247 */
1248 spr_register(env, SPR_UAMR, "UAMR",
1249 &spr_read_generic, &spr_write_amr,
1250 &spr_read_generic, &spr_write_amr,
1251 0);
1252 spr_register_kvm_hv(env, SPR_AMR, "AMR",
1253 SPR_NOACCESS, SPR_NOACCESS,
1254 &spr_read_generic, &spr_write_amr,
1255 &spr_read_generic, &spr_write_generic,
1256 KVM_REG_PPC_AMR, 0);
1257 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
1258 SPR_NOACCESS, SPR_NOACCESS,
1259 &spr_read_generic, &spr_write_uamor,
1260 &spr_read_generic, &spr_write_generic,
1261 KVM_REG_PPC_UAMOR, 0);
1262 spr_register_hv(env, SPR_AMOR, "AMOR",
1263 SPR_NOACCESS, SPR_NOACCESS,
1264 SPR_NOACCESS, SPR_NOACCESS,
1265 &spr_read_generic, &spr_write_generic,
1266 0);
1267 #endif /* !CONFIG_USER_ONLY */
1268 }
1269
1270 static void gen_spr_iamr(CPUPPCState *env)
1271 {
1272 #ifndef CONFIG_USER_ONLY
1273 spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
1274 SPR_NOACCESS, SPR_NOACCESS,
1275 &spr_read_generic, &spr_write_iamr,
1276 &spr_read_generic, &spr_write_generic,
1277 KVM_REG_PPC_IAMR, 0);
1278 #endif /* !CONFIG_USER_ONLY */
1279 }
1280 #endif /* TARGET_PPC64 */
1281
1282 #ifndef CONFIG_USER_ONLY
1283 static void spr_read_thrm(DisasContext *ctx, int gprn, int sprn)
1284 {
1285 gen_helper_fixup_thrm(cpu_env);
1286 gen_load_spr(cpu_gpr[gprn], sprn);
1287 spr_load_dump_spr(sprn);
1288 }
1289 #endif /* !CONFIG_USER_ONLY */
1290
1291 static void gen_spr_thrm(CPUPPCState *env)
1292 {
1293 /* Thermal management */
1294 /* XXX : not implemented */
1295 spr_register(env, SPR_THRM1, "THRM1",
1296 SPR_NOACCESS, SPR_NOACCESS,
1297 &spr_read_thrm, &spr_write_generic,
1298 0x00000000);
1299 /* XXX : not implemented */
1300 spr_register(env, SPR_THRM2, "THRM2",
1301 SPR_NOACCESS, SPR_NOACCESS,
1302 &spr_read_thrm, &spr_write_generic,
1303 0x00000000);
1304 /* XXX : not implemented */
1305 spr_register(env, SPR_THRM3, "THRM3",
1306 SPR_NOACCESS, SPR_NOACCESS,
1307 &spr_read_thrm, &spr_write_generic,
1308 0x00000000);
1309 }
1310
1311 /* SPR specific to PowerPC 604 implementation */
1312 static void gen_spr_604(CPUPPCState *env)
1313 {
1314 /* Processor identification */
1315 spr_register(env, SPR_PIR, "PIR",
1316 SPR_NOACCESS, SPR_NOACCESS,
1317 &spr_read_generic, &spr_write_pir,
1318 0x00000000);
1319 /* Breakpoints */
1320 /* XXX : not implemented */
1321 spr_register(env, SPR_IABR, "IABR",
1322 SPR_NOACCESS, SPR_NOACCESS,
1323 &spr_read_generic, &spr_write_generic,
1324 0x00000000);
1325 /* XXX : not implemented */
1326 spr_register_kvm(env, SPR_DABR, "DABR",
1327 SPR_NOACCESS, SPR_NOACCESS,
1328 &spr_read_generic, &spr_write_generic,
1329 KVM_REG_PPC_DABR, 0x00000000);
1330 /* Performance counters */
1331 /* XXX : not implemented */
1332 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
1333 SPR_NOACCESS, SPR_NOACCESS,
1334 &spr_read_generic, &spr_write_generic,
1335 0x00000000);
1336 /* XXX : not implemented */
1337 spr_register(env, SPR_7XX_PMC1, "PMC1",
1338 SPR_NOACCESS, SPR_NOACCESS,
1339 &spr_read_generic, &spr_write_generic,
1340 0x00000000);
1341 /* XXX : not implemented */
1342 spr_register(env, SPR_7XX_PMC2, "PMC2",
1343 SPR_NOACCESS, SPR_NOACCESS,
1344 &spr_read_generic, &spr_write_generic,
1345 0x00000000);
1346 /* XXX : not implemented */
1347 spr_register(env, SPR_7XX_SIAR, "SIAR",
1348 SPR_NOACCESS, SPR_NOACCESS,
1349 &spr_read_generic, SPR_NOACCESS,
1350 0x00000000);
1351 /* XXX : not implemented */
1352 spr_register(env, SPR_SDA, "SDA",
1353 SPR_NOACCESS, SPR_NOACCESS,
1354 &spr_read_generic, SPR_NOACCESS,
1355 0x00000000);
1356 /* External access control */
1357 /* XXX : not implemented */
1358 spr_register(env, SPR_EAR, "EAR",
1359 SPR_NOACCESS, SPR_NOACCESS,
1360 &spr_read_generic, &spr_write_generic,
1361 0x00000000);
1362 }
1363
1364 /* SPR specific to PowerPC 603 implementation */
1365 static void gen_spr_603(CPUPPCState *env)
1366 {
1367 /* External access control */
1368 /* XXX : not implemented */
1369 spr_register(env, SPR_EAR, "EAR",
1370 SPR_NOACCESS, SPR_NOACCESS,
1371 &spr_read_generic, &spr_write_generic,
1372 0x00000000);
1373 /* Breakpoints */
1374 /* XXX : not implemented */
1375 spr_register(env, SPR_IABR, "IABR",
1376 SPR_NOACCESS, SPR_NOACCESS,
1377 &spr_read_generic, &spr_write_generic,
1378 0x00000000);
1379
1380 }
1381
1382 /* SPR specific to PowerPC G2 implementation */
1383 static void gen_spr_G2(CPUPPCState *env)
1384 {
1385 /* Memory base address */
1386 /* MBAR */
1387 /* XXX : not implemented */
1388 spr_register(env, SPR_MBAR, "MBAR",
1389 SPR_NOACCESS, SPR_NOACCESS,
1390 &spr_read_generic, &spr_write_generic,
1391 0x00000000);
1392 /* Exception processing */
1393 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1394 SPR_NOACCESS, SPR_NOACCESS,
1395 &spr_read_generic, &spr_write_generic,
1396 0x00000000);
1397 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1398 SPR_NOACCESS, SPR_NOACCESS,
1399 &spr_read_generic, &spr_write_generic,
1400 0x00000000);
1401 /* Breakpoints */
1402 /* XXX : not implemented */
1403 spr_register(env, SPR_DABR, "DABR",
1404 SPR_NOACCESS, SPR_NOACCESS,
1405 &spr_read_generic, &spr_write_generic,
1406 0x00000000);
1407 /* XXX : not implemented */
1408 spr_register(env, SPR_DABR2, "DABR2",
1409 SPR_NOACCESS, SPR_NOACCESS,
1410 &spr_read_generic, &spr_write_generic,
1411 0x00000000);
1412 /* XXX : not implemented */
1413 spr_register(env, SPR_IABR, "IABR",
1414 SPR_NOACCESS, SPR_NOACCESS,
1415 &spr_read_generic, &spr_write_generic,
1416 0x00000000);
1417 /* XXX : not implemented */
1418 spr_register(env, SPR_IABR2, "IABR2",
1419 SPR_NOACCESS, SPR_NOACCESS,
1420 &spr_read_generic, &spr_write_generic,
1421 0x00000000);
1422 /* XXX : not implemented */
1423 spr_register(env, SPR_IBCR, "IBCR",
1424 SPR_NOACCESS, SPR_NOACCESS,
1425 &spr_read_generic, &spr_write_generic,
1426 0x00000000);
1427 /* XXX : not implemented */
1428 spr_register(env, SPR_DBCR, "DBCR",
1429 SPR_NOACCESS, SPR_NOACCESS,
1430 &spr_read_generic, &spr_write_generic,
1431 0x00000000);
1432 }
1433
1434 /* SPR specific to PowerPC 602 implementation */
1435 static void gen_spr_602(CPUPPCState *env)
1436 {
1437 /* ESA registers */
1438 /* XXX : not implemented */
1439 spr_register(env, SPR_SER, "SER",
1440 SPR_NOACCESS, SPR_NOACCESS,
1441 &spr_read_generic, &spr_write_generic,
1442 0x00000000);
1443 /* XXX : not implemented */
1444 spr_register(env, SPR_SEBR, "SEBR",
1445 SPR_NOACCESS, SPR_NOACCESS,
1446 &spr_read_generic, &spr_write_generic,
1447 0x00000000);
1448 /* XXX : not implemented */
1449 spr_register(env, SPR_ESASRR, "ESASRR",
1450 SPR_NOACCESS, SPR_NOACCESS,
1451 &spr_read_generic, &spr_write_generic,
1452 0x00000000);
1453 /* Floating point status */
1454 /* XXX : not implemented */
1455 spr_register(env, SPR_SP, "SP",
1456 SPR_NOACCESS, SPR_NOACCESS,
1457 &spr_read_generic, &spr_write_generic,
1458 0x00000000);
1459 /* XXX : not implemented */
1460 spr_register(env, SPR_LT, "LT",
1461 SPR_NOACCESS, SPR_NOACCESS,
1462 &spr_read_generic, &spr_write_generic,
1463 0x00000000);
1464 /* Watchdog timer */
1465 /* XXX : not implemented */
1466 spr_register(env, SPR_TCR, "TCR",
1467 SPR_NOACCESS, SPR_NOACCESS,
1468 &spr_read_generic, &spr_write_generic,
1469 0x00000000);
1470 /* Interrupt base */
1471 spr_register(env, SPR_IBR, "IBR",
1472 SPR_NOACCESS, SPR_NOACCESS,
1473 &spr_read_generic, &spr_write_generic,
1474 0x00000000);
1475 /* XXX : not implemented */
1476 spr_register(env, SPR_IABR, "IABR",
1477 SPR_NOACCESS, SPR_NOACCESS,
1478 &spr_read_generic, &spr_write_generic,
1479 0x00000000);
1480 }
1481
1482 /* SPR specific to PowerPC 601 implementation */
1483 static void gen_spr_601(CPUPPCState *env)
1484 {
1485 /* Multiplication/division register */
1486 /* MQ */
1487 spr_register(env, SPR_MQ, "MQ",
1488 &spr_read_generic, &spr_write_generic,
1489 &spr_read_generic, &spr_write_generic,
1490 0x00000000);
1491 /* RTC registers */
1492 spr_register(env, SPR_601_RTCU, "RTCU",
1493 SPR_NOACCESS, SPR_NOACCESS,
1494 SPR_NOACCESS, &spr_write_601_rtcu,
1495 0x00000000);
1496 spr_register(env, SPR_601_VRTCU, "RTCU",
1497 &spr_read_601_rtcu, SPR_NOACCESS,
1498 &spr_read_601_rtcu, SPR_NOACCESS,
1499 0x00000000);
1500 spr_register(env, SPR_601_RTCL, "RTCL",
1501 SPR_NOACCESS, SPR_NOACCESS,
1502 SPR_NOACCESS, &spr_write_601_rtcl,
1503 0x00000000);
1504 spr_register(env, SPR_601_VRTCL, "RTCL",
1505 &spr_read_601_rtcl, SPR_NOACCESS,
1506 &spr_read_601_rtcl, SPR_NOACCESS,
1507 0x00000000);
1508 /* Timer */
1509 #if 0 /* ? */
1510 spr_register(env, SPR_601_UDECR, "UDECR",
1511 &spr_read_decr, SPR_NOACCESS,
1512 &spr_read_decr, SPR_NOACCESS,
1513 0x00000000);
1514 #endif
1515 /* External access control */
1516 /* XXX : not implemented */
1517 spr_register(env, SPR_EAR, "EAR",
1518 SPR_NOACCESS, SPR_NOACCESS,
1519 &spr_read_generic, &spr_write_generic,
1520 0x00000000);
1521 /* Memory management */
1522 #if !defined(CONFIG_USER_ONLY)
1523 spr_register(env, SPR_IBAT0U, "IBAT0U",
1524 SPR_NOACCESS, SPR_NOACCESS,
1525 &spr_read_601_ubat, &spr_write_601_ubatu,
1526 0x00000000);
1527 spr_register(env, SPR_IBAT0L, "IBAT0L",
1528 SPR_NOACCESS, SPR_NOACCESS,
1529 &spr_read_601_ubat, &spr_write_601_ubatl,
1530 0x00000000);
1531 spr_register(env, SPR_IBAT1U, "IBAT1U",
1532 SPR_NOACCESS, SPR_NOACCESS,
1533 &spr_read_601_ubat, &spr_write_601_ubatu,
1534 0x00000000);
1535 spr_register(env, SPR_IBAT1L, "IBAT1L",
1536 SPR_NOACCESS, SPR_NOACCESS,
1537 &spr_read_601_ubat, &spr_write_601_ubatl,
1538 0x00000000);
1539 spr_register(env, SPR_IBAT2U, "IBAT2U",
1540 SPR_NOACCESS, SPR_NOACCESS,
1541 &spr_read_601_ubat, &spr_write_601_ubatu,
1542 0x00000000);
1543 spr_register(env, SPR_IBAT2L, "IBAT2L",
1544 SPR_NOACCESS, SPR_NOACCESS,
1545 &spr_read_601_ubat, &spr_write_601_ubatl,
1546 0x00000000);
1547 spr_register(env, SPR_IBAT3U, "IBAT3U",
1548 SPR_NOACCESS, SPR_NOACCESS,
1549 &spr_read_601_ubat, &spr_write_601_ubatu,
1550 0x00000000);
1551 spr_register(env, SPR_IBAT3L, "IBAT3L",
1552 SPR_NOACCESS, SPR_NOACCESS,
1553 &spr_read_601_ubat, &spr_write_601_ubatl,
1554 0x00000000);
1555 env->nb_BATs = 4;
1556 #endif
1557 }
1558
1559 static void gen_spr_74xx(CPUPPCState *env)
1560 {
1561 /* Processor identification */
1562 spr_register(env, SPR_PIR, "PIR",
1563 SPR_NOACCESS, SPR_NOACCESS,
1564 &spr_read_generic, &spr_write_pir,
1565 0x00000000);
1566 /* XXX : not implemented */
1567 spr_register(env, SPR_74XX_MMCR2, "MMCR2",
1568 SPR_NOACCESS, SPR_NOACCESS,
1569 &spr_read_generic, &spr_write_generic,
1570 0x00000000);
1571 /* XXX : not implemented */
1572 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
1573 &spr_read_ureg, SPR_NOACCESS,
1574 &spr_read_ureg, SPR_NOACCESS,
1575 0x00000000);
1576 /* XXX: not implemented */
1577 spr_register(env, SPR_BAMR, "BAMR",
1578 SPR_NOACCESS, SPR_NOACCESS,
1579 &spr_read_generic, &spr_write_generic,
1580 0x00000000);
1581 /* XXX : not implemented */
1582 spr_register(env, SPR_MSSCR0, "MSSCR0",
1583 SPR_NOACCESS, SPR_NOACCESS,
1584 &spr_read_generic, &spr_write_generic,
1585 0x00000000);
1586 /* Hardware implementation registers */
1587 /* XXX : not implemented */
1588 spr_register(env, SPR_HID0, "HID0",
1589 SPR_NOACCESS, SPR_NOACCESS,
1590 &spr_read_generic, &spr_write_generic,
1591 0x00000000);
1592 /* XXX : not implemented */
1593 spr_register(env, SPR_HID1, "HID1",
1594 SPR_NOACCESS, SPR_NOACCESS,
1595 &spr_read_generic, &spr_write_generic,
1596 0x00000000);
1597 /* Altivec */
1598 spr_register(env, SPR_VRSAVE, "VRSAVE",
1599 &spr_read_generic, &spr_write_generic,
1600 &spr_read_generic, &spr_write_generic,
1601 0x00000000);
1602 /* XXX : not implemented */
1603 spr_register(env, SPR_L2CR, "L2CR",
1604 SPR_NOACCESS, SPR_NOACCESS,
1605 &spr_read_generic, spr_access_nop,
1606 0x00000000);
1607 /* Not strictly an SPR */
1608 vscr_init(env, 0x00010000);
1609 }
1610
1611 static void gen_l3_ctrl(CPUPPCState *env)
1612 {
1613 /* L3CR */
1614 /* XXX : not implemented */
1615 spr_register(env, SPR_L3CR, "L3CR",
1616 SPR_NOACCESS, SPR_NOACCESS,
1617 &spr_read_generic, &spr_write_generic,
1618 0x00000000);
1619 /* L3ITCR0 */
1620 /* XXX : not implemented */
1621 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1622 SPR_NOACCESS, SPR_NOACCESS,
1623 &spr_read_generic, &spr_write_generic,
1624 0x00000000);
1625 /* L3PM */
1626 /* XXX : not implemented */
1627 spr_register(env, SPR_L3PM, "L3PM",
1628 SPR_NOACCESS, SPR_NOACCESS,
1629 &spr_read_generic, &spr_write_generic,
1630 0x00000000);
1631 }
1632
1633 static void gen_74xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
1634 {
1635 #if !defined(CONFIG_USER_ONLY)
1636 env->nb_tlb = nb_tlbs;
1637 env->nb_ways = nb_ways;
1638 env->id_tlbs = 1;
1639 env->tlb_type = TLB_6XX;
1640 /* XXX : not implemented */
1641 spr_register(env, SPR_PTEHI, "PTEHI",
1642 SPR_NOACCESS, SPR_NOACCESS,
1643 &spr_read_generic, &spr_write_generic,
1644 0x00000000);
1645 /* XXX : not implemented */
1646 spr_register(env, SPR_PTELO, "PTELO",
1647 SPR_NOACCESS, SPR_NOACCESS,
1648 &spr_read_generic, &spr_write_generic,
1649 0x00000000);
1650 /* XXX : not implemented */
1651 spr_register(env, SPR_TLBMISS, "TLBMISS",
1652 SPR_NOACCESS, SPR_NOACCESS,
1653 &spr_read_generic, &spr_write_generic,
1654 0x00000000);
1655 #endif
1656 }
1657
1658 #if !defined(CONFIG_USER_ONLY)
1659 static void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn)
1660 {
1661 TCGv t0 = tcg_temp_new();
1662
1663 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE);
1664 gen_store_spr(sprn, t0);
1665 tcg_temp_free(t0);
1666 }
1667
1668 static void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
1669 {
1670 TCGv t0 = tcg_temp_new();
1671
1672 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE);
1673 gen_store_spr(sprn, t0);
1674 tcg_temp_free(t0);
1675 }
1676
1677 static void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn)
1678 {
1679 gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
1680 }
1681
1682 static void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn)
1683 {
1684 TCGv_i32 t0 = tcg_const_i32(sprn);
1685 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1686 tcg_temp_free_i32(t0);
1687 }
1688 static void spr_write_eplc(DisasContext *ctx, int sprn, int gprn)
1689 {
1690 gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]);
1691 }
1692 static void spr_write_epsc(DisasContext *ctx, int sprn, int gprn)
1693 {
1694 gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]);
1695 }
1696
1697 #endif
1698
1699 static void gen_spr_usprg3(CPUPPCState *env)
1700 {
1701 spr_register(env, SPR_USPRG3, "USPRG3",
1702 &spr_read_ureg, SPR_NOACCESS,
1703 &spr_read_ureg, SPR_NOACCESS,
1704 0x00000000);
1705 }
1706
1707 static void gen_spr_usprgh(CPUPPCState *env)
1708 {
1709 spr_register(env, SPR_USPRG4, "USPRG4",
1710 &spr_read_ureg, SPR_NOACCESS,
1711 &spr_read_ureg, SPR_NOACCESS,
1712 0x00000000);
1713 spr_register(env, SPR_USPRG5, "USPRG5",
1714 &spr_read_ureg, SPR_NOACCESS,
1715 &spr_read_ureg, SPR_NOACCESS,
1716 0x00000000);
1717 spr_register(env, SPR_USPRG6, "USPRG6",
1718 &spr_read_ureg, SPR_NOACCESS,
1719 &spr_read_ureg, SPR_NOACCESS,
1720 0x00000000);
1721 spr_register(env, SPR_USPRG7, "USPRG7",
1722 &spr_read_ureg, SPR_NOACCESS,
1723 &spr_read_ureg, SPR_NOACCESS,
1724 0x00000000);
1725 }
1726
1727 /* PowerPC BookE SPR */
1728 static void gen_spr_BookE(CPUPPCState *env, uint64_t ivor_mask)
1729 {
1730 const char *ivor_names[64] = {
1731 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1732 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1733 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1734 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1735 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1736 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1737 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1738 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1739 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1740 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1741 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1742 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1743 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1744 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1745 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1746 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1747 };
1748 #define SPR_BOOKE_IVORxx (-1)
1749 int ivor_sprn[64] = {
1750 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1751 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1752 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1753 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1754 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1755 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1756 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1757 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1758 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1759 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1760 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1761 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1762 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1763 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1764 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1765 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1766 };
1767 int i;
1768
1769 /* Interrupt processing */
1770 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1771 SPR_NOACCESS, SPR_NOACCESS,
1772 &spr_read_generic, &spr_write_generic,
1773 0x00000000);
1774 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1775 SPR_NOACCESS, SPR_NOACCESS,
1776 &spr_read_generic, &spr_write_generic,
1777 0x00000000);
1778 /* Debug */
1779 /* XXX : not implemented */
1780 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1781 SPR_NOACCESS, SPR_NOACCESS,
1782 &spr_read_generic, &spr_write_generic,
1783 0x00000000);
1784 /* XXX : not implemented */
1785 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1786 SPR_NOACCESS, SPR_NOACCESS,
1787 &spr_read_generic, &spr_write_generic,
1788 0x00000000);
1789 /* XXX : not implemented */
1790 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1791 SPR_NOACCESS, SPR_NOACCESS,
1792 &spr_read_generic, &spr_write_generic,
1793 0x00000000);
1794 /* XXX : not implemented */
1795 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1796 SPR_NOACCESS, SPR_NOACCESS,
1797 &spr_read_generic, &spr_write_generic,
1798 0x00000000);
1799 /* XXX : not implemented */
1800 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1801 SPR_NOACCESS, SPR_NOACCESS,
1802 &spr_read_generic, &spr_write_40x_dbcr0,
1803 0x00000000);
1804 /* XXX : not implemented */
1805 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1806 SPR_NOACCESS, SPR_NOACCESS,
1807 &spr_read_generic, &spr_write_generic,
1808 0x00000000);
1809 /* XXX : not implemented */
1810 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1811 SPR_NOACCESS, SPR_NOACCESS,
1812 &spr_read_generic, &spr_write_generic,
1813 0x00000000);
1814 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
1815 SPR_NOACCESS, SPR_NOACCESS,
1816 &spr_read_generic, &spr_write_generic,
1817 0x00000000);
1818 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
1819 SPR_NOACCESS, SPR_NOACCESS,
1820 &spr_read_generic, &spr_write_generic,
1821 0x00000000);
1822 /* XXX : not implemented */
1823 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1824 SPR_NOACCESS, SPR_NOACCESS,
1825 &spr_read_generic, &spr_write_clear,
1826 0x00000000);
1827 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1828 SPR_NOACCESS, SPR_NOACCESS,
1829 &spr_read_generic, &spr_write_generic,
1830 0x00000000);
1831 spr_register(env, SPR_BOOKE_ESR, "ESR",
1832 SPR_NOACCESS, SPR_NOACCESS,
1833 &spr_read_generic, &spr_write_generic,
1834 0x00000000);
1835 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1836 SPR_NOACCESS, SPR_NOACCESS,
1837 &spr_read_generic, &spr_write_excp_prefix,
1838 0x00000000);
1839 /* Exception vectors */
1840 for (i = 0; i < 64; i++) {
1841 if (ivor_mask & (1ULL << i)) {
1842 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1843 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1844 exit(1);
1845 }
1846 spr_register(env, ivor_sprn[i], ivor_names[i],
1847 SPR_NOACCESS, SPR_NOACCESS,
1848 &spr_read_generic, &spr_write_excp_vector,
1849 0x00000000);
1850 }
1851 }
1852 spr_register(env, SPR_BOOKE_PID, "PID",
1853 SPR_NOACCESS, SPR_NOACCESS,
1854 &spr_read_generic, &spr_write_booke_pid,
1855 0x00000000);
1856 spr_register(env, SPR_BOOKE_TCR, "TCR",
1857 SPR_NOACCESS, SPR_NOACCESS,
1858 &spr_read_generic, &spr_write_booke_tcr,
1859 0x00000000);
1860 spr_register(env, SPR_BOOKE_TSR, "TSR",
1861 SPR_NOACCESS, SPR_NOACCESS,
1862 &spr_read_generic, &spr_write_booke_tsr,
1863 0x00000000);
1864 /* Timer */
1865 spr_register(env, SPR_DECR, "DECR",
1866 SPR_NOACCESS, SPR_NOACCESS,
1867 &spr_read_decr, &spr_write_decr,
1868 0x00000000);
1869 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1870 SPR_NOACCESS, SPR_NOACCESS,
1871 SPR_NOACCESS, &spr_write_generic,
1872 0x00000000);
1873 /* SPRGs */
1874 spr_register(env, SPR_USPRG0, "USPRG0",
1875 &spr_read_generic, &spr_write_generic,
1876 &spr_read_generic, &spr_write_generic,
1877 0x00000000);
1878 spr_register(env, SPR_SPRG4, "SPRG4",
1879 SPR_NOACCESS, SPR_NOACCESS,
1880 &spr_read_generic, &spr_write_generic,
1881 0x00000000);
1882 spr_register(env, SPR_SPRG5, "SPRG5",
1883 SPR_NOACCESS, SPR_NOACCESS,
1884 &spr_read_generic, &spr_write_generic,
1885 0x00000000);
1886 spr_register(env, SPR_SPRG6, "SPRG6",
1887 SPR_NOACCESS, SPR_NOACCESS,
1888 &spr_read_generic, &spr_write_generic,
1889 0x00000000);
1890 spr_register(env, SPR_SPRG7, "SPRG7",
1891 SPR_NOACCESS, SPR_NOACCESS,
1892 &spr_read_generic, &spr_write_generic,
1893 0x00000000);
1894 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8",
1895 SPR_NOACCESS, SPR_NOACCESS,
1896 &spr_read_generic, &spr_write_generic,
1897 0x00000000);
1898 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9",
1899 SPR_NOACCESS, SPR_NOACCESS,
1900 &spr_read_generic, &spr_write_generic,
1901 0x00000000);
1902 }
1903
1904 static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1905 uint32_t maxsize, uint32_t flags,
1906 uint32_t nentries)
1907 {
1908 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1909 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1910 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1911 flags | nentries;
1912 }
1913
1914 /* BookE 2.06 storage control registers */
1915 static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1916 uint32_t *tlbncfg, uint32_t mmucfg)
1917 {
1918 #if !defined(CONFIG_USER_ONLY)
1919 const char *mas_names[8] = {
1920 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1921 };
1922 int mas_sprn[8] = {
1923 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1924 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1925 };
1926 int i;
1927
1928 /* TLB assist registers */
1929 /* XXX : not implemented */
1930 for (i = 0; i < 8; i++) {
1931 void (*uea_write)(DisasContext *ctx, int sprn, int gprn) =
1932 &spr_write_generic32;
1933 if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
1934 uea_write = &spr_write_generic;
1935 }
1936 if (mas_mask & (1 << i)) {
1937 spr_register(env, mas_sprn[i], mas_names[i],
1938 SPR_NOACCESS, SPR_NOACCESS,
1939 &spr_read_generic, uea_write,
1940 0x00000000);
1941 }
1942 }
1943 if (env->nb_pids > 1) {
1944 /* XXX : not implemented */
1945 spr_register(env, SPR_BOOKE_PID1, "PID1",
1946 SPR_NOACCESS, SPR_NOACCESS,
1947 &spr_read_generic, &spr_write_booke_pid,
1948 0x00000000);
1949 }
1950 if (env->nb_pids > 2) {
1951 /* XXX : not implemented */
1952 spr_register(env, SPR_BOOKE_PID2, "PID2",
1953 SPR_NOACCESS, SPR_NOACCESS,
1954 &spr_read_generic, &spr_write_booke_pid,
1955 0x00000000);
1956 }
1957
1958 spr_register(env, SPR_BOOKE_EPLC, "EPLC",
1959 SPR_NOACCESS, SPR_NOACCESS,
1960 &spr_read_generic, &spr_write_eplc,
1961 0x00000000);
1962 spr_register(env, SPR_BOOKE_EPSC, "EPSC",
1963 SPR_NOACCESS, SPR_NOACCESS,
1964 &spr_read_generic, &spr_write_epsc,
1965 0x00000000);
1966
1967 /* XXX : not implemented */
1968 spr_register(env, SPR_MMUCFG, "MMUCFG",
1969 SPR_NOACCESS, SPR_NOACCESS,
1970 &spr_read_generic, SPR_NOACCESS,
1971 mmucfg);
1972 switch (env->nb_ways) {
1973 case 4:
1974 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1975 SPR_NOACCESS, SPR_NOACCESS,
1976 &spr_read_generic, SPR_NOACCESS,
1977 tlbncfg[3]);
1978 /* Fallthru */
1979 case 3:
1980 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1981 SPR_NOACCESS, SPR_NOACCESS,
1982 &spr_read_generic, SPR_NOACCESS,
1983 tlbncfg[2]);
1984 /* Fallthru */
1985 case 2:
1986 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1987 SPR_NOACCESS, SPR_NOACCESS,
1988 &spr_read_generic, SPR_NOACCESS,
1989 tlbncfg[1]);
1990 /* Fallthru */
1991 case 1:
1992 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1993 SPR_NOACCESS, SPR_NOACCESS,
1994 &spr_read_generic, SPR_NOACCESS,
1995 tlbncfg[0]);
1996 /* Fallthru */
1997 case 0:
1998 default:
1999 break;
2000 }
2001 #endif
2002
2003 gen_spr_usprgh(env);
2004 }
2005
2006 /* SPR specific to PowerPC 440 implementation */
2007 static void gen_spr_440(CPUPPCState *env)
2008 {
2009 /* Cache control */
2010 /* XXX : not implemented */
2011 spr_register(env, SPR_440_DNV0, "DNV0",
2012 SPR_NOACCESS, SPR_NOACCESS,
2013 &spr_read_generic, &spr_write_generic,
2014 0x00000000);
2015 /* XXX : not implemented */
2016 spr_register(env, SPR_440_DNV1, "DNV1",
2017 SPR_NOACCESS, SPR_NOACCESS,
2018 &spr_read_generic, &spr_write_generic,
2019 0x00000000);
2020 /* XXX : not implemented */
2021 spr_register(env, SPR_440_DNV2, "DNV2",
2022 SPR_NOACCESS, SPR_NOACCESS,
2023 &spr_read_generic, &spr_write_generic,
2024 0x00000000);
2025 /* XXX : not implemented */
2026 spr_register(env, SPR_440_DNV3, "DNV3",
2027 SPR_NOACCESS, SPR_NOACCESS,
2028 &spr_read_generic, &spr_write_generic,
2029 0x00000000);
2030 /* XXX : not implemented */
2031 spr_register(env, SPR_440_DTV0, "DTV0",
2032 SPR_NOACCESS, SPR_NOACCESS,
2033 &spr_read_generic, &spr_write_generic,
2034 0x00000000);
2035 /* XXX : not implemented */
2036 spr_register(env, SPR_440_DTV1, "DTV1",
2037 SPR_NOACCESS, SPR_NOACCESS,
2038 &spr_read_generic, &spr_write_generic,
2039 0x00000000);
2040 /* XXX : not implemented */
2041 spr_register(env, SPR_440_DTV2, "DTV2",
2042 SPR_NOACCESS, SPR_NOACCESS,
2043 &spr_read_generic, &spr_write_generic,
2044 0x00000000);
2045 /* XXX : not implemented */
2046 spr_register(env, SPR_440_DTV3, "DTV3",
2047 SPR_NOACCESS, SPR_NOACCESS,
2048 &spr_read_generic, &spr_write_generic,
2049 0x00000000);
2050 /* XXX : not implemented */
2051 spr_register(env, SPR_440_DVLIM, "DVLIM",
2052 SPR_NOACCESS, SPR_NOACCESS,
2053 &spr_read_generic, &spr_write_generic,
2054 0x00000000);
2055 /* XXX : not implemented */
2056 spr_register(env, SPR_440_INV0, "INV0",
2057 SPR_NOACCESS, SPR_NOACCESS,
2058 &spr_read_generic, &spr_write_generic,
2059 0x00000000);
2060 /* XXX : not implemented */
2061 spr_register(env, SPR_440_INV1, "INV1",
2062 SPR_NOACCESS, SPR_NOACCESS,
2063 &spr_read_generic, &spr_write_generic,
2064 0x00000000);
2065 /* XXX : not implemented */
2066 spr_register(env, SPR_440_INV2, "INV2",
2067 SPR_NOACCESS, SPR_NOACCESS,
2068 &spr_read_generic, &spr_write_generic,
2069 0x00000000);
2070 /* XXX : not implemented */
2071 spr_register(env, SPR_440_INV3, "INV3",
2072 SPR_NOACCESS, SPR_NOACCESS,
2073 &spr_read_generic, &spr_write_generic,
2074 0x00000000);
2075 /* XXX : not implemented */
2076 spr_register(env, SPR_440_ITV0, "ITV0",
2077 SPR_NOACCESS, SPR_NOACCESS,
2078 &spr_read_generic, &spr_write_generic,
2079 0x00000000);
2080 /* XXX : not implemented */
2081 spr_register(env, SPR_440_ITV1, "ITV1",
2082 SPR_NOACCESS, SPR_NOACCESS,
2083 &spr_read_generic, &spr_write_generic,
2084 0x00000000);
2085 /* XXX : not implemented */
2086 spr_register(env, SPR_440_ITV2, "ITV2",
2087 SPR_NOACCESS, SPR_NOACCESS,
2088 &spr_read_generic, &spr_write_generic,
2089 0x00000000);
2090 /* XXX : not implemented */
2091 spr_register(env, SPR_440_ITV3, "ITV3",
2092 SPR_NOACCESS, SPR_NOACCESS,
2093 &spr_read_generic, &spr_write_generic,
2094 0x00000000);
2095 /* XXX : not implemented */
2096 spr_register(env, SPR_440_IVLIM, "IVLIM",
2097 SPR_NOACCESS, SPR_NOACCESS,
2098 &spr_read_generic, &spr_write_generic,
2099 0x00000000);
2100 /* Cache debug */
2101 /* XXX : not implemented */
2102 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
2103 SPR_NOACCESS, SPR_NOACCESS,
2104 &spr_read_generic, SPR_NOACCESS,
2105 0x00000000);
2106 /* XXX : not implemented */
2107 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
2108 SPR_NOACCESS, SPR_NOACCESS,
2109 &spr_read_generic, SPR_NOACCESS,
2110 0x00000000);
2111 /* XXX : not implemented */
2112 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
2113 SPR_NOACCESS, SPR_NOACCESS,
2114 &spr_read_generic, SPR_NOACCESS,
2115 0x00000000);
2116 /* XXX : not implemented */
2117 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
2118 SPR_NOACCESS, SPR_NOACCESS,
2119 &spr_read_generic, SPR_NOACCESS,
2120 0x00000000);
2121 /* XXX : not implemented */
2122 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
2123 SPR_NOACCESS, SPR_NOACCESS,
2124 &spr_read_generic, SPR_NOACCESS,
2125 0x00000000);
2126 /* XXX : not implemented */
2127 spr_register(env, SPR_440_DBDR, "DBDR",
2128 SPR_NOACCESS, SPR_NOACCESS,
2129 &spr_read_generic, &spr_write_generic,
2130 0x00000000);
2131 /* Processor control */
2132 spr_register(env, SPR_4xx_CCR0, "CCR0",
2133 SPR_NOACCESS, SPR_NOACCESS,
2134 &spr_read_generic, &spr_write_generic,
2135 0x00000000);
2136 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
2137 SPR_NOACCESS, SPR_NOACCESS,
2138 &spr_read_generic, SPR_NOACCESS,
2139 0x00000000);
2140 /* Storage control */
2141 spr_register(env, SPR_440_MMUCR, "MMUCR",
2142 SPR_NOACCESS, SPR_NOACCESS,
2143 &spr_read_generic, &spr_write_generic,
2144 0x00000000);
2145 }
2146
2147 /* SPR shared between PowerPC 40x implementations */
2148 static void gen_spr_40x(CPUPPCState *env)
2149 {
2150 /* Cache */
2151 /* not emulated, as QEMU do not emulate caches */
2152 spr_register(env, SPR_40x_DCCR, "DCCR",
2153 SPR_NOACCESS, SPR_NOACCESS,
2154 &spr_read_generic, &spr_write_generic,
2155 0x00000000);
2156 /* not emulated, as QEMU do not emulate caches */
2157 spr_register(env, SPR_40x_ICCR, "ICCR",
2158 SPR_NOACCESS, SPR_NOACCESS,
2159 &spr_read_generic, &spr_write_generic,
2160 0x00000000);
2161 /* not emulated, as QEMU do not emulate caches */
2162 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
2163 SPR_NOACCESS, SPR_NOACCESS,
2164 &spr_read_generic, SPR_NOACCESS,
2165 0x00000000);
2166 /* Exception */
2167 spr_register(env, SPR_40x_DEAR, "DEAR",
2168 SPR_NOACCESS, SPR_NOACCESS,
2169 &spr_read_generic, &spr_write_generic,
2170 0x00000000);
2171 spr_register(env, SPR_40x_ESR, "ESR",
2172 SPR_NOACCESS, SPR_NOACCESS,
2173 &spr_read_generic, &spr_write_generic,
2174 0x00000000);
2175 spr_register(env, SPR_40x_EVPR, "EVPR",
2176 SPR_NOACCESS, SPR_NOACCESS,
2177 &spr_read_generic, &spr_write_excp_prefix,
2178 0x00000000);
2179 spr_register(env, SPR_40x_SRR2, "SRR2",
2180 &spr_read_generic, &spr_write_generic,
2181 &spr_read_generic, &spr_write_generic,
2182 0x00000000);
2183 spr_register(env, SPR_40x_SRR3, "SRR3",
2184 &spr_read_generic, &spr_write_generic,
2185 &spr_read_generic, &spr_write_generic,
2186 0x00000000);
2187 /* Timers */
2188 spr_register(env, SPR_40x_PIT, "PIT",
2189 SPR_NOACCESS, SPR_NOACCESS,
2190 &spr_read_40x_pit, &spr_write_40x_pit,
2191 0x00000000);
2192 spr_register(env, SPR_40x_TCR, "TCR",
2193 SPR_NOACCESS, SPR_NOACCESS,
2194 &spr_read_generic, &spr_write_booke_tcr,
2195 0x00000000);
2196 spr_register(env, SPR_40x_TSR, "TSR",
2197 SPR_NOACCESS, SPR_NOACCESS,
2198 &spr_read_generic, &spr_write_booke_tsr,
2199 0x00000000);
2200 }
2201
2202 /* SPR specific to PowerPC 405 implementation */
2203 static void gen_spr_405(CPUPPCState *env)
2204 {
2205 /* MMU */
2206 spr_register(env, SPR_40x_PID, "PID",
2207 SPR_NOACCESS, SPR_NOACCESS,
2208 &spr_read_generic, &spr_write_generic,
2209 0x00000000);
2210 spr_register(env, SPR_4xx_CCR0, "CCR0",
2211 SPR_NOACCESS, SPR_NOACCESS,
2212 &spr_read_generic, &spr_write_generic,
2213 0x00700000);
2214 /* Debug interface */
2215 /* XXX : not implemented */
2216 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2217 SPR_NOACCESS, SPR_NOACCESS,
2218 &spr_read_generic, &spr_write_40x_dbcr0,
2219 0x00000000);
2220 /* XXX : not implemented */
2221 spr_register(env, SPR_405_DBCR1, "DBCR1",
2222 SPR_NOACCESS, SPR_NOACCESS,
2223 &spr_read_generic, &spr_write_generic,
2224 0x00000000);
2225 /* XXX : not implemented */
2226 spr_register(env, SPR_40x_DBSR, "DBSR",
2227 SPR_NOACCESS, SPR_NOACCESS,
2228 &spr_read_generic, &spr_write_clear,
2229 /* Last reset was system reset */
2230 0x00000300);
2231 /* XXX : not implemented */
2232 spr_register(env, SPR_40x_DAC1, "DAC1",
2233 SPR_NOACCESS, SPR_NOACCESS,
2234 &spr_read_generic, &spr_write_generic,
2235 0x00000000);
2236 spr_register(env, SPR_40x_DAC2, "DAC2",
2237 SPR_NOACCESS, SPR_NOACCESS,
2238 &spr_read_generic, &spr_write_generic,
2239 0x00000000);
2240 /* XXX : not implemented */
2241 spr_register(env, SPR_405_DVC1, "DVC1",
2242 SPR_NOACCESS, SPR_NOACCESS,
2243 &spr_read_generic, &spr_write_generic,
2244 0x00000000);
2245 /* XXX : not implemented */
2246 spr_register(env, SPR_405_DVC2, "DVC2",
2247 SPR_NOACCESS, SPR_NOACCESS,
2248 &spr_read_generic, &spr_write_generic,
2249 0x00000000);
2250 /* XXX : not implemented */
2251 spr_register(env, SPR_40x_IAC1, "IAC1",
2252 SPR_NOACCESS, SPR_NOACCESS,
2253 &spr_read_generic, &spr_write_generic,
2254 0x00000000);
2255 spr_register(env, SPR_40x_IAC2, "IAC2",
2256 SPR_NOACCESS, SPR_NOACCESS,
2257 &spr_read_generic, &spr_write_generic,
2258 0x00000000);
2259 /* XXX : not implemented */
2260 spr_register(env, SPR_405_IAC3, "IAC3",
2261 SPR_NOACCESS, SPR_NOACCESS,
2262 &spr_read_generic, &spr_write_generic,
2263 0x00000000);
2264 /* XXX : not implemented */
2265 spr_register(env, SPR_405_IAC4, "IAC4",
2266 SPR_NOACCESS, SPR_NOACCESS,
2267 &spr_read_generic, &spr_write_generic,
2268 0x00000000);
2269 /* Storage control */
2270 /* XXX: TODO: not implemented */
2271 spr_register(env, SPR_405_SLER, "SLER",
2272 SPR_NOACCESS, SPR_NOACCESS,
2273 &spr_read_generic, &spr_write_40x_sler,
2274 0x00000000);
2275 spr_register(env, SPR_40x_ZPR, "ZPR",
2276 SPR_NOACCESS, SPR_NOACCESS,
2277 &spr_read_generic, &spr_write_generic,
2278 0x00000000);
2279 /* XXX : not implemented */
2280 spr_register(env, SPR_405_SU0R, "SU0R",
2281 SPR_NOACCESS, SPR_NOACCESS,
2282 &spr_read_generic, &spr_write_generic,
2283 0x00000000);
2284 /* SPRG */
2285 spr_register(env, SPR_USPRG0, "USPRG0",
2286 &spr_read_ureg, SPR_NOACCESS,
2287 &spr_read_ureg, SPR_NOACCESS,
2288 0x00000000);
2289 spr_register(env, SPR_SPRG4, "SPRG4",
2290 SPR_NOACCESS, SPR_NOACCESS,
2291 &spr_read_generic, &spr_write_generic,
2292 0x00000000);
2293 spr_register(env, SPR_SPRG5, "SPRG5",
2294 SPR_NOACCESS, SPR_NOACCESS,
2295 spr_read_generic, &spr_write_generic,
2296 0x00000000);
2297 spr_register(env, SPR_SPRG6, "SPRG6",
2298 SPR_NOACCESS, SPR_NOACCESS,
2299 spr_read_generic, &spr_write_generic,
2300 0x00000000);
2301 spr_register(env, SPR_SPRG7, "SPRG7",
2302 SPR_NOACCESS, SPR_NOACCESS,
2303 spr_read_generic, &spr_write_generic,
2304 0x00000000);
2305 gen_spr_usprgh(env);
2306 }
2307
2308 /* SPR shared between PowerPC 401 & 403 implementations */
2309 static void gen_spr_401_403(CPUPPCState *env)
2310 {
2311 /* Time base */
2312 spr_register(env, SPR_403_VTBL, "TBL",
2313 &spr_read_tbl, SPR_NOACCESS,
2314 &spr_read_tbl, SPR_NOACCESS,
2315 0x00000000);
2316 spr_register(env, SPR_403_TBL, "TBL",
2317 SPR_NOACCESS, SPR_NOACCESS,
2318 SPR_NOACCESS, &spr_write_tbl,
2319 0x00000000);
2320 spr_register(env, SPR_403_VTBU, "TBU",
2321 &spr_read_tbu, SPR_NOACCESS,
2322 &spr_read_tbu, SPR_NOACCESS,
2323 0x00000000);
2324 spr_register(env, SPR_403_TBU, "TBU",
2325 SPR_NOACCESS, SPR_NOACCESS,
2326 SPR_NOACCESS, &spr_write_tbu,
2327 0x00000000);
2328 /* Debug */
2329 /* not emulated, as QEMU do not emulate caches */
2330 spr_register(env, SPR_403_CDBCR, "CDBCR",
2331 SPR_NOACCESS, SPR_NOACCESS,
2332 &spr_read_generic, &spr_write_generic,
2333 0x00000000);
2334 }
2335
2336 /* SPR specific to PowerPC 401 implementation */
2337 static void gen_spr_401(CPUPPCState *env)
2338 {
2339 /* Debug interface */
2340 /* XXX : not implemented */
2341 spr_register(env, SPR_40x_DBCR0, "DBCR",
2342 SPR_NOACCESS, SPR_NOACCESS,
2343 &spr_read_generic, &spr_write_40x_dbcr0,
2344 0x00000000);
2345 /* XXX : not implemented */
2346 spr_register(env, SPR_40x_DBSR, "DBSR",
2347 SPR_NOACCESS, SPR_NOACCESS,
2348 &spr_read_generic, &spr_write_clear,
2349 /* Last reset was system reset */
2350 0x00000300);
2351 /* XXX : not implemented */
2352 spr_register(env, SPR_40x_DAC1, "DAC",
2353 SPR_NOACCESS, SPR_NOACCESS,
2354 &spr_read_generic, &spr_write_generic,
2355 0x00000000);
2356 /* XXX : not implemented */
2357 spr_register(env, SPR_40x_IAC1, "IAC",
2358 SPR_NOACCESS, SPR_NOACCESS,
2359 &spr_read_generic, &spr_write_generic,
2360 0x00000000);
2361 /* Storage control */
2362 /* XXX: TODO: not implemented */
2363 spr_register(env, SPR_405_SLER, "SLER",
2364 SPR_NOACCESS, SPR_NOACCESS,
2365 &spr_read_generic, &spr_write_40x_sler,
2366 0x00000000);
2367 /* not emulated, as QEMU never does speculative access */
2368 spr_register(env, SPR_40x_SGR, "SGR",
2369 SPR_NOACCESS, SPR_NOACCESS,
2370 &spr_read_generic, &spr_write_generic,
2371 0xFFFFFFFF);
2372 /* not emulated, as QEMU do not emulate caches */
2373 spr_register(env, SPR_40x_DCWR, "DCWR",
2374 SPR_NOACCESS, SPR_NOACCESS,
2375 &spr_read_generic, &spr_write_generic,
2376 0x00000000);
2377 }
2378
2379 static void gen_spr_401x2(CPUPPCState *env)
2380 {
2381 gen_spr_401(env);
2382 spr_register(env, SPR_40x_PID, "PID",
2383 SPR_NOACCESS, SPR_NOACCESS,
2384 &spr_read_generic, &spr_write_generic,
2385 0x00000000);
2386 spr_register(env, SPR_40x_ZPR, "ZPR",
2387 SPR_NOACCESS, SPR_NOACCESS,
2388 &spr_read_generic, &spr_write_generic,
2389 0x00000000);
2390 }
2391
2392 /* SPR specific to PowerPC 403 implementation */
2393 static void gen_spr_403(CPUPPCState *env)
2394 {
2395 /* Debug interface */
2396 /* XXX : not implemented */
2397 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2398 SPR_NOACCESS, SPR_NOACCESS,
2399 &spr_read_generic, &spr_write_40x_dbcr0,
2400 0x00000000);
2401 /* XXX : not implemented */
2402 spr_register(env, SPR_40x_DBSR, "DBSR",
2403 SPR_NOACCESS, SPR_NOACCESS,
2404 &spr_read_generic, &spr_write_clear,
2405 /* Last reset was system reset */
2406 0x00000300);
2407 /* XXX : not implemented */
2408 spr_register(env, SPR_40x_DAC1, "DAC1",
2409 SPR_NOACCESS, SPR_NOACCESS,
2410 &spr_read_generic, &spr_write_generic,
2411 0x00000000);
2412 /* XXX : not implemented */
2413 spr_register(env, SPR_40x_DAC2, "DAC2",
2414 SPR_NOACCESS, SPR_NOACCESS,
2415 &spr_read_generic, &spr_write_generic,
2416 0x00000000);
2417 /* XXX : not implemented */
2418 spr_register(env, SPR_40x_IAC1, "IAC1",
2419 SPR_NOACCESS, SPR_NOACCESS,
2420 &spr_read_generic, &spr_write_generic,
2421 0x00000000);
2422 /* XXX : not implemented */
2423 spr_register(env, SPR_40x_IAC2, "IAC2",
2424 SPR_NOACCESS, SPR_NOACCESS,
2425 &spr_read_generic, &spr_write_generic,
2426 0x00000000);
2427 }
2428
2429 static void gen_spr_403_real(CPUPPCState *env)
2430 {
2431 spr_register(env, SPR_403_PBL1, "PBL1",
2432 SPR_NOACCESS, SPR_NOACCESS,
2433 &spr_read_403_pbr, &spr_write_403_pbr,
2434 0x00000000);
2435 spr_register(env, SPR_403_PBU1, "PBU1",
2436 SPR_NOACCESS, SPR_NOACCESS,
2437 &spr_read_403_pbr, &spr_write_403_pbr,
2438 0x00000000);
2439 spr_register(env, SPR_403_PBL2, "PBL2",
2440 SPR_NOACCESS, SPR_NOACCESS,
2441 &spr_read_403_pbr, &spr_write_403_pbr,
2442 0x00000000);
2443 spr_register(env, SPR_403_PBU2, "PBU2",
2444 SPR_NOACCESS, SPR_NOACCESS,
2445 &spr_read_403_pbr, &spr_write_403_pbr,
2446 0x00000000);
2447 }
2448
2449 static void gen_spr_403_mmu(CPUPPCState *env)
2450 {
2451 /* MMU */
2452 spr_register(env, SPR_40x_PID, "PID",
2453 SPR_NOACCESS, SPR_NOACCESS,
2454 &spr_read_generic, &spr_write_generic,
2455 0x00000000);
2456 spr_register(env, SPR_40x_ZPR, "ZPR",
2457 SPR_NOACCESS, SPR_NOACCESS,
2458 &spr_read_generic, &spr_write_generic,
2459 0x00000000);
2460 }
2461
2462 /* SPR specific to PowerPC compression coprocessor extension */
2463 static void gen_spr_compress(CPUPPCState *env)
2464 {
2465 /* XXX : not implemented */
2466 spr_register(env, SPR_401_SKR, "SKR",
2467 SPR_NOACCESS, SPR_NOACCESS,
2468 &spr_read_generic, &spr_write_generic,
2469 0x00000000);
2470 }
2471
2472 static void gen_spr_5xx_8xx(CPUPPCState *env)
2473 {
2474 /* Exception processing */
2475 spr_register_kvm(env, SPR_DSISR, "DSISR",
2476 SPR_NOACCESS, SPR_NOACCESS,
2477 &spr_read_generic, &spr_write_generic,
2478 KVM_REG_PPC_DSISR, 0x00000000);
2479 spr_register_kvm(env, SPR_DAR, "DAR",
2480 SPR_NOACCESS, SPR_NOACCESS,
2481 &spr_read_generic, &spr_write_generic,
2482 KVM_REG_PPC_DAR, 0x00000000);
2483 /* Timer */
2484 spr_register(env, SPR_DECR, "DECR",
2485 SPR_NOACCESS, SPR_NOACCESS,
2486 &spr_read_decr, &spr_write_decr,
2487 0x00000000);
2488 /* XXX : not implemented */
2489 spr_register(env, SPR_MPC_EIE, "EIE",
2490 SPR_NOACCESS, SPR_NOACCESS,
2491 &spr_read_generic, &spr_write_generic,
2492 0x00000000);
2493 /* XXX : not implemented */
2494 spr_register(env, SPR_MPC_EID, "EID",
2495 SPR_NOACCESS, SPR_NOACCESS,
2496 &spr_read_generic, &spr_write_generic,
2497 0x00000000);
2498 /* XXX : not implemented */
2499 spr_register(env, SPR_MPC_NRI, "NRI",
2500 SPR_NOACCESS, SPR_NOACCESS,
2501 &spr_read_generic, &spr_write_generic,
2502 0x00000000);
2503 /* XXX : not implemented */
2504 spr_register(env, SPR_MPC_CMPA, "CMPA",
2505 SPR_NOACCESS, SPR_NOACCESS,
2506 &spr_read_generic, &spr_write_generic,
2507 0x00000000);
2508 /* XXX : not implemented */
2509 spr_register(env, SPR_MPC_CMPB, "CMPB",
2510 SPR_NOACCESS, SPR_NOACCESS,
2511 &spr_read_generic, &spr_write_generic,
2512 0x00000000);
2513 /* XXX : not implemented */
2514 spr_register(env, SPR_MPC_CMPC, "CMPC",
2515 SPR_NOACCESS, SPR_NOACCESS,
2516 &spr_read_generic, &spr_write_generic,
2517 0x00000000);
2518 /* XXX : not implemented */
2519 spr_register(env, SPR_MPC_CMPD, "CMPD",
2520 SPR_NOACCESS, SPR_NOACCESS,
2521 &spr_read_generic, &spr_write_generic,
2522 0x00000000);
2523 /* XXX : not implemented */
2524 spr_register(env, SPR_MPC_ECR, "ECR",
2525 SPR_NOACCESS, SPR_NOACCESS,
2526 &spr_read_generic, &spr_write_generic,
2527 0x00000000);
2528 /* XXX : not implemented */
2529 spr_register(env, SPR_MPC_DER, "DER",
2530 SPR_NOACCESS, SPR_NOACCESS,
2531 &spr_read_generic, &spr_write_generic,
2532 0x00000000);
2533 /* XXX : not implemented */
2534 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2535 SPR_NOACCESS, SPR_NOACCESS,
2536 &spr_read_generic, &spr_write_generic,
2537 0x00000000);
2538 /* XXX : not implemented */
2539 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2540 SPR_NOACCESS, SPR_NOACCESS,
2541 &spr_read_generic, &spr_write_generic,
2542 0x00000000);
2543 /* XXX : not implemented */
2544 spr_register(env, SPR_MPC_CMPE, "CMPE",
2545 SPR_NOACCESS, SPR_NOACCESS,
2546 &spr_read_generic, &spr_write_generic,
2547 0x00000000);
2548 /* XXX : not implemented */
2549 spr_register(env, SPR_MPC_CMPF, "CMPF",
2550 SPR_NOACCESS, SPR_NOACCESS,
2551 &spr_read_generic, &spr_write_generic,
2552 0x00000000);
2553 /* XXX : not implemented */
2554 spr_register(env, SPR_MPC_CMPG, "CMPG",
2555 SPR_NOACCESS, SPR_NOACCESS,
2556 &spr_read_generic, &spr_write_generic,
2557 0x00000000);
2558 /* XXX : not implemented */
2559 spr_register(env, SPR_MPC_CMPH, "CMPH",
2560 SPR_NOACCESS, SPR_NOACCESS,
2561 &spr_read_generic, &spr_write_generic,
2562 0x00000000);
2563 /* XXX : not implemented */
2564 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2565 SPR_NOACCESS, SPR_NOACCESS,
2566 &spr_read_generic, &spr_write_generic,
2567 0x00000000);
2568 /* XXX : not implemented */
2569 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2570 SPR_NOACCESS, SPR_NOACCESS,
2571 &spr_read_generic, &spr_write_generic,
2572 0x00000000);
2573 /* XXX : not implemented */
2574 spr_register(env, SPR_MPC_BAR, "BAR",
2575 SPR_NOACCESS, SPR_NOACCESS,
2576 &spr_read_generic, &spr_write_generic,
2577 0x00000000);
2578 /* XXX : not implemented */
2579 spr_register(env, SPR_MPC_DPDR, "DPDR",
2580 SPR_NOACCESS, SPR_NOACCESS,
2581 &spr_read_generic, &spr_write_generic,
2582 0x00000000);
2583 /* XXX : not implemented */
2584 spr_register(env, SPR_MPC_IMMR, "IMMR",
2585 SPR_NOACCESS, SPR_NOACCESS,
2586 &spr_read_generic, &spr_write_generic,
2587 0x00000000);
2588 }
2589
2590 static void gen_spr_5xx(CPUPPCState *env)
2591 {
2592 /* XXX : not implemented */
2593 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2594 SPR_NOACCESS, SPR_NOACCESS,
2595 &spr_read_generic, &spr_write_generic,
2596 0x00000000);
2597 /* XXX : not implemented */
2598 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2599 SPR_NOACCESS, SPR_NOACCESS,
2600 &spr_read_generic, &spr_write_generic,
2601 0x00000000);
2602 /* XXX : not implemented */
2603 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2604 SPR_NOACCESS, SPR_NOACCESS,
2605 &spr_read_generic, &spr_write_generic,
2606 0x00000000);
2607 /* XXX : not implemented */
2608 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2609 SPR_NOACCESS, SPR_NOACCESS,
2610 &spr_read_generic, &spr_write_generic,
2611 0x00000000);
2612 /* XXX : not implemented */
2613 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2614 SPR_NOACCESS, SPR_NOACCESS,
2615 &spr_read_generic, &spr_write_generic,
2616 0x00000000);
2617 /* XXX : not implemented */
2618 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2619 SPR_NOACCESS, SPR_NOACCESS,
2620 &spr_read_generic, &spr_write_generic,
2621 0x00000000);
2622 /* XXX : not implemented */
2623 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2624 SPR_NOACCESS, SPR_NOACCESS,
2625 &spr_read_generic, &spr_write_generic,
2626 0x00000000);
2627 /* XXX : not implemented */
2628 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2629 SPR_NOACCESS, SPR_NOACCESS,
2630 &spr_read_generic, &spr_write_generic,
2631 0x00000000);
2632 /* XXX : not implemented */
2633 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2634 SPR_NOACCESS, SPR_NOACCESS,
2635 &spr_read_generic, &spr_write_generic,
2636 0x00000000);
2637 /* XXX : not implemented */
2638 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2639 SPR_NOACCESS, SPR_NOACCESS,
2640 &spr_read_generic, &spr_write_generic,
2641 0x00000000);
2642 /* XXX : not implemented */
2643 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2644 SPR_NOACCESS, SPR_NOACCESS,
2645 &spr_read_generic, &spr_write_generic,
2646 0x00000000);
2647 /* XXX : not implemented */
2648 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2649 SPR_NOACCESS, SPR_NOACCESS,
2650 &spr_read_generic, &spr_write_generic,
2651 0x00000000);
2652 /* XXX : not implemented */
2653 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2654 SPR_NOACCESS, SPR_NOACCESS,
2655 &spr_read_generic, &spr_write_generic,
2656 0x00000000);
2657 /* XXX : not implemented */
2658 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2659 SPR_NOACCESS, SPR_NOACCESS,
2660 &spr_read_generic, &spr_write_generic,
2661 0x00000000);
2662 /* XXX : not implemented */
2663 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2664 SPR_NOACCESS, SPR_NOACCESS,
2665 &spr_read_generic, &spr_write_generic,
2666 0x00000000);
2667 /* XXX : not implemented */
2668 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2669 SPR_NOACCESS, SPR_NOACCESS,
2670 &spr_read_generic, &spr_write_generic,
2671 0x00000000);
2672 /* XXX : not implemented */
2673 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2674 SPR_NOACCESS, SPR_NOACCESS,
2675 &spr_read_generic, &spr_write_generic,
2676 0x00000000);
2677 /* XXX : not implemented */
2678 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2679 SPR_NOACCESS, SPR_NOACCESS,
2680 &spr_read_generic, &spr_write_generic,
2681 0x00000000);
2682 /* XXX : not implemented */
2683 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2684 SPR_NOACCESS, SPR_NOACCESS,
2685 &spr_read_generic, &spr_write_generic,
2686 0x00000000);
2687 /* XXX : not implemented */
2688 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2689 SPR_NOACCESS, SPR_NOACCESS,
2690 &spr_read_generic, &spr_write_generic,
2691 0x00000000);
2692 /* XXX : not implemented */
2693 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2694 SPR_NOACCESS, SPR_NOACCESS,
2695 &spr_read_generic, &spr_write_generic,
2696 0x00000000);
2697 }
2698
2699 static void gen_spr_8xx(CPUPPCState *env)
2700 {
2701 /* XXX : not implemented */
2702 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2703 SPR_NOACCESS, SPR_NOACCESS,
2704 &spr_read_generic, &spr_write_generic,
2705 0x00000000);
2706 /* XXX : not implemented */
2707 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2708 SPR_NOACCESS, SPR_NOACCESS,
2709 &spr_read_generic, &spr_write_generic,
2710 0x00000000);
2711 /* XXX : not implemented */
2712 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2713 SPR_NOACCESS, SPR_NOACCESS,
2714 &spr_read_generic, &spr_write_generic,
2715 0x00000000);
2716 /* XXX : not implemented */
2717 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2718 SPR_NOACCESS, SPR_NOACCESS,
2719 &spr_read_generic, &spr_write_generic,
2720 0x00000000);
2721 /* XXX : not implemented */
2722 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2723 SPR_NOACCESS, SPR_NOACCESS,
2724 &spr_read_generic, &spr_write_generic,
2725 0x00000000);
2726 /* XXX : not implemented */
2727 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2728 SPR_NOACCESS, SPR_NOACCESS,
2729 &spr_read_generic, &spr_write_generic,
2730 0x00000000);
2731 /* XXX : not implemented */
2732 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2733 SPR_NOACCESS, SPR_NOACCESS,
2734 &spr_read_generic, &spr_write_generic,
2735 0x00000000);
2736 /* XXX : not implemented */
2737 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2738 SPR_NOACCESS, SPR_NOACCESS,
2739 &spr_read_generic, &spr_write_generic,
2740 0x00000000);
2741 /* XXX : not implemented */
2742 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2743 SPR_NOACCESS, SPR_NOACCESS,
2744 &spr_read_generic, &spr_write_generic,
2745 0x00000000);
2746 /* XXX : not implemented */
2747 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2748 SPR_NOACCESS, SPR_NOACCESS,
2749 &spr_read_generic, &spr_write_generic,
2750 0x00000000);
2751 /* XXX : not implemented */
2752 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2753 SPR_NOACCESS, SPR_NOACCESS,
2754 &spr_read_generic, &spr_write_generic,
2755 0x00000000);
2756 /* XXX : not implemented */
2757 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2758 SPR_NOACCESS, SPR_NOACCESS,
2759 &spr_read_generic, &spr_write_generic,
2760 0x00000000);
2761 /* XXX : not implemented */
2762 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2763 SPR_NOACCESS, SPR_NOACCESS,
2764 &spr_read_generic, &spr_write_generic,
2765 0x00000000);
2766 /* XXX : not implemented */
2767 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2768 SPR_NOACCESS, SPR_NOACCESS,
2769 &spr_read_generic, &spr_write_generic,
2770 0x00000000);
2771 /* XXX : not implemented */
2772 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2773 SPR_NOACCESS, SPR_NOACCESS,
2774 &spr_read_generic, &spr_write_generic,
2775 0x00000000);
2776 /* XXX : not implemented */
2777 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2778 SPR_NOACCESS, SPR_NOACCESS,
2779 &spr_read_generic, &spr_write_generic,
2780 0x00000000);
2781 /* XXX : not implemented */
2782 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2783 SPR_NOACCESS, SPR_NOACCESS,
2784 &spr_read_generic, &spr_write_generic,
2785 0x00000000);
2786 /* XXX : not implemented */
2787 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2788 SPR_NOACCESS, SPR_NOACCESS,
2789 &spr_read_generic, &spr_write_generic,
2790 0x00000000);
2791 /* XXX : not implemented */
2792 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2793 SPR_NOACCESS, SPR_NOACCESS,
2794 &spr_read_generic, &spr_write_generic,
2795 0x00000000);
2796 /* XXX : not implemented */
2797 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2798 SPR_NOACCESS, SPR_NOACCESS,
2799 &spr_read_generic, &spr_write_generic,
2800 0x00000000);
2801 /* XXX : not implemented */
2802 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2803 SPR_NOACCESS, SPR_NOACCESS,
2804 &spr_read_generic, &spr_write_generic,
2805 0x00000000);
2806 /* XXX : not implemented */
2807 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2808 SPR_NOACCESS, SPR_NOACCESS,
2809 &spr_read_generic, &spr_write_generic,
2810 0x00000000);
2811 /* XXX : not implemented */
2812 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2813 SPR_NOACCESS, SPR_NOACCESS,
2814 &spr_read_generic, &spr_write_generic,
2815 0x00000000);
2816 /* XXX : not implemented */
2817 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2818 SPR_NOACCESS, SPR_NOACCESS,
2819 &spr_read_generic, &spr_write_generic,
2820 0x00000000);
2821 /* XXX : not implemented */
2822 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2823 SPR_NOACCESS, SPR_NOACCESS,
2824 &spr_read_generic, &spr_write_generic,
2825 0x00000000);
2826 }
2827
2828 /*
2829 * AMR => SPR 29 (Power 2.04)
2830 * CTRL => SPR 136 (Power 2.04)
2831 * CTRL => SPR 152 (Power 2.04)
2832 * SCOMC => SPR 276 (64 bits ?)
2833 * SCOMD => SPR 277 (64 bits ?)
2834 * TBU40 => SPR 286 (Power 2.04 hypv)
2835 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2836 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2837 * HDSISR => SPR 306 (Power 2.04 hypv)
2838 * HDAR => SPR 307 (Power 2.04 hypv)
2839 * PURR => SPR 309 (Power 2.04 hypv)
2840 * HDEC => SPR 310 (Power 2.04 hypv)
2841 * HIOR => SPR 311 (hypv)
2842 * RMOR => SPR 312 (970)
2843 * HRMOR => SPR 313 (Power 2.04 hypv)
2844 * HSRR0 => SPR 314 (Power 2.04 hypv)
2845 * HSRR1 => SPR 315 (Power 2.04 hypv)
2846 * LPIDR => SPR 317 (970)
2847 * EPR => SPR 702 (Power 2.04 emb)
2848 * perf => 768-783 (Power 2.04)
2849 * perf => 784-799 (Power 2.04)
2850 * PPR => SPR 896 (Power 2.04)
2851 * DABRX => 1015 (Power 2.04 hypv)
2852 * FPECR => SPR 1022 (?)
2853 * ... and more (thermal management, performance counters, ...)
2854 */
2855
2856 /*****************************************************************************/
2857 /* Exception vectors models */
2858 static void init_excp_4xx_real(CPUPPCState *env)
2859 {
2860 #if !defined(CONFIG_USER_ONLY)
2861 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2862 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2863 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2864 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2865 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2866 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2867 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2868 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2869 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2870 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2871 env->ivor_mask = 0x0000FFF0UL;
2872 env->ivpr_mask = 0xFFFF0000UL;
2873 /* Hardware reset vector */
2874 env->hreset_vector = 0xFFFFFFFCUL;
2875 #endif
2876 }
2877
2878 static void init_excp_4xx_softmmu(CPUPPCState *env)
2879 {
2880 #if !defined(CONFIG_USER_ONLY)
2881 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2882 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2883 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2884 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2885 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2886 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2887 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2888 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2889 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2890 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2891 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2892 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2893 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2894 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2895 env->ivor_mask = 0x0000FFF0UL;
2896 env->ivpr_mask = 0xFFFF0000UL;
2897 /* Hardware reset vector */
2898 env->hreset_vector = 0xFFFFFFFCUL;
2899 #endif
2900 }
2901
2902 static void init_excp_MPC5xx(CPUPPCState *env)
2903 {
2904 #if !defined(CONFIG_USER_ONLY)
2905 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2906 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2907 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2908 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2909 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2910 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2911 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2912 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2913 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2914 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2915 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2916 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2917 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2918 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2919 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2920 env->ivor_mask = 0x0000FFF0UL;
2921 env->ivpr_mask = 0xFFFF0000UL;
2922 /* Hardware reset vector */
2923 env->hreset_vector = 0x00000100UL;
2924 #endif
2925 }
2926
2927 static void init_excp_MPC8xx(CPUPPCState *env)
2928 {
2929 #if !defined(CONFIG_USER_ONLY)
2930 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2931 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2932 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2933 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2934 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2935 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2936 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2937 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2938 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2939 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2940 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2941 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2942 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2943 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2944 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2945 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2946 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2947 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2948 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2949 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2950 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2951 env->ivor_mask = 0x0000FFF0UL;
2952 env->ivpr_mask = 0xFFFF0000UL;
2953 /* Hardware reset vector */
2954 env->hreset_vector = 0x00000100UL;
2955 #endif
2956 }
2957
2958 static void init_excp_G2(CPUPPCState *env)
2959 {
2960 #if !defined(CONFIG_USER_ONLY)
2961 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2962 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2963 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2964 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2965 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2966 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2967 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2968 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2969 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2970 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2971 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2972 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2973 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2974 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2975 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2976 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2977 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2978 /* Hardware reset vector */
2979 env->hreset_vector = 0x00000100UL;
2980 #endif
2981 }
2982
2983 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
2984 {
2985 #if !defined(CONFIG_USER_ONLY)
2986 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2987 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2988 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2989 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2990 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2991 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2992 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2993 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2994 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2995 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2996 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2997 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2998 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2999 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
3000 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
3001 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
3002 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
3003 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
3004 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
3005 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
3006 env->ivor_mask = 0x0000FFF7UL;
3007 env->ivpr_mask = ivpr_mask;
3008 /* Hardware reset vector */
3009 env->hreset_vector = 0xFFFFFFFCUL;
3010 #endif
3011 }
3012
3013 static void init_excp_BookE(CPUPPCState *env)
3014 {
3015 #if !defined(CONFIG_USER_ONLY)
3016 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
3017 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
3018 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
3019 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
3020 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
3021 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
3022 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
3023 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
3024 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
3025 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
3026 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
3027 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
3028 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
3029 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
3030 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
3031 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
3032 env->ivor_mask = 0x0000FFF0UL;
3033 env->ivpr_mask = 0xFFFF0000UL;
3034 /* Hardware reset vector */
3035 env->hreset_vector = 0xFFFFFFFCUL;
3036 #endif
3037 }
3038
3039 static void init_excp_601(CPUPPCState *env)
3040 {
3041 #if !defined(CONFIG_USER_ONLY)
3042 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3043 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3044 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3045 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3046 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3047 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3048 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3049 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3050 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3051 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
3052 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3053 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
3054 /* Hardware reset vector */
3055 env->hreset_vector = 0x00000100UL;
3056 #endif
3057 }
3058
3059 static void init_excp_602(CPUPPCState *env)
3060 {
3061 #if !defined(CONFIG_USER_ONLY)
3062 /* XXX: exception prefix has a special behavior on 602 */
3063 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3064 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3065 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3066 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3067 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3068 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3069 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3070 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3071 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3072 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3073 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3074 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3075 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3076 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3077 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3078 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3079 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
3080 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
3081 /* Hardware reset vector */
3082 env->hreset_vector = 0x00000100UL;
3083 #endif
3084 }
3085
3086 static void init_excp_603(CPUPPCState *env)
3087 {
3088 #if !defined(CONFIG_USER_ONLY)
3089 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3090 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3091 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3092 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3093 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3094 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3095 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3096 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3097 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3098 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3099 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3100 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3101 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3102 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3103 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3104 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3105 /* Hardware reset vector */
3106 env->hreset_vector = 0x00000100UL;
3107 #endif
3108 }
3109
3110 static void init_excp_604(CPUPPCState *env)
3111 {
3112 #if !defined(CONFIG_USER_ONLY)
3113 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3114 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3115 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3116 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3117 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3118 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3119 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3120 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3121 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3122 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3123 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3124 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3125 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3126 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3127 /* Hardware reset vector */
3128 env->hreset_vector = 0x00000100UL;
3129 #endif
3130 }
3131
3132 static void init_excp_7x0(CPUPPCState *env)
3133 {
3134 #if !defined(CONFIG_USER_ONLY)
3135 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3136 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3137 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3138 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3139 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3140 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3141 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3142 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3143 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3144 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3145 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3146 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3147 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3148 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3149 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3150 /* Hardware reset vector */
3151 env->hreset_vector = 0x00000100UL;
3152 #endif
3153 }
3154
3155 static void init_excp_750cl(CPUPPCState *env)
3156 {
3157 #if !defined(CONFIG_USER_ONLY)
3158 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3159 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3160 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3161 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3162 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3163 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3164 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3165 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3166 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3167 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3168 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3169 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3170 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3171 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3172 /* Hardware reset vector */
3173 env->hreset_vector = 0x00000100UL;
3174 #endif
3175 }
3176
3177 static void init_excp_750cx(CPUPPCState *env)
3178 {
3179 #if !defined(CONFIG_USER_ONLY)
3180 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3181 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3182 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3183 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3184 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3185 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3186 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3187 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3188 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3189 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3190 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3191 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3192 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3193 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3194 /* Hardware reset vector */
3195 env->hreset_vector = 0x00000100UL;
3196 #endif
3197 }
3198
3199 /* XXX: Check if this is correct */
3200 static void init_excp_7x5(CPUPPCState *env)
3201 {
3202 #if !defined(CONFIG_USER_ONLY)
3203 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3204 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3205 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3206 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3207 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3208 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3209 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3210 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3211 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3212 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3213 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3214 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3215 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3216 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3217 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3218 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3219 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3220 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3221 /* Hardware reset vector */
3222 env->hreset_vector = 0x00000100UL;
3223 #endif
3224 }
3225
3226 static void init_excp_7400(CPUPPCState *env)
3227 {
3228 #if !defined(CONFIG_USER_ONLY)
3229 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3230 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3231 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3232 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3233 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3234 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3235 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3236 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3237 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3238 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3239 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3240 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3241 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3242 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3243 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3244 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3245 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3246 /* Hardware reset vector */
3247 env->hreset_vector = 0x00000100UL;
3248 #endif
3249 }
3250
3251 static void init_excp_7450(CPUPPCState *env)
3252 {
3253 #if !defined(CONFIG_USER_ONLY)
3254 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3255 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3256 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3257 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3258 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3259 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3260 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3261 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3262 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3263 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3264 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3265 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3266 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3267 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3268 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3269 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3270 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3271 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3272 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3273 /* Hardware reset vector */
3274 env->hreset_vector = 0x00000100UL;
3275 #endif
3276 }
3277
3278 #if defined(TARGET_PPC64)
3279 static void init_excp_970(CPUPPCState *env)
3280 {
3281 #if !defined(CONFIG_USER_ONLY)
3282 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3283 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3284 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3285 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3286 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3287 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3288 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3289 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3290 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3291 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3292 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3293 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3294 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3295 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3296 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3297 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3298 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3299 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3300 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3301 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3302 /* Hardware reset vector */
3303 env->hreset_vector = 0x0000000000000100ULL;
3304 #endif
3305 }
3306
3307 static void init_excp_POWER7(CPUPPCState *env)
3308 {
3309 #if !defined(CONFIG_USER_ONLY)
3310 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3311 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3312 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3313 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3314 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3315 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3316 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3317 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3318 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3319 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3320 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3321 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3322 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3323 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3324 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00;
3325 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20;
3326 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40;
3327 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60;
3328 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3329 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3330 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40;
3331 /* Hardware reset vector */
3332 env->hreset_vector = 0x0000000000000100ULL;
3333 #endif
3334 }
3335
3336 static void init_excp_POWER8(CPUPPCState *env)
3337 {
3338 init_excp_POWER7(env);
3339
3340 #if !defined(CONFIG_USER_ONLY)
3341 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00;
3342 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60;
3343 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80;
3344 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80;
3345 #endif
3346 }
3347
3348 static void init_excp_POWER9(CPUPPCState *env)
3349 {
3350 init_excp_POWER8(env);
3351
3352 #if !defined(CONFIG_USER_ONLY)
3353 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0;
3354 #endif
3355 }
3356
3357 #endif
3358
3359 /*****************************************************************************/
3360 /* Power management enable checks */
3361 static int check_pow_none(CPUPPCState *env)
3362 {
3363 return 0;
3364 }
3365
3366 static int check_pow_nocheck(CPUPPCState *env)
3367 {
3368 return 1;
3369 }
3370
3371 static int check_pow_hid0(CPUPPCState *env)
3372 {
3373 if (env->spr[SPR_HID0] & 0x00E00000) {
3374 return 1;
3375 }
3376
3377 return 0;
3378 }
3379
3380 static int check_pow_hid0_74xx(CPUPPCState *env)
3381 {
3382 if (env->spr[SPR_HID0] & 0x00600000) {
3383 return 1;
3384 }
3385
3386 return 0;
3387 }
3388
3389 static bool ppc_cpu_interrupts_big_endian_always(PowerPCCPU *cpu)
3390 {
3391 return true;
3392 }
3393
3394 #ifdef TARGET_PPC64
3395 static bool ppc_cpu_interrupts_big_endian_lpcr(PowerPCCPU *cpu)
3396 {
3397 return !(cpu->env.spr[SPR_LPCR] & LPCR_ILE);
3398 }
3399 #endif
3400
3401 /*****************************************************************************/
3402 /* PowerPC implementations definitions */
3403
3404 #define POWERPC_FAMILY(_name) \
3405 static void \
3406 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
3407 \
3408 static const TypeInfo \
3409 glue(glue(ppc_, _name), _cpu_family_type_info) = { \
3410 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
3411 .parent = TYPE_POWERPC_CPU, \
3412 .abstract = true, \
3413 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
3414 }; \
3415 \
3416 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
3417 { \
3418 type_register_static( \
3419 &glue(glue(ppc_, _name), _cpu_family_type_info)); \
3420 } \
3421 \
3422 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
3423 \
3424 static void glue(glue(ppc_, _name), _cpu_family_class_init)
3425
3426 static void init_proc_401(CPUPPCState *env)
3427 {
3428 gen_spr_40x(env);
3429 gen_spr_401_403(env);
3430 gen_spr_401(env);
3431 init_excp_4xx_real(env);
3432 env->dcache_line_size = 32;
3433 env->icache_line_size = 32;
3434 /* Allocate hardware IRQ controller */
3435 ppc40x_irq_init(ppc_env_get_cpu(env));
3436
3437 SET_FIT_PERIOD(12, 16, 20, 24);
3438 SET_WDT_PERIOD(16, 20, 24, 28);
3439 }
3440
3441 POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
3442 {
3443 DeviceClass *dc = DEVICE_CLASS(oc);
3444 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3445
3446 dc->desc = "PowerPC 401";
3447 pcc->init_proc = init_proc_401;
3448 pcc->check_pow = check_pow_nocheck;
3449 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3450 PPC_WRTEE | PPC_DCR |
3451 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3452 PPC_CACHE_DCBZ |
3453 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3454 PPC_4xx_COMMON | PPC_40x_EXCP;
3455 pcc->msr_mask = (1ull << MSR_KEY) |
3456 (1ull << MSR_POW) |
3457 (1ull << MSR_CE) |
3458 (1ull << MSR_ILE) |
3459 (1ull << MSR_EE) |
3460 (1ull << MSR_PR) |
3461 (1ull << MSR_ME) |
3462 (1ull << MSR_DE) |
3463 (1ull << MSR_LE);
3464 pcc->mmu_model = POWERPC_MMU_REAL;
3465 pcc->excp_model = POWERPC_EXCP_40x;
3466 pcc->bus_model = PPC_FLAGS_INPUT_401;
3467 pcc->bfd_mach = bfd_mach_ppc_403;
3468 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3469 POWERPC_FLAG_BUS_CLK;
3470 }
3471
3472 static void init_proc_401x2(CPUPPCState *env)
3473 {
3474 gen_spr_40x(env);
3475 gen_spr_401_403(env);
3476 gen_spr_401x2(env);
3477 gen_spr_compress(env);
3478 /* Memory management */
3479 #if !defined(CONFIG_USER_ONLY)
3480 env->nb_tlb = 64;
3481 env->nb_ways = 1;
3482 env->id_tlbs = 0;
3483 env->tlb_type = TLB_EMB;
3484 #endif
3485 init_excp_4xx_softmmu(env);
3486 env->dcache_line_size = 32;
3487 env->icache_line_size = 32;
3488 /* Allocate hardware IRQ controller */
3489 ppc40x_irq_init(ppc_env_get_cpu(env));
3490
3491 SET_FIT_PERIOD(12, 16, 20, 24);
3492 SET_WDT_PERIOD(16, 20, 24, 28);
3493 }
3494
3495 POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
3496 {
3497 DeviceClass *dc = DEVICE_CLASS(oc);
3498 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3499
3500 dc->desc = "PowerPC 401x2";
3501 pcc->init_proc = init_proc_401x2;
3502 pcc->check_pow = check_pow_nocheck;
3503 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3504 PPC_DCR | PPC_WRTEE |
3505 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3506 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3507 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3508 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3509 PPC_4xx_COMMON | PPC_40x_EXCP;
3510 pcc->msr_mask = (1ull << 20) |
3511 (1ull << MSR_KEY) |
3512 (1ull << MSR_POW) |
3513 (1ull << MSR_CE) |
3514 (1ull << MSR_ILE) |
3515 (1ull << MSR_EE) |
3516 (1ull << MSR_PR) |
3517 (1ull << MSR_ME) |
3518 (1ull << MSR_DE) |
3519 (1ull << MSR_IR) |
3520 (1ull << MSR_DR) |
3521 (1ull << MSR_LE);
3522 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3523 pcc->excp_model = POWERPC_EXCP_40x;
3524 pcc->bus_model = PPC_FLAGS_INPUT_401;
3525 pcc->bfd_mach = bfd_mach_ppc_403;
3526 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3527 POWERPC_FLAG_BUS_CLK;
3528 }
3529
3530 static void init_proc_401x3(CPUPPCState *env)
3531 {
3532 gen_spr_40x(env);
3533 gen_spr_401_403(env);
3534 gen_spr_401(env);
3535 gen_spr_401x2(env);
3536 gen_spr_compress(env);
3537 init_excp_4xx_softmmu(env);
3538 env->dcache_line_size = 32;
3539 env->icache_line_size = 32;
3540 /* Allocate hardware IRQ controller */
3541 ppc40x_irq_init(ppc_env_get_cpu(env));
3542
3543 SET_FIT_PERIOD(12, 16, 20, 24);
3544 SET_WDT_PERIOD(16, 20, 24, 28);
3545 }
3546
3547 POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
3548 {
3549 DeviceClass *dc = DEVICE_CLASS(oc);
3550 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3551
3552 dc->desc = "PowerPC 401x3";
3553 pcc->init_proc = init_proc_401x3;
3554 pcc->check_pow = check_pow_nocheck;
3555 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3556 PPC_DCR | PPC_WRTEE |
3557 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3558 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3559 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3560 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3561 PPC_4xx_COMMON | PPC_40x_EXCP;
3562 pcc->msr_mask = (1ull << 20) |
3563 (1ull << MSR_KEY) |
3564 (1ull << MSR_POW) |
3565 (1ull << MSR_CE) |
3566 (1ull << MSR_ILE) |
3567 (1ull << MSR_EE) |
3568 (1ull << MSR_PR) |
3569 (1ull << MSR_ME) |
3570 (1ull << MSR_DWE) |
3571 (1ull << MSR_DE) |
3572 (1ull << MSR_IR) |
3573 (1ull << MSR_DR) |
3574 (1ull << MSR_LE);
3575 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3576 pcc->excp_model = POWERPC_EXCP_40x;
3577 pcc->bus_model = PPC_FLAGS_INPUT_401;
3578 pcc->bfd_mach = bfd_mach_ppc_403;
3579 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3580 POWERPC_FLAG_BUS_CLK;
3581 }
3582
3583 static void init_proc_IOP480(CPUPPCState *env)
3584 {
3585 gen_spr_40x(env);
3586 gen_spr_401_403(env);
3587 gen_spr_401x2(env);
3588 gen_spr_compress(env);
3589 /* Memory management */
3590 #if !defined(CONFIG_USER_ONLY)
3591 env->nb_tlb = 64;
3592 env->nb_ways = 1;
3593 env->id_tlbs = 0;
3594 env->tlb_type = TLB_EMB;
3595 #endif
3596 init_excp_4xx_softmmu(env);
3597 env->dcache_line_size = 32;
3598 env->icache_line_size = 32;
3599 /* Allocate hardware IRQ controller */
3600 ppc40x_irq_init(ppc_env_get_cpu(env));
3601
3602 SET_FIT_PERIOD(8, 12, 16, 20);
3603 SET_WDT_PERIOD(16, 20, 24, 28);
3604 }
3605
3606 POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
3607 {
3608 DeviceClass *dc = DEVICE_CLASS(oc);
3609 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3610
3611 dc->desc = "IOP480";
3612 pcc->init_proc = init_proc_IOP480;
3613 pcc->check_pow = check_pow_nocheck;
3614 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3615 PPC_DCR | PPC_WRTEE |
3616 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3617 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3618 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3619 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3620 PPC_4xx_COMMON | PPC_40x_EXCP;
3621 pcc->msr_mask = (1ull << 20) |
3622 (1ull << MSR_KEY) |
3623 (1ull << MSR_POW) |
3624 (1ull << MSR_CE) |
3625 (1ull << MSR_ILE) |
3626 (1ull << MSR_EE) |
3627 (1ull << MSR_PR) |
3628 (1ull << MSR_ME) |
3629 (1ull << MSR_DE) |
3630 (1ull << MSR_IR) |
3631 (1ull << MSR_DR) |
3632 (1ull << MSR_LE);
3633 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3634 pcc->excp_model = POWERPC_EXCP_40x;
3635 pcc->bus_model = PPC_FLAGS_INPUT_401;
3636 pcc->bfd_mach = bfd_mach_ppc_403;
3637 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3638 POWERPC_FLAG_BUS_CLK;
3639 }
3640
3641 static void init_proc_403(CPUPPCState *env)
3642 {
3643 gen_spr_40x(env);
3644 gen_spr_401_403(env);
3645 gen_spr_403(env);
3646 gen_spr_403_real(env);
3647 init_excp_4xx_real(env);
3648 env->dcache_line_size = 32;
3649 env->icache_line_size = 32;
3650 /* Allocate hardware IRQ controller */
3651 ppc40x_irq_init(ppc_env_get_cpu(env));
3652
3653 SET_FIT_PERIOD(8, 12, 16, 20);
3654 SET_WDT_PERIOD(16, 20, 24, 28);
3655 }
3656
3657 POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
3658 {
3659 DeviceClass *dc = DEVICE_CLASS(oc);
3660 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3661
3662 dc->desc = "PowerPC 403";
3663 pcc->init_proc = init_proc_403;
3664 pcc->check_pow = check_pow_nocheck;
3665 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3666 PPC_DCR | PPC_WRTEE |
3667 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3668 PPC_CACHE_DCBZ |
3669 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3670 PPC_4xx_COMMON | PPC_40x_EXCP;
3671 pcc->msr_mask = (1ull << MSR_POW) |
3672 (1ull << MSR_CE) |
3673 (1ull << MSR_ILE) |
3674 (1ull << MSR_EE) |
3675 (1ull << MSR_PR) |
3676 (1ull << MSR_ME) |
3677 (1ull << MSR_PE) |
3678 (1ull << MSR_PX) |
3679 (1ull << MSR_LE);
3680 pcc->mmu_model = POWERPC_MMU_REAL;
3681 pcc->excp_model = POWERPC_EXCP_40x;
3682 pcc->bus_model = PPC_FLAGS_INPUT_401;
3683 pcc->bfd_mach = bfd_mach_ppc_403;
3684 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3685 POWERPC_FLAG_BUS_CLK;
3686 }
3687
3688 static void init_proc_403GCX(CPUPPCState *env)
3689 {
3690 gen_spr_40x(env);
3691 gen_spr_401_403(env);
3692 gen_spr_403(env);
3693 gen_spr_403_real(env);
3694 gen_spr_403_mmu(env);
3695 /* Bus access control */
3696 /* not emulated, as QEMU never does speculative access */
3697 spr_register(env, SPR_40x_SGR, "SGR",
3698 SPR_NOACCESS, SPR_NOACCESS,
3699 &spr_read_generic, &spr_write_generic,
3700 0xFFFFFFFF);
3701 /* not emulated, as QEMU do not emulate caches */
3702 spr_register(env, SPR_40x_DCWR, "DCWR",
3703 SPR_NOACCESS, SPR_NOACCESS,
3704 &spr_read_generic, &spr_write_generic,
3705 0x00000000);
3706 /* Memory management */
3707 #if !defined(CONFIG_USER_ONLY)
3708 env->nb_tlb = 64;
3709 env->nb_ways = 1;
3710 env->id_tlbs = 0;
3711 env->tlb_type = TLB_EMB;
3712 #endif
3713 init_excp_4xx_softmmu(env);
3714 env->dcache_line_size = 32;
3715 env->icache_line_size = 32;
3716 /* Allocate hardware IRQ controller */
3717 ppc40x_irq_init(ppc_env_get_cpu(env));
3718
3719 SET_FIT_PERIOD(8, 12, 16, 20);
3720 SET_WDT_PERIOD(16, 20, 24, 28);
3721 }
3722
3723 POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
3724 {
3725 DeviceClass *dc = DEVICE_CLASS(oc);
3726 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3727
3728 dc->desc = "PowerPC 403 GCX";
3729 pcc->init_proc = init_proc_403GCX;
3730 pcc->check_pow = check_pow_nocheck;
3731 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3732 PPC_DCR | PPC_WRTEE |
3733 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3734 PPC_CACHE_DCBZ |
3735 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3736 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3737 PPC_4xx_COMMON | PPC_40x_EXCP;
3738 pcc->msr_mask = (1ull << MSR_POW) |
3739 (1ull << MSR_CE) |
3740 (1ull << MSR_ILE) |
3741 (1ull << MSR_EE) |
3742 (1ull << MSR_PR) |
3743 (1ull << MSR_ME) |
3744 (1ull << MSR_PE) |
3745 (1ull << MSR_PX) |
3746 (1ull << MSR_LE);
3747 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3748 pcc->excp_model = POWERPC_EXCP_40x;
3749 pcc->bus_model = PPC_FLAGS_INPUT_401;
3750 pcc->bfd_mach = bfd_mach_ppc_403;
3751 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3752 POWERPC_FLAG_BUS_CLK;
3753 }
3754
3755 static void init_proc_405(CPUPPCState *env)
3756 {
3757 /* Time base */
3758 gen_tbl(env);
3759 gen_spr_40x(env);
3760 gen_spr_405(env);
3761 /* Bus access control */
3762 /* not emulated, as QEMU never does speculative access */
3763 spr_register(env, SPR_40x_SGR, "SGR",
3764 SPR_NOACCESS, SPR_NOACCESS,
3765 &spr_read_generic, &spr_write_generic,
3766 0xFFFFFFFF);
3767 /* not emulated, as QEMU do not emulate caches */
3768 spr_register(env, SPR_40x_DCWR, "DCWR",
3769 SPR_NOACCESS, SPR_NOACCESS,
3770 &spr_read_generic, &spr_write_generic,
3771 0x00000000);
3772 /* Memory management */
3773 #if !defined(CONFIG_USER_ONLY)
3774 env->nb_tlb = 64;
3775 env->nb_ways = 1;
3776 env->id_tlbs = 0;
3777 env->tlb_type = TLB_EMB;
3778 #endif
3779 init_excp_4xx_softmmu(env);
3780 env->dcache_line_size = 32;
3781 env->icache_line_size = 32;
3782 /* Allocate hardware IRQ controller */
3783 ppc40x_irq_init(ppc_env_get_cpu(env));
3784
3785 SET_FIT_PERIOD(8, 12, 16, 20);
3786 SET_WDT_PERIOD(16, 20, 24, 28);
3787 }
3788
3789 POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
3790 {
3791 DeviceClass *dc = DEVICE_CLASS(oc);
3792 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3793
3794 dc->desc = "PowerPC 405";
3795 pcc->init_proc = init_proc_405;
3796 pcc->check_pow = check_pow_nocheck;
3797 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3798 PPC_DCR | PPC_WRTEE |
3799 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3800 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3801 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3802 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3803 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
3804 pcc->msr_mask = (1ull << MSR_POW) |
3805 (1ull << MSR_CE) |
3806 (1ull << MSR_EE) |
3807 (1ull << MSR_PR) |
3808 (1ull << MSR_FP) |
3809 (1ull << MSR_DWE) |
3810 (1ull << MSR_DE) |
3811 (1ull << MSR_IR) |
3812 (1ull << MSR_DR);
3813 pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
3814 pcc->excp_model = POWERPC_EXCP_40x;
3815 pcc->bus_model = PPC_FLAGS_INPUT_405;
3816 pcc->bfd_mach = bfd_mach_ppc_403;
3817 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3818 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3819 }
3820
3821 static void init_proc_440EP(CPUPPCState *env)
3822 {
3823 /* Time base */
3824 gen_tbl(env);
3825 gen_spr_BookE(env, 0x000000000000FFFFULL);
3826 gen_spr_440(env);
3827 gen_spr_usprgh(env);
3828 /* Processor identification */
3829 spr_register(env, SPR_BOOKE_PIR, "PIR",
3830 SPR_NOACCESS, SPR_NOACCESS,
3831 &spr_read_generic, &spr_write_pir,
3832 0x00000000);
3833 /* XXX : not implemented */
3834 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3835 SPR_NOACCESS, SPR_NOACCESS,
3836 &spr_read_generic, &spr_write_generic,
3837 0x00000000);
3838 /* XXX : not implemented */
3839 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3840 SPR_NOACCESS, SPR_NOACCESS,
3841 &spr_read_generic, &spr_write_generic,
3842 0x00000000);
3843 /* XXX : not implemented */
3844 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3845 SPR_NOACCESS, SPR_NOACCESS,
3846 &spr_read_generic, &spr_write_generic,
3847 0x00000000);
3848 /* XXX : not implemented */
3849 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3850 SPR_NOACCESS, SPR_NOACCESS,
3851 &spr_read_generic, &spr_write_generic,
3852 0x00000000);
3853 /* XXX : not implemented */
3854 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3855 SPR_NOACCESS, SPR_NOACCESS,
3856 &spr_read_generic, &spr_write_generic,
3857 0x00000000);
3858 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3859 SPR_NOACCESS, SPR_NOACCESS,
3860 &spr_read_generic, &spr_write_generic,
3861 0x00000000);
3862 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3863 SPR_NOACCESS, SPR_NOACCESS,
3864 &spr_read_generic, &spr_write_generic,
3865 0x00000000);
3866 /* XXX : not implemented */
3867 spr_register(env, SPR_440_CCR1, "CCR1",
3868 SPR_NOACCESS, SPR_NOACCESS,
3869 &spr_read_generic, &spr_write_generic,
3870 0x00000000);
3871 /* Memory management */
3872 #if !defined(CONFIG_USER_ONLY)
3873 env->nb_tlb = 64;
3874 env->nb_ways = 1;
3875 env->id_tlbs = 0;
3876 env->tlb_type = TLB_EMB;
3877 #endif
3878 init_excp_BookE(env);
3879 env->dcache_line_size = 32;
3880 env->icache_line_size = 32;
3881 ppc40x_irq_init(ppc_env_get_cpu(env));
3882
3883 SET_FIT_PERIOD(12, 16, 20, 24);
3884 SET_WDT_PERIOD(20, 24, 28, 32);
3885 }
3886
3887 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
3888 {
3889 DeviceClass *dc = DEVICE_CLASS(oc);
3890 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3891
3892 dc->desc = "PowerPC 440 EP";
3893 pcc->init_proc = init_proc_440EP;
3894 pcc->check_pow = check_pow_nocheck;
3895 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3896 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3897 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3898 PPC_FLOAT_STFIWX |
3899 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3900 PPC_CACHE | PPC_CACHE_ICBI |
3901 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3902 PPC_MEM_TLBSYNC | PPC_MFTB |
3903 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3904 PPC_440_SPEC;
3905 pcc->msr_mask = (1ull << MSR_POW) |
3906 (1ull << MSR_CE) |
3907 (1ull << MSR_EE) |
3908 (1ull << MSR_PR) |
3909 (1ull << MSR_FP) |
3910 (1ull << MSR_ME) |
3911 (1ull << MSR_FE0) |
3912 (1ull << MSR_DWE) |
3913 (1ull << MSR_DE) |
3914 (1ull << MSR_FE1) |
3915 (1ull << MSR_IR) |
3916 (1ull << MSR_DR);
3917 pcc->mmu_model = POWERPC_MMU_BOOKE;
3918 pcc->excp_model = POWERPC_EXCP_BOOKE;
3919 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3920 pcc->bfd_mach = bfd_mach_ppc_403;
3921 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3922 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3923 }
3924
3925 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data)
3926 {
3927 DeviceClass *dc = DEVICE_CLASS(oc);
3928 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3929
3930 dc->desc = "PowerPC 460 EX";
3931 pcc->init_proc = init_proc_440EP;
3932 pcc->check_pow = check_pow_nocheck;
3933 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3934 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3935 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3936 PPC_FLOAT_STFIWX |
3937 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI |
3938 PPC_CACHE | PPC_CACHE_ICBI |
3939 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3940 PPC_MEM_TLBSYNC | PPC_MFTB |
3941 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3942 PPC_440_SPEC;
3943 pcc->msr_mask = (1ull << MSR_POW) |
3944 (1ull << MSR_CE) |
3945 (1ull << MSR_EE) |
3946 (1ull << MSR_PR) |
3947 (1ull << MSR_FP) |
3948 (1ull << MSR_ME) |
3949 (1ull << MSR_FE0) |
3950 (1ull << MSR_DWE) |
3951 (1ull << MSR_DE) |
3952 (1ull << MSR_FE1) |
3953 (1ull << MSR_IR) |
3954 (1ull << MSR_DR);
3955 pcc->mmu_model = POWERPC_MMU_BOOKE;
3956 pcc->excp_model = POWERPC_EXCP_BOOKE;
3957 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3958 pcc->bfd_mach = bfd_mach_ppc_403;
3959 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3960 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3961 }
3962
3963 static void init_proc_440GP(CPUPPCState *env)
3964 {
3965 /* Time base */
3966 gen_tbl(env);
3967 gen_spr_BookE(env, 0x000000000000FFFFULL);
3968 gen_spr_440(env);
3969 gen_spr_usprgh(env);
3970 /* Processor identification */
3971 spr_register(env, SPR_BOOKE_PIR, "PIR",
3972 SPR_NOACCESS, SPR_NOACCESS,
3973 &spr_read_generic, &spr_write_pir,
3974 0x00000000);
3975 /* XXX : not implemented */
3976 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3977 SPR_NOACCESS, SPR_NOACCESS,
3978 &spr_read_generic, &spr_write_generic,
3979 0x00000000);
3980 /* XXX : not implemented */
3981 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3982 SPR_NOACCESS, SPR_NOACCESS,
3983 &spr_read_generic, &spr_write_generic,
3984 0x00000000);
3985 /* XXX : not implemented */
3986 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3987 SPR_NOACCESS, SPR_NOACCESS,
3988 &spr_read_generic, &spr_write_generic,
3989 0x00000000);
3990 /* XXX : not implemented */
3991 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3992 SPR_NOACCESS, SPR_NOACCESS,
3993 &spr_read_generic, &spr_write_generic,
3994 0x00000000);
3995 /* Memory management */
3996 #if !defined(CONFIG_USER_ONLY)
3997 env->nb_tlb = 64;
3998 env->nb_ways = 1;
3999 env->id_tlbs = 0;
4000 env->tlb_type = TLB_EMB;
4001 #endif
4002 init_excp_BookE(env);
4003 env->dcache_line_size = 32;
4004 env->icache_line_size = 32;
4005 /* XXX: TODO: allocate internal IRQ controller */
4006
4007 SET_FIT_PERIOD(12, 16, 20, 24);
4008 SET_WDT_PERIOD(20, 24, 28, 32);
4009 }
4010
4011 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
4012 {
4013 DeviceClass *dc = DEVICE_CLASS(oc);
4014 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4015
4016 dc->desc = "PowerPC 440 GP";
4017 pcc->init_proc = init_proc_440GP;
4018 pcc->check_pow = check_pow_nocheck;
4019 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4020 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
4021 PPC_CACHE | PPC_CACHE_ICBI |
4022 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4023 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
4024 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4025 PPC_440_SPEC;
4026 pcc->msr_mask = (1ull << MSR_POW) |
4027 (1ull << MSR_CE) |
4028 (1ull << MSR_EE) |
4029 (1ull << MSR_PR) |
4030 (1ull << MSR_FP) |
4031 (1ull << MSR_ME) |
4032 (1ull << MSR_FE0) |
4033 (1ull << MSR_DWE) |
4034 (1ull << MSR_DE) |
4035 (1ull << MSR_FE1) |
4036 (1ull << MSR_IR) |
4037 (1ull << MSR_DR);
4038 pcc->mmu_model = POWERPC_MMU_BOOKE;
4039 pcc->excp_model = POWERPC_EXCP_BOOKE;
4040 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4041 pcc->bfd_mach = bfd_mach_ppc_403;
4042 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4043 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4044 }
4045
4046 static void init_proc_440x4(CPUPPCState *env)
4047 {
4048 /* Time base */
4049 gen_tbl(env);
4050 gen_spr_BookE(env, 0x000000000000FFFFULL);
4051 gen_spr_440(env);
4052 gen_spr_usprgh(env);
4053 /* Processor identification */
4054 spr_register(env, SPR_BOOKE_PIR, "PIR",
4055 SPR_NOACCESS, SPR_NOACCESS,
4056 &spr_read_generic, &spr_write_pir,
4057 0x00000000);
4058 /* XXX : not implemented */
4059 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4060 SPR_NOACCESS, SPR_NOACCESS,
4061 &spr_read_generic, &spr_write_generic,
4062 0x00000000);
4063 /* XXX : not implemented */
4064 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4065 SPR_NOACCESS, SPR_NOACCESS,
4066 &spr_read_generic, &spr_write_generic,
4067 0x00000000);
4068 /* XXX : not implemented */
4069 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
4070 SPR_NOACCESS, SPR_NOACCESS,
4071 &spr_read_generic, &spr_write_generic,
4072 0x00000000);
4073 /* XXX : not implemented */
4074 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
4075 SPR_NOACCESS, SPR_NOACCESS,
4076 &spr_read_generic, &spr_write_generic,
4077 0x00000000);
4078 /* Memory management */
4079 #if !defined(CONFIG_USER_ONLY)
4080 env->nb_tlb = 64;
4081 env->nb_ways = 1;
4082 env->id_tlbs = 0;
4083 env->tlb_type = TLB_EMB;
4084 #endif
4085 init_excp_BookE(env);
4086 env->dcache_line_size = 32;
4087 env->icache_line_size = 32;
4088 /* XXX: TODO: allocate internal IRQ controller */
4089
4090 SET_FIT_PERIOD(12, 16, 20, 24);
4091 SET_WDT_PERIOD(20, 24, 28, 32);
4092 }
4093
4094 POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
4095 {
4096 DeviceClass *dc = DEVICE_CLASS(oc);
4097 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4098
4099 dc->desc = "PowerPC 440x4";
4100 pcc->init_proc = init_proc_440x4;
4101 pcc->check_pow = check_pow_nocheck;
4102 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4103 PPC_DCR | PPC_WRTEE |
4104 PPC_CACHE | PPC_CACHE_ICBI |
4105 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4106 PPC_MEM_TLBSYNC | PPC_MFTB |
4107 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4108 PPC_440_SPEC;
4109 pcc->msr_mask = (1ull << MSR_POW) |
4110 (1ull << MSR_CE) |
4111 (1ull << MSR_EE) |
4112 (1ull << MSR_PR) |
4113 (1ull << MSR_FP) |
4114 (1ull << MSR_ME) |
4115 (1ull << MSR_FE0) |
4116 (1ull << MSR_DWE) |
4117 (1ull << MSR_DE) |
4118 (1ull << MSR_FE1) |
4119 (1ull << MSR_IR) |
4120 (1ull << MSR_DR);
4121 pcc->mmu_model = POWERPC_MMU_BOOKE;
4122 pcc->excp_model = POWERPC_EXCP_BOOKE;
4123 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4124 pcc->bfd_mach = bfd_mach_ppc_403;
4125 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4126 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4127 }
4128
4129 static void init_proc_440x5(CPUPPCState *env)
4130 {
4131 /* Time base */
4132 gen_tbl(env);
4133 gen_spr_BookE(env, 0x000000000000FFFFULL);
4134 gen_spr_440(env);
4135 gen_spr_usprgh(env);
4136 /* Processor identification */
4137 spr_register(env, SPR_BOOKE_PIR, "PIR",
4138 SPR_NOACCESS, SPR_NOACCESS,
4139 &spr_read_generic, &spr_write_pir,
4140 0x00000000);
4141 /* XXX : not implemented */
4142 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4143 SPR_NOACCESS, SPR_NOACCESS,
4144 &spr_read_generic, &spr_write_generic,
4145 0x00000000);
4146 /* XXX : not implemented */
4147 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4148 SPR_NOACCESS, SPR_NOACCESS,
4149 &spr_read_generic, &spr_write_generic,
4150 0x00000000);
4151 /* XXX : not implemented */
4152 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
4153 SPR_NOACCESS, SPR_NOACCESS,
4154 &spr_read_generic, &spr_write_generic,
4155 0x00000000);
4156 /* XXX : not implemented */
4157 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
4158 SPR_NOACCESS, SPR_NOACCESS,
4159 &spr_read_generic, &spr_write_generic,
4160 0x00000000);
4161 /* XXX : not implemented */
4162 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4163 SPR_NOACCESS, SPR_NOACCESS,
4164 &spr_read_generic, &spr_write_generic,
4165 0x00000000);
4166 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4167 SPR_NOACCESS, SPR_NOACCESS,
4168 &spr_read_generic, &spr_write_generic,
4169 0x00000000);
4170 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4171 SPR_NOACCESS, SPR_NOACCESS,
4172 &spr_read_generic, &spr_write_generic,
4173 0x00000000);
4174 /* XXX : not implemented */
4175 spr_register(env, SPR_440_CCR1, "CCR1",
4176 SPR_NOACCESS, SPR_NOACCESS,
4177 &spr_read_generic, &spr_write_generic,
4178 0x00000000);
4179 /* Memory management */
4180 #if !defined(CONFIG_USER_ONLY)
4181 env->nb_tlb = 64;
4182 env->nb_ways = 1;
4183 env->id_tlbs = 0;
4184 env->tlb_type = TLB_EMB;
4185 #endif
4186 init_excp_BookE(env);
4187 env->dcache_line_size = 32;
4188 env->icache_line_size = 32;
4189 ppc40x_irq_init(ppc_env_get_cpu(env));
4190
4191 SET_FIT_PERIOD(12, 16, 20, 24);
4192 SET_WDT_PERIOD(20, 24, 28, 32);
4193 }
4194
4195 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
4196 {
4197 DeviceClass *dc = DEVICE_CLASS(oc);
4198 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4199
4200 dc->desc = "PowerPC 440x5";
4201 pcc->init_proc = init_proc_440x5;
4202 pcc->check_pow = check_pow_nocheck;
4203 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4204 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
4205 PPC_CACHE | PPC_CACHE_ICBI |
4206 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4207 PPC_MEM_TLBSYNC | PPC_MFTB |
4208 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4209 PPC_440_SPEC;
4210 pcc->msr_mask = (1ull << MSR_POW) |
4211 (1ull << MSR_CE) |
4212 (1ull << MSR_EE) |
4213 (1ull << MSR_PR) |
4214 (1ull << MSR_FP) |
4215 (1ull << MSR_ME) |
4216 (1ull << MSR_FE0) |
4217 (1ull << MSR_DWE) |
4218 (1ull << MSR_DE) |
4219 (1ull << MSR_FE1) |
4220 (1ull << MSR_IR) |
4221 (1ull << MSR_DR);
4222 pcc->mmu_model = POWERPC_MMU_BOOKE;
4223 pcc->excp_model = POWERPC_EXCP_BOOKE;
4224 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4225 pcc->bfd_mach = bfd_mach_ppc_403;
4226 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4227 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4228 }
4229
4230 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data)
4231 {
4232 DeviceClass *dc = DEVICE_CLASS(oc);
4233 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4234
4235 dc->desc = "PowerPC 440x5 with double precision FPU";
4236 pcc->init_proc = init_proc_440x5;
4237 pcc->check_pow = check_pow_nocheck;
4238 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4239 PPC_FLOAT | PPC_FLOAT_FSQRT |
4240 PPC_FLOAT_STFIWX |
4241 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
4242 PPC_CACHE | PPC_CACHE_ICBI |
4243 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4244 PPC_MEM_TLBSYNC | PPC_MFTB |
4245 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4246 PPC_440_SPEC;
4247 pcc->insns_flags2 = PPC2_FP_CVT_S64;
4248 pcc->msr_mask = (1ull << MSR_POW) |
4249 (1ull << MSR_CE) |
4250 (1ull << MSR_EE) |
4251 (1ull << MSR_PR) |
4252 (1ull << MSR_FP) |
4253 (1ull << MSR_ME) |
4254 (1ull << MSR_FE0) |
4255 (1ull << MSR_DWE) |
4256 (1ull << MSR_DE) |
4257 (1ull << MSR_FE1) |
4258 (1ull << MSR_IR) |
4259 (1ull << MSR_DR);
4260 pcc->mmu_model = POWERPC_MMU_BOOKE;
4261 pcc->excp_model = POWERPC_EXCP_BOOKE;
4262 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4263 pcc->bfd_mach = bfd_mach_ppc_403;
4264 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4265 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4266 }
4267
4268 static void init_proc_MPC5xx(CPUPPCState *env)
4269 {
4270 /* Time base */
4271 gen_tbl(env);
4272 gen_spr_5xx_8xx(env);
4273 gen_spr_5xx(env);
4274 init_excp_MPC5xx(env);
4275 env->dcache_line_size = 32;
4276 env->icache_line_size = 32;
4277 /* XXX: TODO: allocate internal IRQ controller */
4278 }
4279
4280 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
4281 {
4282 DeviceClass *dc = DEVICE_CLASS(oc);
4283 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4284
4285 dc->desc = "Freescale 5xx cores (aka RCPU)";
4286 pcc->init_proc = init_proc_MPC5xx;
4287 pcc->check_pow = check_pow_none;
4288 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4289 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4290 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
4291 PPC_MFTB;
4292 pcc->msr_mask = (1ull << MSR_ILE) |
4293 (1ull << MSR_EE) |
4294 (1ull << MSR_PR) |
4295 (1ull << MSR_FP) |
4296 (1ull << MSR_ME) |
4297 (1ull << MSR_FE0) |
4298 (1ull << MSR_SE) |
4299 (1ull << MSR_DE) |
4300 (1ull << MSR_FE1) |
4301 (1ull << MSR_EP) |
4302 (1ull << MSR_RI) |
4303 (1ull << MSR_LE);
4304 pcc->mmu_model = POWERPC_MMU_REAL;
4305 pcc->excp_model = POWERPC_EXCP_603;
4306 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4307 pcc->bfd_mach = bfd_mach_ppc_505;
4308 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4309 POWERPC_FLAG_BUS_CLK;
4310 }
4311
4312 static void init_proc_MPC8xx(CPUPPCState *env)
4313 {
4314 /* Time base */
4315 gen_tbl(env);
4316 gen_spr_5xx_8xx(env);
4317 gen_spr_8xx(env);
4318 init_excp_MPC8xx(env);
4319 env->dcache_line_size = 32;
4320 env->icache_line_size = 32;
4321 /* XXX: TODO: allocate internal IRQ controller */
4322 }
4323
4324 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
4325 {
4326 DeviceClass *dc = DEVICE_CLASS(oc);
4327 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4328
4329 dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
4330 pcc->init_proc = init_proc_MPC8xx;
4331 pcc->check_pow = check_pow_none;
4332 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4333 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4334 PPC_CACHE_ICBI | PPC_MFTB;
4335 pcc->msr_mask = (1ull << MSR_ILE) |
4336 (1ull << MSR_EE) |
4337 (1ull << MSR_PR) |
4338 (1ull << MSR_FP) |
4339 (1ull << MSR_ME) |
4340 (1ull << MSR_SE) |
4341 (1ull << MSR_DE) |
4342 (1ull << MSR_EP) |
4343 (1ull << MSR_IR) |
4344 (1ull << MSR_DR) |
4345 (1ull << MSR_RI) |
4346 (1ull << MSR_LE);
4347 pcc->mmu_model = POWERPC_MMU_MPC8xx;
4348 pcc->excp_model = POWERPC_EXCP_603;
4349 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4350 pcc->bfd_mach = bfd_mach_ppc_860;
4351 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4352 POWERPC_FLAG_BUS_CLK;
4353 }
4354
4355 /* Freescale 82xx cores (aka PowerQUICC-II) */
4356
4357 static void init_proc_G2(CPUPPCState *env)
4358 {
4359 gen_spr_ne_601(env);
4360 gen_spr_sdr1(env);
4361 gen_spr_G2_755(env);
4362 gen_spr_G2(env);
4363 /* Time base */
4364 gen_tbl(env);
4365 /* External access control */
4366 /* XXX : not implemented */
4367 spr_register(env, SPR_EAR, "EAR",
4368 SPR_NOACCESS, SPR_NOACCESS,
4369 &spr_read_generic, &spr_write_generic,
4370 0x00000000);
4371 /* Hardware implementation register */
4372 /* XXX : not implemented */
4373 spr_register(env, SPR_HID0, "HID0",
4374 SPR_NOACCESS, SPR_NOACCESS,
4375 &spr_read_generic, &spr_write_generic,
4376 0x00000000);
4377 /* XXX : not implemented */
4378 spr_register(env, SPR_HID1, "HID1",
4379 SPR_NOACCESS, SPR_NOACCESS,
4380 &spr_read_generic, &spr_write_generic,
4381 0x00000000);
4382 /* XXX : not implemented */
4383 spr_register(env, SPR_HID2, "HID2",
4384 SPR_NOACCESS, SPR_NOACCESS,
4385 &spr_read_generic, &spr_write_generic,
4386 0x00000000);
4387 /* Memory management */
4388 gen_low_BATs(env);
4389 gen_high_BATs(env);
4390 gen_6xx_7xx_soft_tlb(env, 64, 2);
4391 init_excp_G2(env);
4392 env->dcache_line_size = 32;
4393 env->icache_line_size = 32;
4394 /* Allocate hardware IRQ controller */
4395 ppc6xx_irq_init(ppc_env_get_cpu(env));
4396 }
4397
4398 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
4399 {
4400 DeviceClass *dc = DEVICE_CLASS(oc);
4401 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4402
4403 dc->desc = "PowerPC G2";
4404 pcc->init_proc = init_proc_G2;
4405 pcc->check_pow = check_pow_hid0;
4406 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4407 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4408 PPC_FLOAT_STFIWX |
4409 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4410 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4411 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4412 PPC_SEGMENT | PPC_EXTERN;
4413 pcc->msr_mask = (1ull << MSR_POW) |
4414 (1ull << MSR_TGPR) |
4415 (1ull << MSR_EE) |
4416 (1ull << MSR_PR) |
4417 (1ull << MSR_FP) |
4418 (1ull << MSR_ME) |
4419 (1ull << MSR_FE0) |
4420 (1ull << MSR_SE) |
4421 (1ull << MSR_DE) |
4422 (1ull << MSR_FE1) |
4423 (1ull << MSR_AL) |
4424 (1ull << MSR_EP) |
4425 (1ull << MSR_IR) |
4426 (1ull << MSR_DR) |
4427 (1ull << MSR_RI);
4428 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4429 pcc->excp_model = POWERPC_EXCP_G2;
4430 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4431 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4432 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4433 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4434 }
4435
4436 static void init_proc_G2LE(CPUPPCState *env)
4437 {
4438 gen_spr_ne_601(env);
4439 gen_spr_sdr1(env);
4440 gen_spr_G2_755(env);
4441 gen_spr_G2(env);
4442 /* Time base */
4443 gen_tbl(env);
4444 /* External access control */
4445 /* XXX : not implemented */
4446 spr_register(env, SPR_EAR, "EAR",
4447 SPR_NOACCESS, SPR_NOACCESS,
4448 &spr_read_generic, &spr_write_generic,
4449 0x00000000);
4450 /* Hardware implementation register */
4451 /* XXX : not implemented */
4452 spr_register(env, SPR_HID0, "HID0",
4453 SPR_NOACCESS, SPR_NOACCESS,
4454 &spr_read_generic, &spr_write_generic,
4455 0x00000000);
4456 /* XXX : not implemented */
4457 spr_register(env, SPR_HID1, "HID1",
4458 SPR_NOACCESS, SPR_NOACCESS,
4459 &spr_read_generic, &spr_write_generic,
4460 0x00000000);
4461 /* XXX : not implemented */
4462 spr_register(env, SPR_HID2, "HID2",
4463 SPR_NOACCESS, SPR_NOACCESS,
4464 &spr_read_generic, &spr_write_generic,
4465 0x00000000);
4466
4467 /* Memory management */
4468 gen_low_BATs(env);
4469 gen_high_BATs(env);
4470 gen_6xx_7xx_soft_tlb(env, 64, 2);
4471 init_excp_G2(env);
4472 env->dcache_line_size = 32;
4473 env->icache_line_size = 32;
4474 /* Allocate hardware IRQ controller */
4475 ppc6xx_irq_init(ppc_env_get_cpu(env));
4476 }
4477
4478 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
4479 {
4480 DeviceClass *dc = DEVICE_CLASS(oc);
4481 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4482
4483 dc->desc = "PowerPC G2LE";
4484 pcc->init_proc = init_proc_G2LE;
4485 pcc->check_pow = check_pow_hid0;
4486 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4487 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4488 PPC_FLOAT_STFIWX |
4489 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4490 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4491 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4492 PPC_SEGMENT | PPC_EXTERN;
4493 pcc->msr_mask = (1ull << MSR_POW) |
4494 (1ull << MSR_TGPR) |
4495 (1ull << MSR_ILE) |
4496 (1ull << MSR_EE) |
4497 (1ull << MSR_PR) |
4498 (1ull << MSR_FP) |
4499 (1ull << MSR_ME) |
4500 (1ull << MSR_FE0) |
4501 (1ull << MSR_SE) |
4502 (1ull << MSR_DE) |
4503 (1ull << MSR_FE1) |
4504 (1ull << MSR_AL) |
4505 (1ull << MSR_EP) |
4506 (1ull << MSR_IR) |
4507 (1ull << MSR_DR) |
4508 (1ull << MSR_RI) |
4509 (1ull << MSR_LE);
4510 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4511 pcc->excp_model = POWERPC_EXCP_G2;
4512 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4513 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4514 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4515 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4516 }
4517
4518 static void init_proc_e200(CPUPPCState *env)
4519 {
4520 /* Time base */
4521 gen_tbl(env);
4522 gen_spr_BookE(env, 0x000000070000FFFFULL);
4523 /* XXX : not implemented */
4524 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4525 &spr_read_spefscr, &spr_write_spefscr,
4526 &spr_read_spefscr, &spr_write_spefscr,
4527 0x00000000);
4528 /* Memory management */
4529 gen_spr_BookE206(env, 0x0000005D, NULL, 0);
4530 /* XXX : not implemented */
4531 spr_register(env, SPR_HID0, "HID0",
4532 SPR_NOACCESS, SPR_NOACCESS,
4533 &spr_read_generic, &spr_write_generic,
4534 0x00000000);
4535 /* XXX : not implemented */
4536 spr_register(env, SPR_HID1, "HID1",
4537 SPR_NOACCESS, SPR_NOACCESS,
4538 &spr_read_generic, &spr_write_generic,
4539 0x00000000);
4540 /* XXX : not implemented */
4541 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
4542 SPR_NOACCESS, SPR_NOACCESS,
4543 &spr_read_generic, &spr_write_generic,
4544 0x00000000);
4545 /* XXX : not implemented */
4546 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4547 SPR_NOACCESS, SPR_NOACCESS,
4548 &spr_read_generic, &spr_write_generic,
4549 0x00000000);
4550 /* XXX : not implemented */
4551 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4552 SPR_NOACCESS, SPR_NOACCESS,
4553 &spr_read_generic, &spr_write_generic,
4554 0x00000000);
4555 /* XXX : not implemented */
4556 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4557 SPR_NOACCESS, SPR_NOACCESS,
4558 &spr_read_generic, &spr_write_generic,
4559 0x00000000);
4560 /* XXX : not implemented */
4561 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4562 SPR_NOACCESS, SPR_NOACCESS,
4563 &spr_read_generic, &spr_write_generic,
4564 0x00000000);
4565 /* XXX : not implemented */
4566 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4567 &spr_read_generic, SPR_NOACCESS,
4568 &spr_read_generic, SPR_NOACCESS,
4569 0x00000000);
4570 /* XXX : not implemented */
4571 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4572 SPR_NOACCESS, SPR_NOACCESS,
4573 &spr_read_generic, &spr_write_generic,
4574 0x00000000);
4575 /* XXX : not implemented */
4576 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4577 SPR_NOACCESS, SPR_NOACCESS,
4578 &spr_read_generic, &spr_write_generic,
4579 0x00000000);
4580 /* XXX : not implemented */
4581 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4582 SPR_NOACCESS, SPR_NOACCESS,
4583 &spr_read_generic, &spr_write_generic,
4584 0x00000000);
4585 /* XXX : not implemented */
4586 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4587 SPR_NOACCESS, SPR_NOACCESS,
4588 &spr_read_generic, &spr_write_generic,
4589 0x00000000);
4590 /* XXX : not implemented */
4591 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4592 SPR_NOACCESS, SPR_NOACCESS,
4593 &spr_read_generic, &spr_write_generic,
4594 0x00000000);
4595 /* XXX : not implemented */
4596 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4597 SPR_NOACCESS, SPR_NOACCESS,
4598 &spr_read_generic, &spr_write_generic,
4599 0x00000000);
4600 /* XXX : not implemented */
4601 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4602 SPR_NOACCESS, SPR_NOACCESS,
4603 &spr_read_generic, &spr_write_generic,
4604 0x00000000); /* TOFIX */
4605 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4606 SPR_NOACCESS, SPR_NOACCESS,
4607 &spr_read_generic, &spr_write_generic,
4608 0x00000000);
4609 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4610 SPR_NOACCESS, SPR_NOACCESS,
4611 &spr_read_generic, &spr_write_generic,
4612 0x00000000);
4613 #if !defined(CONFIG_USER_ONLY)
4614 env->nb_tlb = 64;
4615 env->nb_ways = 1;
4616 env->id_tlbs = 0;
4617 env->tlb_type = TLB_EMB;
4618 #endif
4619 init_excp_e200(env, 0xFFFF0000UL);
4620 env->dcache_line_size = 32;
4621 env->icache_line_size = 32;
4622 /* XXX: TODO: allocate internal IRQ controller */
4623 }
4624
4625 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
4626 {
4627 DeviceClass *dc = DEVICE_CLASS(oc);
4628 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4629
4630 dc->desc = "e200 core";
4631 pcc->init_proc = init_proc_e200;
4632 pcc->check_pow = check_pow_hid0;
4633 /*
4634 * XXX: unimplemented instructions:
4635 * dcblc
4636 * dcbtlst
4637 * dcbtstls
4638 * icblc
4639 * icbtls
4640 * tlbivax
4641 * all SPE multiply-accumulate instructions
4642 */
4643 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4644 PPC_SPE | PPC_SPE_SINGLE |
4645 PPC_WRTEE | PPC_RFDI |
4646 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4647 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4648 PPC_MEM_TLBSYNC | PPC_TLBIVAX |
4649 PPC_BOOKE;
4650 pcc->msr_mask = (1ull << MSR_UCLE) |
4651 (1ull << MSR_SPE) |
4652 (1ull << MSR_POW) |
4653 (1ull << MSR_CE) |
4654 (1ull << MSR_EE) |
4655 (1ull << MSR_PR) |
4656 (1ull << MSR_FP) |
4657 (1ull << MSR_ME) |
4658 (1ull << MSR_FE0) |
4659 (1ull << MSR_DWE) |
4660 (1ull << MSR_DE) |
4661 (1ull << MSR_FE1) |
4662 (1ull << MSR_IR) |
4663 (1ull << MSR_DR);
4664 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4665 pcc->excp_model = POWERPC_EXCP_BOOKE;
4666 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4667 pcc->bfd_mach = bfd_mach_ppc_860;
4668 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4669 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4670 POWERPC_FLAG_BUS_CLK;
4671 }
4672
4673 static void init_proc_e300(CPUPPCState *env)
4674 {
4675 gen_spr_ne_601(env);
4676 gen_spr_sdr1(env);
4677 gen_spr_603(env);
4678 /* Time base */
4679 gen_tbl(env);
4680 /* hardware implementation registers */
4681 /* XXX : not implemented */
4682 spr_register(env, SPR_HID0, "HID0",
4683 SPR_NOACCESS, SPR_NOACCESS,
4684 &spr_read_generic, &spr_write_generic,
4685 0x00000000);
4686 /* XXX : not implemented */
4687 spr_register(env, SPR_HID1, "HID1",
4688 SPR_NOACCESS, SPR_NOACCESS,
4689 &spr_read_generic, &spr_write_generic,
4690 0x00000000);
4691 /* XXX : not implemented */
4692 spr_register(env, SPR_HID2, "HID2",
4693 SPR_NOACCESS, SPR_NOACCESS,
4694 &spr_read_generic, &spr_write_generic,
4695 0x00000000);
4696 /* Breakpoints */
4697 /* XXX : not implemented */
4698 spr_register(env, SPR_DABR, "DABR",
4699 SPR_NOACCESS, SPR_NOACCESS,
4700 &spr_read_generic, &spr_write_generic,
4701 0x00000000);
4702 /* XXX : not implemented */
4703 spr_register(env, SPR_DABR2, "DABR2",
4704 SPR_NOACCESS, SPR_NOACCESS,
4705 &spr_read_generic, &spr_write_generic,
4706 0x00000000);
4707 /* XXX : not implemented */
4708 spr_register(env, SPR_IABR2, "IABR2",
4709 SPR_NOACCESS, SPR_NOACCESS,
4710 &spr_read_generic, &spr_write_generic,
4711 0x00000000);
4712 /* XXX : not implemented */
4713 spr_register(env, SPR_IBCR, "IBCR",
4714 SPR_NOACCESS, SPR_NOACCESS,
4715 &spr_read_generic, &spr_write_generic,
4716 0x00000000);
4717 /* XXX : not implemented */
4718 spr_register(env, SPR_DBCR, "DBCR",
4719 SPR_NOACCESS, SPR_NOACCESS,
4720 &spr_read_generic, &spr_write_generic,
4721 0x00000000);
4722 /* Memory management */
4723 gen_low_BATs(env);
4724 gen_high_BATs(env);
4725 gen_6xx_7xx_soft_tlb(env, 64, 2);
4726 init_excp_603(env);
4727 env->dcache_line_size = 32;
4728 env->icache_line_size = 32;
4729 /* Allocate hardware IRQ controller */
4730 ppc6xx_irq_init(ppc_env_get_cpu(env));
4731 }
4732
4733 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
4734 {
4735 DeviceClass *dc = DEVICE_CLASS(oc);
4736 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4737
4738 dc->desc = "e300 core";
4739 pcc->init_proc = init_proc_e300;
4740 pcc->check_pow = check_pow_hid0;
4741 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4742 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4743 PPC_FLOAT_STFIWX |
4744 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4745 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4746 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4747 PPC_SEGMENT | PPC_EXTERN;
4748 pcc->msr_mask = (1ull << MSR_POW) |
4749 (1ull << MSR_TGPR) |
4750 (1ull << MSR_ILE) |
4751 (1ull << MSR_EE) |
4752 (1ull << MSR_PR) |
4753 (1ull << MSR_FP) |
4754 (1ull << MSR_ME) |
4755 (1ull << MSR_FE0) |
4756 (1ull << MSR_SE) |
4757 (1ull << MSR_DE) |
4758 (1ull << MSR_FE1) |
4759 (1ull << MSR_AL) |
4760 (1ull << MSR_EP) |
4761 (1ull << MSR_IR) |
4762 (1ull << MSR_DR) |
4763 (1ull << MSR_RI) |
4764 (1ull << MSR_LE);
4765 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4766 pcc->excp_model = POWERPC_EXCP_603;
4767 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4768 pcc->bfd_mach = bfd_mach_ppc_603;
4769 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4770 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4771 }
4772
4773 #if !defined(CONFIG_USER_ONLY)
4774 static void spr_write_mas73(DisasContext *ctx, int sprn, int gprn)
4775 {
4776 TCGv val = tcg_temp_new();
4777 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
4778 gen_store_spr(SPR_BOOKE_MAS3, val);
4779 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
4780 gen_store_spr(SPR_BOOKE_MAS7, val);
4781 tcg_temp_free(val);
4782 }
4783
4784 static void spr_read_mas73(DisasContext *ctx, int gprn, int sprn)
4785 {
4786 TCGv mas7 = tcg_temp_new();
4787 TCGv mas3 = tcg_temp_new();
4788 gen_load_spr(mas7, SPR_BOOKE_MAS7);
4789 tcg_gen_shli_tl(mas7, mas7, 32);
4790 gen_load_spr(mas3, SPR_BOOKE_MAS3);
4791 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
4792 tcg_temp_free(mas3);
4793 tcg_temp_free(mas7);
4794 }
4795
4796 #endif
4797
4798 enum fsl_e500_version {
4799 fsl_e500v1,
4800 fsl_e500v2,
4801 fsl_e500mc,
4802 fsl_e5500,
4803 fsl_e6500,
4804 };
4805
4806 static void init_proc_e500(CPUPPCState *env, int version)
4807 {
4808 PowerPCCPU *cpu = ppc_env_get_cpu(env);
4809 uint32_t tlbncfg[2];
4810 uint64_t ivor_mask;
4811 uint64_t ivpr_mask = 0xFFFF0000ULL;
4812 uint32_t l1cfg0 = 0x3800 /* 8 ways */
4813 | 0x0020; /* 32 kb */
4814 uint32_t l1cfg1 = 0x3800 /* 8 ways */
4815 | 0x0020; /* 32 kb */
4816 uint32_t mmucfg = 0;
4817 #if !defined(CONFIG_USER_ONLY)
4818 int i;
4819 #endif
4820
4821 /* Time base */
4822 gen_tbl(env);
4823 /*
4824 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4825 * complain when accessing them.
4826 * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4827 */
4828 switch (version) {
4829 case fsl_e500v1:
4830 case fsl_e500v2:
4831 default:
4832 ivor_mask = 0x0000000F0000FFFFULL;
4833 break;
4834 case fsl_e500mc:
4835 case fsl_e5500:
4836 ivor_mask = 0x000003FE0000FFFFULL;
4837 break;
4838 case fsl_e6500:
4839 ivor_mask = 0x000003FF0000FFFFULL;
4840 break;
4841 }
4842 gen_spr_BookE(env, ivor_mask);
4843 gen_spr_usprg3(env);
4844 /* Processor identification */
4845 spr_register(env, SPR_BOOKE_PIR, "PIR",
4846 SPR_NOACCESS, SPR_NOACCESS,
4847 &spr_read_generic, &spr_write_pir,
4848 0x00000000);
4849 /* XXX : not implemented */
4850 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4851 &spr_read_spefscr, &spr_write_spefscr,
4852 &spr_read_spefscr, &spr_write_spefscr,
4853 0x00000000);
4854 #if !defined(CONFIG_USER_ONLY)
4855 /* Memory management */
4856 env->nb_pids = 3;
4857 env->nb_ways = 2;
4858 env->id_tlbs = 0;
4859 switch (version) {
4860 case fsl_e500v1:
4861 tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4862 tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4863 break;
4864 case fsl_e500v2:
4865 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4866 tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4867 break;
4868 case fsl_e500mc:
4869 case fsl_e5500:
4870 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4871 tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
4872 break;
4873 case fsl_e6500:
4874 mmucfg = 0x6510B45;
4875 env->nb_pids = 1;
4876 tlbncfg[0] = 0x08052400;
4877 tlbncfg[1] = 0x40028040;
4878 break;
4879 default:
4880 cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n",
4881 env->spr[SPR_PVR]);
4882 }
4883 #endif
4884 /* Cache sizes */
4885 switch (version) {
4886 case fsl_e500v1:
4887 case fsl_e500v2:
4888 env->dcache_line_size = 32;
4889 env->icache_line_size = 32;
4890 break;
4891 case fsl_e500mc:
4892 case fsl_e5500:
4893 env->dcache_line_size = 64;
4894 env->icache_line_size = 64;
4895 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
4896 l1cfg1 |= 0x1000000; /* 64 byte cache block size */
4897 break;
4898 case fsl_e6500:
4899 env->dcache_line_size = 32;
4900 env->icache_line_size = 32;
4901 l1cfg0 |= 0x0F83820;
4902 l1cfg1 |= 0x0B83820;
4903 break;
4904 default:
4905 cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n",
4906 env->spr[SPR_PVR]);
4907 }
4908 gen_spr_BookE206(env, 0x000000DF, tlbncfg, mmucfg);
4909 /* XXX : not implemented */
4910 spr_register(env, SPR_HID0, "HID0",
4911 SPR_NOACCESS, SPR_NOACCESS,
4912 &spr_read_generic, &spr_write_generic,
4913 0x00000000);
4914 /* XXX : not implemented */
4915 spr_register(env, SPR_HID1, "HID1",
4916 SPR_NOACCESS, SPR_NOACCESS,
4917 &spr_read_generic, &spr_write_generic,
4918 0x00000000);
4919 /* XXX : not implemented */
4920 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4921 SPR_NOACCESS, SPR_NOACCESS,
4922 &spr_read_generic, &spr_write_generic,
4923 0x00000000);
4924 /* XXX : not implemented */
4925 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4926 SPR_NOACCESS, SPR_NOACCESS,
4927 &spr_read_generic, &spr_write_generic,
4928 0x00000000);
4929 /* XXX : not implemented */
4930 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4931 SPR_NOACCESS, SPR_NOACCESS,
4932 &spr_read_generic, &spr_write_generic,
4933 0x00000000);
4934 /* XXX : not implemented */
4935 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4936 SPR_NOACCESS, SPR_NOACCESS,
4937 &spr_read_generic, &spr_write_generic,
4938 0x00000000);
4939 /* XXX : not implemented */
4940 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4941 SPR_NOACCESS, SPR_NOACCESS,
4942 &spr_read_generic, &spr_write_generic,
4943 0x00000000);
4944 /* XXX : not implemented */
4945 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4946 SPR_NOACCESS, SPR_NOACCESS,
4947 &spr_read_generic, &spr_write_generic,
4948 0x00000000);
4949 /* XXX : not implemented */
4950 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4951 &spr_read_generic, SPR_NOACCESS,
4952 &spr_read_generic, SPR_NOACCESS,
4953 l1cfg0);
4954 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1",
4955 &spr_read_generic, SPR_NOACCESS,
4956 &spr_read_generic, SPR_NOACCESS,
4957 l1cfg1);
4958 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4959 SPR_NOACCESS, SPR_NOACCESS,
4960 &spr_read_generic, &spr_write_e500_l1csr0,
4961 0x00000000);
4962 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4963 SPR_NOACCESS, SPR_NOACCESS,
4964 &spr_read_generic, &spr_write_e500_l1csr1,
4965 0x00000000);
4966 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4967 SPR_NOACCESS, SPR_NOACCESS,
4968 &spr_read_generic, &spr_write_generic,
4969 0x00000000);
4970 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4971 SPR_NOACCESS, SPR_NOACCESS,
4972 &spr_read_generic, &spr_write_generic,
4973 0x00000000);
4974 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4975 SPR_NOACCESS, SPR_NOACCESS,
4976 &spr_read_generic, &spr_write_booke206_mmucsr0,
4977 0x00000000);
4978 spr_register(env, SPR_BOOKE_EPR, "EPR",
4979 SPR_NOACCESS, SPR_NOACCESS,
4980 &spr_read_generic, SPR_NOACCESS,
4981 0x00000000);
4982 /* XXX better abstract into Emb.xxx features */
4983 if ((version == fsl_e5500) || (version == fsl_e6500)) {
4984 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
4985 SPR_NOACCESS, SPR_NOACCESS,
4986 &spr_read_generic, &spr_write_generic,
4987 0x00000000);
4988 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
4989 SPR_NOACCESS, SPR_NOACCESS,
4990 &spr_read_mas73, &spr_write_mas73,
4991 0x00000000);
4992 ivpr_mask = (target_ulong)~0xFFFFULL;
4993 }
4994
4995 if (version == fsl_e6500) {
4996 /* Thread identification */
4997 spr_register(env, SPR_TIR, "TIR",
4998 SPR_NOACCESS, SPR_NOACCESS,
4999 &spr_read_generic, SPR_NOACCESS,
5000 0x00000000);
5001 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS",
5002 SPR_NOACCESS, SPR_NOACCESS,
5003 &spr_read_generic, SPR_NOACCESS,
5004 0x00000004);
5005 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS",
5006 SPR_NOACCESS, SPR_NOACCESS,
5007 &spr_read_generic, SPR_NOACCESS,
5008 0x7FFFFFFC);
5009 }
5010
5011 #if !defined(CONFIG_USER_ONLY)
5012 env->nb_tlb = 0;
5013 env->tlb_type = TLB_MAS;
5014 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
5015 env->nb_tlb += booke206_tlb_size(env, i);
5016 }
5017 #endif
5018
5019 init_excp_e200(env, ivpr_mask);
5020 /* Allocate hardware IRQ controller */
5021 ppce500_irq_init(ppc_env_get_cpu(env));
5022 }
5023
5024 static void init_proc_e500v1(CPUPPCState *env)
5025 {
5026 init_proc_e500(env, fsl_e500v1);
5027 }
5028
5029 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
5030 {
5031 DeviceClass *dc = DEVICE_CLASS(oc);
5032 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5033
5034 dc->desc = "e500v1 core";
5035 pcc->init_proc = init_proc_e500v1;
5036 pcc->check_pow = check_pow_hid0;
5037 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
5038 PPC_SPE | PPC_SPE_SINGLE |
5039 PPC_WRTEE | PPC_RFDI |
5040 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5041 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5042 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
5043 pcc->insns_flags2 = PPC2_BOOKE206;
5044 pcc->msr_mask = (1ull << MSR_UCLE) |
5045 (1ull << MSR_SPE) |
5046 (1ull << MSR_POW) |
5047 (1ull << MSR_CE) |
5048 (1ull << MSR_EE) |
5049 (1ull << MSR_PR) |
5050 (1ull << MSR_FP) |
5051 (1ull << MSR_ME) |
5052 (1ull << MSR_FE0) |
5053 (1ull << MSR_DWE) |
5054 (1ull << MSR_DE) |
5055 (1ull << MSR_FE1) |
5056 (1ull << MSR_IR) |
5057 (1ull << MSR_DR);
5058 pcc->mmu_model = POWERPC_MMU_BOOKE206;
5059 pcc->excp_model = POWERPC_EXCP_BOOKE;
5060 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5061 pcc->bfd_mach = bfd_mach_ppc_860;
5062 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
5063 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
5064 POWERPC_FLAG_BUS_CLK;
5065 }
5066
5067 static void init_proc_e500v2(CPUPPCState *env)
5068 {
5069 init_proc_e500(env, fsl_e500v2);
5070 }
5071
5072 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
5073 {
5074 DeviceClass *dc = DEVICE_CLASS(oc);
5075 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5076
5077 dc->desc = "e500v2 core";
5078 pcc->init_proc = init_proc_e500v2;
5079 pcc->check_pow = check_pow_hid0;
5080 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
5081 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
5082 PPC_WRTEE | PPC_RFDI |
5083 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5084 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5085 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
5086 pcc->insns_flags2 = PPC2_BOOKE206;
5087 pcc->msr_mask = (1ull << MSR_UCLE) |
5088 (1ull << MSR_SPE) |
5089 (1ull << MSR_POW) |
5090 (1ull << MSR_CE) |
5091 (1ull << MSR_EE) |
5092 (1ull << MSR_PR) |
5093 (1ull << MSR_FP) |
5094 (1ull << MSR_ME) |
5095 (1ull << MSR_FE0) |
5096 (1ull << MSR_DWE) |
5097 (1ull << MSR_DE) |
5098 (1ull << MSR_FE1) |
5099 (1ull << MSR_IR) |
5100 (1ull << MSR_DR);
5101 pcc->mmu_model = POWERPC_MMU_BOOKE206;
5102 pcc->excp_model = POWERPC_EXCP_BOOKE;
5103 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5104 pcc->bfd_mach = bfd_mach_ppc_860;
5105 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
5106 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
5107 POWERPC_FLAG_BUS_CLK;
5108 }
5109
5110 static void init_proc_e500mc(CPUPPCState *env)
5111 {
5112 init_proc_e500(env, fsl_e500mc);
5113 }
5114
5115 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
5116 {
5117 DeviceClass *dc = DEVICE_CLASS(oc);
5118 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5119
5120 dc->desc = "e500mc core";
5121 pcc->init_proc = init_proc_e500mc;
5122 pcc->check_pow = check_pow_none;
5123 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
5124 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
5125 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5126 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5127 PPC_FLOAT | PPC_FLOAT_FRES |
5128 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
5129 PPC_FLOAT_STFIWX | PPC_WAIT |
5130 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
5131 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
5132 pcc->msr_mask = (1ull << MSR_GS) |
5133 (1ull << MSR_UCLE) |
5134 (1ull << MSR_CE) |
5135 (1ull << MSR_EE) |
5136 (1ull << MSR_PR) |
5137 (1ull << MSR_FP) |
5138 (1ull << MSR_ME) |
5139 (1ull << MSR_FE0) |
5140 (1ull << MSR_DE) |
5141 (1ull << MSR_FE1) |
5142 (1ull << MSR_IR) |
5143 (1ull << MSR_DR) |
5144 (1ull << MSR_PX) |
5145 (1ull << MSR_RI);
5146 pcc->mmu_model = POWERPC_MMU_BOOKE206;
5147 pcc->excp_model = POWERPC_EXCP_BOOKE;
5148 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5149 /* FIXME: figure out the correct flag for e500mc */
5150 pcc->bfd_mach = bfd_mach_ppc_e500;
5151 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
5152 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5153 }
5154
5155 #ifdef TARGET_PPC64
5156 static void init_proc_e5500(CPUPPCState *env)
5157 {
5158 init_proc_e500(env, fsl_e5500);
5159 }
5160
5161 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
5162 {
5163 DeviceClass *dc = DEVICE_CLASS(oc);
5164 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5165
5166 dc->desc = "e5500 core";
5167 pcc->init_proc = init_proc_e5500;
5168 pcc->check_pow = check_pow_none;
5169 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
5170 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
5171 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5172 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5173 PPC_FLOAT | PPC_FLOAT_FRES |
5174 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
5175 PPC_FLOAT_STFIWX | PPC_WAIT |
5176 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
5177 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
5178 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | \
5179 PPC2_FP_CVT_S64;
5180 pcc->msr_mask = (1ull << MSR_CM) |
5181 (1ull << MSR_GS) |
5182 (1ull << MSR_UCLE) |
5183 (1ull << MSR_CE) |
5184 (1ull << MSR_EE) |
5185 (1ull << MSR_PR) |
5186 (1ull << MSR_FP) |
5187 (1ull << MSR_ME) |
5188 (1ull << MSR_FE0) |
5189 (1ull << MSR_DE) |
5190 (1ull << MSR_FE1) |
5191 (1ull << MSR_IR) |
5192 (1ull << MSR_DR) |
5193 (1ull << MSR_PX) |
5194 (1ull << MSR_RI);
5195 pcc->mmu_model = POWERPC_MMU_BOOKE206;
5196 pcc->excp_model = POWERPC_EXCP_BOOKE;
5197 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5198 /* FIXME: figure out the correct flag for e5500 */
5199 pcc->bfd_mach = bfd_mach_ppc_e500;
5200 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
5201 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5202 }
5203
5204 static void init_proc_e6500(CPUPPCState *env)
5205 {
5206 init_proc_e500(env, fsl_e6500);
5207 }
5208
5209 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data)
5210 {
5211 DeviceClass *dc = DEVICE_CLASS(oc);
5212 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5213
5214 dc->desc = "e6500 core";
5215 pcc->init_proc = init_proc_e6500;
5216 pcc->check_pow = check_pow_none;
5217 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
5218 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
5219 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5220 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5221 PPC_FLOAT | PPC_FLOAT_FRES |
5222 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
5223 PPC_FLOAT_STFIWX | PPC_WAIT |
5224 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
5225 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC;
5226 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | \
5227 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206;
5228 pcc->msr_mask = (1ull << MSR_CM) |
5229 (1ull << MSR_GS) |
5230 (1ull << MSR_UCLE) |
5231 (1ull << MSR_CE) |
5232 (1ull << MSR_EE) |
5233 (1ull << MSR_PR) |
5234 (1ull << MSR_FP) |
5235 (1ull << MSR_ME) |
5236 (1ull << MSR_FE0) |
5237 (1ull << MSR_DE) |
5238 (1ull << MSR_FE1) |
5239 (1ull << MSR_IS) |
5240 (1ull << MSR_DS) |
5241 (1ull << MSR_PX) |
5242 (1ull << MSR_RI) |
5243 (1ull << MSR_VR);
5244 pcc->mmu_model = POWERPC_MMU_BOOKE206;
5245 pcc->excp_model = POWERPC_EXCP_BOOKE;
5246 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5247 pcc->bfd_mach = bfd_mach_ppc_e500;
5248 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
5249 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE;
5250 }
5251
5252 #endif
5253
5254 /* Non-embedded PowerPC */
5255
5256 #define POWERPC_MSRR_601 (0x0000000000001040ULL)
5257
5258 static void init_proc_601(CPUPPCState *env)
5259 {
5260 gen_spr_ne_601(env);
5261 gen_spr_sdr1(env);
5262 gen_spr_601(env);
5263 /* Hardware implementation registers */
5264 /* XXX : not implemented */
5265 spr_register(env, SPR_HID0, "HID0",
5266 SPR_NOACCESS, SPR_NOACCESS,
5267 &spr_read_generic, &spr_write_hid0_601,
5268 0x80010080);
5269 /* XXX : not implemented */
5270 spr_register(env, SPR_HID1, "HID1",
5271 SPR_NOACCESS, SPR_NOACCESS,
5272 &spr_read_generic, &spr_write_generic,
5273 0x00000000);
5274 /* XXX : not implemented */
5275 spr_register(env, SPR_601_HID2, "HID2",
5276 SPR_NOACCESS, SPR_NOACCESS,
5277 &spr_read_generic, &spr_write_generic,
5278 0x00000000);
5279 /* XXX : not implemented */
5280 spr_register(env, SPR_601_HID5, "HID5",
5281 SPR_NOACCESS, SPR_NOACCESS,
5282 &spr_read_generic, &spr_write_generic,
5283 0x00000000);
5284 /* Memory management */
5285 init_excp_601(env);
5286 /*
5287 * XXX: beware that dcache line size is 64
5288 * but dcbz uses 32 bytes "sectors"
5289 * XXX: this breaks clcs instruction !
5290 */
5291 env->dcache_line_size = 32;
5292 env->icache_line_size = 64;
5293 /* Allocate hardware IRQ controller */
5294 ppc6xx_irq_init(ppc_env_get_cpu(env));
5295 }
5296
5297 POWERPC_FAMILY(601)(ObjectClass *oc, void *data)
5298 {
5299 DeviceClass *dc = DEVICE_CLASS(oc);
5300 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5301
5302 dc->desc = "PowerPC 601";
5303 pcc->init_proc = init_proc_601;
5304 pcc->check_pow = check_pow_none;
5305 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
5306 PPC_FLOAT |
5307 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5308 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
5309 PPC_SEGMENT | PPC_EXTERN;
5310 pcc->msr_mask = (1ull << MSR_EE) |
5311 (1ull << MSR_PR) |
5312 (1ull << MSR_FP) |
5313 (1ull << MSR_ME) |
5314 (1ull << MSR_FE0) |
5315 (1ull << MSR_SE) |
5316 (1ull << MSR_FE1) |
5317 (1ull << MSR_EP) |
5318 (1ull << MSR_IR) |
5319 (1ull << MSR_DR);
5320 pcc->mmu_model = POWERPC_MMU_601;
5321 #if defined(CONFIG_SOFTMMU)
5322 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5323 #endif
5324 pcc->excp_model = POWERPC_EXCP_601;
5325 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5326 pcc->bfd_mach = bfd_mach_ppc_601;
5327 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
5328 }
5329
5330 #define POWERPC_MSRR_601v (0x0000000000001040ULL)
5331
5332 static void init_proc_601v(CPUPPCState *env)
5333 {
5334 init_proc_601(env);
5335 /* XXX : not implemented */
5336 spr_register(env, SPR_601_HID15, "HID15",
5337 SPR_NOACCESS, SPR_NOACCESS,
5338 &spr_read_generic, &spr_write_generic,
5339 0x00000000);
5340 }
5341
5342 POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
5343 {
5344 DeviceClass *dc = DEVICE_CLASS(oc);
5345 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5346
5347 dc->desc = "PowerPC 601v";
5348 pcc->init_proc = init_proc_601v;
5349 pcc->check_pow = check_pow_none;
5350 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
5351 PPC_FLOAT |
5352 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5353 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
5354 PPC_SEGMENT | PPC_EXTERN;
5355 pcc->msr_mask = (1ull << MSR_EE) |
5356 (1ull << MSR_PR) |
5357 (1ull << MSR_FP) |
5358 (1ull << MSR_ME) |
5359 (1ull << MSR_FE0) |
5360 (1ull << MSR_SE) |
5361 (1ull << MSR_FE1) |
5362 (1ull << MSR_EP) |
5363 (1ull << MSR_IR) |
5364 (1ull << MSR_DR);
5365 pcc->mmu_model = POWERPC_MMU_601;
5366 #if defined(CONFIG_SOFTMMU)
5367 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5368 #endif
5369 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5370 pcc->bfd_mach = bfd_mach_ppc_601;
5371 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
5372 }
5373
5374 static void init_proc_602(CPUPPCState *env)
5375 {
5376 gen_spr_ne_601(env);
5377 gen_spr_sdr1(env);
5378 gen_spr_602(env);
5379 /* Time base */
5380 gen_tbl(env);
5381 /* hardware implementation registers */
5382 /* XXX : not implemented */
5383 spr_register(env, SPR_HID0, "HID0",
5384 SPR_NOACCESS, SPR_NOACCESS,
5385 &spr_read_generic, &spr_write_generic,
5386 0x00000000);
5387 /* XXX : not implemented */
5388 spr_register(env, SPR_HID1, "HID1",
5389 SPR_NOACCESS, SPR_NOACCESS,
5390 &spr_read_generic, &spr_write_generic,
5391 0x00000000);
5392 /* Memory management */
5393 gen_low_BATs(env);
5394 gen_6xx_7xx_soft_tlb(env, 64, 2);
5395 init_excp_602(env);
5396 env->dcache_line_size = 32;
5397 env->icache_line_size = 32;
5398 /* Allocate hardware IRQ controller */
5399 ppc6xx_irq_init(ppc_env_get_cpu(env));
5400 }
5401
5402 POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
5403 {
5404 DeviceClass *dc = DEVICE_CLASS(oc);
5405 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5406
5407 dc->desc = "PowerPC 602";
5408 pcc->init_proc = init_proc_602;
5409 pcc->check_pow = check_pow_hid0;
5410 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5411 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5412 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5413 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5414 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5415 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC |
5416 PPC_SEGMENT | PPC_602_SPEC;
5417 pcc->msr_mask = (1ull << MSR_VSX) |
5418 (1ull << MSR_SA) |
5419 (1ull << MSR_POW) |
5420 (1ull << MSR_TGPR) |
5421 (1ull << MSR_ILE) |
5422 (1ull << MSR_EE) |
5423 (1ull << MSR_PR) |
5424 (1ull << MSR_FP) |
5425 (1ull << MSR_ME) |
5426 (1ull << MSR_FE0) |
5427 (1ull << MSR_SE) |
5428 (1ull << MSR_DE) |
5429 (1ull << MSR_FE1) |
5430 (1ull << MSR_EP) |
5431 (1ull << MSR_IR) |
5432 (1ull << MSR_DR) |
5433 (1ull << MSR_RI) |
5434 (1ull << MSR_LE);
5435 /* XXX: 602 MMU is quite specific. Should add a special case */
5436 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5437 pcc->excp_model = POWERPC_EXCP_602;
5438 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5439 pcc->bfd_mach = bfd_mach_ppc_602;
5440 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5441 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5442 }
5443
5444 static void init_proc_603(CPUPPCState *env)
5445 {
5446 gen_spr_ne_601(env);
5447 gen_spr_sdr1(env);
5448 gen_spr_603(env);
5449 /* Time base */
5450 gen_tbl(env);
5451 /* hardware implementation registers */
5452 /* XXX : not implemented */
5453 spr_register(env, SPR_HID0, "HID0",
5454 SPR_NOACCESS, SPR_NOACCESS,
5455 &spr_read_generic, &spr_write_generic,
5456 0x00000000);
5457 /* XXX : not implemented */
5458 spr_register(env, SPR_HID1, "HID1",
5459 SPR_NOACCESS, SPR_NOACCESS,
5460 &spr_read_generic, &spr_write_generic,
5461 0x00000000);
5462 /* Memory management */
5463 gen_low_BATs(env);
5464 gen_6xx_7xx_soft_tlb(env, 64, 2);
5465 init_excp_603(env);
5466 env->dcache_line_size = 32;
5467 env->icache_line_size = 32;
5468 /* Allocate hardware IRQ controller */
5469 ppc6xx_irq_init(ppc_env_get_cpu(env));
5470 }
5471
5472 POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
5473 {
5474 DeviceClass *dc = DEVICE_CLASS(oc);
5475 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5476
5477 dc->desc = "PowerPC 603";
5478 pcc->init_proc = init_proc_603;
5479 pcc->check_pow = check_pow_hid0;
5480 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5481 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5482 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5483 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5484 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5485 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5486 PPC_SEGMENT | PPC_EXTERN;
5487 pcc->msr_mask = (1ull << MSR_POW) |
5488 (1ull << MSR_TGPR) |
5489 (1ull << MSR_ILE) |
5490 (1ull << MSR_EE) |
5491 (1ull << MSR_PR) |
5492 (1ull << MSR_FP) |
5493 (1ull << MSR_ME) |
5494 (1ull << MSR_FE0) |
5495 (1ull << MSR_SE) |
5496 (1ull << MSR_DE) |
5497 (1ull << MSR_FE1) |
5498 (1ull << MSR_EP) |
5499 (1ull << MSR_IR) |
5500 (1ull << MSR_DR) |
5501 (1ull << MSR_RI) |
5502 (1ull << MSR_LE);
5503 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5504 pcc->excp_model = POWERPC_EXCP_603;
5505 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5506 pcc->bfd_mach = bfd_mach_ppc_603;
5507 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5508 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5509 }
5510
5511 static void init_proc_603E(CPUPPCState *env)
5512 {
5513 gen_spr_ne_601(env);
5514 gen_spr_sdr1(env);
5515 gen_spr_603(env);
5516 /* Time base */
5517 gen_tbl(env);
5518 /* hardware implementation registers */
5519 /* XXX : not implemented */
5520 spr_register(env, SPR_HID0, "HID0",
5521 SPR_NOACCESS, SPR_NOACCESS,
5522 &spr_read_generic, &spr_write_generic,
5523 0x00000000);
5524 /* XXX : not implemented */
5525 spr_register(env, SPR_HID1, "HID1",
5526 SPR_NOACCESS, SPR_NOACCESS,
5527 &spr_read_generic, &spr_write_generic,
5528 0x00000000);
5529 /* Memory management */
5530 gen_low_BATs(env);
5531 gen_6xx_7xx_soft_tlb(env, 64, 2);
5532 init_excp_603(env);
5533 env->dcache_line_size = 32;
5534 env->icache_line_size = 32;
5535 /* Allocate hardware IRQ controller */
5536 ppc6xx_irq_init(ppc_env_get_cpu(env));
5537 }
5538
5539 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
5540 {
5541 DeviceClass *dc = DEVICE_CLASS(oc);
5542 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5543
5544 dc->desc = "PowerPC 603e";
5545 pcc->init_proc = init_proc_603E;
5546 pcc->check_pow = check_pow_hid0;
5547 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5548 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5549 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5550 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5551 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5552 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5553 PPC_SEGMENT | PPC_EXTERN;
5554 pcc->msr_mask = (1ull << MSR_POW) |
5555 (1ull << MSR_TGPR) |
5556 (1ull << MSR_ILE) |
5557 (1ull << MSR_EE) |
5558 (1ull << MSR_PR) |
5559 (1ull << MSR_FP) |
5560 (1ull << MSR_ME) |
5561 (1ull << MSR_FE0) |
5562 (1ull << MSR_SE) |
5563 (1ull << MSR_DE) |
5564 (1ull << MSR_FE1) |
5565 (1ull << MSR_EP) |
5566 (1ull << MSR_IR) |
5567 (1ull << MSR_DR) |
5568 (1ull << MSR_RI) |
5569 (1ull << MSR_LE);
5570 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5571 pcc->excp_model = POWERPC_EXCP_603E;
5572 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5573 pcc->bfd_mach = bfd_mach_ppc_ec603e;
5574 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5575 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5576 }
5577
5578 static void init_proc_604(CPUPPCState *env)
5579 {
5580 gen_spr_ne_601(env);
5581 gen_spr_sdr1(env);
5582 gen_spr_604(env);
5583 /* Time base */
5584 gen_tbl(env);
5585 /* Hardware implementation registers */
5586 /* XXX : not implemented */
5587 spr_register(env, SPR_HID0, "HID0",
5588 SPR_NOACCESS, SPR_NOACCESS,
5589 &spr_read_generic, &spr_write_generic,
5590 0x00000000);
5591 /* Memory management */
5592 gen_low_BATs(env);
5593 init_excp_604(env);
5594 env->dcache_line_size = 32;
5595 env->icache_line_size = 32;
5596 /* Allocate hardware IRQ controller */
5597 ppc6xx_irq_init(ppc_env_get_cpu(env));
5598 }
5599
5600 POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
5601 {
5602 DeviceClass *dc = DEVICE_CLASS(oc);
5603 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5604
5605 dc->desc = "PowerPC 604";
5606 pcc->init_proc = init_proc_604;
5607 pcc->check_pow = check_pow_nocheck;
5608 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5609 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5610 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5611 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5612 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5613 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5614 PPC_SEGMENT | PPC_EXTERN;
5615 pcc->msr_mask = (1ull << MSR_POW) |
5616 (1ull << MSR_ILE) |
5617 (1ull << MSR_EE) |
5618 (1ull << MSR_PR) |
5619 (1ull << MSR_FP) |
5620 (1ull << MSR_ME) |
5621 (1ull << MSR_FE0) |
5622 (1ull << MSR_SE) |
5623 (1ull << MSR_DE) |
5624 (1ull << MSR_FE1) |
5625 (1ull << MSR_EP) |
5626 (1ull << MSR_IR) |
5627 (1ull << MSR_DR) |
5628 (1ull << MSR_PMM) |
5629 (1ull << MSR_RI) |
5630 (1ull << MSR_LE);
5631 pcc->mmu_model = POWERPC_MMU_32B;
5632 #if defined(CONFIG_SOFTMMU)
5633 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5634 #endif
5635 pcc->excp_model = POWERPC_EXCP_604;
5636 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5637 pcc->bfd_mach = bfd_mach_ppc_604;
5638 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5639 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5640 }
5641
5642 static void init_proc_604E(CPUPPCState *env)
5643 {
5644 gen_spr_ne_601(env);
5645 gen_spr_sdr1(env);
5646 gen_spr_604(env);
5647 /* XXX : not implemented */
5648 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
5649 SPR_NOACCESS, SPR_NOACCESS,
5650 &spr_read_generic, &spr_write_generic,
5651 0x00000000);
5652 /* XXX : not implemented */
5653 spr_register(env, SPR_7XX_PMC3, "PMC3",
5654 SPR_NOACCESS, SPR_NOACCESS,
5655 &spr_read_generic, &spr_write_generic,
5656 0x00000000);
5657 /* XXX : not implemented */
5658 spr_register(env, SPR_7XX_PMC4, "PMC4",
5659 SPR_NOACCESS, SPR_NOACCESS,
5660 &spr_read_generic, &spr_write_generic,
5661 0x00000000);
5662 /* Time base */
5663 gen_tbl(env);
5664 /* Hardware implementation registers */
5665 /* XXX : not implemented */
5666 spr_register(env, SPR_HID0, "HID0",
5667 SPR_NOACCESS, SPR_NOACCESS,
5668 &spr_read_generic, &spr_write_generic,
5669 0x00000000);
5670 /* XXX : not implemented */
5671 spr_register(env, SPR_HID1, "HID1",
5672 SPR_NOACCESS, SPR_NOACCESS,
5673 &spr_read_generic, &spr_write_generic,
5674 0x00000000);
5675 /* Memory management */
5676 gen_low_BATs(env);
5677 init_excp_604(env);
5678 env->dcache_line_size = 32;
5679 env->icache_line_size = 32;
5680 /* Allocate hardware IRQ controller */
5681 ppc6xx_irq_init(ppc_env_get_cpu(env));
5682 }
5683
5684 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
5685 {
5686 DeviceClass *dc = DEVICE_CLASS(oc);
5687 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5688
5689 dc->desc = "PowerPC 604E";
5690 pcc->init_proc = init_proc_604E;
5691 pcc->check_pow = check_pow_nocheck;
5692 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5693 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5694 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5695 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5696 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5697 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5698 PPC_SEGMENT | PPC_EXTERN;
5699 pcc->msr_mask = (1ull << MSR_POW) |
5700 (1ull << MSR_ILE) |
5701 (1ull << MSR_EE) |
5702 (1ull << MSR_PR) |
5703 (1ull << MSR_FP) |
5704 (1ull << MSR_ME) |
5705 (1ull << MSR_FE0) |
5706 (1ull << MSR_SE) |
5707 (1ull << MSR_DE) |
5708 (1ull << MSR_FE1) |
5709 (1ull << MSR_EP) |
5710 (1ull << MSR_IR) |
5711 (1ull << MSR_DR) |
5712 (1ull << MSR_PMM) |
5713 (1ull << MSR_RI) |
5714 (1ull << MSR_LE);
5715 pcc->mmu_model = POWERPC_MMU_32B;
5716 #if defined(CONFIG_SOFTMMU)
5717 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5718 #endif
5719 pcc->excp_model = POWERPC_EXCP_604;
5720 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5721 pcc->bfd_mach = bfd_mach_ppc_604;
5722 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5723 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5724 }
5725
5726 static void init_proc_740(CPUPPCState *env)
5727 {
5728 gen_spr_ne_601(env);
5729 gen_spr_sdr1(env);
5730 gen_spr_7xx(env);
5731 /* Time base */
5732 gen_tbl(env);
5733 /* Thermal management */
5734 gen_spr_thrm(env);
5735 /* Hardware implementation registers */
5736 /* XXX : not implemented */
5737 spr_register(env, SPR_HID0, "HID0",
5738 SPR_NOACCESS, SPR_NOACCESS,
5739 &spr_read_generic, &spr_write_generic,
5740 0x00000000);
5741 /* XXX : not implemented */
5742 spr_register(env, SPR_HID1, "HID1",
5743 SPR_NOACCESS, SPR_NOACCESS,
5744 &spr_read_generic, &spr_write_generic,
5745 0x00000000);
5746 /* Memory management */
5747 gen_low_BATs(env);
5748 init_excp_7x0(env);
5749 env->dcache_line_size = 32;
5750 env->icache_line_size = 32;
5751 /* Allocate hardware IRQ controller */
5752 ppc6xx_irq_init(ppc_env_get_cpu(env));
5753 }
5754
5755 POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
5756 {
5757 DeviceClass *dc = DEVICE_CLASS(oc);
5758 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5759
5760 dc->desc = "PowerPC 740";
5761 pcc->init_proc = init_proc_740;
5762 pcc->check_pow = check_pow_hid0;
5763 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5764 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5765 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5766 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5767 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5768 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5769 PPC_SEGMENT | PPC_EXTERN;
5770 pcc->msr_mask = (1ull << MSR_POW) |
5771 (1ull << MSR_ILE) |
5772 (1ull << MSR_EE) |
5773 (1ull << MSR_PR) |
5774 (1ull << MSR_FP) |
5775 (1ull << MSR_ME) |
5776 (1ull << MSR_FE0) |
5777 (1ull << MSR_SE) |
5778 (1ull << MSR_DE) |
5779 (1ull << MSR_FE1) |
5780 (1ull << MSR_EP) |
5781 (1ull << MSR_IR) |
5782 (1ull << MSR_DR) |
5783 (1ull << MSR_PMM) |
5784 (1ull << MSR_RI) |
5785 (1ull << MSR_LE);
5786 pcc->mmu_model = POWERPC_MMU_32B;
5787 #if defined(CONFIG_SOFTMMU)
5788 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5789 #endif
5790 pcc->excp_model = POWERPC_EXCP_7x0;
5791 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5792 pcc->bfd_mach = bfd_mach_ppc_750;
5793 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5794 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5795 }
5796
5797 static void init_proc_750(CPUPPCState *env)
5798 {
5799 gen_spr_ne_601(env);
5800 gen_spr_sdr1(env);
5801 gen_spr_7xx(env);
5802 /* XXX : not implemented */
5803 spr_register(env, SPR_L2CR, "L2CR",
5804 SPR_NOACCESS, SPR_NOACCESS,
5805 &spr_read_generic, spr_access_nop,
5806 0x00000000);
5807 /* Time base */
5808 gen_tbl(env);
5809 /* Thermal management */
5810 gen_spr_thrm(env);
5811 /* Hardware implementation registers */
5812 /* XXX : not implemented */
5813 spr_register(env, SPR_HID0, "HID0",
5814 SPR_NOACCESS, SPR_NOACCESS,
5815 &spr_read_generic, &spr_write_generic,
5816 0x00000000);
5817 /* XXX : not implemented */
5818 spr_register(env, SPR_HID1, "HID1",
5819 SPR_NOACCESS, SPR_NOACCESS,
5820 &spr_read_generic, &spr_write_generic,
5821 0x00000000);
5822 /* Memory management */
5823 gen_low_BATs(env);
5824 /*
5825 * XXX: high BATs are also present but are known to be bugged on
5826 * die version 1.x
5827 */
5828 init_excp_7x0(env);
5829 env->dcache_line_size = 32;
5830 env->icache_line_size = 32;
5831 /* Allocate hardware IRQ controller */
5832 ppc6xx_irq_init(ppc_env_get_cpu(env));
5833 }
5834
5835 POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
5836 {
5837 DeviceClass *dc = DEVICE_CLASS(oc);
5838 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5839
5840 dc->desc = "PowerPC 750";
5841 pcc->init_proc = init_proc_750;
5842 pcc->check_pow = check_pow_hid0;
5843 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5844 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5845 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5846 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5847 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5848 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5849 PPC_SEGMENT | PPC_EXTERN;
5850 pcc->msr_mask = (1ull << MSR_POW) |
5851 (1ull << MSR_ILE) |
5852 (1ull << MSR_EE) |
5853 (1ull << MSR_PR) |
5854 (1ull << MSR_FP) |
5855 (1ull << MSR_ME) |
5856 (1ull << MSR_FE0) |
5857 (1ull << MSR_SE) |
5858 (1ull << MSR_DE) |
5859 (1ull << MSR_FE1) |
5860 (1ull << MSR_EP) |
5861 (1ull << MSR_IR) |
5862 (1ull << MSR_DR) |
5863 (1ull << MSR_PMM) |
5864 (1ull << MSR_RI) |
5865 (1ull << MSR_LE);
5866 pcc->mmu_model = POWERPC_MMU_32B;
5867 #if defined(CONFIG_SOFTMMU)
5868 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5869 #endif
5870 pcc->excp_model = POWERPC_EXCP_7x0;
5871 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5872 pcc->bfd_mach = bfd_mach_ppc_750;
5873 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5874 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5875 }
5876
5877 static void init_proc_750cl(CPUPPCState *env)
5878 {
5879 gen_spr_ne_601(env);
5880 gen_spr_sdr1(env);
5881 gen_spr_7xx(env);
5882 /* XXX : not implemented */
5883 spr_register(env, SPR_L2CR, "L2CR",
5884 SPR_NOACCESS, SPR_NOACCESS,
5885 &spr_read_generic, spr_access_nop,
5886 0x00000000);
5887 /* Time base */
5888 gen_tbl(env);
5889 /* Thermal management */
5890 /* Those registers are fake on 750CL */
5891 spr_register(env, SPR_THRM1, "THRM1",
5892 SPR_NOACCESS, SPR_NOACCESS,
5893 &spr_read_generic, &spr_write_generic,
5894 0x00000000);
5895 spr_register(env, SPR_THRM2, "THRM2",
5896 SPR_NOACCESS, SPR_NOACCESS,
5897 &spr_read_generic, &spr_write_generic,
5898 0x00000000);
5899 spr_register(env, SPR_THRM3, "THRM3",
5900 SPR_NOACCESS, SPR_NOACCESS,
5901 &spr_read_generic, &spr_write_generic,
5902 0x00000000);
5903 /* XXX: not implemented */
5904 spr_register(env, SPR_750_TDCL, "TDCL",
5905 SPR_NOACCESS, SPR_NOACCESS,
5906 &spr_read_generic, &spr_write_generic,
5907 0x00000000);
5908 spr_register(env, SPR_750_TDCH, "TDCH",
5909 SPR_NOACCESS, SPR_NOACCESS,
5910 &spr_read_generic, &spr_write_generic,
5911 0x00000000);
5912 /* DMA */
5913 /* XXX : not implemented */
5914 spr_register(env, SPR_750_WPAR, "WPAR",
5915 SPR_NOACCESS, SPR_NOACCESS,
5916 &spr_read_generic, &spr_write_generic,
5917 0x00000000);
5918 spr_register(env, SPR_750_DMAL, "DMAL",
5919 SPR_NOACCESS, SPR_NOACCESS,
5920 &spr_read_generic, &spr_write_generic,
5921 0x00000000);
5922 spr_register(env, SPR_750_DMAU, "DMAU",
5923 SPR_NOACCESS, SPR_NOACCESS,
5924 &spr_read_generic, &spr_write_generic,
5925 0x00000000);
5926 /* Hardware implementation registers */
5927 /* XXX : not implemented */
5928 spr_register(env, SPR_HID0, "HID0",
5929 SPR_NOACCESS, SPR_NOACCESS,
5930 &spr_read_generic, &spr_write_generic,
5931 0x00000000);
5932 /* XXX : not implemented */
5933 spr_register(env, SPR_HID1, "HID1",
5934 SPR_NOACCESS, SPR_NOACCESS,
5935 &spr_read_generic, &spr_write_generic,
5936 0x00000000);
5937 /* XXX : not implemented */
5938 spr_register(env, SPR_750CL_HID2, "HID2",
5939 SPR_NOACCESS, SPR_NOACCESS,
5940 &spr_read_generic, &spr_write_generic,
5941 0x00000000);
5942 /* XXX : not implemented */
5943 spr_register(env, SPR_750CL_HID4, "HID4",
5944 SPR_NOACCESS, SPR_NOACCESS,
5945 &spr_read_generic, &spr_write_generic,
5946 0x00000000);
5947 /* Quantization registers */
5948 /* XXX : not implemented */
5949 spr_register(env, SPR_750_GQR0, "GQR0",
5950 SPR_NOACCESS, SPR_NOACCESS,
5951 &spr_read_generic, &spr_write_generic,
5952 0x00000000);
5953 /* XXX : not implemented */
5954 spr_register(env, SPR_750_GQR1, "GQR1",
5955 SPR_NOACCESS, SPR_NOACCESS,
5956 &spr_read_generic, &spr_write_generic,
5957 0x00000000);
5958 /* XXX : not implemented */
5959 spr_register(env, SPR_750_GQR2, "GQR2",
5960 SPR_NOACCESS, SPR_NOACCESS,
5961 &spr_read_generic, &spr_write_generic,
5962 0x00000000);
5963 /* XXX : not implemented */
5964 spr_register(env, SPR_750_GQR3, "GQR3",
5965 SPR_NOACCESS, SPR_NOACCESS,
5966 &spr_read_generic, &spr_write_generic,
5967 0x00000000);
5968 /* XXX : not implemented */
5969 spr_register(env, SPR_750_GQR4, "GQR4",
5970 SPR_NOACCESS, SPR_NOACCESS,
5971 &spr_read_generic, &spr_write_generic,
5972 0x00000000);
5973 /* XXX : not implemented */
5974 spr_register(env, SPR_750_GQR5, "GQR5",
5975 SPR_NOACCESS, SPR_NOACCESS,
5976 &spr_read_generic, &spr_write_generic,
5977 0x00000000);
5978 /* XXX : not implemented */
5979 spr_register(env, SPR_750_GQR6, "GQR6",
5980 SPR_NOACCESS, SPR_NOACCESS,
5981 &spr_read_generic, &spr_write_generic,
5982 0x00000000);
5983 /* XXX : not implemented */
5984 spr_register(env, SPR_750_GQR7, "GQR7",
5985 SPR_NOACCESS, SPR_NOACCESS,
5986 &spr_read_generic, &spr_write_generic,
5987 0x00000000);
5988 /* Memory management */
5989 gen_low_BATs(env);
5990 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
5991 gen_high_BATs(env);
5992 init_excp_750cl(env);
5993 env->dcache_line_size = 32;
5994 env->icache_line_size = 32;
5995 /* Allocate hardware IRQ controller */
5996 ppc6xx_irq_init(ppc_env_get_cpu(env));
5997 }
5998
5999 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
6000 {
6001 DeviceClass *dc = DEVICE_CLASS(oc);
6002 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6003
6004 dc->desc = "PowerPC 750 CL";
6005 pcc->init_proc = init_proc_750cl;
6006 pcc->check_pow = check_pow_hid0;
6007 /*
6008 * XXX: not implemented:
6009 * cache lock instructions:
6010 * dcbz_l
6011 * floating point paired instructions
6012 * psq_lux
6013 * psq_lx
6014 * psq_stux
6015 * psq_stx
6016 * ps_abs
6017 * ps_add
6018 * ps_cmpo0
6019 * ps_cmpo1
6020 * ps_cmpu0
6021 * ps_cmpu1
6022 * ps_div
6023 * ps_madd
6024 * ps_madds0
6025 * ps_madds1
6026 * ps_merge00
6027 * ps_merge01
6028 * ps_merge10
6029 * ps_merge11
6030 * ps_mr
6031 * ps_msub
6032 * ps_mul
6033 * ps_muls0
6034 * ps_muls1
6035 * ps_nabs
6036 * ps_neg
6037 * ps_nmadd
6038 * ps_nmsub
6039 * ps_res
6040 * ps_rsqrte
6041 * ps_sel
6042 * ps_sub
6043 * ps_sum0
6044 * ps_sum1
6045 */
6046 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6047 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6048 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6049 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6050 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6051 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6052 PPC_SEGMENT | PPC_EXTERN;
6053 pcc->msr_mask = (1ull << MSR_POW) |
6054 (1ull << MSR_ILE) |
6055 (1ull << MSR_EE) |
6056 (1ull << MSR_PR) |
6057 (1ull << MSR_FP) |
6058 (1ull << MSR_ME) |
6059 (1ull << MSR_FE0) |
6060 (1ull << MSR_SE) |
6061 (1ull << MSR_DE) |
6062 (1ull << MSR_FE1) |
6063 (1ull << MSR_EP) |
6064 (1ull << MSR_IR) |
6065 (1ull << MSR_DR) |
6066 (1ull << MSR_PMM) |
6067 (1ull << MSR_RI) |
6068 (1ull << MSR_LE);
6069 pcc->mmu_model = POWERPC_MMU_32B;
6070 #if defined(CONFIG_SOFTMMU)
6071 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6072 #endif
6073 pcc->excp_model = POWERPC_EXCP_7x0;
6074 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6075 pcc->bfd_mach = bfd_mach_ppc_750;
6076 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6077 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6078 }
6079
6080 static void init_proc_750cx(CPUPPCState *env)
6081 {
6082 gen_spr_ne_601(env);
6083 gen_spr_sdr1(env);
6084 gen_spr_7xx(env);
6085 /* XXX : not implemented */
6086 spr_register(env, SPR_L2CR, "L2CR",
6087 SPR_NOACCESS, SPR_NOACCESS,
6088 &spr_read_generic, spr_access_nop,
6089 0x00000000);
6090 /* Time base */
6091 gen_tbl(env);
6092 /* Thermal management */
6093 gen_spr_thrm(env);
6094 /* This register is not implemented but is present for compatibility */
6095 spr_register(env, SPR_SDA, "SDA",
6096 SPR_NOACCESS, SPR_NOACCESS,
6097 &spr_read_generic, &spr_write_generic,
6098 0x00000000);
6099 /* Hardware implementation registers */
6100 /* XXX : not implemented */
6101 spr_register(env, SPR_HID0, "HID0",
6102 SPR_NOACCESS, SPR_NOACCESS,
6103 &spr_read_generic, &spr_write_generic,
6104 0x00000000);
6105 /* XXX : not implemented */
6106 spr_register(env, SPR_HID1, "HID1",
6107 SPR_NOACCESS, SPR_NOACCESS,
6108 &spr_read_generic, &spr_write_generic,
6109 0x00000000);
6110 /* Memory management */
6111 gen_low_BATs(env);
6112 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
6113 gen_high_BATs(env);
6114 init_excp_750cx(env);
6115 env->dcache_line_size = 32;
6116 env->icache_line_size = 32;
6117 /* Allocate hardware IRQ controller */
6118 ppc6xx_irq_init(ppc_env_get_cpu(env));
6119 }
6120
6121 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
6122 {
6123 DeviceClass *dc = DEVICE_CLASS(oc);
6124 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6125
6126 dc->desc = "PowerPC 750CX";
6127 pcc->init_proc = init_proc_750cx;
6128 pcc->check_pow = check_pow_hid0;
6129 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6130 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6131 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6132 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6133 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6134 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6135 PPC_SEGMENT | PPC_EXTERN;
6136 pcc->msr_mask = (1ull << MSR_POW) |
6137 (1ull << MSR_ILE) |
6138 (1ull << MSR_EE) |
6139 (1ull << MSR_PR) |
6140 (1ull << MSR_FP) |
6141 (1ull << MSR_ME) |
6142 (1ull << MSR_FE0) |
6143 (1ull << MSR_SE) |
6144 (1ull << MSR_DE) |
6145 (1ull << MSR_FE1) |
6146 (1ull << MSR_EP) |
6147 (1ull << MSR_IR) |
6148 (1ull << MSR_DR) |
6149 (1ull << MSR_PMM) |
6150 (1ull << MSR_RI) |
6151 (1ull << MSR_LE);
6152 pcc->mmu_model = POWERPC_MMU_32B;
6153 #if defined(CONFIG_SOFTMMU)
6154 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6155 #endif
6156 pcc->excp_model = POWERPC_EXCP_7x0;
6157 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6158 pcc->bfd_mach = bfd_mach_ppc_750;
6159 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6160 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6161 }
6162
6163 static void init_proc_750fx(CPUPPCState *env)
6164 {
6165 gen_spr_ne_601(env);
6166 gen_spr_sdr1(env);
6167 gen_spr_7xx(env);
6168 /* XXX : not implemented */
6169 spr_register(env, SPR_L2CR, "L2CR",
6170 SPR_NOACCESS, SPR_NOACCESS,
6171 &spr_read_generic, spr_access_nop,
6172 0x00000000);
6173 /* Time base */
6174 gen_tbl(env);
6175 /* Thermal management */
6176 gen_spr_thrm(env);
6177 /* XXX : not implemented */
6178 spr_register(env, SPR_750_THRM4, "THRM4",
6179 SPR_NOACCESS, SPR_NOACCESS,
6180 &spr_read_generic, &spr_write_generic,
6181 0x00000000);
6182 /* Hardware implementation registers */
6183 /* XXX : not implemented */
6184 spr_register(env, SPR_HID0, "HID0",
6185 SPR_NOACCESS, SPR_NOACCESS,
6186 &spr_read_generic, &spr_write_generic,
6187 0x00000000);
6188 /* XXX : not implemented */
6189 spr_register(env, SPR_HID1, "HID1",
6190 SPR_NOACCESS, SPR_NOACCESS,
6191 &spr_read_generic, &spr_write_generic,
6192 0x00000000);
6193 /* XXX : not implemented */
6194 spr_register(env, SPR_750FX_HID2, "HID2",
6195 SPR_NOACCESS, SPR_NOACCESS,
6196 &spr_read_generic, &spr_write_generic,
6197 0x00000000);
6198 /* Memory management */
6199 gen_low_BATs(env);
6200 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
6201 gen_high_BATs(env);
6202 init_excp_7x0(env);
6203 env->dcache_line_size = 32;
6204 env->icache_line_size = 32;
6205 /* Allocate hardware IRQ controller */
6206 ppc6xx_irq_init(ppc_env_get_cpu(env));
6207 }
6208
6209 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
6210 {
6211 DeviceClass *dc = DEVICE_CLASS(oc);
6212 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6213
6214 dc->desc = "PowerPC 750FX";
6215 pcc->init_proc = init_proc_750fx;
6216 pcc->check_pow = check_pow_hid0;
6217 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6218 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6219 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6220 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6221 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6222 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6223 PPC_SEGMENT | PPC_EXTERN;
6224 pcc->msr_mask = (1ull << MSR_POW) |
6225 (1ull << MSR_ILE) |
6226 (1ull << MSR_EE) |
6227 (1ull << MSR_PR) |
6228 (1ull << MSR_FP) |
6229 (1ull << MSR_ME) |
6230 (1ull << MSR_FE0) |
6231 (1ull << MSR_SE) |
6232 (1ull << MSR_DE) |
6233 (1ull << MSR_FE1) |
6234 (1ull << MSR_EP) |
6235 (1ull << MSR_IR) |
6236 (1ull << MSR_DR) |
6237 (1ull << MSR_PMM) |
6238 (1ull << MSR_RI) |
6239 (1ull << MSR_LE);
6240 pcc->mmu_model = POWERPC_MMU_32B;
6241 #if defined(CONFIG_SOFTMMU)
6242 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6243 #endif
6244 pcc->excp_model = POWERPC_EXCP_7x0;
6245 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6246 pcc->bfd_mach = bfd_mach_ppc_750;
6247 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6248 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6249 }
6250
6251 static void init_proc_750gx(CPUPPCState *env)
6252 {
6253 gen_spr_ne_601(env);
6254 gen_spr_sdr1(env);
6255 gen_spr_7xx(env);
6256 /* XXX : not implemented (XXX: different from 750fx) */
6257 spr_register(env, SPR_L2CR, "L2CR",
6258 SPR_NOACCESS, SPR_NOACCESS,
6259 &spr_read_generic, spr_access_nop,
6260 0x00000000);
6261 /* Time base */
6262 gen_tbl(env);
6263 /* Thermal management */
6264 gen_spr_thrm(env);
6265 /* XXX : not implemented */
6266 spr_register(env, SPR_750_THRM4, "THRM4",
6267 SPR_NOACCESS, SPR_NOACCESS,
6268 &spr_read_generic, &spr_write_generic,
6269 0x00000000);
6270 /* Hardware implementation registers */
6271 /* XXX : not implemented (XXX: different from 750fx) */
6272 spr_register(env, SPR_HID0, "HID0",
6273 SPR_NOACCESS, SPR_NOACCESS,
6274 &spr_read_generic, &spr_write_generic,
6275 0x00000000);
6276 /* XXX : not implemented */
6277 spr_register(env, SPR_HID1, "HID1",
6278 SPR_NOACCESS, SPR_NOACCESS,
6279 &spr_read_generic, &spr_write_generic,
6280 0x00000000);
6281 /* XXX : not implemented (XXX: different from 750fx) */
6282 spr_register(env, SPR_750FX_HID2, "HID2",
6283 SPR_NOACCESS, SPR_NOACCESS,
6284 &spr_read_generic, &spr_write_generic,
6285 0x00000000);
6286 /* Memory management */
6287 gen_low_BATs(env);
6288 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
6289 gen_high_BATs(env);
6290 init_excp_7x0(env);
6291 env->dcache_line_size = 32;
6292 env->icache_line_size = 32;
6293 /* Allocate hardware IRQ controller */
6294 ppc6xx_irq_init(ppc_env_get_cpu(env));
6295 }
6296
6297 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
6298 {
6299 DeviceClass *dc = DEVICE_CLASS(oc);
6300 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6301
6302 dc->desc = "PowerPC 750GX";
6303 pcc->init_proc = init_proc_750gx;
6304 pcc->check_pow = check_pow_hid0;
6305 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6306 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6307 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6308 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6309 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6310 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6311 PPC_SEGMENT | PPC_EXTERN;
6312 pcc->msr_mask = (1ull << MSR_POW) |
6313 (1ull << MSR_ILE) |
6314 (1ull << MSR_EE) |
6315 (1ull << MSR_PR) |
6316 (1ull << MSR_FP) |
6317 (1ull << MSR_ME) |
6318 (1ull << MSR_FE0) |
6319 (1ull << MSR_SE) |
6320 (1ull << MSR_DE) |
6321 (1ull << MSR_FE1) |
6322 (1ull << MSR_EP) |
6323 (1ull << MSR_IR) |
6324 (1ull << MSR_DR) |
6325 (1ull << MSR_PMM) |
6326 (1ull << MSR_RI) |
6327 (1ull << MSR_LE);
6328 pcc->mmu_model = POWERPC_MMU_32B;
6329 #if defined(CONFIG_SOFTMMU)
6330 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6331 #endif
6332 pcc->excp_model = POWERPC_EXCP_7x0;
6333 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6334 pcc->bfd_mach = bfd_mach_ppc_750;
6335 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6336 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6337 }
6338
6339 static void init_proc_745(CPUPPCState *env)
6340 {
6341 gen_spr_ne_601(env);
6342 gen_spr_sdr1(env);
6343 gen_spr_7xx(env);
6344 gen_spr_G2_755(env);
6345 /* Time base */
6346 gen_tbl(env);
6347 /* Thermal management */
6348 gen_spr_thrm(env);
6349 /* Hardware implementation registers */
6350 /* XXX : not implemented */
6351 spr_register(env, SPR_HID0, "HID0",
6352 SPR_NOACCESS, SPR_NOACCESS,
6353 &spr_read_generic, &spr_write_generic,
6354 0x00000000);
6355 /* XXX : not implemented */
6356 spr_register(env, SPR_HID1, "HID1",
6357 SPR_NOACCESS, SPR_NOACCESS,
6358 &spr_read_generic, &spr_write_generic,
6359 0x00000000);
6360 /* XXX : not implemented */
6361 spr_register(env, SPR_HID2, "HID2",
6362 SPR_NOACCESS, SPR_NOACCESS,
6363 &spr_read_generic, &spr_write_generic,
6364 0x00000000);
6365 /* Memory management */
6366 gen_low_BATs(env);
6367 gen_high_BATs(env);
6368 gen_6xx_7xx_soft_tlb(env, 64, 2);
6369 init_excp_7x5(env);
6370 env->dcache_line_size = 32;
6371 env->icache_line_size = 32;
6372 /* Allocate hardware IRQ controller */
6373 ppc6xx_irq_init(ppc_env_get_cpu(env));
6374 }
6375
6376 POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
6377 {
6378 DeviceClass *dc = DEVICE_CLASS(oc);
6379 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6380
6381 dc->desc = "PowerPC 745";
6382 pcc->init_proc = init_proc_745;
6383 pcc->check_pow = check_pow_hid0;
6384 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6385 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6386 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6387 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6388 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6389 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
6390 PPC_SEGMENT | PPC_EXTERN;
6391 pcc->msr_mask = (1ull << MSR_POW) |
6392 (1ull << MSR_ILE) |
6393 (1ull << MSR_EE) |
6394 (1ull << MSR_PR) |
6395 (1ull << MSR_FP) |
6396 (1ull << MSR_ME) |
6397 (1ull << MSR_FE0) |
6398 (1ull << MSR_SE) |
6399 (1ull << MSR_DE) |
6400 (1ull << MSR_FE1) |
6401 (1ull << MSR_EP) |
6402 (1ull << MSR_IR) |
6403 (1ull << MSR_DR) |
6404 (1ull << MSR_PMM) |
6405 (1ull << MSR_RI) |
6406 (1ull << MSR_LE);
6407 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
6408 pcc->excp_model = POWERPC_EXCP_7x5;
6409 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6410 pcc->bfd_mach = bfd_mach_ppc_750;
6411 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6412 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6413 }
6414
6415 static void init_proc_755(CPUPPCState *env)
6416 {
6417 gen_spr_ne_601(env);
6418 gen_spr_sdr1(env);
6419 gen_spr_7xx(env);
6420 gen_spr_G2_755(env);
6421 /* Time base */
6422 gen_tbl(env);
6423 /* L2 cache control */
6424 /* XXX : not implemented */
6425 spr_register(env, SPR_L2CR, "L2CR",
6426 SPR_NOACCESS, SPR_NOACCESS,
6427 &spr_read_generic, spr_access_nop,
6428 0x00000000);
6429 /* XXX : not implemented */
6430 spr_register(env, SPR_L2PMCR, "L2PMCR",
6431 SPR_NOACCESS, SPR_NOACCESS,
6432 &spr_read_generic, &spr_write_generic,
6433 0x00000000);
6434 /* Thermal management */
6435 gen_spr_thrm(env);
6436 /* Hardware implementation registers */
6437 /* XXX : not implemented */
6438 spr_register(env, SPR_HID0, "HID0",
6439 SPR_NOACCESS, SPR_NOACCESS,
6440 &spr_read_generic, &spr_write_generic,
6441 0x00000000);
6442 /* XXX : not implemented */
6443 spr_register(env, SPR_HID1, "HID1",
6444 SPR_NOACCESS, SPR_NOACCESS,
6445 &spr_read_generic, &spr_write_generic,
6446 0x00000000);
6447 /* XXX : not implemented */
6448 spr_register(env, SPR_HID2, "HID2",
6449 SPR_NOACCESS, SPR_NOACCESS,
6450 &spr_read_generic, &spr_write_generic,
6451 0x00000000);
6452 /* Memory management */
6453 gen_low_BATs(env);
6454 gen_high_BATs(env);
6455 gen_6xx_7xx_soft_tlb(env, 64, 2);
6456 init_excp_7x5(env);
6457 env->dcache_line_size = 32;
6458 env->icache_line_size = 32;
6459 /* Allocate hardware IRQ controller */
6460 ppc6xx_irq_init(ppc_env_get_cpu(env));
6461 }
6462
6463 POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
6464 {
6465 DeviceClass *dc = DEVICE_CLASS(oc);
6466 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6467
6468 dc->desc = "PowerPC 755";
6469 pcc->init_proc = init_proc_755;
6470 pcc->check_pow = check_pow_hid0;
6471 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6472 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6473 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6474 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6475 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6476 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
6477 PPC_SEGMENT | PPC_EXTERN;
6478 pcc->msr_mask = (1ull << MSR_POW) |
6479 (1ull << MSR_ILE) |
6480 (1ull << MSR_EE) |
6481 (1ull << MSR_PR) |
6482 (1ull << MSR_FP) |
6483 (1ull << MSR_ME) |
6484 (1ull << MSR_FE0) |
6485 (1ull << MSR_SE) |
6486 (1ull << MSR_DE) |
6487 (1ull << MSR_FE1) |
6488 (1ull << MSR_EP) |
6489 (1ull << MSR_IR) |
6490 (1ull << MSR_DR) |
6491 (1ull << MSR_PMM) |
6492 (1ull << MSR_RI) |
6493 (1ull << MSR_LE);
6494 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
6495 pcc->excp_model = POWERPC_EXCP_7x5;
6496 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6497 pcc->bfd_mach = bfd_mach_ppc_750;
6498 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6499 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6500 }
6501
6502 static void init_proc_7400(CPUPPCState *env)
6503 {
6504 gen_spr_ne_601(env);
6505 gen_spr_sdr1(env);
6506 gen_spr_7xx(env);
6507 /* Time base */
6508 gen_tbl(env);
6509 /* 74xx specific SPR */
6510 gen_spr_74xx(env);
6511 /* XXX : not implemented */
6512 spr_register(env, SPR_UBAMR, "UBAMR",
6513 &spr_read_ureg, SPR_NOACCESS,
6514 &spr_read_ureg, SPR_NOACCESS,
6515 0x00000000);
6516 /* XXX: this seems not implemented on all revisions. */
6517 /* XXX : not implemented */
6518 spr_register(env, SPR_MSSCR1, "MSSCR1",
6519 SPR_NOACCESS, SPR_NOACCESS,
6520 &spr_read_generic, &spr_write_generic,
6521 0x00000000);
6522 /* Thermal management */
6523 gen_spr_thrm(env);
6524 /* Memory management */
6525 gen_low_BATs(env);
6526 init_excp_7400(env);
6527 env->dcache_line_size = 32;
6528 env->icache_line_size = 32;
6529 /* Allocate hardware IRQ controller */
6530 ppc6xx_irq_init(ppc_env_get_cpu(env));
6531 }
6532
6533 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
6534 {
6535 DeviceClass *dc = DEVICE_CLASS(oc);
6536 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6537
6538 dc->desc = "PowerPC 7400 (aka G4)";
6539 pcc->init_proc = init_proc_7400;
6540 pcc->check_pow = check_pow_hid0;
6541 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6542 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6543 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6544 PPC_FLOAT_STFIWX |
6545 PPC_CACHE | PPC_CACHE_ICBI |
6546 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6547 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6548 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6549 PPC_MEM_TLBIA |
6550 PPC_SEGMENT | PPC_EXTERN |
6551 PPC_ALTIVEC;
6552 pcc->msr_mask = (1ull << MSR_VR) |
6553 (1ull << MSR_POW) |
6554 (1ull << MSR_ILE) |
6555 (1ull << MSR_EE) |
6556 (1ull << MSR_PR) |
6557 (1ull << MSR_FP) |
6558 (1ull << MSR_ME) |
6559 (1ull << MSR_FE0) |
6560 (1ull << MSR_SE) |
6561 (1ull << MSR_DE) |
6562 (1ull << MSR_FE1) |
6563 (1ull << MSR_EP) |
6564 (1ull << MSR_IR) |
6565 (1ull << MSR_DR) |
6566 (1ull << MSR_PMM) |
6567 (1ull << MSR_RI) |
6568 (1ull << MSR_LE);
6569 pcc->mmu_model = POWERPC_MMU_32B;
6570 #if defined(CONFIG_SOFTMMU)
6571 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6572 #endif
6573 pcc->excp_model = POWERPC_EXCP_74xx;
6574 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6575 pcc->bfd_mach = bfd_mach_ppc_7400;
6576 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6577 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6578 POWERPC_FLAG_BUS_CLK;
6579 }
6580
6581 static void init_proc_7410(CPUPPCState *env)
6582 {
6583 gen_spr_ne_601(env);
6584 gen_spr_sdr1(env);
6585 gen_spr_7xx(env);
6586 /* Time base */
6587 gen_tbl(env);
6588 /* 74xx specific SPR */
6589 gen_spr_74xx(env);
6590 /* XXX : not implemented */
6591 spr_register(env, SPR_UBAMR, "UBAMR",
6592 &spr_read_ureg, SPR_NOACCESS,
6593 &spr_read_ureg, SPR_NOACCESS,
6594 0x00000000);
6595 /* Thermal management */
6596 gen_spr_thrm(env);
6597 /* L2PMCR */
6598 /* XXX : not implemented */
6599 spr_register(env, SPR_L2PMCR, "L2PMCR",
6600 SPR_NOACCESS, SPR_NOACCESS,
6601 &spr_read_generic, &spr_write_generic,
6602 0x00000000);
6603 /* LDSTDB */
6604 /* XXX : not implemented */
6605 spr_register(env, SPR_LDSTDB, "LDSTDB",
6606 SPR_NOACCESS, SPR_NOACCESS,
6607 &spr_read_generic, &spr_write_generic,
6608 0x00000000);
6609 /* Memory management */
6610 gen_low_BATs(env);
6611 init_excp_7400(env);
6612 env->dcache_line_size = 32;
6613 env->icache_line_size = 32;
6614 /* Allocate hardware IRQ controller */
6615 ppc6xx_irq_init(ppc_env_get_cpu(env));
6616 }
6617
6618 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
6619 {
6620 DeviceClass *dc = DEVICE_CLASS(oc);
6621 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6622
6623 dc->desc = "PowerPC 7410 (aka G4)";
6624 pcc->init_proc = init_proc_7410;
6625 pcc->check_pow = check_pow_hid0;
6626 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6627 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6628 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6629 PPC_FLOAT_STFIWX |
6630 PPC_CACHE | PPC_CACHE_ICBI |
6631 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6632 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6633 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6634 PPC_MEM_TLBIA |
6635 PPC_SEGMENT | PPC_EXTERN |
6636 PPC_ALTIVEC;
6637 pcc->msr_mask = (1ull << MSR_VR) |
6638 (1ull << MSR_POW) |
6639 (1ull << MSR_ILE) |
6640 (1ull << MSR_EE) |
6641 (1ull << MSR_PR) |
6642 (1ull << MSR_FP) |
6643 (1ull << MSR_ME) |
6644 (1ull << MSR_FE0) |
6645 (1ull << MSR_SE) |
6646 (1ull << MSR_DE) |
6647 (1ull << MSR_FE1) |
6648 (1ull << MSR_EP) |
6649 (1ull << MSR_IR) |
6650 (1ull << MSR_DR) |
6651 (1ull << MSR_PMM) |
6652 (1ull << MSR_RI) |
6653 (1ull << MSR_LE);
6654 pcc->mmu_model = POWERPC_MMU_32B;
6655 #if defined(CONFIG_SOFTMMU)
6656 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6657 #endif
6658 pcc->excp_model = POWERPC_EXCP_74xx;
6659 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6660 pcc->bfd_mach = bfd_mach_ppc_7400;
6661 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6662 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6663 POWERPC_FLAG_BUS_CLK;
6664 }
6665
6666 static void init_proc_7440(CPUPPCState *env)
6667 {
6668 gen_spr_ne_601(env);
6669 gen_spr_sdr1(env);
6670 gen_spr_7xx(env);
6671 /* Time base */
6672 gen_tbl(env);
6673 /* 74xx specific SPR */
6674 gen_spr_74xx(env);
6675 /* XXX : not implemented */
6676 spr_register(env, SPR_UBAMR, "UBAMR",
6677 &spr_read_ureg, SPR_NOACCESS,
6678 &spr_read_ureg, SPR_NOACCESS,
6679 0x00000000);
6680 /* LDSTCR */
6681 /* XXX : not implemented */
6682 spr_register(env, SPR_LDSTCR, "LDSTCR",
6683 SPR_NOACCESS, SPR_NOACCESS,
6684 &spr_read_generic, &spr_write_generic,
6685 0x00000000);
6686 /* ICTRL */
6687 /* XXX : not implemented */
6688 spr_register(env, SPR_ICTRL, "ICTRL",
6689 SPR_NOACCESS, SPR_NOACCESS,
6690 &spr_read_generic, &spr_write_generic,
6691 0x00000000);
6692 /* MSSSR0 */
6693 /* XXX : not implemented */
6694 spr_register(env, SPR_MSSSR0, "MSSSR0",
6695 SPR_NOACCESS, SPR_NOACCESS,
6696 &spr_read_generic, &spr_write_generic,
6697 0x00000000);
6698 /* PMC */
6699 /* XXX : not implemented */
6700 spr_register(env, SPR_7XX_PMC5, "PMC5",
6701 SPR_NOACCESS, SPR_NOACCESS,
6702 &spr_read_generic, &spr_write_generic,
6703 0x00000000);
6704 /* XXX : not implemented */
6705 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6706 &spr_read_ureg, SPR_NOACCESS,
6707 &spr_read_ureg, SPR_NOACCESS,
6708 0x00000000);
6709 /* XXX : not implemented */
6710 spr_register(env, SPR_7XX_PMC6, "PMC6",
6711 SPR_NOACCESS, SPR_NOACCESS,
6712 &spr_read_generic, &spr_write_generic,
6713 0x00000000);
6714 /* XXX : not implemented */
6715 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6716 &spr_read_ureg, SPR_NOACCESS,
6717 &spr_read_ureg, SPR_NOACCESS,
6718 0x00000000);
6719 /* Memory management */
6720 gen_low_BATs(env);
6721 gen_74xx_soft_tlb(env, 128, 2);
6722 init_excp_7450(env);
6723 env->dcache_line_size = 32;
6724 env->icache_line_size = 32;
6725 /* Allocate hardware IRQ controller */
6726 ppc6xx_irq_init(ppc_env_get_cpu(env));
6727 }
6728
6729 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
6730 {
6731 DeviceClass *dc = DEVICE_CLASS(oc);
6732 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6733
6734 dc->desc = "PowerPC 7440 (aka G4)";
6735 pcc->init_proc = init_proc_7440;
6736 pcc->check_pow = check_pow_hid0_74xx;
6737 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6738 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6739 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6740 PPC_FLOAT_STFIWX |
6741 PPC_CACHE | PPC_CACHE_ICBI |
6742 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6743 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6744 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6745 PPC_MEM_TLBIA | PPC_74xx_TLB |
6746 PPC_SEGMENT | PPC_EXTERN |
6747 PPC_ALTIVEC;
6748 pcc->msr_mask = (1ull << MSR_VR) |
6749 (1ull << MSR_POW) |
6750 (1ull << MSR_ILE) |
6751 (1ull << MSR_EE) |
6752 (1ull << MSR_PR) |
6753 (1ull << MSR_FP) |
6754 (1ull << MSR_ME) |
6755 (1ull << MSR_FE0) |
6756 (1ull << MSR_SE) |
6757 (1ull << MSR_DE) |
6758 (1ull << MSR_FE1) |
6759 (1ull << MSR_EP) |
6760 (1ull << MSR_IR) |
6761 (1ull << MSR_DR) |
6762 (1ull << MSR_PMM) |
6763 (1ull << MSR_RI) |
6764 (1ull << MSR_LE);
6765 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6766 pcc->excp_model = POWERPC_EXCP_74xx;
6767 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6768 pcc->bfd_mach = bfd_mach_ppc_7400;
6769 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6770 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6771 POWERPC_FLAG_BUS_CLK;
6772 }
6773
6774 static void init_proc_7450(CPUPPCState *env)
6775 {
6776 gen_spr_ne_601(env);
6777 gen_spr_sdr1(env);
6778 gen_spr_7xx(env);
6779 /* Time base */
6780 gen_tbl(env);
6781 /* 74xx specific SPR */
6782 gen_spr_74xx(env);
6783 /* Level 3 cache control */
6784 gen_l3_ctrl(env);
6785 /* L3ITCR1 */
6786 /* XXX : not implemented */
6787 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6788 SPR_NOACCESS, SPR_NOACCESS,
6789 &spr_read_generic, &spr_write_generic,
6790 0x00000000);
6791 /* L3ITCR2 */
6792 /* XXX : not implemented */
6793 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6794 SPR_NOACCESS, SPR_NOACCESS,
6795 &spr_read_generic, &spr_write_generic,
6796 0x00000000);
6797 /* L3ITCR3 */
6798 /* XXX : not implemented */
6799 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6800 SPR_NOACCESS, SPR_NOACCESS,
6801 &spr_read_generic, &spr_write_generic,
6802 0x00000000);
6803 /* L3OHCR */
6804 /* XXX : not implemented */
6805 spr_register(env, SPR_L3OHCR, "L3OHCR",
6806 SPR_NOACCESS, SPR_NOACCESS,
6807 &spr_read_generic, &spr_write_generic,
6808 0x00000000);
6809 /* XXX : not implemented */
6810 spr_register(env, SPR_UBAMR, "UBAMR",
6811 &spr_read_ureg, SPR_NOACCESS,
6812 &spr_read_ureg, SPR_NOACCESS,
6813 0x00000000);
6814 /* LDSTCR */
6815 /* XXX : not implemented */
6816 spr_register(env, SPR_LDSTCR, "LDSTCR",
6817 SPR_NOACCESS, SPR_NOACCESS,
6818 &spr_read_generic, &spr_write_generic,
6819 0x00000000);
6820 /* ICTRL */
6821 /* XXX : not implemented */
6822 spr_register(env, SPR_ICTRL, "ICTRL",
6823 SPR_NOACCESS, SPR_NOACCESS,
6824 &spr_read_generic, &spr_write_generic,
6825 0x00000000);
6826 /* MSSSR0 */
6827 /* XXX : not implemented */
6828 spr_register(env, SPR_MSSSR0, "MSSSR0",
6829 SPR_NOACCESS, SPR_NOACCESS,
6830 &spr_read_generic, &spr_write_generic,
6831 0x00000000);
6832 /* PMC */
6833 /* XXX : not implemented */
6834 spr_register(env, SPR_7XX_PMC5, "PMC5",
6835 SPR_NOACCESS, SPR_NOACCESS,
6836 &spr_read_generic, &spr_write_generic,
6837 0x00000000);
6838 /* XXX : not implemented */
6839 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6840 &spr_read_ureg, SPR_NOACCESS,
6841 &spr_read_ureg, SPR_NOACCESS,
6842 0x00000000);
6843 /* XXX : not implemented */
6844 spr_register(env, SPR_7XX_PMC6, "PMC6",
6845 SPR_NOACCESS, SPR_NOACCESS,
6846 &spr_read_generic, &spr_write_generic,
6847 0x00000000);
6848 /* XXX : not implemented */
6849 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6850 &spr_read_ureg, SPR_NOACCESS,
6851 &spr_read_ureg, SPR_NOACCESS,
6852 0x00000000);
6853 /* Memory management */
6854 gen_low_BATs(env);
6855 gen_74xx_soft_tlb(env, 128, 2);
6856 init_excp_7450(env);
6857 env->dcache_line_size = 32;
6858 env->icache_line_size = 32;
6859 /* Allocate hardware IRQ controller */
6860 ppc6xx_irq_init(ppc_env_get_cpu(env));
6861 }
6862
6863 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
6864 {
6865 DeviceClass *dc = DEVICE_CLASS(oc);
6866 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6867
6868 dc->desc = "PowerPC 7450 (aka G4)";
6869 pcc->init_proc = init_proc_7450;
6870 pcc->check_pow = check_pow_hid0_74xx;
6871 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6872 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6873 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6874 PPC_FLOAT_STFIWX |
6875 PPC_CACHE | PPC_CACHE_ICBI |
6876 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6877 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6878 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6879 PPC_MEM_TLBIA | PPC_74xx_TLB |
6880 PPC_SEGMENT | PPC_EXTERN |
6881 PPC_ALTIVEC;
6882 pcc->msr_mask = (1ull << MSR_VR) |
6883 (1ull << MSR_POW) |
6884 (1ull << MSR_ILE) |
6885 (1ull << MSR_EE) |
6886 (1ull << MSR_PR) |
6887 (1ull << MSR_FP) |
6888 (1ull << MSR_ME) |
6889 (1ull << MSR_FE0) |
6890 (1ull << MSR_SE) |
6891 (1ull << MSR_DE) |
6892 (1ull << MSR_FE1) |
6893 (1ull << MSR_EP) |
6894 (1ull << MSR_IR) |
6895 (1ull << MSR_DR) |
6896 (1ull << MSR_PMM) |
6897 (1ull << MSR_RI) |
6898 (1ull << MSR_LE);
6899 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6900 pcc->excp_model = POWERPC_EXCP_74xx;
6901 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6902 pcc->bfd_mach = bfd_mach_ppc_7400;
6903 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6904 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6905 POWERPC_FLAG_BUS_CLK;
6906 }
6907
6908 static void init_proc_7445(CPUPPCState *env)
6909 {
6910 gen_spr_ne_601(env);
6911 gen_spr_sdr1(env);
6912 gen_spr_7xx(env);
6913 /* Time base */
6914 gen_tbl(env);
6915 /* 74xx specific SPR */
6916 gen_spr_74xx(env);
6917 /* LDSTCR */
6918 /* XXX : not implemented */
6919 spr_register(env, SPR_LDSTCR, "LDSTCR",
6920 SPR_NOACCESS, SPR_NOACCESS,
6921 &spr_read_generic, &spr_write_generic,
6922 0x00000000);
6923 /* ICTRL */
6924 /* XXX : not implemented */
6925 spr_register(env, SPR_ICTRL, "ICTRL",
6926 SPR_NOACCESS, SPR_NOACCESS,
6927 &spr_read_generic, &spr_write_generic,
6928 0x00000000);
6929 /* MSSSR0 */
6930 /* XXX : not implemented */
6931 spr_register(env, SPR_MSSSR0, "MSSSR0",
6932 SPR_NOACCESS, SPR_NOACCESS,
6933 &spr_read_generic, &spr_write_generic,
6934 0x00000000);
6935 /* PMC */
6936 /* XXX : not implemented */
6937 spr_register(env, SPR_7XX_PMC5, "PMC5",
6938 SPR_NOACCESS, SPR_NOACCESS,
6939 &spr_read_generic, &spr_write_generic,
6940 0x00000000);
6941 /* XXX : not implemented */
6942 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6943 &spr_read_ureg, SPR_NOACCESS,
6944 &spr_read_ureg, SPR_NOACCESS,
6945 0x00000000);
6946 /* XXX : not implemented */
6947 spr_register(env, SPR_7XX_PMC6, "PMC6",
6948 SPR_NOACCESS, SPR_NOACCESS,
6949 &spr_read_generic, &spr_write_generic,
6950 0x00000000);
6951 /* XXX : not implemented */
6952 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6953 &spr_read_ureg, SPR_NOACCESS,
6954 &spr_read_ureg, SPR_NOACCESS,
6955 0x00000000);
6956 /* SPRGs */
6957 spr_register(env, SPR_SPRG4, "SPRG4",
6958 SPR_NOACCESS, SPR_NOACCESS,
6959 &spr_read_generic, &spr_write_generic,
6960 0x00000000);
6961 spr_register(env, SPR_USPRG4, "USPRG4",
6962 &spr_read_ureg, SPR_NOACCESS,
6963 &spr_read_ureg, SPR_NOACCESS,
6964 0x00000000);
6965 spr_register(env, SPR_SPRG5, "SPRG5",
6966 SPR_NOACCESS, SPR_NOACCESS,
6967 &spr_read_generic, &spr_write_generic,
6968 0x00000000);
6969 spr_register(env, SPR_USPRG5, "USPRG5",
6970 &spr_read_ureg, SPR_NOACCESS,
6971 &spr_read_ureg, SPR_NOACCESS,
6972 0x00000000);
6973 spr_register(env, SPR_SPRG6, "SPRG6",
6974 SPR_NOACCESS, SPR_NOACCESS,
6975 &spr_read_generic, &spr_write_generic,
6976 0x00000000);
6977 spr_register(env, SPR_USPRG6, "USPRG6",
6978 &spr_read_ureg, SPR_NOACCESS,
6979 &spr_read_ureg, SPR_NOACCESS,
6980 0x00000000);
6981 spr_register(env, SPR_SPRG7, "SPRG7",
6982 SPR_NOACCESS, SPR_NOACCESS,
6983 &spr_read_generic, &spr_write_generic,
6984 0x00000000);
6985 spr_register(env, SPR_USPRG7, "USPRG7",
6986 &spr_read_ureg, SPR_NOACCESS,
6987 &spr_read_ureg, SPR_NOACCESS,
6988 0x00000000);
6989 /* Memory management */
6990 gen_low_BATs(env);
6991 gen_high_BATs(env);
6992 gen_74xx_soft_tlb(env, 128, 2);
6993 init_excp_7450(env);
6994 env->dcache_line_size = 32;
6995 env->icache_line_size = 32;
6996 /* Allocate hardware IRQ controller */
6997 ppc6xx_irq_init(ppc_env_get_cpu(env));
6998 }
6999
7000 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
7001 {
7002 DeviceClass *dc = DEVICE_CLASS(oc);
7003 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7004
7005 dc->desc = "PowerPC 7445 (aka G4)";
7006 pcc->init_proc = init_proc_7445;
7007 pcc->check_pow = check_pow_hid0_74xx;
7008 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7009 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7010 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7011 PPC_FLOAT_STFIWX |
7012 PPC_CACHE | PPC_CACHE_ICBI |
7013 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7014 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7015 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7016 PPC_MEM_TLBIA | PPC_74xx_TLB |
7017 PPC_SEGMENT | PPC_EXTERN |
7018 PPC_ALTIVEC;
7019 pcc->msr_mask = (1ull << MSR_VR) |
7020 (1ull << MSR_POW) |
7021 (1ull << MSR_ILE) |
7022 (1ull << MSR_EE) |
7023 (1ull << MSR_PR) |
7024 (1ull << MSR_FP) |
7025 (1ull << MSR_ME) |
7026 (1ull << MSR_FE0) |
7027 (1ull << MSR_SE) |
7028 (1ull << MSR_DE) |
7029 (1ull << MSR_FE1) |
7030 (1ull << MSR_EP) |
7031 (1ull << MSR_IR) |
7032 (1ull << MSR_DR) |
7033 (1ull << MSR_PMM) |
7034 (1ull << MSR_RI) |
7035 (1ull << MSR_LE);
7036 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
7037 pcc->excp_model = POWERPC_EXCP_74xx;
7038 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7039 pcc->bfd_mach = bfd_mach_ppc_7400;
7040 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7041 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7042 POWERPC_FLAG_BUS_CLK;
7043 }
7044
7045 static void init_proc_7455(CPUPPCState *env)
7046 {
7047 gen_spr_ne_601(env);
7048 gen_spr_sdr1(env);
7049 gen_spr_7xx(env);
7050 /* Time base */
7051 gen_tbl(env);
7052 /* 74xx specific SPR */
7053 gen_spr_74xx(env);
7054 /* Level 3 cache control */
7055 gen_l3_ctrl(env);
7056 /* LDSTCR */
7057 /* XXX : not implemented */
7058 spr_register(env, SPR_LDSTCR, "LDSTCR",
7059 SPR_NOACCESS, SPR_NOACCESS,
7060 &spr_read_generic, &spr_write_generic,
7061 0x00000000);
7062 /* ICTRL */
7063 /* XXX : not implemented */
7064 spr_register(env, SPR_ICTRL, "ICTRL",
7065 SPR_NOACCESS, SPR_NOACCESS,
7066 &spr_read_generic, &spr_write_generic,
7067 0x00000000);
7068 /* MSSSR0 */
7069 /* XXX : not implemented */
7070 spr_register(env, SPR_MSSSR0, "MSSSR0",
7071 SPR_NOACCESS, SPR_NOACCESS,
7072 &spr_read_generic, &spr_write_generic,
7073 0x00000000);
7074 /* PMC */
7075 /* XXX : not implemented */
7076 spr_register(env, SPR_7XX_PMC5, "PMC5",
7077 SPR_NOACCESS, SPR_NOACCESS,
7078 &spr_read_generic, &spr_write_generic,
7079 0x00000000);
7080 /* XXX : not implemented */
7081 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
7082 &spr_read_ureg, SPR_NOACCESS,
7083 &spr_read_ureg, SPR_NOACCESS,
7084 0x00000000);
7085 /* XXX : not implemented */
7086 spr_register(env, SPR_7XX_PMC6, "PMC6",
7087 SPR_NOACCESS, SPR_NOACCESS,
7088 &spr_read_generic, &spr_write_generic,
7089 0x00000000);
7090 /* XXX : not implemented */
7091 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
7092 &spr_read_ureg, SPR_NOACCESS,
7093 &spr_read_ureg, SPR_NOACCESS,
7094 0x00000000);
7095 /* SPRGs */
7096 spr_register(env, SPR_SPRG4, "SPRG4",
7097 SPR_NOACCESS, SPR_NOACCESS,
7098 &spr_read_generic, &spr_write_generic,
7099 0x00000000);
7100 spr_register(env, SPR_USPRG4, "USPRG4",
7101 &spr_read_ureg, SPR_NOACCESS,
7102 &spr_read_ureg, SPR_NOACCESS,
7103 0x00000000);
7104 spr_register(env, SPR_SPRG5, "SPRG5",
7105 SPR_NOACCESS, SPR_NOACCESS,
7106 &spr_read_generic, &spr_write_generic,
7107 0x00000000);
7108 spr_register(env, SPR_USPRG5, "USPRG5",
7109 &spr_read_ureg, SPR_NOACCESS,
7110 &spr_read_ureg, SPR_NOACCESS,
7111 0x00000000);
7112 spr_register(env, SPR_SPRG6, "SPRG6",
7113 SPR_NOACCESS, SPR_NOACCESS,
7114 &spr_read_generic, &spr_write_generic,
7115 0x00000000);
7116 spr_register(env, SPR_USPRG6, "USPRG6",
7117 &spr_read_ureg, SPR_NOACCESS,
7118 &spr_read_ureg, SPR_NOACCESS,
7119 0x00000000);
7120 spr_register(env, SPR_SPRG7, "SPRG7",
7121 SPR_NOACCESS, SPR_NOACCESS,
7122 &spr_read_generic, &spr_write_generic,
7123 0x00000000);
7124 spr_register(env, SPR_USPRG7, "USPRG7",
7125 &spr_read_ureg, SPR_NOACCESS,
7126 &spr_read_ureg, SPR_NOACCESS,
7127 0x00000000);
7128 /* Memory management */
7129 gen_low_BATs(env);
7130 gen_high_BATs(env);
7131 gen_74xx_soft_tlb(env, 128, 2);
7132 init_excp_7450(env);
7133 env->dcache_line_size = 32;
7134 env->icache_line_size = 32;
7135 /* Allocate hardware IRQ controller */
7136 ppc6xx_irq_init(ppc_env_get_cpu(env));
7137 }
7138
7139 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
7140 {
7141 DeviceClass *dc = DEVICE_CLASS(oc);
7142 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7143
7144 dc->desc = "PowerPC 7455 (aka G4)";
7145 pcc->init_proc = init_proc_7455;
7146 pcc->check_pow = check_pow_hid0_74xx;
7147 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7148 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7149 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7150 PPC_FLOAT_STFIWX |
7151 PPC_CACHE | PPC_CACHE_ICBI |
7152 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7153 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7154 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7155 PPC_MEM_TLBIA | PPC_74xx_TLB |
7156 PPC_SEGMENT | PPC_EXTERN |
7157 PPC_ALTIVEC;
7158 pcc->msr_mask = (1ull << MSR_VR) |
7159 (1ull << MSR_POW) |
7160 (1ull << MSR_ILE) |
7161 (1ull << MSR_EE) |
7162 (1ull << MSR_PR) |
7163 (1ull << MSR_FP) |
7164 (1ull << MSR_ME) |
7165 (1ull << MSR_FE0) |
7166 (1ull << MSR_SE) |
7167 (1ull << MSR_DE) |
7168 (1ull << MSR_FE1) |
7169 (1ull << MSR_EP) |
7170 (1ull << MSR_IR) |
7171 (1ull << MSR_DR) |
7172 (1ull << MSR_PMM) |
7173 (1ull << MSR_RI) |
7174 (1ull << MSR_LE);
7175 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
7176 pcc->excp_model = POWERPC_EXCP_74xx;
7177 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7178 pcc->bfd_mach = bfd_mach_ppc_7400;
7179 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7180 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7181 POWERPC_FLAG_BUS_CLK;
7182 }
7183
7184 static void init_proc_7457(CPUPPCState *env)
7185 {
7186 gen_spr_ne_601(env);
7187 gen_spr_sdr1(env);
7188 gen_spr_7xx(env);
7189 /* Time base */
7190 gen_tbl(env);
7191 /* 74xx specific SPR */
7192 gen_spr_74xx(env);
7193 /* Level 3 cache control */
7194 gen_l3_ctrl(env);
7195 /* L3ITCR1 */
7196 /* XXX : not implemented */
7197 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
7198 SPR_NOACCESS, SPR_NOACCESS,
7199 &spr_read_generic, &spr_write_generic,
7200 0x00000000);
7201 /* L3ITCR2 */
7202 /* XXX : not implemented */
7203 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
7204 SPR_NOACCESS, SPR_NOACCESS,
7205 &spr_read_generic, &spr_write_generic,
7206 0x00000000);
7207 /* L3ITCR3 */
7208 /* XXX : not implemented */
7209 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
7210 SPR_NOACCESS, SPR_NOACCESS,
7211 &spr_read_generic, &spr_write_generic,
7212 0x00000000);
7213 /* L3OHCR */
7214 /* XXX : not implemented */
7215 spr_register(env, SPR_L3OHCR, "L3OHCR",
7216 SPR_NOACCESS, SPR_NOACCESS,
7217 &spr_read_generic, &spr_write_generic,
7218 0x00000000);
7219 /* LDSTCR */
7220 /* XXX : not implemented */
7221 spr_register(env, SPR_LDSTCR, "LDSTCR",
7222 SPR_NOACCESS, SPR_NOACCESS,
7223 &spr_read_generic, &spr_write_generic,
7224 0x00000000);
7225 /* ICTRL */
7226 /* XXX : not implemented */
7227 spr_register(env, SPR_ICTRL, "ICTRL",
7228 SPR_NOACCESS, SPR_NOACCESS,
7229 &spr_read_generic, &spr_write_generic,
7230 0x00000000);
7231 /* MSSSR0 */
7232 /* XXX : not implemented */
7233 spr_register(env, SPR_MSSSR0, "MSSSR0",
7234 SPR_NOACCESS, SPR_NOACCESS,
7235 &spr_read_generic, &spr_write_generic,
7236 0x00000000);
7237 /* PMC */
7238 /* XXX : not implemented */
7239 spr_register(env, SPR_7XX_PMC5, "PMC5",
7240 SPR_NOACCESS, SPR_NOACCESS,
7241 &spr_read_generic, &spr_write_generic,
7242 0x00000000);
7243 /* XXX : not implemented */
7244 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
7245 &spr_read_ureg, SPR_NOACCESS,
7246 &spr_read_ureg, SPR_NOACCESS,
7247 0x00000000);
7248 /* XXX : not implemented */
7249 spr_register(env, SPR_7XX_PMC6, "PMC6",
7250 SPR_NOACCESS, SPR_NOACCESS,
7251 &spr_read_generic, &spr_write_generic,
7252 0x00000000);
7253 /* XXX : not implemented */
7254 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
7255 &spr_read_ureg, SPR_NOACCESS,
7256 &spr_read_ureg, SPR_NOACCESS,
7257 0x00000000);
7258 /* SPRGs */
7259 spr_register(env, SPR_SPRG4, "SPRG4",
7260 SPR_NOACCESS, SPR_NOACCESS,
7261 &spr_read_generic, &spr_write_generic,
7262 0x00000000);
7263 spr_register(env, SPR_USPRG4, "USPRG4",
7264 &spr_read_ureg, SPR_NOACCESS,
7265 &spr_read_ureg, SPR_NOACCESS,
7266 0x00000000);
7267 spr_register(env, SPR_SPRG5, "SPRG5",
7268 SPR_NOACCESS, SPR_NOACCESS,
7269 &spr_read_generic, &spr_write_generic,
7270 0x00000000);
7271 spr_register(env, SPR_USPRG5, "USPRG5",
7272 &spr_read_ureg, SPR_NOACCESS,
7273 &spr_read_ureg, SPR_NOACCESS,
7274 0x00000000);
7275 spr_register(env, SPR_SPRG6, "SPRG6",
7276 SPR_NOACCESS, SPR_NOACCESS,
7277 &spr_read_generic, &spr_write_generic,
7278 0x00000000);
7279 spr_register(env, SPR_USPRG6, "USPRG6",
7280 &spr_read_ureg, SPR_NOACCESS,
7281 &spr_read_ureg, SPR_NOACCESS,
7282 0x00000000);
7283 spr_register(env, SPR_SPRG7, "SPRG7",
7284 SPR_NOACCESS, SPR_NOACCESS,
7285 &spr_read_generic, &spr_write_generic,
7286 0x00000000);
7287 spr_register(env, SPR_USPRG7, "USPRG7",
7288 &spr_read_ureg, SPR_NOACCESS,
7289 &spr_read_ureg, SPR_NOACCESS,
7290 0x00000000);
7291 /* Memory management */
7292 gen_low_BATs(env);
7293 gen_high_BATs(env);
7294 gen_74xx_soft_tlb(env, 128, 2);
7295 init_excp_7450(env);
7296 env->dcache_line_size = 32;
7297 env->icache_line_size = 32;
7298 /* Allocate hardware IRQ controller */
7299 ppc6xx_irq_init(ppc_env_get_cpu(env));
7300 }
7301
7302 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
7303 {
7304 DeviceClass *dc = DEVICE_CLASS(oc);
7305 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7306
7307 dc->desc = "PowerPC 7457 (aka G4)";
7308 pcc->init_proc = init_proc_7457;
7309 pcc->check_pow = check_pow_hid0_74xx;
7310 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7311 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7312 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7313 PPC_FLOAT_STFIWX |
7314 PPC_CACHE | PPC_CACHE_ICBI |
7315 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7316 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7317 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7318 PPC_MEM_TLBIA | PPC_74xx_TLB |
7319 PPC_SEGMENT | PPC_EXTERN |
7320 PPC_ALTIVEC;
7321 pcc->msr_mask = (1ull << MSR_VR) |
7322 (1ull << MSR_POW) |
7323 (1ull << MSR_ILE) |
7324 (1ull << MSR_EE) |
7325 (1ull << MSR_PR) |
7326 (1ull << MSR_FP) |
7327 (1ull << MSR_ME) |
7328 (1ull << MSR_FE0) |
7329 (1ull << MSR_SE) |
7330 (1ull << MSR_DE) |
7331 (1ull << MSR_FE1) |
7332 (1ull << MSR_EP) |
7333 (1ull << MSR_IR) |
7334 (1ull << MSR_DR) |
7335 (1ull << MSR_PMM) |
7336 (1ull << MSR_RI) |
7337 (1ull << MSR_LE);
7338 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
7339 pcc->excp_model = POWERPC_EXCP_74xx;
7340 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7341 pcc->bfd_mach = bfd_mach_ppc_7400;
7342 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7343 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7344 POWERPC_FLAG_BUS_CLK;
7345 }
7346
7347 static void init_proc_e600(CPUPPCState *env)
7348 {
7349 gen_spr_ne_601(env);
7350 gen_spr_sdr1(env);
7351 gen_spr_7xx(env);
7352 /* Time base */
7353 gen_tbl(env);
7354 /* 74xx specific SPR */
7355 gen_spr_74xx(env);
7356 /* XXX : not implemented */
7357 spr_register(env, SPR_UBAMR, "UBAMR",
7358 &spr_read_ureg, SPR_NOACCESS,
7359 &spr_read_ureg, SPR_NOACCESS,
7360 0x00000000);
7361 /* XXX : not implemented */
7362 spr_register(env, SPR_LDSTCR, "LDSTCR",
7363 SPR_NOACCESS, SPR_NOACCESS,
7364 &spr_read_generic, &spr_write_generic,
7365 0x00000000);
7366 /* XXX : not implemented */
7367 spr_register(env, SPR_ICTRL, "ICTRL",
7368 SPR_NOACCESS, SPR_NOACCESS,
7369 &spr_read_generic, &spr_write_generic,
7370 0x00000000);
7371 /* XXX : not implemented */
7372 spr_register(env, SPR_MSSSR0, "MSSSR0",
7373 SPR_NOACCESS, SPR_NOACCESS,
7374 &spr_read_generic, &spr_write_generic,
7375 0x00000000);
7376 /* XXX : not implemented */
7377 spr_register(env, SPR_7XX_PMC5, "PMC5",
7378 SPR_NOACCESS, SPR_NOACCESS,
7379 &spr_read_generic, &spr_write_generic,
7380 0x00000000);
7381 /* XXX : not implemented */
7382 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
7383 &spr_read_ureg, SPR_NOACCESS,
7384 &spr_read_ureg, SPR_NOACCESS,
7385 0x00000000);
7386 /* XXX : not implemented */
7387 spr_register(env, SPR_7XX_PMC6, "PMC6",
7388 SPR_NOACCESS, SPR_NOACCESS,
7389 &spr_read_generic, &spr_write_generic,
7390 0x00000000);
7391 /* XXX : not implemented */
7392 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
7393 &spr_read_ureg, SPR_NOACCESS,
7394 &spr_read_ureg, SPR_NOACCESS,
7395 0x00000000);
7396 /* SPRGs */
7397 spr_register(env, SPR_SPRG4, "SPRG4",
7398 SPR_NOACCESS, SPR_NOACCESS,
7399 &spr_read_generic, &spr_write_generic,
7400 0x00000000);
7401 spr_register(env, SPR_USPRG4, "USPRG4",
7402 &spr_read_ureg, SPR_NOACCESS,
7403 &spr_read_ureg, SPR_NOACCESS,
7404 0x00000000);
7405 spr_register(env, SPR_SPRG5, "SPRG5",
7406 SPR_NOACCESS, SPR_NOACCESS,
7407 &spr_read_generic, &spr_write_generic,
7408 0x00000000);
7409 spr_register(env, SPR_USPRG5, "USPRG5",
7410 &spr_read_ureg, SPR_NOACCESS,
7411 &spr_read_ureg, SPR_NOACCESS,
7412 0x00000000);
7413 spr_register(env, SPR_SPRG6, "SPRG6",
7414 SPR_NOACCESS, SPR_NOACCESS,
7415 &spr_read_generic, &spr_write_generic,
7416 0x00000000);
7417 spr_register(env, SPR_USPRG6, "USPRG6",
7418 &spr_read_ureg, SPR_NOACCESS,
7419 &spr_read_ureg, SPR_NOACCESS,
7420 0x00000000);
7421 spr_register(env, SPR_SPRG7, "SPRG7",
7422 SPR_NOACCESS, SPR_NOACCESS,
7423 &spr_read_generic, &spr_write_generic,
7424 0x00000000);
7425 spr_register(env, SPR_USPRG7, "USPRG7",
7426 &spr_read_ureg, SPR_NOACCESS,
7427 &spr_read_ureg, SPR_NOACCESS,
7428 0x00000000);
7429 /* Memory management */
7430 gen_low_BATs(env);
7431 gen_high_BATs(env);
7432 gen_74xx_soft_tlb(env, 128, 2);
7433 init_excp_7450(env);
7434 env->dcache_line_size = 32;
7435 env->icache_line_size = 32;
7436 /* Allocate hardware IRQ controller */
7437 ppc6xx_irq_init(ppc_env_get_cpu(env));
7438 }
7439
7440 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
7441 {
7442 DeviceClass *dc = DEVICE_CLASS(oc);
7443 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7444
7445 dc->desc = "PowerPC e600";
7446 pcc->init_proc = init_proc_e600;
7447 pcc->check_pow = check_pow_hid0_74xx;
7448 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7449 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7450 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7451 PPC_FLOAT_STFIWX |
7452 PPC_CACHE | PPC_CACHE_ICBI |
7453 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7454 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7455 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7456 PPC_MEM_TLBIA | PPC_74xx_TLB |
7457 PPC_SEGMENT | PPC_EXTERN |
7458 PPC_ALTIVEC;
7459 pcc->insns_flags2 = PPC_NONE;
7460 pcc->msr_mask = (1ull << MSR_VR) |
7461 (1ull << MSR_POW) |
7462 (1ull << MSR_ILE) |
7463 (1ull << MSR_EE) |
7464 (1ull << MSR_PR) |
7465 (1ull << MSR_FP) |
7466 (1ull << MSR_ME) |
7467 (1ull << MSR_FE0) |
7468 (1ull << MSR_SE) |
7469 (1ull << MSR_DE) |
7470 (1ull << MSR_FE1) |
7471 (1ull << MSR_EP) |
7472 (1ull << MSR_IR) |
7473 (1ull << MSR_DR) |
7474 (1ull << MSR_PMM) |
7475 (1ull << MSR_RI) |
7476 (1ull << MSR_LE);
7477 pcc->mmu_model = POWERPC_MMU_32B;
7478 #if defined(CONFIG_SOFTMMU)
7479 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
7480 #endif
7481 pcc->excp_model = POWERPC_EXCP_74xx;
7482 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7483 pcc->bfd_mach = bfd_mach_ppc_7400;
7484 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7485 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7486 POWERPC_FLAG_BUS_CLK;
7487 }
7488
7489 #if defined(TARGET_PPC64)
7490 #if defined(CONFIG_USER_ONLY)
7491 #define POWERPC970_HID5_INIT 0x00000080
7492 #else
7493 #define POWERPC970_HID5_INIT 0x00000000
7494 #endif
7495
7496 static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
7497 int bit, int sprn, int cause)
7498 {
7499 TCGv_i32 t1 = tcg_const_i32(bit);
7500 TCGv_i32 t2 = tcg_const_i32(sprn);
7501 TCGv_i32 t3 = tcg_const_i32(cause);
7502
7503 gen_helper_fscr_facility_check(cpu_env, t1, t2, t3);
7504
7505 tcg_temp_free_i32(t3);
7506 tcg_temp_free_i32(t2);
7507 tcg_temp_free_i32(t1);
7508 }
7509
7510 static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn,
7511 int bit, int sprn, int cause)
7512 {
7513 TCGv_i32 t1 = tcg_const_i32(bit);
7514 TCGv_i32 t2 = tcg_const_i32(sprn);
7515 TCGv_i32 t3 = tcg_const_i32(cause);
7516
7517 gen_helper_msr_facility_check(cpu_env, t1, t2, t3);
7518
7519 tcg_temp_free_i32(t3);
7520 tcg_temp_free_i32(t2);
7521 tcg_temp_free_i32(t1);
7522 }
7523
7524 static void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn)
7525 {
7526 TCGv spr_up = tcg_temp_new();
7527 TCGv spr = tcg_temp_new();
7528
7529 gen_load_spr(spr, sprn - 1);
7530 tcg_gen_shri_tl(spr_up, spr, 32);
7531 tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up);
7532
7533 tcg_temp_free(spr);
7534 tcg_temp_free(spr_up);
7535 }
7536
7537 static void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn)
7538 {
7539 TCGv spr = tcg_temp_new();
7540
7541 gen_load_spr(spr, sprn - 1);
7542 tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32);
7543 gen_store_spr(sprn - 1, spr);
7544
7545 tcg_temp_free(spr);
7546 }
7547
7548 static int check_pow_970(CPUPPCState *env)
7549 {
7550 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) {
7551 return 1;
7552 }
7553
7554 return 0;
7555 }
7556
7557 static void gen_spr_970_hid(CPUPPCState *env)
7558 {
7559 /* Hardware implementation registers */
7560 /* XXX : not implemented */
7561 spr_register(env, SPR_HID0, "HID0",
7562 SPR_NOACCESS, SPR_NOACCESS,
7563 &spr_read_generic, &spr_write_clear,
7564 0x60000000);
7565 spr_register(env, SPR_HID1, "HID1",
7566 SPR_NOACCESS, SPR_NOACCESS,
7567 &spr_read_generic, &spr_write_generic,
7568 0x00000000);
7569 spr_register(env, SPR_970_HID5, "HID5",
7570 SPR_NOACCESS, SPR_NOACCESS,
7571 &spr_read_generic, &spr_write_generic,
7572 POWERPC970_HID5_INIT);
7573 }
7574
7575 static void gen_spr_970_hior(CPUPPCState *env)
7576 {
7577 spr_register(env, SPR_HIOR, "SPR_HIOR",
7578 SPR_NOACCESS, SPR_NOACCESS,
7579 &spr_read_hior, &spr_write_hior,
7580 0x00000000);
7581 }
7582
7583 static void gen_spr_book3s_ctrl(CPUPPCState *env)
7584 {
7585 spr_register(env, SPR_CTRL, "SPR_CTRL",
7586 SPR_NOACCESS, SPR_NOACCESS,
7587 SPR_NOACCESS, &spr_write_generic,
7588 0x00000000);
7589 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
7590 &spr_read_ureg, SPR_NOACCESS,
7591 &spr_read_ureg, SPR_NOACCESS,
7592 0x00000000);
7593 }
7594
7595 static void gen_spr_book3s_altivec(CPUPPCState *env)
7596 {
7597 if (!(env->insns_flags & PPC_ALTIVEC)) {
7598 return;
7599 }
7600
7601 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE",
7602 &spr_read_generic, &spr_write_generic,
7603 &spr_read_generic, &spr_write_generic,
7604 KVM_REG_PPC_VRSAVE, 0x00000000);
7605
7606 /*
7607 * Can't find information on what this should be on reset. This
7608 * value is the one used by 74xx processors.
7609 */
7610 vscr_init(env, 0x00010000);
7611 }
7612
7613 static void gen_spr_book3s_dbg(CPUPPCState *env)
7614 {
7615 /*
7616 * TODO: different specs define different scopes for these,
7617 * will have to address this:
7618 * 970: super/write and super/read
7619 * powerisa 2.03..2.04: hypv/write and super/read.
7620 * powerisa 2.05 and newer: hypv/write and hypv/read.
7621 */
7622 spr_register_kvm(env, SPR_DABR, "DABR",
7623 SPR_NOACCESS, SPR_NOACCESS,
7624 &spr_read_generic, &spr_write_generic,
7625 KVM_REG_PPC_DABR, 0x00000000);
7626 spr_register_kvm(env, SPR_DABRX, "DABRX",
7627 SPR_NOACCESS, SPR_NOACCESS,
7628 &spr_read_generic, &spr_write_generic,
7629 KVM_REG_PPC_DABRX, 0x00000000);
7630 }
7631
7632 static void gen_spr_book3s_207_dbg(CPUPPCState *env)
7633 {
7634 spr_register_kvm_hv(env, SPR_DAWR, "DAWR",
7635 SPR_NOACCESS, SPR_NOACCESS,
7636 SPR_NOACCESS, SPR_NOACCESS,
7637 &spr_read_generic, &spr_write_generic,
7638 KVM_REG_PPC_DAWR, 0x00000000);
7639 spr_register_kvm_hv(env, SPR_DAWRX, "DAWRX",
7640 SPR_NOACCESS, SPR_NOACCESS,
7641 SPR_NOACCESS, SPR_NOACCESS,
7642 &spr_read_generic, &spr_write_generic,
7643 KVM_REG_PPC_DAWRX, 0x00000000);
7644 spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
7645 SPR_NOACCESS, SPR_NOACCESS,
7646 SPR_NOACCESS, SPR_NOACCESS,
7647 &spr_read_generic, &spr_write_generic,
7648 KVM_REG_PPC_CIABR, 0x00000000);
7649 }
7650
7651 static void gen_spr_970_dbg(CPUPPCState *env)
7652 {
7653 /* Breakpoints */
7654 spr_register(env, SPR_IABR, "IABR",
7655 SPR_NOACCESS, SPR_NOACCESS,
7656 &spr_read_generic, &spr_write_generic,
7657 0x00000000);
7658 }
7659
7660 static void gen_spr_book3s_pmu_sup(CPUPPCState *env)
7661 {
7662 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0",
7663 SPR_NOACCESS, SPR_NOACCESS,
7664 &spr_read_generic, &spr_write_generic,
7665 KVM_REG_PPC_MMCR0, 0x00000000);
7666 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1",
7667 SPR_NOACCESS, SPR_NOACCESS,
7668 &spr_read_generic, &spr_write_generic,
7669 KVM_REG_PPC_MMCR1, 0x00000000);
7670 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA",
7671 SPR_NOACCESS, SPR_NOACCESS,
7672 &spr_read_generic, &spr_write_generic,
7673 KVM_REG_PPC_MMCRA, 0x00000000);
7674 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1",
7675 SPR_NOACCESS, SPR_NOACCESS,
7676 &spr_read_generic, &spr_write_generic,
7677 KVM_REG_PPC_PMC1, 0x00000000);
7678 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2",
7679 SPR_NOACCESS, SPR_NOACCESS,
7680 &spr_read_generic, &spr_write_generic,
7681 KVM_REG_PPC_PMC2, 0x00000000);
7682 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3",
7683 SPR_NOACCESS, SPR_NOACCESS,
7684 &spr_read_generic, &spr_write_generic,
7685 KVM_REG_PPC_PMC3, 0x00000000);
7686 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4",
7687 SPR_NOACCESS, SPR_NOACCESS,
7688 &spr_read_generic, &spr_write_generic,
7689 KVM_REG_PPC_PMC4, 0x00000000);
7690 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5",
7691 SPR_NOACCESS, SPR_NOACCESS,
7692 &spr_read_generic, &spr_write_generic,
7693 KVM_REG_PPC_PMC5, 0x00000000);
7694 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6",
7695 SPR_NOACCESS, SPR_NOACCESS,
7696 &spr_read_generic, &spr_write_generic,
7697 KVM_REG_PPC_PMC6, 0x00000000);
7698 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR",
7699 SPR_NOACCESS, SPR_NOACCESS,
7700 &spr_read_generic, &spr_write_generic,
7701 KVM_REG_PPC_SIAR, 0x00000000);
7702 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR",
7703 SPR_NOACCESS, SPR_NOACCESS,
7704 &spr_read_generic, &spr_write_generic,
7705 KVM_REG_PPC_SDAR, 0x00000000);
7706 }
7707
7708 static void gen_spr_book3s_pmu_user(CPUPPCState *env)
7709 {
7710 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
7711 &spr_read_ureg, SPR_NOACCESS,
7712 &spr_read_ureg, &spr_write_ureg,
7713 0x00000000);
7714 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1",
7715 &spr_read_ureg, SPR_NOACCESS,
7716 &spr_read_ureg, &spr_write_ureg,
7717 0x00000000);
7718 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA",
7719 &spr_read_ureg, SPR_NOACCESS,
7720 &spr_read_ureg, &spr_write_ureg,
7721 0x00000000);
7722 spr_register(env, SPR_POWER_UPMC1, "UPMC1",
7723 &spr_read_ureg, SPR_NOACCESS,
7724 &spr_read_ureg, &spr_write_ureg,
7725 0x00000000);
7726 spr_register(env, SPR_POWER_UPMC2, "UPMC2",
7727 &spr_read_ureg, SPR_NOACCESS,
7728 &spr_read_ureg, &spr_write_ureg,
7729 0x00000000);
7730 spr_register(env, SPR_POWER_UPMC3, "UPMC3",
7731 &spr_read_ureg, SPR_NOACCESS,
7732 &spr_read_ureg, &spr_write_ureg,
7733 0x00000000);
7734 spr_register(env, SPR_POWER_UPMC4, "UPMC4",
7735 &spr_read_ureg, SPR_NOACCESS,
7736 &spr_read_ureg, &spr_write_ureg,
7737 0x00000000);
7738 spr_register(env, SPR_POWER_UPMC5, "UPMC5",
7739 &spr_read_ureg, SPR_NOACCESS,
7740 &spr_read_ureg, &spr_write_ureg,
7741 0x00000000);
7742 spr_register(env, SPR_POWER_UPMC6, "UPMC6",
7743 &spr_read_ureg, SPR_NOACCESS,
7744 &spr_read_ureg, &spr_write_ureg,
7745 0x00000000);
7746 spr_register(env, SPR_POWER_USIAR, "USIAR",
7747 &spr_read_ureg, SPR_NOACCESS,
7748 &spr_read_ureg, &spr_write_ureg,
7749 0x00000000);
7750 spr_register(env, SPR_POWER_USDAR, "USDAR",
7751 &spr_read_ureg, SPR_NOACCESS,
7752 &spr_read_ureg, &spr_write_ureg,
7753 0x00000000);
7754 }
7755
7756 static void gen_spr_970_pmu_sup(CPUPPCState *env)
7757 {
7758 spr_register_kvm(env, SPR_970_PMC7, "PMC7",
7759 SPR_NOACCESS, SPR_NOACCESS,
7760 &spr_read_generic, &spr_write_generic,
7761 KVM_REG_PPC_PMC7, 0x00000000);
7762 spr_register_kvm(env, SPR_970_PMC8, "PMC8",
7763 SPR_NOACCESS, SPR_NOACCESS,
7764 &spr_read_generic, &spr_write_generic,
7765 KVM_REG_PPC_PMC8, 0x00000000);
7766 }
7767
7768 static void gen_spr_970_pmu_user(CPUPPCState *env)
7769 {
7770 spr_register(env, SPR_970_UPMC7, "UPMC7",
7771 &spr_read_ureg, SPR_NOACCESS,
7772 &spr_read_ureg, &spr_write_ureg,
7773 0x00000000);
7774 spr_register(env, SPR_970_UPMC8, "UPMC8",
7775 &spr_read_ureg, SPR_NOACCESS,
7776 &spr_read_ureg, &spr_write_ureg,
7777 0x00000000);
7778 }
7779
7780 static void gen_spr_power8_pmu_sup(CPUPPCState *env)
7781 {
7782 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
7783 SPR_NOACCESS, SPR_NOACCESS,
7784 &spr_read_generic, &spr_write_generic,
7785 KVM_REG_PPC_MMCR2, 0x00000000);
7786 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS",
7787 SPR_NOACCESS, SPR_NOACCESS,
7788 &spr_read_generic, &spr_write_generic,
7789 KVM_REG_PPC_MMCRS, 0x00000000);
7790 spr_register_kvm(env, SPR_POWER_SIER, "SIER",
7791 SPR_NOACCESS, SPR_NOACCESS,
7792 &spr_read_generic, &spr_write_generic,
7793 KVM_REG_PPC_SIER, 0x00000000);
7794 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1",
7795 SPR_NOACCESS, SPR_NOACCESS,
7796 &spr_read_generic, &spr_write_generic,
7797 KVM_REG_PPC_SPMC1, 0x00000000);
7798 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2",
7799 SPR_NOACCESS, SPR_NOACCESS,
7800 &spr_read_generic, &spr_write_generic,
7801 KVM_REG_PPC_SPMC2, 0x00000000);
7802 spr_register_kvm(env, SPR_TACR, "TACR",
7803 SPR_NOACCESS, SPR_NOACCESS,
7804 &spr_read_generic, &spr_write_generic,
7805 KVM_REG_PPC_TACR, 0x00000000);
7806 spr_register_kvm(env, SPR_TCSCR, "TCSCR",
7807 SPR_NOACCESS, SPR_NOACCESS,
7808 &spr_read_generic, &spr_write_generic,
7809 KVM_REG_PPC_TCSCR, 0x00000000);
7810 spr_register_kvm(env, SPR_CSIGR, "CSIGR",
7811 SPR_NOACCESS, SPR_NOACCESS,
7812 &spr_read_generic, &spr_write_generic,
7813 KVM_REG_PPC_CSIGR, 0x00000000);
7814 }
7815
7816 static void gen_spr_power8_pmu_user(CPUPPCState *env)
7817 {
7818 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
7819 &spr_read_ureg, SPR_NOACCESS,
7820 &spr_read_ureg, &spr_write_ureg,
7821 0x00000000);
7822 spr_register(env, SPR_POWER_USIER, "USIER",
7823 &spr_read_generic, SPR_NOACCESS,
7824 &spr_read_generic, &spr_write_generic,
7825 0x00000000);
7826 }
7827
7828 static void gen_spr_power5p_ear(CPUPPCState *env)
7829 {
7830 /* External access control */
7831 spr_register(env, SPR_EAR, "EAR",
7832 SPR_NOACCESS, SPR_NOACCESS,
7833 &spr_read_generic, &spr_write_generic,
7834 0x00000000);
7835 }
7836
7837 #if !defined(CONFIG_USER_ONLY)
7838 static void spr_write_hmer(DisasContext *ctx, int sprn, int gprn)
7839 {
7840 TCGv hmer = tcg_temp_new();
7841
7842 gen_load_spr(hmer, sprn);
7843 tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer);
7844 gen_store_spr(sprn, hmer);
7845 spr_store_dump_spr(sprn);
7846 tcg_temp_free(hmer);
7847 }
7848
7849 static void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn)
7850 {
7851 gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]);
7852 }
7853
7854 static void spr_write_970_hid4(DisasContext *ctx, int sprn, int gprn)
7855 {
7856 #if defined(TARGET_PPC64)
7857 spr_write_generic(ctx, sprn, gprn);
7858 gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]);
7859 #endif
7860 }
7861
7862 #endif /* !defined(CONFIG_USER_ONLY) */
7863
7864 static void gen_spr_970_lpar(CPUPPCState *env)
7865 {
7866 #if !defined(CONFIG_USER_ONLY)
7867 /* Logical partitionning */
7868 /* PPC970: HID4 is effectively the LPCR */
7869 spr_register(env, SPR_970_HID4, "HID4",
7870 SPR_NOACCESS, SPR_NOACCESS,
7871 &spr_read_generic, &spr_write_970_hid4,
7872 0x00000000);
7873 #endif
7874 }
7875
7876 static void gen_spr_power5p_lpar(CPUPPCState *env)
7877 {
7878 #if !defined(CONFIG_USER_ONLY)
7879 /* Logical partitionning */
7880 spr_register_kvm_hv(env, SPR_LPCR, "LPCR",
7881 SPR_NOACCESS, SPR_NOACCESS,
7882 SPR_NOACCESS, SPR_NOACCESS,
7883 &spr_read_generic, &spr_write_lpcr,
7884 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1);
7885 spr_register_hv(env, SPR_HDEC, "HDEC",
7886 SPR_NOACCESS, SPR_NOACCESS,
7887 SPR_NOACCESS, SPR_NOACCESS,
7888 &spr_read_hdecr, &spr_write_hdecr, 0);
7889 #endif
7890 }
7891
7892 static void gen_spr_book3s_ids(CPUPPCState *env)
7893 {
7894 /* FIXME: Will need to deal with thread vs core only SPRs */
7895
7896 /* Processor identification */
7897 spr_register_hv(env, SPR_PIR, "PIR",
7898 SPR_NOACCESS, SPR_NOACCESS,
7899 &spr_read_generic, SPR_NOACCESS,
7900 &spr_read_generic, NULL,
7901 0x00000000);
7902 spr_register_hv(env, SPR_HID0, "HID0",
7903 SPR_NOACCESS, SPR_NOACCESS,
7904 SPR_NOACCESS, SPR_NOACCESS,
7905 &spr_read_generic, &spr_write_generic,
7906 0x00000000);
7907 spr_register_hv(env, SPR_TSCR, "TSCR",
7908 SPR_NOACCESS, SPR_NOACCESS,
7909 SPR_NOACCESS, SPR_NOACCESS,
7910 &spr_read_generic, &spr_write_generic,
7911 0x00000000);
7912 spr_register_hv(env, SPR_HMER, "HMER",
7913 SPR_NOACCESS, SPR_NOACCESS,
7914 SPR_NOACCESS, SPR_NOACCESS,
7915 &spr_read_generic, &spr_write_hmer,
7916 0x00000000);
7917 spr_register_hv(env, SPR_HMEER, "HMEER",
7918 SPR_NOACCESS, SPR_NOACCESS,
7919 SPR_NOACCESS, SPR_NOACCESS,
7920 &spr_read_generic, &spr_write_generic,
7921 0x00000000);
7922 spr_register_hv(env, SPR_TFMR, "TFMR",
7923 SPR_NOACCESS, SPR_NOACCESS,
7924 SPR_NOACCESS, SPR_NOACCESS,
7925 &spr_read_generic, &spr_write_generic,
7926 0x00000000);
7927 spr_register_hv(env, SPR_LPIDR, "LPIDR",
7928 SPR_NOACCESS, SPR_NOACCESS,
7929 SPR_NOACCESS, SPR_NOACCESS,
7930 &spr_read_generic, &spr_write_lpidr,
7931 0x00000000);
7932 spr_register_hv(env, SPR_HFSCR, "HFSCR",
7933 SPR_NOACCESS, SPR_NOACCESS,
7934 SPR_NOACCESS, SPR_NOACCESS,
7935 &spr_read_generic, &spr_write_generic,
7936 0x00000000);
7937 spr_register_hv(env, SPR_MMCRC, "MMCRC",
7938 SPR_NOACCESS, SPR_NOACCESS,
7939 SPR_NOACCESS, SPR_NOACCESS,
7940 &spr_read_generic, &spr_write_generic,
7941 0x00000000);
7942 spr_register_hv(env, SPR_MMCRH, "MMCRH",
7943 SPR_NOACCESS, SPR_NOACCESS,
7944 SPR_NOACCESS, SPR_NOACCESS,
7945 &spr_read_generic, &spr_write_generic,
7946 0x00000000);
7947 spr_register_hv(env, SPR_HSPRG0, "HSPRG0",
7948 SPR_NOACCESS, SPR_NOACCESS,
7949 SPR_NOACCESS, SPR_NOACCESS,
7950 &spr_read_generic, &spr_write_generic,
7951 0x00000000);
7952 spr_register_hv(env, SPR_HSPRG1, "HSPRG1",
7953 SPR_NOACCESS, SPR_NOACCESS,
7954 SPR_NOACCESS, SPR_NOACCESS,
7955 &spr_read_generic, &spr_write_generic,
7956 0x00000000);
7957 spr_register_hv(env, SPR_HSRR0, "HSRR0",
7958 SPR_NOACCESS, SPR_NOACCESS,
7959 SPR_NOACCESS, SPR_NOACCESS,
7960 &spr_read_generic, &spr_write_generic,
7961 0x00000000);
7962 spr_register_hv(env, SPR_HSRR1, "HSRR1",
7963 SPR_NOACCESS, SPR_NOACCESS,
7964 SPR_NOACCESS, SPR_NOACCESS,
7965 &spr_read_generic, &spr_write_generic,
7966 0x00000000);
7967 spr_register_hv(env, SPR_HDAR, "HDAR",
7968 SPR_NOACCESS, SPR_NOACCESS,
7969 SPR_NOACCESS, SPR_NOACCESS,
7970 &spr_read_generic, &spr_write_generic,
7971 0x00000000);
7972 spr_register_hv(env, SPR_HDSISR, "HDSISR",
7973 SPR_NOACCESS, SPR_NOACCESS,
7974 SPR_NOACCESS, SPR_NOACCESS,
7975 &spr_read_generic, &spr_write_generic,
7976 0x00000000);
7977 spr_register_hv(env, SPR_RMOR, "RMOR",
7978 SPR_NOACCESS, SPR_NOACCESS,
7979 SPR_NOACCESS, SPR_NOACCESS,
7980 &spr_read_generic, &spr_write_generic,
7981 0x00000000);
7982 spr_register_hv(env, SPR_HRMOR, "HRMOR",
7983 SPR_NOACCESS, SPR_NOACCESS,
7984 SPR_NOACCESS, SPR_NOACCESS,
7985 &spr_read_generic, &spr_write_generic,
7986 0x00000000);
7987 }
7988
7989 static void gen_spr_power8_ids(CPUPPCState *env)
7990 {
7991 /* Thread identification */
7992 spr_register(env, SPR_TIR, "TIR",
7993 SPR_NOACCESS, SPR_NOACCESS,
7994 &spr_read_generic, SPR_NOACCESS,
7995 0x00000000);
7996 }
7997
7998 static void gen_spr_book3s_purr(CPUPPCState *env)
7999 {
8000 #if !defined(CONFIG_USER_ONLY)
8001 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
8002 spr_register_kvm(env, SPR_PURR, "PURR",
8003 &spr_read_purr, SPR_NOACCESS,
8004 &spr_read_purr, SPR_NOACCESS,
8005 KVM_REG_PPC_PURR, 0x00000000);
8006 spr_register_kvm(env, SPR_SPURR, "SPURR",
8007 &spr_read_purr, SPR_NOACCESS,
8008 &spr_read_purr, SPR_NOACCESS,
8009 KVM_REG_PPC_SPURR, 0x00000000);
8010 #endif
8011 }
8012
8013 static void gen_spr_power6_dbg(CPUPPCState *env)
8014 {
8015 #if !defined(CONFIG_USER_ONLY)
8016 spr_register(env, SPR_CFAR, "SPR_CFAR",
8017 SPR_NOACCESS, SPR_NOACCESS,
8018 &spr_read_cfar, &spr_write_cfar,
8019 0x00000000);
8020 #endif
8021 }
8022
8023 static void gen_spr_power5p_common(CPUPPCState *env)
8024 {
8025 spr_register_kvm(env, SPR_PPR, "PPR",
8026 &spr_read_generic, &spr_write_generic,
8027 &spr_read_generic, &spr_write_generic,
8028 KVM_REG_PPC_PPR, 0x00000000);
8029 }
8030
8031 static void gen_spr_power6_common(CPUPPCState *env)
8032 {
8033 #if !defined(CONFIG_USER_ONLY)
8034 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
8035 SPR_NOACCESS, SPR_NOACCESS,
8036 &spr_read_generic, &spr_write_generic,
8037 KVM_REG_PPC_DSCR, 0x00000000);
8038 #endif
8039 /*
8040 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of
8041 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access.
8042 */
8043 spr_register_hv(env, SPR_PCR, "PCR",
8044 SPR_NOACCESS, SPR_NOACCESS,
8045 SPR_NOACCESS, SPR_NOACCESS,
8046 &spr_read_generic, &spr_write_pcr,
8047 0x00000000);
8048 }
8049
8050 static void spr_read_tar(DisasContext *ctx, int gprn, int sprn)
8051 {
8052 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
8053 spr_read_generic(ctx, gprn, sprn);
8054 }
8055
8056 static void spr_write_tar(DisasContext *ctx, int sprn, int gprn)
8057 {
8058 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
8059 spr_write_generic(ctx, sprn, gprn);
8060 }
8061
8062 static void gen_spr_power8_tce_address_control(CPUPPCState *env)
8063 {
8064 spr_register_kvm(env, SPR_TAR, "TAR",
8065 &spr_read_tar, &spr_write_tar,
8066 &spr_read_generic, &spr_write_generic,
8067 KVM_REG_PPC_TAR, 0x00000000);
8068 }
8069
8070 static void spr_read_tm(DisasContext *ctx, int gprn, int sprn)
8071 {
8072 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
8073 spr_read_generic(ctx, gprn, sprn);
8074 }
8075
8076 static void spr_write_tm(DisasContext *ctx, int sprn, int gprn)
8077 {
8078 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
8079 spr_write_generic(ctx, sprn, gprn);
8080 }
8081
8082 static void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn)
8083 {
8084 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
8085 spr_read_prev_upper32(ctx, gprn, sprn);
8086 }
8087
8088 static void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn)
8089 {
8090 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
8091 spr_write_prev_upper32(ctx, sprn, gprn);
8092 }
8093
8094 static void gen_spr_power8_tm(CPUPPCState *env)
8095 {
8096 spr_register_kvm(env, SPR_TFHAR, "TFHAR",
8097 &spr_read_tm, &spr_write_tm,
8098 &spr_read_tm, &spr_write_tm,
8099 KVM_REG_PPC_TFHAR, 0x00000000);
8100 spr_register_kvm(env, SPR_TFIAR, "TFIAR",
8101 &spr_read_tm, &spr_write_tm,
8102 &spr_read_tm, &spr_write_tm,
8103 KVM_REG_PPC_TFIAR, 0x00000000);
8104 spr_register_kvm(env, SPR_TEXASR, "TEXASR",
8105 &spr_read_tm, &spr_write_tm,
8106 &spr_read_tm, &spr_write_tm,
8107 KVM_REG_PPC_TEXASR, 0x00000000);
8108 spr_register(env, SPR_TEXASRU, "TEXASRU",
8109 &spr_read_tm_upper32, &spr_write_tm_upper32,
8110 &spr_read_tm_upper32, &spr_write_tm_upper32,
8111 0x00000000);
8112 }
8113
8114 static void spr_read_ebb(DisasContext *ctx, int gprn, int sprn)
8115 {
8116 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
8117 spr_read_generic(ctx, gprn, sprn);
8118 }
8119
8120 static void spr_write_ebb(DisasContext *ctx, int sprn, int gprn)
8121 {
8122 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
8123 spr_write_generic(ctx, sprn, gprn);
8124 }
8125
8126 static void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn)
8127 {
8128 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
8129 spr_read_prev_upper32(ctx, gprn, sprn);
8130 }
8131
8132 static void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn)
8133 {
8134 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
8135 spr_write_prev_upper32(ctx, sprn, gprn);
8136 }
8137
8138 static void gen_spr_power8_ebb(CPUPPCState *env)
8139 {
8140 spr_register(env, SPR_BESCRS, "BESCRS",
8141 &spr_read_ebb, &spr_write_ebb,
8142 &spr_read_generic, &spr_write_generic,
8143 0x00000000);
8144 spr_register(env, SPR_BESCRSU, "BESCRSU",
8145 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
8146 &spr_read_prev_upper32, &spr_write_prev_upper32,
8147 0x00000000);
8148 spr_register(env, SPR_BESCRR, "BESCRR",
8149 &spr_read_ebb, &spr_write_ebb,
8150 &spr_read_generic, &spr_write_generic,
8151 0x00000000);
8152 spr_register(env, SPR_BESCRRU, "BESCRRU",
8153 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
8154 &spr_read_prev_upper32, &spr_write_prev_upper32,
8155 0x00000000);
8156 spr_register_kvm(env, SPR_EBBHR, "EBBHR",
8157 &spr_read_ebb, &spr_write_ebb,
8158 &spr_read_generic, &spr_write_generic,
8159 KVM_REG_PPC_EBBHR, 0x00000000);
8160 spr_register_kvm(env, SPR_EBBRR, "EBBRR",
8161 &spr_read_ebb, &spr_write_ebb,
8162 &spr_read_generic, &spr_write_generic,
8163 KVM_REG_PPC_EBBRR, 0x00000000);
8164 spr_register_kvm(env, SPR_BESCR, "BESCR",
8165 &spr_read_ebb, &spr_write_ebb,
8166 &spr_read_generic, &spr_write_generic,
8167 KVM_REG_PPC_BESCR, 0x00000000);
8168 }
8169
8170 /* Virtual Time Base */
8171 static void gen_spr_vtb(CPUPPCState *env)
8172 {
8173 spr_register_kvm(env, SPR_VTB, "VTB",
8174 SPR_NOACCESS, SPR_NOACCESS,
8175 &spr_read_tbl, SPR_NOACCESS,
8176 KVM_REG_PPC_VTB, 0x00000000);
8177 }
8178
8179 static void gen_spr_power8_fscr(CPUPPCState *env)
8180 {
8181 #if defined(CONFIG_USER_ONLY)
8182 target_ulong initval = 1ULL << FSCR_TAR;
8183 #else
8184 target_ulong initval = 0;
8185 #endif
8186 spr_register_kvm(env, SPR_FSCR, "FSCR",
8187 SPR_NOACCESS, SPR_NOACCESS,
8188 &spr_read_generic, &spr_write_generic,
8189 KVM_REG_PPC_FSCR, initval);
8190 }
8191
8192 static void gen_spr_power8_pspb(CPUPPCState *env)
8193 {
8194 spr_register_kvm(env, SPR_PSPB, "PSPB",
8195 SPR_NOACCESS, SPR_NOACCESS,
8196 &spr_read_generic, &spr_write_generic32,
8197 KVM_REG_PPC_PSPB, 0);
8198 }
8199
8200 static void gen_spr_power8_ic(CPUPPCState *env)
8201 {
8202 #if !defined(CONFIG_USER_ONLY)
8203 spr_register_hv(env, SPR_IC, "IC",
8204 SPR_NOACCESS, SPR_NOACCESS,
8205 &spr_read_generic, SPR_NOACCESS,
8206 &spr_read_generic, &spr_write_generic,
8207 0);
8208 #endif
8209 }
8210
8211 static void gen_spr_power8_book4(CPUPPCState *env)
8212 {
8213 /* Add a number of P8 book4 registers */
8214 #if !defined(CONFIG_USER_ONLY)
8215 spr_register_kvm(env, SPR_ACOP, "ACOP",
8216 SPR_NOACCESS, SPR_NOACCESS,
8217 &spr_read_generic, &spr_write_generic,
8218 KVM_REG_PPC_ACOP, 0);
8219 spr_register_kvm(env, SPR_BOOKS_PID, "PID",
8220 SPR_NOACCESS, SPR_NOACCESS,
8221 &spr_read_generic, &spr_write_pidr,
8222 KVM_REG_PPC_PID, 0);
8223 spr_register_kvm(env, SPR_WORT, "WORT",
8224 SPR_NOACCESS, SPR_NOACCESS,
8225 &spr_read_generic, &spr_write_generic,
8226 KVM_REG_PPC_WORT, 0);
8227 #endif
8228 }
8229
8230 static void gen_spr_power7_book4(CPUPPCState *env)
8231 {
8232 /* Add a number of P7 book4 registers */
8233 #if !defined(CONFIG_USER_ONLY)
8234 spr_register_kvm(env, SPR_ACOP, "ACOP",
8235 SPR_NOACCESS, SPR_NOACCESS,
8236 &spr_read_generic, &spr_write_generic,
8237 KVM_REG_PPC_ACOP, 0);
8238 spr_register_kvm(env, SPR_BOOKS_PID, "PID",
8239 SPR_NOACCESS, SPR_NOACCESS,
8240 &spr_read_generic, &spr_write_generic,
8241 KVM_REG_PPC_PID, 0);
8242 #endif
8243 }
8244
8245 static void gen_spr_power8_rpr(CPUPPCState *env)
8246 {
8247 #if !defined(CONFIG_USER_ONLY)
8248 spr_register_hv(env, SPR_RPR, "RPR",
8249 SPR_NOACCESS, SPR_NOACCESS,
8250 SPR_NOACCESS, SPR_NOACCESS,
8251 &spr_read_generic, &spr_write_generic,
8252 0x00000103070F1F3F);
8253 #endif
8254 }
8255
8256 static void gen_spr_power9_mmu(CPUPPCState *env)
8257 {
8258 #if !defined(CONFIG_USER_ONLY)
8259 /* Partition Table Control */
8260 spr_register_kvm_hv(env, SPR_PTCR, "PTCR",
8261 SPR_NOACCESS, SPR_NOACCESS,
8262 SPR_NOACCESS, SPR_NOACCESS,
8263 &spr_read_generic, &spr_write_ptcr,
8264 KVM_REG_PPC_PTCR, 0x00000000);
8265 #endif
8266 }
8267
8268 static void init_proc_book3s_common(CPUPPCState *env)
8269 {
8270 gen_spr_ne_601(env);
8271 gen_tbl(env);
8272 gen_spr_usprg3(env);
8273 gen_spr_book3s_altivec(env);
8274 gen_spr_book3s_pmu_sup(env);
8275 gen_spr_book3s_pmu_user(env);
8276 gen_spr_book3s_ctrl(env);
8277 }
8278
8279 static void init_proc_970(CPUPPCState *env)
8280 {
8281 /* Common Registers */
8282 init_proc_book3s_common(env);
8283 gen_spr_sdr1(env);
8284 gen_spr_book3s_dbg(env);
8285
8286 /* 970 Specific Registers */
8287 gen_spr_970_hid(env);
8288 gen_spr_970_hior(env);
8289 gen_low_BATs(env);
8290 gen_spr_970_pmu_sup(env);
8291 gen_spr_970_pmu_user(env);
8292 gen_spr_970_lpar(env);
8293 gen_spr_970_dbg(env);
8294
8295 /* env variables */
8296 env->dcache_line_size = 128;
8297 env->icache_line_size = 128;
8298
8299 /* Allocate hardware IRQ controller */
8300 init_excp_970(env);
8301 ppc970_irq_init(ppc_env_get_cpu(env));
8302 }
8303
8304 POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
8305 {
8306 DeviceClass *dc = DEVICE_CLASS(oc);
8307 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8308
8309 dc->desc = "PowerPC 970";
8310 pcc->init_proc = init_proc_970;
8311 pcc->check_pow = check_pow_970;
8312 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
8313 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8314 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8315 PPC_FLOAT_STFIWX |
8316 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8317 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8318 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8319 PPC_64B | PPC_ALTIVEC |
8320 PPC_SEGMENT_64B | PPC_SLBI;
8321 pcc->insns_flags2 = PPC2_FP_CVT_S64;
8322 pcc->msr_mask = (1ull << MSR_SF) |
8323 (1ull << MSR_VR) |
8324 (1ull << MSR_POW) |
8325 (1ull << MSR_EE) |
8326 (1ull << MSR_PR) |
8327 (1ull << MSR_FP) |
8328 (1ull << MSR_ME) |
8329 (1ull << MSR_FE0) |
8330 (1ull << MSR_SE) |
8331 (1ull << MSR_DE) |
8332 (1ull << MSR_FE1) |
8333 (1ull << MSR_IR) |
8334 (1ull << MSR_DR) |
8335 (1ull << MSR_PMM) |
8336 (1ull << MSR_RI);
8337 pcc->mmu_model = POWERPC_MMU_64B;
8338 #if defined(CONFIG_SOFTMMU)
8339 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8340 pcc->hash64_opts = &ppc_hash64_opts_basic;
8341 #endif
8342 pcc->excp_model = POWERPC_EXCP_970;
8343 pcc->bus_model = PPC_FLAGS_INPUT_970;
8344 pcc->bfd_mach = bfd_mach_ppc64;
8345 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8346 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8347 POWERPC_FLAG_BUS_CLK;
8348 pcc->l1_dcache_size = 0x8000;
8349 pcc->l1_icache_size = 0x10000;
8350 }
8351
8352 static void init_proc_power5plus(CPUPPCState *env)
8353 {
8354 /* Common Registers */
8355 init_proc_book3s_common(env);
8356 gen_spr_sdr1(env);
8357 gen_spr_book3s_dbg(env);
8358
8359 /* POWER5+ Specific Registers */
8360 gen_spr_970_hid(env);
8361 gen_spr_970_hior(env);
8362 gen_low_BATs(env);
8363 gen_spr_970_pmu_sup(env);
8364 gen_spr_970_pmu_user(env);
8365 gen_spr_power5p_common(env);
8366 gen_spr_power5p_lpar(env);
8367 gen_spr_power5p_ear(env);
8368
8369 /* env variables */
8370 env->dcache_line_size = 128;
8371 env->icache_line_size = 128;
8372
8373 /* Allocate hardware IRQ controller */
8374 init_excp_970(env);
8375 ppc970_irq_init(ppc_env_get_cpu(env));
8376 }
8377
8378 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
8379 {
8380 DeviceClass *dc = DEVICE_CLASS(oc);
8381 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8382
8383 dc->fw_name = "PowerPC,POWER5";
8384 dc->desc = "POWER5+";
8385 pcc->init_proc = init_proc_power5plus;
8386 pcc->check_pow = check_pow_970;
8387 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
8388 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8389 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8390 PPC_FLOAT_STFIWX |
8391 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8392 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8393 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8394 PPC_64B |
8395 PPC_SEGMENT_64B | PPC_SLBI;
8396 pcc->insns_flags2 = PPC2_FP_CVT_S64;
8397 pcc->msr_mask = (1ull << MSR_SF) |
8398 (1ull << MSR_VR) |
8399 (1ull << MSR_POW) |
8400 (1ull << MSR_EE) |
8401 (1ull << MSR_PR) |
8402 (1ull << MSR_FP) |
8403 (1ull << MSR_ME) |
8404 (1ull << MSR_FE0) |
8405 (1ull << MSR_SE) |
8406 (1ull << MSR_DE) |
8407 (1ull << MSR_FE1) |
8408 (1ull << MSR_IR) |
8409 (1ull << MSR_DR) |
8410 (1ull << MSR_PMM) |
8411 (1ull << MSR_RI);
8412 pcc->mmu_model = POWERPC_MMU_2_03;
8413 #if defined(CONFIG_SOFTMMU)
8414 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8415 pcc->hash64_opts = &ppc_hash64_opts_basic;
8416 pcc->lrg_decr_bits = 32;
8417 #endif
8418 pcc->excp_model = POWERPC_EXCP_970;
8419 pcc->bus_model = PPC_FLAGS_INPUT_970;
8420 pcc->bfd_mach = bfd_mach_ppc64;
8421 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8422 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8423 POWERPC_FLAG_BUS_CLK;
8424 pcc->l1_dcache_size = 0x8000;
8425 pcc->l1_icache_size = 0x10000;
8426 }
8427
8428 /*
8429 * The CPU used to have a "compat" property which set the
8430 * compatibility mode PVR. However, this was conceptually broken - it
8431 * only makes sense on the pseries machine type (otherwise the guest
8432 * owns the PCR and can control the compatibility mode itself). It's
8433 * been replaced with the 'max-cpu-compat' property on the pseries
8434 * machine type. For backwards compatibility, pseries specially
8435 * parses the -cpu parameter and converts old compat= parameters into
8436 * the appropriate machine parameters. This stub implementation of
8437 * the parameter catches any uses on explicitly created CPUs.
8438 */
8439 static void getset_compat_deprecated(Object *obj, Visitor *v, const char *name,
8440 void *opaque, Error **errp)
8441 {
8442 QNull *null = NULL;
8443
8444 if (!qtest_enabled()) {
8445 warn_report("CPU 'compat' property is deprecated and has no effect; "
8446 "use max-cpu-compat machine property instead");
8447 }
8448 visit_type_null(v, name, &null, NULL);
8449 qobject_unref(null);
8450 }
8451
8452 static const PropertyInfo ppc_compat_deprecated_propinfo = {
8453 .name = "str",
8454 .description = "compatibility mode (deprecated)",
8455 .get = getset_compat_deprecated,
8456 .set = getset_compat_deprecated,
8457 };
8458 static Property powerpc_servercpu_properties[] = {
8459 {
8460 .name = "compat",
8461 .info = &ppc_compat_deprecated_propinfo,
8462 },
8463 DEFINE_PROP_END_OF_LIST(),
8464 };
8465
8466 static void init_proc_POWER7(CPUPPCState *env)
8467 {
8468 /* Common Registers */
8469 init_proc_book3s_common(env);
8470 gen_spr_sdr1(env);
8471 gen_spr_book3s_dbg(env);
8472
8473 /* POWER7 Specific Registers */
8474 gen_spr_book3s_ids(env);
8475 gen_spr_amr(env);
8476 gen_spr_book3s_purr(env);
8477 gen_spr_power5p_common(env);
8478 gen_spr_power5p_lpar(env);
8479 gen_spr_power5p_ear(env);
8480 gen_spr_power6_common(env);
8481 gen_spr_power6_dbg(env);
8482 gen_spr_power7_book4(env);
8483
8484 /* env variables */
8485 env->dcache_line_size = 128;
8486 env->icache_line_size = 128;
8487
8488 /* Allocate hardware IRQ controller */
8489 init_excp_POWER7(env);
8490 ppcPOWER7_irq_init(ppc_env_get_cpu(env));
8491 }
8492
8493 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr)
8494 {
8495 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) {
8496 return true;
8497 }
8498 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) {
8499 return true;
8500 }
8501 return false;
8502 }
8503
8504 static bool cpu_has_work_POWER7(CPUState *cs)
8505 {
8506 PowerPCCPU *cpu = POWERPC_CPU(cs);
8507 CPUPPCState *env = &cpu->env;
8508
8509 if (cs->halted) {
8510 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
8511 return false;
8512 }
8513 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
8514 (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) {
8515 return true;
8516 }
8517 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
8518 (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) {
8519 return true;
8520 }
8521 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
8522 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
8523 return true;
8524 }
8525 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
8526 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
8527 return true;
8528 }
8529 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
8530 return true;
8531 }
8532 return false;
8533 } else {
8534 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
8535 }
8536 }
8537
8538 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
8539 {
8540 DeviceClass *dc = DEVICE_CLASS(oc);
8541 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8542 CPUClass *cc = CPU_CLASS(oc);
8543
8544 dc->fw_name = "PowerPC,POWER7";
8545 dc->desc = "POWER7";
8546 dc->props = powerpc_servercpu_properties;
8547 pcc->pvr_match = ppc_pvr_match_power7;
8548 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05;
8549 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
8550 pcc->init_proc = init_proc_POWER7;
8551 pcc->check_pow = check_pow_nocheck;
8552 cc->has_work = cpu_has_work_POWER7;
8553 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
8554 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8555 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8556 PPC_FLOAT_FRSQRTES |
8557 PPC_FLOAT_STFIWX |
8558 PPC_FLOAT_EXT |
8559 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8560 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8561 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8562 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
8563 PPC_SEGMENT_64B | PPC_SLBI |
8564 PPC_POPCNTB | PPC_POPCNTWD |
8565 PPC_CILDST;
8566 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
8567 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
8568 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
8569 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 |
8570 PPC2_PM_ISA206;
8571 pcc->msr_mask = (1ull << MSR_SF) |
8572 (1ull << MSR_VR) |
8573 (1ull << MSR_VSX) |
8574 (1ull << MSR_EE) |
8575 (1ull << MSR_PR) |
8576 (1ull << MSR_FP) |
8577 (1ull << MSR_ME) |
8578 (1ull << MSR_FE0) |
8579 (1ull << MSR_SE) |
8580 (1ull << MSR_DE) |
8581 (1ull << MSR_FE1) |
8582 (1ull << MSR_IR) |
8583 (1ull << MSR_DR) |
8584 (1ull << MSR_PMM) |
8585 (1ull << MSR_RI) |
8586 (1ull << MSR_LE);
8587 pcc->mmu_model = POWERPC_MMU_2_06;
8588 #if defined(CONFIG_SOFTMMU)
8589 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8590 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
8591 pcc->lrg_decr_bits = 32;
8592 #endif
8593 pcc->excp_model = POWERPC_EXCP_POWER7;
8594 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
8595 pcc->bfd_mach = bfd_mach_ppc64;
8596 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8597 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8598 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
8599 POWERPC_FLAG_VSX;
8600 pcc->l1_dcache_size = 0x8000;
8601 pcc->l1_icache_size = 0x8000;
8602 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
8603 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2;
8604 }
8605
8606 static void init_proc_POWER8(CPUPPCState *env)
8607 {
8608 /* Common Registers */
8609 init_proc_book3s_common(env);
8610 gen_spr_sdr1(env);
8611 gen_spr_book3s_207_dbg(env);
8612
8613 /* POWER8 Specific Registers */
8614 gen_spr_book3s_ids(env);
8615 gen_spr_amr(env);
8616 gen_spr_iamr(env);
8617 gen_spr_book3s_purr(env);
8618 gen_spr_power5p_common(env);
8619 gen_spr_power5p_lpar(env);
8620 gen_spr_power5p_ear(env);
8621 gen_spr_power6_common(env);
8622 gen_spr_power6_dbg(env);
8623 gen_spr_power8_tce_address_control(env);
8624 gen_spr_power8_ids(env);
8625 gen_spr_power8_ebb(env);
8626 gen_spr_power8_fscr(env);
8627 gen_spr_power8_pmu_sup(env);
8628 gen_spr_power8_pmu_user(env);
8629 gen_spr_power8_tm(env);
8630 gen_spr_power8_pspb(env);
8631 gen_spr_vtb(env);
8632 gen_spr_power8_ic(env);
8633 gen_spr_power8_book4(env);
8634 gen_spr_power8_rpr(env);
8635
8636 /* env variables */
8637 env->dcache_line_size = 128;
8638 env->icache_line_size = 128;
8639
8640 /* Allocate hardware IRQ controller */
8641 init_excp_POWER8(env);
8642 ppcPOWER7_irq_init(ppc_env_get_cpu(env));
8643 }
8644
8645 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr)
8646 {
8647 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) {
8648 return true;
8649 }
8650 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) {
8651 return true;
8652 }
8653 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) {
8654 return true;
8655 }
8656 return false;
8657 }
8658
8659 static bool cpu_has_work_POWER8(CPUState *cs)
8660 {
8661 PowerPCCPU *cpu = POWERPC_CPU(cs);
8662 CPUPPCState *env = &cpu->env;
8663
8664 if (cs->halted) {
8665 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
8666 return false;
8667 }
8668 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
8669 (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) {
8670 return true;
8671 }
8672 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
8673 (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) {
8674 return true;
8675 }
8676 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
8677 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
8678 return true;
8679 }
8680 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
8681 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
8682 return true;
8683 }
8684 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
8685 (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) {
8686 return true;
8687 }
8688 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
8689 (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) {
8690 return true;
8691 }
8692 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
8693 return true;
8694 }
8695 return false;
8696 } else {
8697 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
8698 }
8699 }
8700
8701 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
8702 {
8703 DeviceClass *dc = DEVICE_CLASS(oc);
8704 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8705 CPUClass *cc = CPU_CLASS(oc);
8706
8707 dc->fw_name = "PowerPC,POWER8";
8708 dc->desc = "POWER8";
8709 dc->props = powerpc_servercpu_properties;
8710 pcc->pvr_match = ppc_pvr_match_power8;
8711 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
8712 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
8713 pcc->init_proc = init_proc_POWER8;
8714 pcc->check_pow = check_pow_nocheck;
8715 cc->has_work = cpu_has_work_POWER8;
8716 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
8717 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8718 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8719 PPC_FLOAT_FRSQRTES |
8720 PPC_FLOAT_STFIWX |
8721 PPC_FLOAT_EXT |
8722 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8723 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8724 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8725 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
8726 PPC_SEGMENT_64B | PPC_SLBI |
8727 PPC_POPCNTB | PPC_POPCNTWD |
8728 PPC_CILDST;
8729 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
8730 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
8731 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
8732 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
8733 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
8734 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
8735 PPC2_TM | PPC2_PM_ISA206;
8736 pcc->msr_mask = (1ull << MSR_SF) |
8737 (1ull << MSR_SHV) |
8738 (1ull << MSR_TM) |
8739 (1ull << MSR_VR) |
8740 (1ull << MSR_VSX) |
8741 (1ull << MSR_EE) |
8742 (1ull << MSR_PR) |
8743 (1ull << MSR_FP) |
8744 (1ull << MSR_ME) |
8745 (1ull << MSR_FE0) |
8746 (1ull << MSR_SE) |
8747 (1ull << MSR_DE) |
8748 (1ull << MSR_FE1) |
8749 (1ull << MSR_IR) |
8750 (1ull << MSR_DR) |
8751 (1ull << MSR_PMM) |
8752 (1ull << MSR_RI) |
8753 (1ull << MSR_TS0) |
8754 (1ull << MSR_TS1) |
8755 (1ull << MSR_LE);
8756 pcc->mmu_model = POWERPC_MMU_2_07;
8757 #if defined(CONFIG_SOFTMMU)
8758 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8759 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
8760 pcc->lrg_decr_bits = 32;
8761 #endif
8762 pcc->excp_model = POWERPC_EXCP_POWER8;
8763 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
8764 pcc->bfd_mach = bfd_mach_ppc64;
8765 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8766 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8767 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
8768 POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
8769 pcc->l1_dcache_size = 0x8000;
8770 pcc->l1_icache_size = 0x8000;
8771 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
8772 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
8773 LPCR_P8_PECE3 | LPCR_P8_PECE4;
8774 }
8775
8776 #ifdef CONFIG_SOFTMMU
8777 /*
8778 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
8779 * Encoded as array of int_32s in the form:
8780 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
8781 * x -> AP encoding
8782 * y -> radix mode supported page size (encoded as a shift)
8783 */
8784 static struct ppc_radix_page_info POWER9_radix_page_info = {
8785 .count = 4,
8786 .entries = {
8787 0x0000000c, /* 4K - enc: 0x0 */
8788 0xa0000010, /* 64K - enc: 0x5 */
8789 0x20000015, /* 2M - enc: 0x1 */
8790 0x4000001e /* 1G - enc: 0x2 */
8791 }
8792 };
8793 #endif /* CONFIG_SOFTMMU */
8794
8795 static void init_proc_POWER9(CPUPPCState *env)
8796 {
8797 /* Common Registers */
8798 init_proc_book3s_common(env);
8799 gen_spr_book3s_207_dbg(env);
8800
8801 /* POWER8 Specific Registers */
8802 gen_spr_book3s_ids(env);
8803 gen_spr_amr(env);
8804 gen_spr_iamr(env);
8805 gen_spr_book3s_purr(env);
8806 gen_spr_power5p_common(env);
8807 gen_spr_power5p_lpar(env);
8808 gen_spr_power5p_ear(env);
8809 gen_spr_power6_common(env);
8810 gen_spr_power6_dbg(env);
8811 gen_spr_power8_tce_address_control(env);
8812 gen_spr_power8_ids(env);
8813 gen_spr_power8_ebb(env);
8814 gen_spr_power8_fscr(env);
8815 gen_spr_power8_pmu_sup(env);
8816 gen_spr_power8_pmu_user(env);
8817 gen_spr_power8_tm(env);
8818 gen_spr_power8_pspb(env);
8819 gen_spr_vtb(env);
8820 gen_spr_power8_ic(env);
8821 gen_spr_power8_book4(env);
8822 gen_spr_power8_rpr(env);
8823 gen_spr_power9_mmu(env);
8824
8825 /* POWER9 Specific registers */
8826 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
8827 spr_read_generic, spr_write_generic,
8828 KVM_REG_PPC_TIDR, 0);
8829
8830 /* FIXME: Filter fields properly based on privilege level */
8831 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
8832 spr_read_generic, spr_write_generic,
8833 KVM_REG_PPC_PSSCR, 0);
8834
8835 /* env variables */
8836 env->dcache_line_size = 128;
8837 env->icache_line_size = 128;
8838
8839 /* Allocate hardware IRQ controller */
8840 init_excp_POWER9(env);
8841 ppcPOWER9_irq_init(ppc_env_get_cpu(env));
8842 }
8843
8844 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr)
8845 {
8846 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) {
8847 return true;
8848 }
8849 return false;
8850 }
8851
8852 static bool cpu_has_work_POWER9(CPUState *cs)
8853 {
8854 PowerPCCPU *cpu = POWERPC_CPU(cs);
8855 CPUPPCState *env = &cpu->env;
8856
8857 if (cs->halted) {
8858 uint64_t psscr = env->spr[SPR_PSSCR];
8859
8860 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
8861 return false;
8862 }
8863
8864 /* If EC is clear, just return true on any pending interrupt */
8865 if (!(psscr & PSSCR_EC)) {
8866 return true;
8867 }
8868 /* External Exception */
8869 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
8870 (env->spr[SPR_LPCR] & LPCR_EEE)) {
8871 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
8872 if (heic == 0 || !msr_hv || msr_pr) {
8873 return true;
8874 }
8875 }
8876 /* Decrementer Exception */
8877 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
8878 (env->spr[SPR_LPCR] & LPCR_DEE)) {
8879 return true;
8880 }
8881 /* Machine Check or Hypervisor Maintenance Exception */
8882 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
8883 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
8884 return true;
8885 }
8886 /* Privileged Doorbell Exception */
8887 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
8888 (env->spr[SPR_LPCR] & LPCR_PDEE)) {
8889 return true;
8890 }
8891 /* Hypervisor Doorbell Exception */
8892 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
8893 (env->spr[SPR_LPCR] & LPCR_HDEE)) {
8894 return true;
8895 }
8896 /* Hypervisor virtualization exception */
8897 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) &&
8898 (env->spr[SPR_LPCR] & LPCR_HVEE)) {
8899 return true;
8900 }
8901 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
8902 return true;
8903 }
8904 return false;
8905 } else {
8906 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
8907 }
8908 }
8909
8910 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
8911 {
8912 DeviceClass *dc = DEVICE_CLASS(oc);
8913 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8914 CPUClass *cc = CPU_CLASS(oc);
8915
8916 dc->fw_name = "PowerPC,POWER9";
8917 dc->desc = "POWER9";
8918 dc->props = powerpc_servercpu_properties;
8919 pcc->pvr_match = ppc_pvr_match_power9;
8920 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07;
8921 pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 |
8922 PCR_COMPAT_2_05;
8923 pcc->init_proc = init_proc_POWER9;
8924 pcc->check_pow = check_pow_nocheck;
8925 cc->has_work = cpu_has_work_POWER9;
8926 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
8927 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8928 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8929 PPC_FLOAT_FRSQRTES |
8930 PPC_FLOAT_STFIWX |
8931 PPC_FLOAT_EXT |
8932 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8933 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8934 PPC_MEM_TLBSYNC |
8935 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
8936 PPC_SEGMENT_64B | PPC_SLBI |
8937 PPC_POPCNTB | PPC_POPCNTWD |
8938 PPC_CILDST;
8939 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
8940 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
8941 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
8942 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
8943 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
8944 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
8945 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL;
8946 pcc->msr_mask = (1ull << MSR_SF) |
8947 (1ull << MSR_SHV) |
8948 (1ull << MSR_TM) |
8949 (1ull << MSR_VR) |
8950 (1ull << MSR_VSX) |
8951 (1ull << MSR_EE) |
8952 (1ull << MSR_PR) |
8953 (1ull << MSR_FP) |
8954 (1ull << MSR_ME) |
8955 (1ull << MSR_FE0) |
8956 (1ull << MSR_SE) |
8957 (1ull << MSR_DE) |
8958 (1ull << MSR_FE1) |
8959 (1ull << MSR_IR) |
8960 (1ull << MSR_DR) |
8961 (1ull << MSR_PMM) |
8962 (1ull << MSR_RI) |
8963 (1ull << MSR_LE);
8964 pcc->mmu_model = POWERPC_MMU_3_00;
8965 #if defined(CONFIG_SOFTMMU)
8966 pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault;
8967 /* segment page size remain the same */
8968 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
8969 pcc->radix_page_info = &POWER9_radix_page_info;
8970 pcc->lrg_decr_bits = 56;
8971 #endif
8972 pcc->excp_model = POWERPC_EXCP_POWER9;
8973 pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
8974 pcc->bfd_mach = bfd_mach_ppc64;
8975 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8976 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8977 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
8978 POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
8979 pcc->l1_dcache_size = 0x8000;
8980 pcc->l1_icache_size = 0x8000;
8981 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
8982 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
8983 }
8984
8985 #if !defined(CONFIG_USER_ONLY)
8986 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
8987 {
8988 CPUPPCState *env = &cpu->env;
8989
8990 cpu->vhyp = vhyp;
8991
8992 /*
8993 * With a virtual hypervisor mode we never allow the CPU to go
8994 * hypervisor mode itself
8995 */
8996 env->msr_mask &= ~MSR_HVB;
8997 }
8998
8999 #endif /* !defined(CONFIG_USER_ONLY) */
9000
9001 #endif /* defined(TARGET_PPC64) */
9002
9003 /*****************************************************************************/
9004 /* Generic CPU instantiation routine */
9005 static void init_ppc_proc(PowerPCCPU *cpu)
9006 {
9007 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9008 CPUPPCState *env = &cpu->env;
9009 #if !defined(CONFIG_USER_ONLY)
9010 int i;
9011
9012 env->irq_inputs = NULL;
9013 /* Set all exception vectors to an invalid address */
9014 for (i = 0; i < POWERPC_EXCP_NB; i++) {
9015 env->excp_vectors[i] = (target_ulong)(-1ULL);
9016 }
9017 env->ivor_mask = 0x00000000;
9018 env->ivpr_mask = 0x00000000;
9019 /* Default MMU definitions */
9020 env->nb_BATs = 0;
9021 env->nb_tlb = 0;
9022 env->nb_ways = 0;
9023 env->tlb_type = TLB_NONE;
9024 #endif
9025 /* Register SPR common to all PowerPC implementations */
9026 gen_spr_generic(env);
9027 spr_register(env, SPR_PVR, "PVR",
9028 /* Linux permits userspace to read PVR */
9029 #if defined(CONFIG_LINUX_USER)
9030 &spr_read_generic,
9031 #else
9032 SPR_NOACCESS,
9033 #endif
9034 SPR_NOACCESS,
9035 &spr_read_generic, SPR_NOACCESS,
9036 pcc->pvr);
9037 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
9038 if (pcc->svr != POWERPC_SVR_NONE) {
9039 if (pcc->svr & POWERPC_SVR_E500) {
9040 spr_register(env, SPR_E500_SVR, "SVR",
9041 SPR_NOACCESS, SPR_NOACCESS,
9042 &spr_read_generic, SPR_NOACCESS,
9043 pcc->svr & ~POWERPC_SVR_E500);
9044 } else {
9045 spr_register(env, SPR_SVR, "SVR",
9046 SPR_NOACCESS, SPR_NOACCESS,
9047 &spr_read_generic, SPR_NOACCESS,
9048 pcc->svr);
9049 }
9050 }
9051 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
9052 (*pcc->init_proc)(env);
9053
9054 #if !defined(CONFIG_USER_ONLY)
9055 ppc_gdb_gen_spr_xml(cpu);
9056 #endif
9057
9058 /* MSR bits & flags consistency checks */
9059 if (env->msr_mask & (1 << 25)) {
9060 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9061 case POWERPC_FLAG_SPE:
9062 case POWERPC_FLAG_VRE:
9063 break;
9064 default:
9065 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9066 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
9067 exit(1);
9068 }
9069 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9070 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9071 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
9072 exit(1);
9073 }
9074 if (env->msr_mask & (1 << 17)) {
9075 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9076 case POWERPC_FLAG_TGPR:
9077 case POWERPC_FLAG_CE:
9078 break;
9079 default:
9080 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9081 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
9082 exit(1);
9083 }
9084 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9085 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9086 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
9087 exit(1);
9088 }
9089 if (env->msr_mask & (1 << 10)) {
9090 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9091 POWERPC_FLAG_UBLE)) {
9092 case POWERPC_FLAG_SE:
9093 case POWERPC_FLAG_DWE:
9094 case POWERPC_FLAG_UBLE:
9095 break;
9096 default:
9097 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9098 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
9099 "POWERPC_FLAG_UBLE\n");
9100 exit(1);
9101 }
9102 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9103 POWERPC_FLAG_UBLE)) {
9104 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9105 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
9106 "POWERPC_FLAG_UBLE\n");
9107 exit(1);
9108 }
9109 if (env->msr_mask & (1 << 9)) {
9110 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9111 case POWERPC_FLAG_BE:
9112 case POWERPC_FLAG_DE:
9113 break;
9114 default:
9115 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9116 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
9117 exit(1);
9118 }
9119 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9120 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9121 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
9122 exit(1);
9123 }
9124 if (env->msr_mask & (1 << 2)) {
9125 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9126 case POWERPC_FLAG_PX:
9127 case POWERPC_FLAG_PMM:
9128 break;
9129 default:
9130 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9131 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
9132 exit(1);
9133 }
9134 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9135 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9136 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
9137 exit(1);
9138 }
9139 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
9140 fprintf(stderr, "PowerPC flags inconsistency\n"
9141 "Should define the time-base and decrementer clock source\n");
9142 exit(1);
9143 }
9144 /* Allocate TLBs buffer when needed */
9145 #if !defined(CONFIG_USER_ONLY)
9146 if (env->nb_tlb != 0) {
9147 int nb_tlb = env->nb_tlb;
9148 if (env->id_tlbs != 0) {
9149 nb_tlb *= 2;
9150 }
9151 switch (env->tlb_type) {
9152 case TLB_6XX:
9153 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb);
9154 break;
9155 case TLB_EMB:
9156 env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb);
9157 break;
9158 case TLB_MAS:
9159 env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb);
9160 break;
9161 }
9162 /* Pre-compute some useful values */
9163 env->tlb_per_way = env->nb_tlb / env->nb_ways;
9164 }
9165 if (env->irq_inputs == NULL) {
9166 warn_report("no internal IRQ controller registered."
9167 " Attempt QEMU to crash very soon !");
9168 }
9169 #endif
9170 if (env->check_pow == NULL) {
9171 warn_report("no power management check handler registered."
9172 " Attempt QEMU to crash very soon !");
9173 }
9174 }
9175
9176 #if defined(PPC_DUMP_CPU)
9177 static void dump_ppc_sprs(CPUPPCState *env)
9178 {
9179 ppc_spr_t *spr;
9180 #if !defined(CONFIG_USER_ONLY)
9181 uint32_t sr, sw;
9182 #endif
9183 uint32_t ur, uw;
9184 int i, j, n;
9185
9186 printf("Special purpose registers:\n");
9187 for (i = 0; i < 32; i++) {
9188 for (j = 0; j < 32; j++) {
9189 n = (i << 5) | j;
9190 spr = &env->spr_cb[n];
9191 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
9192 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
9193 #if !defined(CONFIG_USER_ONLY)
9194 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
9195 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
9196 if (sw || sr || uw || ur) {
9197 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
9198 (i << 5) | j, (i << 5) | j, spr->name,
9199 sw ? 'w' : '-', sr ? 'r' : '-',
9200 uw ? 'w' : '-', ur ? 'r' : '-');
9201 }
9202 #else
9203 if (uw || ur) {
9204 printf("SPR: %4d (%03x) %-8s u%c%c\n",
9205 (i << 5) | j, (i << 5) | j, spr->name,
9206 uw ? 'w' : '-', ur ? 'r' : '-');
9207 }
9208 #endif
9209 }
9210 }
9211 fflush(stdout);
9212 fflush(stderr);
9213 }
9214 #endif
9215
9216 /*****************************************************************************/
9217
9218 /* Opcode types */
9219 enum {
9220 PPC_DIRECT = 0, /* Opcode routine */
9221 PPC_INDIRECT = 1, /* Indirect opcode table */
9222 };
9223
9224 #define PPC_OPCODE_MASK 0x3
9225
9226 static inline int is_indirect_opcode(void *handler)
9227 {
9228 return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT;
9229 }
9230
9231 static inline opc_handler_t **ind_table(void *handler)
9232 {
9233 return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK);
9234 }
9235
9236 /* Instruction table creation */
9237 /* Opcodes tables creation */
9238 static void fill_new_table(opc_handler_t **table, int len)
9239 {
9240 int i;
9241
9242 for (i = 0; i < len; i++) {
9243 table[i] = &invalid_handler;
9244 }
9245 }
9246
9247 static int create_new_table(opc_handler_t **table, unsigned char idx)
9248 {
9249 opc_handler_t **tmp;
9250
9251 tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN);
9252 fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN);
9253 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
9254
9255 return 0;
9256 }
9257
9258 static int insert_in_table(opc_handler_t **table, unsigned char idx,
9259 opc_handler_t *handler)
9260 {
9261 if (table[idx] != &invalid_handler) {
9262 return -1;
9263 }
9264 table[idx] = handler;
9265
9266 return 0;
9267 }
9268
9269 static int register_direct_insn(opc_handler_t **ppc_opcodes,
9270 unsigned char idx, opc_handler_t *handler)
9271 {
9272 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
9273 printf("*** ERROR: opcode %02x already assigned in main "
9274 "opcode table\n", idx);
9275 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9276 printf(" Registered handler '%s' - new handler '%s'\n",
9277 ppc_opcodes[idx]->oname, handler->oname);
9278 #endif
9279 return -1;
9280 }
9281
9282 return 0;
9283 }
9284
9285 static int register_ind_in_table(opc_handler_t **table,
9286 unsigned char idx1, unsigned char idx2,
9287 opc_handler_t *handler)
9288 {
9289 if (table[idx1] == &invalid_handler) {
9290 if (create_new_table(table, idx1) < 0) {
9291 printf("*** ERROR: unable to create indirect table "
9292 "idx=%02x\n", idx1);
9293 return -1;
9294 }
9295 } else {
9296 if (!is_indirect_opcode(table[idx1])) {
9297 printf("*** ERROR: idx %02x already assigned to a direct "
9298 "opcode\n", idx1);
9299 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9300 printf(" Registered handler '%s' - new handler '%s'\n",
9301 ind_table(table[idx1])[idx2]->oname, handler->oname);
9302 #endif
9303 return -1;
9304 }
9305 }
9306 if (handler != NULL &&
9307 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
9308 printf("*** ERROR: opcode %02x already assigned in "
9309 "opcode table %02x\n", idx2, idx1);
9310 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9311 printf(" Registered handler '%s' - new handler '%s'\n",
9312 ind_table(table[idx1])[idx2]->oname, handler->oname);
9313 #endif
9314 return -1;
9315 }
9316
9317 return 0;
9318 }
9319
9320 static int register_ind_insn(opc_handler_t **ppc_opcodes,
9321 unsigned char idx1, unsigned char idx2,
9322 opc_handler_t *handler)
9323 {
9324 return register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
9325 }
9326
9327 static int register_dblind_insn(opc_handler_t **ppc_opcodes,
9328 unsigned char idx1, unsigned char idx2,
9329 unsigned char idx3, opc_handler_t *handler)
9330 {
9331 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9332 printf("*** ERROR: unable to join indirect table idx "
9333 "[%02x-%02x]\n", idx1, idx2);
9334 return -1;
9335 }
9336 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
9337 handler) < 0) {
9338 printf("*** ERROR: unable to insert opcode "
9339 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
9340 return -1;
9341 }
9342
9343 return 0;
9344 }
9345
9346 static int register_trplind_insn(opc_handler_t **ppc_opcodes,
9347 unsigned char idx1, unsigned char idx2,
9348 unsigned char idx3, unsigned char idx4,
9349 opc_handler_t *handler)
9350 {
9351 opc_handler_t **table;
9352
9353 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9354 printf("*** ERROR: unable to join indirect table idx "
9355 "[%02x-%02x]\n", idx1, idx2);
9356 return -1;
9357 }
9358 table = ind_table(ppc_opcodes[idx1]);
9359 if (register_ind_in_table(table, idx2, idx3, NULL) < 0) {
9360 printf("*** ERROR: unable to join 2nd-level indirect table idx "
9361 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
9362 return -1;
9363 }
9364 table = ind_table(table[idx2]);
9365 if (register_ind_in_table(table, idx3, idx4, handler) < 0) {
9366 printf("*** ERROR: unable to insert opcode "
9367 "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4);
9368 return -1;
9369 }
9370 return 0;
9371 }
9372 static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn)
9373 {
9374 if (insn->opc2 != 0xFF) {
9375 if (insn->opc3 != 0xFF) {
9376 if (insn->opc4 != 0xFF) {
9377 if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2,
9378 insn->opc3, insn->opc4,
9379 &insn->handler) < 0) {
9380 return -1;
9381 }
9382 } else {
9383 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
9384 insn->opc3, &insn->handler) < 0) {
9385 return -1;
9386 }
9387 }
9388 } else {
9389 if (register_ind_insn(ppc_opcodes, insn->opc1,
9390 insn->opc2, &insn->handler) < 0) {
9391 return -1;
9392 }
9393 }
9394 } else {
9395 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) {
9396 return -1;
9397 }
9398 }
9399
9400 return 0;
9401 }
9402
9403 static int test_opcode_table(opc_handler_t **table, int len)
9404 {
9405 int i, count, tmp;
9406
9407 for (i = 0, count = 0; i < len; i++) {
9408 /* Consistency fixup */
9409 if (table[i] == NULL) {
9410 table[i] = &invalid_handler;
9411 }
9412 if (table[i] != &invalid_handler) {
9413 if (is_indirect_opcode(table[i])) {
9414 tmp = test_opcode_table(ind_table(table[i]),
9415 PPC_CPU_INDIRECT_OPCODES_LEN);
9416 if (tmp == 0) {
9417 free(table[i]);
9418 table[i] = &invalid_handler;
9419 } else {
9420 count++;
9421 }
9422 } else {
9423 count++;
9424 }
9425 }
9426 }
9427
9428 return count;
9429 }
9430
9431 static void fix_opcode_tables(opc_handler_t **ppc_opcodes)
9432 {
9433 if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) {
9434 printf("*** WARNING: no opcode defined !\n");
9435 }
9436 }
9437
9438 /*****************************************************************************/
9439 static void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp)
9440 {
9441 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9442 CPUPPCState *env = &cpu->env;
9443 opcode_t *opc;
9444
9445 fill_new_table(env->opcodes, PPC_CPU_OPCODES_LEN);
9446 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
9447 if (((opc->handler.type & pcc->insns_flags) != 0) ||
9448 ((opc->handler.type2 & pcc->insns_flags2) != 0)) {
9449 if (register_insn(env->opcodes, opc) < 0) {
9450 error_setg(errp, "ERROR initializing PowerPC instruction "
9451 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2,
9452 opc->opc3);
9453 return;
9454 }
9455 }
9456 }
9457 fix_opcode_tables(env->opcodes);
9458 fflush(stdout);
9459 fflush(stderr);
9460 }
9461
9462 #if defined(PPC_DUMP_CPU)
9463 static void dump_ppc_insns(CPUPPCState *env)
9464 {
9465 opc_handler_t **table, *handler;
9466 const char *p, *q;
9467 uint8_t opc1, opc2, opc3, opc4;
9468
9469 printf("Instructions set:\n");
9470 /* opc1 is 6 bits long */
9471 for (opc1 = 0x00; opc1 < PPC_CPU_OPCODES_LEN; opc1++) {
9472 table = env->opcodes;
9473 handler = table[opc1];
9474 if (is_indirect_opcode(handler)) {
9475 /* opc2 is 5 bits long */
9476 for (opc2 = 0; opc2 < PPC_CPU_INDIRECT_OPCODES_LEN; opc2++) {
9477 table = env->opcodes;
9478 handler = env->opcodes[opc1];
9479 table = ind_table(handler);
9480 handler = table[opc2];
9481 if (is_indirect_opcode(handler)) {
9482 table = ind_table(handler);
9483 /* opc3 is 5 bits long */
9484 for (opc3 = 0; opc3 < PPC_CPU_INDIRECT_OPCODES_LEN;
9485 opc3++) {
9486 handler = table[opc3];
9487 if (is_indirect_opcode(handler)) {
9488 table = ind_table(handler);
9489 /* opc4 is 5 bits long */
9490 for (opc4 = 0; opc4 < PPC_CPU_INDIRECT_OPCODES_LEN;
9491 opc4++) {
9492 handler = table[opc4];
9493 if (handler->handler != &gen_invalid) {
9494 printf("INSN: %02x %02x %02x %02x -- "
9495 "(%02d %04d %02d) : %s\n",
9496 opc1, opc2, opc3, opc4,
9497 opc1, (opc3 << 5) | opc2, opc4,
9498 handler->oname);
9499 }
9500 }
9501 } else {
9502 if (handler->handler != &gen_invalid) {
9503 /* Special hack to properly dump SPE insns */
9504 p = strchr(handler->oname, '_');
9505 if (p == NULL) {
9506 printf("INSN: %02x %02x %02x (%02d %04d) : "
9507 "%s\n",
9508 opc1, opc2, opc3, opc1,
9509 (opc3 << 5) | opc2,
9510 handler->oname);
9511 } else {
9512 q = "speundef";
9513 if ((p - handler->oname) != strlen(q)
9514 || (memcmp(handler->oname, q, strlen(q))
9515 != 0)) {
9516 /* First instruction */
9517 printf("INSN: %02x %02x %02x"
9518 "(%02d %04d) : %.*s\n",
9519 opc1, opc2 << 1, opc3, opc1,
9520 (opc3 << 6) | (opc2 << 1),
9521 (int)(p - handler->oname),
9522 handler->oname);
9523 }
9524 if (strcmp(p + 1, q) != 0) {
9525 /* Second instruction */
9526 printf("INSN: %02x %02x %02x "
9527 "(%02d %04d) : %s\n", opc1,
9528 (opc2 << 1) | 1, opc3, opc1,
9529 (opc3 << 6) | (opc2 << 1) | 1,
9530 p + 1);
9531 }
9532 }
9533 }
9534 }
9535 }
9536 } else {
9537 if (handler->handler != &gen_invalid) {
9538 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
9539 opc1, opc2, opc1, opc2, handler->oname);
9540 }
9541 }
9542 }
9543 } else {
9544 if (handler->handler != &gen_invalid) {
9545 printf("INSN: %02x -- -- (%02d ----) : %s\n",
9546 opc1, opc1, handler->oname);
9547 }
9548 }
9549 }
9550 }
9551 #endif
9552
9553 static bool avr_need_swap(CPUPPCState *env)
9554 {
9555 #ifdef HOST_WORDS_BIGENDIAN
9556 return msr_le;
9557 #else
9558 return !msr_le;
9559 #endif
9560 }
9561
9562 #if !defined(CONFIG_USER_ONLY)
9563 static int gdb_find_spr_idx(CPUPPCState *env, int n)
9564 {
9565 int i;
9566
9567 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
9568 ppc_spr_t *spr = &env->spr_cb[i];
9569
9570 if (spr->name && spr->gdb_id == n) {
9571 return i;
9572 }
9573 }
9574 return -1;
9575 }
9576
9577 static int gdb_get_spr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9578 {
9579 int reg;
9580 int len;
9581
9582 reg = gdb_find_spr_idx(env, n);
9583 if (reg < 0) {
9584 return 0;
9585 }
9586
9587 len = TARGET_LONG_SIZE;
9588 stn_p(mem_buf, len, env->spr[reg]);
9589 ppc_maybe_bswap_register(env, mem_buf, len);
9590 return len;
9591 }
9592
9593 static int gdb_set_spr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9594 {
9595 int reg;
9596 int len;
9597
9598 reg = gdb_find_spr_idx(env, n);
9599 if (reg < 0) {
9600 return 0;
9601 }
9602
9603 len = TARGET_LONG_SIZE;
9604 ppc_maybe_bswap_register(env, mem_buf, len);
9605 env->spr[reg] = ldn_p(mem_buf, len);
9606
9607 return len;
9608 }
9609 #endif
9610
9611 static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9612 {
9613 if (n < 32) {
9614 stfq_p(mem_buf, *cpu_fpr_ptr(env, n));
9615 ppc_maybe_bswap_register(env, mem_buf, 8);
9616 return 8;
9617 }
9618 if (n == 32) {
9619 stl_p(mem_buf, env->fpscr);
9620 ppc_maybe_bswap_register(env, mem_buf, 4);
9621 return 4;
9622 }
9623 return 0;
9624 }
9625
9626 static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9627 {
9628 if (n < 32) {
9629 ppc_maybe_bswap_register(env, mem_buf, 8);
9630 *cpu_fpr_ptr(env, n) = ldfq_p(mem_buf);
9631 return 8;
9632 }
9633 if (n == 32) {
9634 ppc_maybe_bswap_register(env, mem_buf, 4);
9635 helper_store_fpscr(env, ldl_p(mem_buf), 0xffffffff);
9636 return 4;
9637 }
9638 return 0;
9639 }
9640
9641 static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9642 {
9643 if (n < 32) {
9644 ppc_avr_t *avr = cpu_avr_ptr(env, n);
9645 if (!avr_need_swap(env)) {
9646 stq_p(mem_buf, avr->u64[0]);
9647 stq_p(mem_buf + 8, avr->u64[1]);
9648 } else {
9649 stq_p(mem_buf, avr->u64[1]);
9650 stq_p(mem_buf + 8, avr->u64[0]);
9651 }
9652 ppc_maybe_bswap_register(env, mem_buf, 8);
9653 ppc_maybe_bswap_register(env, mem_buf + 8, 8);
9654 return 16;
9655 }
9656 if (n == 32) {
9657 stl_p(mem_buf, helper_mfvscr(env));
9658 ppc_maybe_bswap_register(env, mem_buf, 4);
9659 return 4;
9660 }
9661 if (n == 33) {
9662 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
9663 ppc_maybe_bswap_register(env, mem_buf, 4);
9664 return 4;
9665 }
9666 return 0;
9667 }
9668
9669 static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9670 {
9671 if (n < 32) {
9672 ppc_avr_t *avr = cpu_avr_ptr(env, n);
9673 ppc_maybe_bswap_register(env, mem_buf, 8);
9674 ppc_maybe_bswap_register(env, mem_buf + 8, 8);
9675 if (!avr_need_swap(env)) {
9676 avr->u64[0] = ldq_p(mem_buf);
9677 avr->u64[1] = ldq_p(mem_buf + 8);
9678 } else {
9679 avr->u64[1] = ldq_p(mem_buf);
9680 avr->u64[0] = ldq_p(mem_buf + 8);
9681 }
9682 return 16;
9683 }
9684 if (n == 32) {
9685 ppc_maybe_bswap_register(env, mem_buf, 4);
9686 helper_mtvscr(env, ldl_p(mem_buf));
9687 return 4;
9688 }
9689 if (n == 33) {
9690 ppc_maybe_bswap_register(env, mem_buf, 4);
9691 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
9692 return 4;
9693 }
9694 return 0;
9695 }
9696
9697 static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9698 {
9699 if (n < 32) {
9700 #if defined(TARGET_PPC64)
9701 stl_p(mem_buf, env->gpr[n] >> 32);
9702 ppc_maybe_bswap_register(env, mem_buf, 4);
9703 #else
9704 stl_p(mem_buf, env->gprh[n]);
9705 #endif
9706 return 4;
9707 }
9708 if (n == 32) {
9709 stq_p(mem_buf, env->spe_acc);
9710 ppc_maybe_bswap_register(env, mem_buf, 8);
9711 return 8;
9712 }
9713 if (n == 33) {
9714 stl_p(mem_buf, env->spe_fscr);
9715 ppc_maybe_bswap_register(env, mem_buf, 4);
9716 return 4;
9717 }
9718 return 0;
9719 }
9720
9721 static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9722 {
9723 if (n < 32) {
9724 #if defined(TARGET_PPC64)
9725 target_ulong lo = (uint32_t)env->gpr[n];
9726 target_ulong hi;
9727
9728 ppc_maybe_bswap_register(env, mem_buf, 4);
9729
9730 hi = (target_ulong)ldl_p(mem_buf) << 32;
9731 env->gpr[n] = lo | hi;
9732 #else
9733 env->gprh[n] = ldl_p(mem_buf);
9734 #endif
9735 return 4;
9736 }
9737 if (n == 32) {
9738 ppc_maybe_bswap_register(env, mem_buf, 8);
9739 env->spe_acc = ldq_p(mem_buf);
9740 return 8;
9741 }
9742 if (n == 33) {
9743 ppc_maybe_bswap_register(env, mem_buf, 4);
9744 env->spe_fscr = ldl_p(mem_buf);
9745 return 4;
9746 }
9747 return 0;
9748 }
9749
9750 static int gdb_get_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9751 {
9752 if (n < 32) {
9753 stq_p(mem_buf, *cpu_vsrl_ptr(env, n));
9754 ppc_maybe_bswap_register(env, mem_buf, 8);
9755 return 8;
9756 }
9757 return 0;
9758 }
9759
9760 static int gdb_set_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9761 {
9762 if (n < 32) {
9763 ppc_maybe_bswap_register(env, mem_buf, 8);
9764 *cpu_vsrl_ptr(env, n) = ldq_p(mem_buf);
9765 return 8;
9766 }
9767 return 0;
9768 }
9769
9770 static int ppc_fixup_cpu(PowerPCCPU *cpu)
9771 {
9772 CPUPPCState *env = &cpu->env;
9773
9774 /*
9775 * TCG doesn't (yet) emulate some groups of instructions that are
9776 * implemented on some otherwise supported CPUs (e.g. VSX and
9777 * decimal floating point instructions on POWER7). We remove
9778 * unsupported instruction groups from the cpu state's instruction
9779 * masks and hope the guest can cope. For at least the pseries
9780 * machine, the unavailability of these instructions can be
9781 * advertised to the guest via the device tree.
9782 */
9783 if ((env->insns_flags & ~PPC_TCG_INSNS)
9784 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) {
9785 warn_report("Disabling some instructions which are not "
9786 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")",
9787 env->insns_flags & ~PPC_TCG_INSNS,
9788 env->insns_flags2 & ~PPC_TCG_INSNS2);
9789 }
9790 env->insns_flags &= PPC_TCG_INSNS;
9791 env->insns_flags2 &= PPC_TCG_INSNS2;
9792 return 0;
9793 }
9794
9795 static void ppc_cpu_realize(DeviceState *dev, Error **errp)
9796 {
9797 CPUState *cs = CPU(dev);
9798 PowerPCCPU *cpu = POWERPC_CPU(dev);
9799 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9800 Error *local_err = NULL;
9801
9802 cpu_exec_realizefn(cs, &local_err);
9803 if (local_err != NULL) {
9804 error_propagate(errp, local_err);
9805 return;
9806 }
9807 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) {
9808 cpu->vcpu_id = cs->cpu_index;
9809 }
9810
9811 if (tcg_enabled()) {
9812 if (ppc_fixup_cpu(cpu) != 0) {
9813 error_setg(errp, "Unable to emulate selected CPU with TCG");
9814 goto unrealize;
9815 }
9816 }
9817
9818 create_ppc_opcodes(cpu, &local_err);
9819 if (local_err != NULL) {
9820 error_propagate(errp, local_err);
9821 goto unrealize;
9822 }
9823 init_ppc_proc(cpu);
9824
9825 if (pcc->insns_flags & PPC_FLOAT) {
9826 gdb_register_coprocessor(cs, gdb_get_float_reg, gdb_set_float_reg,
9827 33, "power-fpu.xml", 0);
9828 }
9829 if (pcc->insns_flags & PPC_ALTIVEC) {
9830 gdb_register_coprocessor(cs, gdb_get_avr_reg, gdb_set_avr_reg,
9831 34, "power-altivec.xml", 0);
9832 }
9833 if (pcc->insns_flags & PPC_SPE) {
9834 gdb_register_coprocessor(cs, gdb_get_spe_reg, gdb_set_spe_reg,
9835 34, "power-spe.xml", 0);
9836 }
9837 if (pcc->insns_flags2 & PPC2_VSX) {
9838 gdb_register_coprocessor(cs, gdb_get_vsx_reg, gdb_set_vsx_reg,
9839 32, "power-vsx.xml", 0);
9840 }
9841 #ifndef CONFIG_USER_ONLY
9842 gdb_register_coprocessor(cs, gdb_get_spr_reg, gdb_set_spr_reg,
9843 pcc->gdb_num_sprs, "power-spr.xml", 0);
9844 #endif
9845 qemu_init_vcpu(cs);
9846
9847 pcc->parent_realize(dev, errp);
9848
9849 #if defined(PPC_DUMP_CPU)
9850 {
9851 CPUPPCState *env = &cpu->env;
9852 const char *mmu_model, *excp_model, *bus_model;
9853 switch (env->mmu_model) {
9854 case POWERPC_MMU_32B:
9855 mmu_model = "PowerPC 32";
9856 break;
9857 case POWERPC_MMU_SOFT_6xx:
9858 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
9859 break;
9860 case POWERPC_MMU_SOFT_74xx:
9861 mmu_model = "PowerPC 74xx with software driven TLBs";
9862 break;
9863 case POWERPC_MMU_SOFT_4xx:
9864 mmu_model = "PowerPC 4xx with software driven TLBs";
9865 break;
9866 case POWERPC_MMU_SOFT_4xx_Z:
9867 mmu_model = "PowerPC 4xx with software driven TLBs "
9868 "and zones protections";
9869 break;
9870 case POWERPC_MMU_REAL:
9871 mmu_model = "PowerPC real mode only";
9872 break;
9873 case POWERPC_MMU_MPC8xx:
9874 mmu_model = "PowerPC MPC8xx";
9875 break;
9876 case POWERPC_MMU_BOOKE:
9877 mmu_model = "PowerPC BookE";
9878 break;
9879 case POWERPC_MMU_BOOKE206:
9880 mmu_model = "PowerPC BookE 2.06";
9881 break;
9882 case POWERPC_MMU_601:
9883 mmu_model = "PowerPC 601";
9884 break;
9885 #if defined(TARGET_PPC64)
9886 case POWERPC_MMU_64B:
9887 mmu_model = "PowerPC 64";
9888 break;
9889 #endif
9890 default:
9891 mmu_model = "Unknown or invalid";
9892 break;
9893 }
9894 switch (env->excp_model) {
9895 case POWERPC_EXCP_STD:
9896 excp_model = "PowerPC";
9897 break;
9898 case POWERPC_EXCP_40x:
9899 excp_model = "PowerPC 40x";
9900 break;
9901 case POWERPC_EXCP_601:
9902 excp_model = "PowerPC 601";
9903 break;
9904 case POWERPC_EXCP_602:
9905 excp_model = "PowerPC 602";
9906 break;
9907 case POWERPC_EXCP_603:
9908 excp_model = "PowerPC 603";
9909 break;
9910 case POWERPC_EXCP_603E:
9911 excp_model = "PowerPC 603e";
9912 break;
9913 case POWERPC_EXCP_604:
9914 excp_model = "PowerPC 604";
9915 break;
9916 case POWERPC_EXCP_7x0:
9917 excp_model = "PowerPC 740/750";
9918 break;
9919 case POWERPC_EXCP_7x5:
9920 excp_model = "PowerPC 745/755";
9921 break;
9922 case POWERPC_EXCP_74xx:
9923 excp_model = "PowerPC 74xx";
9924 break;
9925 case POWERPC_EXCP_BOOKE:
9926 excp_model = "PowerPC BookE";
9927 break;
9928 #if defined(TARGET_PPC64)
9929 case POWERPC_EXCP_970:
9930 excp_model = "PowerPC 970";
9931 break;
9932 #endif
9933 default:
9934 excp_model = "Unknown or invalid";
9935 break;
9936 }
9937 switch (env->bus_model) {
9938 case PPC_FLAGS_INPUT_6xx:
9939 bus_model = "PowerPC 6xx";
9940 break;
9941 case PPC_FLAGS_INPUT_BookE:
9942 bus_model = "PowerPC BookE";
9943 break;
9944 case PPC_FLAGS_INPUT_405:
9945 bus_model = "PowerPC 405";
9946 break;
9947 case PPC_FLAGS_INPUT_401:
9948 bus_model = "PowerPC 401/403";
9949 break;
9950 case PPC_FLAGS_INPUT_RCPU:
9951 bus_model = "RCPU / MPC8xx";
9952 break;
9953 #if defined(TARGET_PPC64)
9954 case PPC_FLAGS_INPUT_970:
9955 bus_model = "PowerPC 970";
9956 break;
9957 #endif
9958 default:
9959 bus_model = "Unknown or invalid";
9960 break;
9961 }
9962 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
9963 " MMU model : %s\n",
9964 object_class_get_name(OBJECT_CLASS(pcc)),
9965 pcc->pvr, pcc->msr_mask, mmu_model);
9966 #if !defined(CONFIG_USER_ONLY)
9967 if (env->tlb.tlb6) {
9968 printf(" %d %s TLB in %d ways\n",
9969 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
9970 env->nb_ways);
9971 }
9972 #endif
9973 printf(" Exceptions model : %s\n"
9974 " Bus model : %s\n",
9975 excp_model, bus_model);
9976 printf(" MSR features :\n");
9977 if (env->flags & POWERPC_FLAG_SPE) {
9978 printf(" signal processing engine enable"
9979 "\n");
9980 } else if (env->flags & POWERPC_FLAG_VRE) {
9981 printf(" vector processor enable\n");
9982 }
9983 if (env->flags & POWERPC_FLAG_TGPR) {
9984 printf(" temporary GPRs\n");
9985 } else if (env->flags & POWERPC_FLAG_CE) {
9986 printf(" critical input enable\n");
9987 }
9988 if (env->flags & POWERPC_FLAG_SE) {
9989 printf(" single-step trace mode\n");
9990 } else if (env->flags & POWERPC_FLAG_DWE) {
9991 printf(" debug wait enable\n");
9992 } else if (env->flags & POWERPC_FLAG_UBLE) {
9993 printf(" user BTB lock enable\n");
9994 }
9995 if (env->flags & POWERPC_FLAG_BE) {
9996 printf(" branch-step trace mode\n");
9997 } else if (env->flags & POWERPC_FLAG_DE) {
9998 printf(" debug interrupt enable\n");
9999 }
10000 if (env->flags & POWERPC_FLAG_PX) {
10001 printf(" inclusive protection\n");
10002 } else if (env->flags & POWERPC_FLAG_PMM) {
10003 printf(" performance monitor mark\n");
10004 }
10005 if (env->flags == POWERPC_FLAG_NONE) {
10006 printf(" none\n");
10007 }
10008 printf(" Time-base/decrementer clock source: %s\n",
10009 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
10010 dump_ppc_insns(env);
10011 dump_ppc_sprs(env);
10012 fflush(stdout);
10013 }
10014 #endif
10015 return;
10016
10017 unrealize:
10018 cpu_exec_unrealizefn(cs);
10019 }
10020
10021 static void ppc_cpu_unrealize(DeviceState *dev, Error **errp)
10022 {
10023 PowerPCCPU *cpu = POWERPC_CPU(dev);
10024 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
10025 CPUPPCState *env = &cpu->env;
10026 Error *local_err = NULL;
10027 opc_handler_t **table, **table_2;
10028 int i, j, k;
10029
10030 pcc->parent_unrealize(dev, &local_err);
10031 if (local_err != NULL) {
10032 error_propagate(errp, local_err);
10033 return;
10034 }
10035
10036 for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) {
10037 if (env->opcodes[i] == &invalid_handler) {
10038 continue;
10039 }
10040 if (is_indirect_opcode(env->opcodes[i])) {
10041 table = ind_table(env->opcodes[i]);
10042 for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) {
10043 if (table[j] == &invalid_handler) {
10044 continue;
10045 }
10046 if (is_indirect_opcode(table[j])) {
10047 table_2 = ind_table(table[j]);
10048 for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) {
10049 if (table_2[k] != &invalid_handler &&
10050 is_indirect_opcode(table_2[k])) {
10051 g_free((opc_handler_t *)((uintptr_t)table_2[k] &
10052 ~PPC_INDIRECT));
10053 }
10054 }
10055 g_free((opc_handler_t *)((uintptr_t)table[j] &
10056 ~PPC_INDIRECT));
10057 }
10058 }
10059 g_free((opc_handler_t *)((uintptr_t)env->opcodes[i] &
10060 ~PPC_INDIRECT));
10061 }
10062 }
10063 }
10064
10065 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
10066 {
10067 ObjectClass *oc = (ObjectClass *)a;
10068 uint32_t pvr = *(uint32_t *)b;
10069 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
10070
10071 /* -cpu host does a PVR lookup during construction */
10072 if (unlikely(strcmp(object_class_get_name(oc),
10073 TYPE_HOST_POWERPC_CPU) == 0)) {
10074 return -1;
10075 }
10076
10077 return pcc->pvr == pvr ? 0 : -1;
10078 }
10079
10080 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
10081 {
10082 GSList *list, *item;
10083 PowerPCCPUClass *pcc = NULL;
10084
10085 list = object_class_get_list(TYPE_POWERPC_CPU, false);
10086 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
10087 if (item != NULL) {
10088 pcc = POWERPC_CPU_CLASS(item->data);
10089 }
10090 g_slist_free(list);
10091
10092 return pcc;
10093 }
10094
10095 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b)
10096 {
10097 ObjectClass *oc = (ObjectClass *)a;
10098 uint32_t pvr = *(uint32_t *)b;
10099 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
10100
10101 /* -cpu host does a PVR lookup during construction */
10102 if (unlikely(strcmp(object_class_get_name(oc),
10103 TYPE_HOST_POWERPC_CPU) == 0)) {
10104 return -1;
10105 }
10106
10107 if (pcc->pvr_match(pcc, pvr)) {
10108 return 0;
10109 }
10110
10111 return -1;
10112 }
10113
10114 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr)
10115 {
10116 GSList *list, *item;
10117 PowerPCCPUClass *pcc = NULL;
10118
10119 list = object_class_get_list(TYPE_POWERPC_CPU, true);
10120 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask);
10121 if (item != NULL) {
10122 pcc = POWERPC_CPU_CLASS(item->data);
10123 }
10124 g_slist_free(list);
10125
10126 return pcc;
10127 }
10128
10129 static const char *ppc_cpu_lookup_alias(const char *alias)
10130 {
10131 int ai;
10132
10133 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) {
10134 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) {
10135 return ppc_cpu_aliases[ai].model;
10136 }
10137 }
10138
10139 return NULL;
10140 }
10141
10142 static ObjectClass *ppc_cpu_class_by_name(const char *name)
10143 {
10144 char *cpu_model, *typename;
10145 ObjectClass *oc;
10146 const char *p;
10147 unsigned long pvr;
10148
10149 /*
10150 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl:
10151 * 0x prefix if present)
10152 */
10153 if (!qemu_strtoul(name, &p, 16, &pvr)) {
10154 int len = p - name;
10155 len = (len == 10) && (name[1] == 'x') ? len - 2 : len;
10156 if ((len == 8) && (*p == '\0')) {
10157 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr));
10158 }
10159 }
10160
10161 cpu_model = g_ascii_strdown(name, -1);
10162 p = ppc_cpu_lookup_alias(cpu_model);
10163 if (p) {
10164 g_free(cpu_model);
10165 cpu_model = g_strdup(p);
10166 }
10167
10168 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model);
10169 oc = object_class_by_name(typename);
10170 g_free(typename);
10171 g_free(cpu_model);
10172
10173 return oc;
10174 }
10175
10176 static void ppc_cpu_parse_featurestr(const char *type, char *features,
10177 Error **errp)
10178 {
10179 Object *machine = qdev_get_machine();
10180 const PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(object_class_by_name(type));
10181
10182 if (!features) {
10183 return;
10184 }
10185
10186 if (object_property_find(machine, "max-cpu-compat", NULL)) {
10187 int i;
10188 char **inpieces;
10189 char *s = features;
10190 Error *local_err = NULL;
10191 char *compat_str = NULL;
10192
10193 /*
10194 * Backwards compatibility hack:
10195 *
10196 * CPUs had a "compat=" property which didn't make sense for
10197 * anything except pseries. It was replaced by "max-cpu-compat"
10198 * machine option. This supports old command lines like
10199 * -cpu POWER8,compat=power7
10200 * By stripping the compat option and applying it to the machine
10201 * before passing it on to the cpu level parser.
10202 */
10203 inpieces = g_strsplit(features, ",", 0);
10204 *s = '\0';
10205 for (i = 0; inpieces[i]; i++) {
10206 if (g_str_has_prefix(inpieces[i], "compat=")) {
10207 compat_str = inpieces[i];
10208 continue;
10209 }
10210 if ((i != 0) && (s != features)) {
10211 s = g_stpcpy(s, ",");
10212 }
10213 s = g_stpcpy(s, inpieces[i]);
10214 }
10215
10216 if (compat_str) {
10217 char *v = compat_str + strlen("compat=");
10218 object_property_set_str(machine, v, "max-cpu-compat", &local_err);
10219 }
10220 g_strfreev(inpieces);
10221 if (local_err) {
10222 error_propagate(errp, local_err);
10223 return;
10224 }
10225 }
10226
10227 /* do property processing with generic handler */
10228 pcc->parent_parse_features(type, features, errp);
10229 }
10230
10231 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc)
10232 {
10233 ObjectClass *oc = OBJECT_CLASS(pcc);
10234
10235 while (oc && !object_class_is_abstract(oc)) {
10236 oc = object_class_get_parent(oc);
10237 }
10238 assert(oc);
10239
10240 return POWERPC_CPU_CLASS(oc);
10241 }
10242
10243 /* Sort by PVR, ordering special case "host" last. */
10244 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
10245 {
10246 ObjectClass *oc_a = (ObjectClass *)a;
10247 ObjectClass *oc_b = (ObjectClass *)b;
10248 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
10249 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
10250 const char *name_a = object_class_get_name(oc_a);
10251 const char *name_b = object_class_get_name(oc_b);
10252
10253 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
10254 return 1;
10255 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
10256 return -1;
10257 } else {
10258 /* Avoid an integer overflow during subtraction */
10259 if (pcc_a->pvr < pcc_b->pvr) {
10260 return -1;
10261 } else if (pcc_a->pvr > pcc_b->pvr) {
10262 return 1;
10263 } else {
10264 return 0;
10265 }
10266 }
10267 }
10268
10269 static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
10270 {
10271 ObjectClass *oc = data;
10272 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
10273 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc));
10274 const char *typename = object_class_get_name(oc);
10275 char *name;
10276 int i;
10277
10278 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
10279 return;
10280 }
10281
10282 name = g_strndup(typename,
10283 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
10284 qemu_printf("PowerPC %-16s PVR %08x\n", name, pcc->pvr);
10285 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
10286 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
10287 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model);
10288
10289 if (alias_oc != oc) {
10290 continue;
10291 }
10292 /*
10293 * If running with KVM, we might update the family alias later, so
10294 * avoid printing the wrong alias here and use "preferred" instead
10295 */
10296 if (strcmp(alias->alias, family->desc) == 0) {
10297 qemu_printf("PowerPC %-16s (alias for preferred %s CPU)\n",
10298 alias->alias, family->desc);
10299 } else {
10300 qemu_printf("PowerPC %-16s (alias for %s)\n",
10301 alias->alias, name);
10302 }
10303 }
10304 g_free(name);
10305 }
10306
10307 void ppc_cpu_list(void)
10308 {
10309 GSList *list;
10310
10311 list = object_class_get_list(TYPE_POWERPC_CPU, false);
10312 list = g_slist_sort(list, ppc_cpu_list_compare);
10313 g_slist_foreach(list, ppc_cpu_list_entry, NULL);
10314 g_slist_free(list);
10315
10316 #ifdef CONFIG_KVM
10317 qemu_printf("\n");
10318 qemu_printf("PowerPC %-16s\n", "host");
10319 #endif
10320 }
10321
10322 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
10323 {
10324 ObjectClass *oc = data;
10325 CpuDefinitionInfoList **first = user_data;
10326 const char *typename;
10327 CpuDefinitionInfoList *entry;
10328 CpuDefinitionInfo *info;
10329
10330 typename = object_class_get_name(oc);
10331 info = g_malloc0(sizeof(*info));
10332 info->name = g_strndup(typename,
10333 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
10334
10335 entry = g_malloc0(sizeof(*entry));
10336 entry->value = info;
10337 entry->next = *first;
10338 *first = entry;
10339 }
10340
10341 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
10342 {
10343 CpuDefinitionInfoList *cpu_list = NULL;
10344 GSList *list;
10345 int i;
10346
10347 list = object_class_get_list(TYPE_POWERPC_CPU, false);
10348 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
10349 g_slist_free(list);
10350
10351 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
10352 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
10353 ObjectClass *oc;
10354 CpuDefinitionInfoList *entry;
10355 CpuDefinitionInfo *info;
10356
10357 oc = ppc_cpu_class_by_name(alias->model);
10358 if (oc == NULL) {
10359 continue;
10360 }
10361
10362 info = g_malloc0(sizeof(*info));
10363 info->name = g_strdup(alias->alias);
10364 info->q_typename = g_strdup(object_class_get_name(oc));
10365
10366 entry = g_malloc0(sizeof(*entry));
10367 entry->value = info;
10368 entry->next = cpu_list;
10369 cpu_list = entry;
10370 }
10371
10372 return cpu_list;
10373 }
10374
10375 static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
10376 {
10377 PowerPCCPU *cpu = POWERPC_CPU(cs);
10378
10379 cpu->env.nip = value;
10380 }
10381
10382 static bool ppc_cpu_has_work(CPUState *cs)
10383 {
10384 PowerPCCPU *cpu = POWERPC_CPU(cs);
10385 CPUPPCState *env = &cpu->env;
10386
10387 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
10388 }
10389
10390 /* CPUClass::reset() */
10391 static void ppc_cpu_reset(CPUState *s)
10392 {
10393 PowerPCCPU *cpu = POWERPC_CPU(s);
10394 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
10395 CPUPPCState *env = &cpu->env;
10396 target_ulong msr;
10397 int i;
10398
10399 pcc->parent_reset(s);
10400
10401 msr = (target_ulong)0;
10402 msr |= (target_ulong)MSR_HVB;
10403 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
10404 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
10405 msr |= (target_ulong)1 << MSR_EP;
10406 #if defined(DO_SINGLE_STEP) && 0
10407 /* Single step trace mode */
10408 msr |= (target_ulong)1 << MSR_SE;
10409 msr |= (target_ulong)1 << MSR_BE;
10410 #endif
10411 #if defined(CONFIG_USER_ONLY)
10412 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
10413 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */
10414 msr |= (target_ulong)1 << MSR_FE1;
10415 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
10416 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */
10417 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
10418 msr |= (target_ulong)1 << MSR_PR;
10419 #if defined(TARGET_PPC64)
10420 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */
10421 #endif
10422 #if !defined(TARGET_WORDS_BIGENDIAN)
10423 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */
10424 if (!((env->msr_mask >> MSR_LE) & 1)) {
10425 fprintf(stderr, "Selected CPU does not support little-endian.\n");
10426 exit(1);
10427 }
10428 #endif
10429 #endif
10430
10431 #if defined(TARGET_PPC64)
10432 if (env->mmu_model & POWERPC_MMU_64) {
10433 msr |= (1ULL << MSR_SF);
10434 }
10435 #endif
10436
10437 hreg_store_msr(env, msr, 1);
10438
10439 #if !defined(CONFIG_USER_ONLY)
10440 env->nip = env->hreset_vector | env->excp_prefix;
10441 if (env->mmu_model != POWERPC_MMU_REAL) {
10442 ppc_tlb_invalidate_all(env);
10443 }
10444 #endif
10445
10446 hreg_compute_hflags(env);
10447 env->reserve_addr = (target_ulong)-1ULL;
10448 /* Be sure no exception or interrupt is pending */
10449 env->pending_interrupts = 0;
10450 s->exception_index = POWERPC_EXCP_NONE;
10451 env->error_code = 0;
10452
10453 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
10454 ppc_spr_t *spr = &env->spr_cb[i];
10455
10456 if (!spr->name) {
10457 continue;
10458 }
10459 env->spr[i] = spr->default_value;
10460 }
10461 }
10462
10463 #ifndef CONFIG_USER_ONLY
10464 static bool ppc_cpu_is_big_endian(CPUState *cs)
10465 {
10466 PowerPCCPU *cpu = POWERPC_CPU(cs);
10467 CPUPPCState *env = &cpu->env;
10468
10469 cpu_synchronize_state(cs);
10470
10471 return !msr_le;
10472 }
10473 #endif
10474
10475 static void ppc_cpu_instance_init(Object *obj)
10476 {
10477 CPUState *cs = CPU(obj);
10478 PowerPCCPU *cpu = POWERPC_CPU(obj);
10479 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
10480 CPUPPCState *env = &cpu->env;
10481
10482 cs->env_ptr = env;
10483 cpu->vcpu_id = UNASSIGNED_CPU_INDEX;
10484
10485 env->msr_mask = pcc->msr_mask;
10486 env->mmu_model = pcc->mmu_model;
10487 env->excp_model = pcc->excp_model;
10488 env->bus_model = pcc->bus_model;
10489 env->insns_flags = pcc->insns_flags;
10490 env->insns_flags2 = pcc->insns_flags2;
10491 env->flags = pcc->flags;
10492 env->bfd_mach = pcc->bfd_mach;
10493 env->check_pow = pcc->check_pow;
10494
10495 /*
10496 * Mark HV mode as supported if the CPU has an MSR_HV bit in the
10497 * msr_mask. The mask can later be cleared by PAPR mode but the hv
10498 * mode support will remain, thus enforcing that we cannot use
10499 * priv. instructions in guest in PAPR mode. For 970 we currently
10500 * simply don't set HV in msr_mask thus simulating an "Apple mode"
10501 * 970. If we ever want to support 970 HV mode, we'll have to add
10502 * a processor attribute of some sort.
10503 */
10504 #if !defined(CONFIG_USER_ONLY)
10505 env->has_hv_mode = !!(env->msr_mask & MSR_HVB);
10506 #endif
10507
10508 ppc_hash64_init(cpu);
10509 }
10510
10511 static void ppc_cpu_instance_finalize(Object *obj)
10512 {
10513 PowerPCCPU *cpu = POWERPC_CPU(obj);
10514
10515 ppc_hash64_finalize(cpu);
10516 }
10517
10518 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr)
10519 {
10520 return pcc->pvr == pvr;
10521 }
10522
10523 static gchar *ppc_gdb_arch_name(CPUState *cs)
10524 {
10525 #if defined(TARGET_PPC64)
10526 return g_strdup("powerpc:common64");
10527 #else
10528 return g_strdup("powerpc:common");
10529 #endif
10530 }
10531
10532 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info)
10533 {
10534 PowerPCCPU *cpu = POWERPC_CPU(cs);
10535 CPUPPCState *env = &cpu->env;
10536
10537 if ((env->hflags >> MSR_LE) & 1) {
10538 info->endian = BFD_ENDIAN_LITTLE;
10539 }
10540 info->mach = env->bfd_mach;
10541 if (!env->bfd_mach) {
10542 #ifdef TARGET_PPC64
10543 info->mach = bfd_mach_ppc64;
10544 #else
10545 info->mach = bfd_mach_ppc;
10546 #endif
10547 }
10548 info->disassembler_options = (char *)"any";
10549 info->print_insn = print_insn_ppc;
10550
10551 info->cap_arch = CS_ARCH_PPC;
10552 #ifdef TARGET_PPC64
10553 info->cap_mode = CS_MODE_64;
10554 #endif
10555 }
10556
10557 static Property ppc_cpu_properties[] = {
10558 DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false),
10559 DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration,
10560 false),
10561 DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration,
10562 false),
10563 DEFINE_PROP_END_OF_LIST(),
10564 };
10565
10566 static void ppc_cpu_class_init(ObjectClass *oc, void *data)
10567 {
10568 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
10569 CPUClass *cc = CPU_CLASS(oc);
10570 DeviceClass *dc = DEVICE_CLASS(oc);
10571
10572 device_class_set_parent_realize(dc, ppc_cpu_realize,
10573 &pcc->parent_realize);
10574 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize,
10575 &pcc->parent_unrealize);
10576 pcc->pvr_match = ppc_pvr_match_default;
10577 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_always;
10578 dc->props = ppc_cpu_properties;
10579
10580 pcc->parent_reset = cc->reset;
10581 cc->reset = ppc_cpu_reset;
10582
10583 cc->class_by_name = ppc_cpu_class_by_name;
10584 pcc->parent_parse_features = cc->parse_features;
10585 cc->parse_features = ppc_cpu_parse_featurestr;
10586 cc->has_work = ppc_cpu_has_work;
10587 cc->do_interrupt = ppc_cpu_do_interrupt;
10588 cc->cpu_exec_interrupt = ppc_cpu_exec_interrupt;
10589 cc->dump_state = ppc_cpu_dump_state;
10590 cc->dump_statistics = ppc_cpu_dump_statistics;
10591 cc->set_pc = ppc_cpu_set_pc;
10592 cc->gdb_read_register = ppc_cpu_gdb_read_register;
10593 cc->gdb_write_register = ppc_cpu_gdb_write_register;
10594 cc->do_unaligned_access = ppc_cpu_do_unaligned_access;
10595 #ifndef CONFIG_USER_ONLY
10596 cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
10597 cc->vmsd = &vmstate_ppc_cpu;
10598 #endif
10599 #if defined(CONFIG_SOFTMMU)
10600 cc->write_elf64_note = ppc64_cpu_write_elf64_note;
10601 cc->write_elf32_note = ppc32_cpu_write_elf32_note;
10602 #endif
10603
10604 cc->gdb_num_core_regs = 71;
10605 #ifndef CONFIG_USER_ONLY
10606 cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml;
10607 #endif
10608 #ifdef USE_APPLE_GDB
10609 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple;
10610 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple;
10611 cc->gdb_num_core_regs = 71 + 32;
10612 #endif
10613
10614 cc->gdb_arch_name = ppc_gdb_arch_name;
10615 #if defined(TARGET_PPC64)
10616 cc->gdb_core_xml_file = "power64-core.xml";
10617 #else
10618 cc->gdb_core_xml_file = "power-core.xml";
10619 #endif
10620 #ifndef CONFIG_USER_ONLY
10621 cc->virtio_is_big_endian = ppc_cpu_is_big_endian;
10622 #endif
10623 #ifdef CONFIG_TCG
10624 cc->tcg_initialize = ppc_translate_init;
10625 cc->tlb_fill = ppc_cpu_tlb_fill;
10626 #endif
10627 cc->disas_set_info = ppc_disas_set_info;
10628
10629 dc->fw_name = "PowerPC,UNKNOWN";
10630 }
10631
10632 static const TypeInfo ppc_cpu_type_info = {
10633 .name = TYPE_POWERPC_CPU,
10634 .parent = TYPE_CPU,
10635 .instance_size = sizeof(PowerPCCPU),
10636 .instance_init = ppc_cpu_instance_init,
10637 .instance_finalize = ppc_cpu_instance_finalize,
10638 .abstract = true,
10639 .class_size = sizeof(PowerPCCPUClass),
10640 .class_init = ppc_cpu_class_init,
10641 };
10642
10643 static const TypeInfo ppc_vhyp_type_info = {
10644 .name = TYPE_PPC_VIRTUAL_HYPERVISOR,
10645 .parent = TYPE_INTERFACE,
10646 .class_size = sizeof(PPCVirtualHypervisorClass),
10647 };
10648
10649 static void ppc_cpu_register_types(void)
10650 {
10651 type_register_static(&ppc_cpu_type_info);
10652 type_register_static(&ppc_vhyp_type_info);
10653 }
10654
10655 type_init(ppc_cpu_register_types)
AR7 emulation for QEMU