target-unicore32/softmmu.c

   1 /*
   2  * Softmmu related functions
   3  *
   4  * Copyright (C) 2010-2012 Guan Xuetao
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation, or any later version.
   9  * See the COPYING file in the top-level directory.
  10  */
  11 #ifdef CONFIG_USER_ONLY
  12 #error This file only exist under softmmu circumstance
  13 #endif
  14
  15 #include <cpu.h>
  16
  17 #undef DEBUG_UC32
  18
  19 #ifdef DEBUG_UC32
  20 #define DPRINTF(fmt, ...) printf("%s: " fmt , __func__, ## __VA_ARGS__)
  21 #else
  22 #define DPRINTF(fmt, ...) do {} while (0)
  23 #endif
  24
  25 #define SUPERPAGE_SIZE             (1 << 22)
  26 #define UC32_PAGETABLE_READ        (1 << 8)
  27 #define UC32_PAGETABLE_WRITE       (1 << 7)
  28 #define UC32_PAGETABLE_EXEC        (1 << 6)
  29 #define UC32_PAGETABLE_EXIST       (1 << 2)
  30 #define PAGETABLE_TYPE(x)          ((x) & 3)
  31
  32
  33 /* Map CPU modes onto saved register banks.  */
  34 static inline int bank_number(int mode)
  35 {
  36     switch (mode) {
  37     case ASR_MODE_USER:
  38     case ASR_MODE_SUSR:
  39         return 0;
  40     case ASR_MODE_PRIV:
  41         return 1;
  42     case ASR_MODE_TRAP:
  43         return 2;
  44     case ASR_MODE_EXTN:
  45         return 3;
  46     case ASR_MODE_INTR:
  47         return 4;
  48     }
  49     cpu_abort(cpu_single_env, "Bad mode %x\n", mode);
  50     return -1;
  51 }
  52
  53 void switch_mode(CPUUniCore32State *env, int mode)
  54 {
  55     int old_mode;
  56     int i;
  57
  58     old_mode = env->uncached_asr & ASR_M;
  59     if (mode == old_mode) {
  60         return;
  61     }
  62
  63     i = bank_number(old_mode);
  64     env->banked_r29[i] = env->regs[29];
  65     env->banked_r30[i] = env->regs[30];
  66     env->banked_bsr[i] = env->bsr;
  67
  68     i = bank_number(mode);
  69     env->regs[29] = env->banked_r29[i];
  70     env->regs[30] = env->banked_r30[i];
  71     env->bsr = env->banked_bsr[i];
  72 }
  73
  74 /* Handle a CPU exception.  */
  75 void do_interrupt(CPUUniCore32State *env)
  76 {
  77     uint32_t addr;
  78     int new_mode;
  79
  80     switch (env->exception_index) {
  81     case UC32_EXCP_PRIV:
  82         new_mode = ASR_MODE_PRIV;
  83         addr = 0x08;
  84         break;
  85     case UC32_EXCP_ITRAP:
  86         DPRINTF("itrap happened at %x\n", env->regs[31]);
  87         new_mode = ASR_MODE_TRAP;
  88         addr = 0x0c;
  89         break;
  90     case UC32_EXCP_DTRAP:
  91         DPRINTF("dtrap happened at %x\n", env->regs[31]);
  92         new_mode = ASR_MODE_TRAP;
  93         addr = 0x10;
  94         break;
  95     case UC32_EXCP_INTR:
  96         new_mode = ASR_MODE_INTR;
  97         addr = 0x18;
  98         break;
  99     default:
 100         cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
 101         return;
 102     }
 103     /* High vectors.  */
 104     if (env->cp0.c1_sys & (1 << 13)) {
 105         addr += 0xffff0000;
 106     }
 107
 108     switch_mode(env, new_mode);
 109     env->bsr = cpu_asr_read(env);
 110     env->uncached_asr = (env->uncached_asr & ~ASR_M) | new_mode;
 111     env->uncached_asr |= ASR_I;
 112     /* The PC already points to the proper instruction.  */
 113     env->regs[30] = env->regs[31];
 114     env->regs[31] = addr;
 115     env->interrupt_request |= CPU_INTERRUPT_EXITTB;
 116 }
 117
 118 static int get_phys_addr_ucv2(CPUUniCore32State *env, uint32_t address,
 119         int access_type, int is_user, uint32_t *phys_ptr, int *prot,
 120         target_ulong *page_size)
 121 {
 122     int code;
 123     uint32_t table;
 124     uint32_t desc;
 125     uint32_t phys_addr;
 126
 127     /* Pagetable walk.  */
 128     /* Lookup l1 descriptor.  */
 129     table = env->cp0.c2_base & 0xfffff000;
 130     table |= (address >> 20) & 0xffc;
 131     desc = ldl_phys(table);
 132     code = 0;
 133     switch (PAGETABLE_TYPE(desc)) {
 134     case 3:
 135         /* Superpage  */
 136         if (!(desc & UC32_PAGETABLE_EXIST)) {
 137             code = 0x0b; /* superpage miss */
 138             goto do_fault;
 139         }
 140         phys_addr = (desc & 0xffc00000) | (address & 0x003fffff);
 141         *page_size = SUPERPAGE_SIZE;
 142         break;
 143     case 0:
 144         /* Lookup l2 entry.  */
 145         if (is_user) {
 146             DPRINTF("PGD address %x, desc %x\n", table, desc);
 147         }
 148         if (!(desc & UC32_PAGETABLE_EXIST)) {
 149             code = 0x05; /* second pagetable miss */
 150             goto do_fault;
 151         }
 152         table = (desc & 0xfffff000) | ((address >> 10) & 0xffc);
 153         desc = ldl_phys(table);
 154         /* 4k page.  */
 155         if (is_user) {
 156             DPRINTF("PTE address %x, desc %x\n", table, desc);
 157         }
 158         if (!(desc & UC32_PAGETABLE_EXIST)) {
 159             code = 0x08; /* page miss */
 160             goto do_fault;
 161         }
 162         switch (PAGETABLE_TYPE(desc)) {
 163         case 0:
 164             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
 165             *page_size = TARGET_PAGE_SIZE;
 166             break;
 167         default:
 168             cpu_abort(env, "wrong page type!");
 169         }
 170         break;
 171     default:
 172         cpu_abort(env, "wrong page type!");
 173     }
 174
 175     *phys_ptr = phys_addr;
 176     *prot = 0;
 177     /* Check access permissions.  */
 178     if (desc & UC32_PAGETABLE_READ) {
 179         *prot |= PAGE_READ;
 180     } else {
 181         if (is_user && (access_type == 0)) {
 182             code = 0x11; /* access unreadable area */
 183             goto do_fault;
 184         }
 185     }
 186
 187     if (desc & UC32_PAGETABLE_WRITE) {
 188         *prot |= PAGE_WRITE;
 189     } else {
 190         if (is_user && (access_type == 1)) {
 191             code = 0x12; /* access unwritable area */
 192             goto do_fault;
 193         }
 194     }
 195
 196     if (desc & UC32_PAGETABLE_EXEC) {
 197         *prot |= PAGE_EXEC;
 198     } else {
 199         if (is_user && (access_type == 2)) {
 200             code = 0x13; /* access unexecutable area */
 201             goto do_fault;
 202         }
 203     }
 204
 205 do_fault:
 206     return code;
 207 }
 208
 209 int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address,
 210                               int access_type, int mmu_idx)
 211 {
 212     uint32_t phys_addr;
 213     target_ulong page_size;
 214     int prot;
 215     int ret, is_user;
 216
 217     ret = 1;
 218     is_user = mmu_idx == MMU_USER_IDX;
 219
 220     if ((env->cp0.c1_sys & 1) == 0) {
 221         /* MMU disabled.  */
 222         phys_addr = address;
 223         prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 224         page_size = TARGET_PAGE_SIZE;
 225         ret = 0;
 226     } else {
 227         if ((address & (1 << 31)) || (is_user)) {
 228             ret = get_phys_addr_ucv2(env, address, access_type, is_user,
 229                                     &phys_addr, &prot, &page_size);
 230             if (is_user) {
 231                 DPRINTF("user space access: ret %x, address %x, "
 232                         "access_type %x, phys_addr %x, prot %x\n",
 233                         ret, address, access_type, phys_addr, prot);
 234             }
 235         } else {
 236             /*IO memory */
 237             phys_addr = address | (1 << 31);
 238             prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 239             page_size = TARGET_PAGE_SIZE;
 240             ret = 0;
 241         }
 242     }
 243
 244     if (ret == 0) {
 245         /* Map a single page.  */
 246         phys_addr &= TARGET_PAGE_MASK;
 247         address &= TARGET_PAGE_MASK;
 248         tlb_set_page(env, address, phys_addr, prot, mmu_idx, page_size);
 249         return 0;
 250     }
 251
 252     env->cp0.c3_faultstatus = ret;
 253     env->cp0.c4_faultaddr = address;
 254     if (access_type == 2) {
 255         env->exception_index = UC32_EXCP_ITRAP;
 256     } else {
 257         env->exception_index = UC32_EXCP_DTRAP;
 258     }
 259     return ret;
 260 }
 261
 262 hwaddr cpu_get_phys_page_debug(CPUUniCore32State *env,
 263         target_ulong addr)
 264 {
 265     cpu_abort(env, "%s not supported yet\n", __func__);
 266     return addr;
 267 }