tcg/tci/tcg-target.c

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2009, 2011 Stefan Weil
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "tcg-be-null.h"
  26
  27 /* TODO list:
  28  * - See TODO comments in code.
  29  */
  30
  31 /* Marker for missing code. */
  32 #define TODO() \
  33     do { \
  34         fprintf(stderr, "TODO %s:%u: %s()\n", \
  35                 __FILE__, __LINE__, __func__); \
  36         tcg_abort(); \
  37     } while (0)
  38
  39 /* Bitfield n...m (in 32 bit value). */
  40 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
  41
  42 /* Macros used in tcg_target_op_defs. */
  43 #define R       "r"
  44 #define RI      "ri"
  45 #if TCG_TARGET_REG_BITS == 32
  46 # define R64    "r", "r"
  47 #else
  48 # define R64    "r"
  49 #endif
  50 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
  51 # define L      "L", "L"
  52 # define S      "S", "S"
  53 #else
  54 # define L      "L"
  55 # define S      "S"
  56 #endif
  57
  58 /* TODO: documentation. */
  59 static const TCGTargetOpDef tcg_target_op_defs[] = {
  60     { INDEX_op_exit_tb, { NULL } },
  61     { INDEX_op_goto_tb, { NULL } },
  62     { INDEX_op_br, { NULL } },
  63
  64     { INDEX_op_ld8u_i32, { R, R } },
  65     { INDEX_op_ld8s_i32, { R, R } },
  66     { INDEX_op_ld16u_i32, { R, R } },
  67     { INDEX_op_ld16s_i32, { R, R } },
  68     { INDEX_op_ld_i32, { R, R } },
  69     { INDEX_op_st8_i32, { R, R } },
  70     { INDEX_op_st16_i32, { R, R } },
  71     { INDEX_op_st_i32, { R, R } },
  72
  73     { INDEX_op_add_i32, { R, RI, RI } },
  74     { INDEX_op_sub_i32, { R, RI, RI } },
  75     { INDEX_op_mul_i32, { R, RI, RI } },
  76 #if TCG_TARGET_HAS_div_i32
  77     { INDEX_op_div_i32, { R, R, R } },
  78     { INDEX_op_divu_i32, { R, R, R } },
  79     { INDEX_op_rem_i32, { R, R, R } },
  80     { INDEX_op_remu_i32, { R, R, R } },
  81 #elif TCG_TARGET_HAS_div2_i32
  82     { INDEX_op_div2_i32, { R, R, "0", "1", R } },
  83     { INDEX_op_divu2_i32, { R, R, "0", "1", R } },
  84 #endif
  85     /* TODO: Does R, RI, RI result in faster code than R, R, RI?
  86        If both operands are constants, we can optimize. */
  87     { INDEX_op_and_i32, { R, RI, RI } },
  88 #if TCG_TARGET_HAS_andc_i32
  89     { INDEX_op_andc_i32, { R, RI, RI } },
  90 #endif
  91 #if TCG_TARGET_HAS_eqv_i32
  92     { INDEX_op_eqv_i32, { R, RI, RI } },
  93 #endif
  94 #if TCG_TARGET_HAS_nand_i32
  95     { INDEX_op_nand_i32, { R, RI, RI } },
  96 #endif
  97 #if TCG_TARGET_HAS_nor_i32
  98     { INDEX_op_nor_i32, { R, RI, RI } },
  99 #endif
 100     { INDEX_op_or_i32, { R, RI, RI } },
 101 #if TCG_TARGET_HAS_orc_i32
 102     { INDEX_op_orc_i32, { R, RI, RI } },
 103 #endif
 104     { INDEX_op_xor_i32, { R, RI, RI } },
 105     { INDEX_op_shl_i32, { R, RI, RI } },
 106     { INDEX_op_shr_i32, { R, RI, RI } },
 107     { INDEX_op_sar_i32, { R, RI, RI } },
 108 #if TCG_TARGET_HAS_rot_i32
 109     { INDEX_op_rotl_i32, { R, RI, RI } },
 110     { INDEX_op_rotr_i32, { R, RI, RI } },
 111 #endif
 112 #if TCG_TARGET_HAS_deposit_i32
 113     { INDEX_op_deposit_i32, { R, "0", R } },
 114 #endif
 115
 116     { INDEX_op_brcond_i32, { R, RI } },
 117
 118     { INDEX_op_setcond_i32, { R, R, RI } },
 119 #if TCG_TARGET_REG_BITS == 64
 120     { INDEX_op_setcond_i64, { R, R, RI } },
 121 #endif /* TCG_TARGET_REG_BITS == 64 */
 122
 123 #if TCG_TARGET_REG_BITS == 32
 124     /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */
 125     { INDEX_op_add2_i32, { R, R, R, R, R, R } },
 126     { INDEX_op_sub2_i32, { R, R, R, R, R, R } },
 127     { INDEX_op_brcond2_i32, { R, R, RI, RI } },
 128     { INDEX_op_mulu2_i32, { R, R, R, R } },
 129     { INDEX_op_setcond2_i32, { R, R, R, RI, RI } },
 130 #endif
 131
 132 #if TCG_TARGET_HAS_not_i32
 133     { INDEX_op_not_i32, { R, R } },
 134 #endif
 135 #if TCG_TARGET_HAS_neg_i32
 136     { INDEX_op_neg_i32, { R, R } },
 137 #endif
 138
 139 #if TCG_TARGET_REG_BITS == 64
 140     { INDEX_op_ld8u_i64, { R, R } },
 141     { INDEX_op_ld8s_i64, { R, R } },
 142     { INDEX_op_ld16u_i64, { R, R } },
 143     { INDEX_op_ld16s_i64, { R, R } },
 144     { INDEX_op_ld32u_i64, { R, R } },
 145     { INDEX_op_ld32s_i64, { R, R } },
 146     { INDEX_op_ld_i64, { R, R } },
 147
 148     { INDEX_op_st8_i64, { R, R } },
 149     { INDEX_op_st16_i64, { R, R } },
 150     { INDEX_op_st32_i64, { R, R } },
 151     { INDEX_op_st_i64, { R, R } },
 152
 153     { INDEX_op_add_i64, { R, RI, RI } },
 154     { INDEX_op_sub_i64, { R, RI, RI } },
 155     { INDEX_op_mul_i64, { R, RI, RI } },
 156 #if TCG_TARGET_HAS_div_i64
 157     { INDEX_op_div_i64, { R, R, R } },
 158     { INDEX_op_divu_i64, { R, R, R } },
 159     { INDEX_op_rem_i64, { R, R, R } },
 160     { INDEX_op_remu_i64, { R, R, R } },
 161 #elif TCG_TARGET_HAS_div2_i64
 162     { INDEX_op_div2_i64, { R, R, "0", "1", R } },
 163     { INDEX_op_divu2_i64, { R, R, "0", "1", R } },
 164 #endif
 165     { INDEX_op_and_i64, { R, RI, RI } },
 166 #if TCG_TARGET_HAS_andc_i64
 167     { INDEX_op_andc_i64, { R, RI, RI } },
 168 #endif
 169 #if TCG_TARGET_HAS_eqv_i64
 170     { INDEX_op_eqv_i64, { R, RI, RI } },
 171 #endif
 172 #if TCG_TARGET_HAS_nand_i64
 173     { INDEX_op_nand_i64, { R, RI, RI } },
 174 #endif
 175 #if TCG_TARGET_HAS_nor_i64
 176     { INDEX_op_nor_i64, { R, RI, RI } },
 177 #endif
 178     { INDEX_op_or_i64, { R, RI, RI } },
 179 #if TCG_TARGET_HAS_orc_i64
 180     { INDEX_op_orc_i64, { R, RI, RI } },
 181 #endif
 182     { INDEX_op_xor_i64, { R, RI, RI } },
 183     { INDEX_op_shl_i64, { R, RI, RI } },
 184     { INDEX_op_shr_i64, { R, RI, RI } },
 185     { INDEX_op_sar_i64, { R, RI, RI } },
 186 #if TCG_TARGET_HAS_rot_i64
 187     { INDEX_op_rotl_i64, { R, RI, RI } },
 188     { INDEX_op_rotr_i64, { R, RI, RI } },
 189 #endif
 190 #if TCG_TARGET_HAS_deposit_i64
 191     { INDEX_op_deposit_i64, { R, "0", R } },
 192 #endif
 193     { INDEX_op_brcond_i64, { R, RI } },
 194
 195 #if TCG_TARGET_HAS_ext8s_i64
 196     { INDEX_op_ext8s_i64, { R, R } },
 197 #endif
 198 #if TCG_TARGET_HAS_ext16s_i64
 199     { INDEX_op_ext16s_i64, { R, R } },
 200 #endif
 201 #if TCG_TARGET_HAS_ext32s_i64
 202     { INDEX_op_ext32s_i64, { R, R } },
 203 #endif
 204 #if TCG_TARGET_HAS_ext8u_i64
 205     { INDEX_op_ext8u_i64, { R, R } },
 206 #endif
 207 #if TCG_TARGET_HAS_ext16u_i64
 208     { INDEX_op_ext16u_i64, { R, R } },
 209 #endif
 210 #if TCG_TARGET_HAS_ext32u_i64
 211     { INDEX_op_ext32u_i64, { R, R } },
 212 #endif
 213     { INDEX_op_ext_i32_i64, { R, R } },
 214     { INDEX_op_extu_i32_i64, { R, R } },
 215 #if TCG_TARGET_HAS_bswap16_i64
 216     { INDEX_op_bswap16_i64, { R, R } },
 217 #endif
 218 #if TCG_TARGET_HAS_bswap32_i64
 219     { INDEX_op_bswap32_i64, { R, R } },
 220 #endif
 221 #if TCG_TARGET_HAS_bswap64_i64
 222     { INDEX_op_bswap64_i64, { R, R } },
 223 #endif
 224 #if TCG_TARGET_HAS_not_i64
 225     { INDEX_op_not_i64, { R, R } },
 226 #endif
 227 #if TCG_TARGET_HAS_neg_i64
 228     { INDEX_op_neg_i64, { R, R } },
 229 #endif
 230 #endif /* TCG_TARGET_REG_BITS == 64 */
 231
 232     { INDEX_op_qemu_ld_i32, { R, L } },
 233     { INDEX_op_qemu_ld_i64, { R64, L } },
 234
 235     { INDEX_op_qemu_st_i32, { R, S } },
 236     { INDEX_op_qemu_st_i64, { R64, S } },
 237
 238 #if TCG_TARGET_HAS_ext8s_i32
 239     { INDEX_op_ext8s_i32, { R, R } },
 240 #endif
 241 #if TCG_TARGET_HAS_ext16s_i32
 242     { INDEX_op_ext16s_i32, { R, R } },
 243 #endif
 244 #if TCG_TARGET_HAS_ext8u_i32
 245     { INDEX_op_ext8u_i32, { R, R } },
 246 #endif
 247 #if TCG_TARGET_HAS_ext16u_i32
 248     { INDEX_op_ext16u_i32, { R, R } },
 249 #endif
 250
 251 #if TCG_TARGET_HAS_bswap16_i32
 252     { INDEX_op_bswap16_i32, { R, R } },
 253 #endif
 254 #if TCG_TARGET_HAS_bswap32_i32
 255     { INDEX_op_bswap32_i32, { R, R } },
 256 #endif
 257
 258     { -1 },
 259 };
 260
 261 static const int tcg_target_reg_alloc_order[] = {
 262     TCG_REG_R0,
 263     TCG_REG_R1,
 264     TCG_REG_R2,
 265     TCG_REG_R3,
 266 #if 0 /* used for TCG_REG_CALL_STACK */
 267     TCG_REG_R4,
 268 #endif
 269     TCG_REG_R5,
 270     TCG_REG_R6,
 271     TCG_REG_R7,
 272 #if TCG_TARGET_NB_REGS >= 16
 273     TCG_REG_R8,
 274     TCG_REG_R9,
 275     TCG_REG_R10,
 276     TCG_REG_R11,
 277     TCG_REG_R12,
 278     TCG_REG_R13,
 279     TCG_REG_R14,
 280     TCG_REG_R15,
 281 #endif
 282 };
 283
 284 #if MAX_OPC_PARAM_IARGS != 5
 285 # error Fix needed, number of supported input arguments changed!
 286 #endif
 287
 288 static const int tcg_target_call_iarg_regs[] = {
 289     TCG_REG_R0,
 290     TCG_REG_R1,
 291     TCG_REG_R2,
 292     TCG_REG_R3,
 293 #if 0 /* used for TCG_REG_CALL_STACK */
 294     TCG_REG_R4,
 295 #endif
 296     TCG_REG_R5,
 297 #if TCG_TARGET_REG_BITS == 32
 298     /* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */
 299     TCG_REG_R6,
 300     TCG_REG_R7,
 301 #if TCG_TARGET_NB_REGS >= 16
 302     TCG_REG_R8,
 303     TCG_REG_R9,
 304     TCG_REG_R10,
 305 #else
 306 # error Too few input registers available
 307 #endif
 308 #endif
 309 };
 310
 311 static const int tcg_target_call_oarg_regs[] = {
 312     TCG_REG_R0,
 313 #if TCG_TARGET_REG_BITS == 32
 314     TCG_REG_R1
 315 #endif
 316 };
 317
 318 #ifndef NDEBUG
 319 static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
 320     "r00",
 321     "r01",
 322     "r02",
 323     "r03",
 324     "r04",
 325     "r05",
 326     "r06",
 327     "r07",
 328 #if TCG_TARGET_NB_REGS >= 16
 329     "r08",
 330     "r09",
 331     "r10",
 332     "r11",
 333     "r12",
 334     "r13",
 335     "r14",
 336     "r15",
 337 #if TCG_TARGET_NB_REGS >= 32
 338     "r16",
 339     "r17",
 340     "r18",
 341     "r19",
 342     "r20",
 343     "r21",
 344     "r22",
 345     "r23",
 346     "r24",
 347     "r25",
 348     "r26",
 349     "r27",
 350     "r28",
 351     "r29",
 352     "r30",
 353     "r31"
 354 #endif
 355 #endif
 356 };
 357 #endif
 358
 359 static void patch_reloc(tcg_insn_unit *code_ptr, int type,
 360                         intptr_t value, intptr_t addend)
 361 {
 362     /* tcg_out_reloc always uses the same type, addend. */
 363     assert(type == sizeof(tcg_target_long));
 364     assert(addend == 0);
 365     assert(value != 0);
 366     if (TCG_TARGET_REG_BITS == 32) {
 367         tcg_patch32(code_ptr, value);
 368     } else {
 369         tcg_patch64(code_ptr, value);
 370     }
 371 }
 372
 373 /* Parse target specific constraints. */
 374 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
 375 {
 376     const char *ct_str = *pct_str;
 377     switch (ct_str[0]) {
 378     case 'r':
 379     case 'L':                   /* qemu_ld constraint */
 380     case 'S':                   /* qemu_st constraint */
 381         ct->ct |= TCG_CT_REG;
 382         tcg_regset_set32(ct->u.regs, 0, BIT(TCG_TARGET_NB_REGS) - 1);
 383         break;
 384     default:
 385         return -1;
 386     }
 387     ct_str++;
 388     *pct_str = ct_str;
 389     return 0;
 390 }
 391
 392 #if defined(CONFIG_DEBUG_TCG_INTERPRETER)
 393 /* Show current bytecode. Used by tcg interpreter. */
 394 void tci_disas(uint8_t opc)
 395 {
 396     const TCGOpDef *def = &tcg_op_defs[opc];
 397     fprintf(stderr, "TCG %s %u, %u, %u\n",
 398             def->name, def->nb_oargs, def->nb_iargs, def->nb_cargs);
 399 }
 400 #endif
 401
 402 /* Write value (native size). */
 403 static void tcg_out_i(TCGContext *s, tcg_target_ulong v)
 404 {
 405     if (TCG_TARGET_REG_BITS == 32) {
 406         tcg_out32(s, v);
 407     } else {
 408         tcg_out64(s, v);
 409     }
 410 }
 411
 412 /* Write opcode. */
 413 static void tcg_out_op_t(TCGContext *s, TCGOpcode op)
 414 {
 415     tcg_out8(s, op);
 416     tcg_out8(s, 0);
 417 }
 418
 419 /* Write register. */
 420 static void tcg_out_r(TCGContext *s, TCGArg t0)
 421 {
 422     assert(t0 < TCG_TARGET_NB_REGS);
 423     tcg_out8(s, t0);
 424 }
 425
 426 /* Write register or constant (native size). */
 427 static void tcg_out_ri(TCGContext *s, int const_arg, TCGArg arg)
 428 {
 429     if (const_arg) {
 430         assert(const_arg == 1);
 431         tcg_out8(s, TCG_CONST);
 432         tcg_out_i(s, arg);
 433     } else {
 434         tcg_out_r(s, arg);
 435     }
 436 }
 437
 438 /* Write register or constant (32 bit). */
 439 static void tcg_out_ri32(TCGContext *s, int const_arg, TCGArg arg)
 440 {
 441     if (const_arg) {
 442         assert(const_arg == 1);
 443         tcg_out8(s, TCG_CONST);
 444         tcg_out32(s, arg);
 445     } else {
 446         tcg_out_r(s, arg);
 447     }
 448 }
 449
 450 #if TCG_TARGET_REG_BITS == 64
 451 /* Write register or constant (64 bit). */
 452 static void tcg_out_ri64(TCGContext *s, int const_arg, TCGArg arg)
 453 {
 454     if (const_arg) {
 455         assert(const_arg == 1);
 456         tcg_out8(s, TCG_CONST);
 457         tcg_out64(s, arg);
 458     } else {
 459         tcg_out_r(s, arg);
 460     }
 461 }
 462 #endif
 463
 464 /* Write label. */
 465 static void tci_out_label(TCGContext *s, TCGLabel *label)
 466 {
 467     if (label->has_value) {
 468         tcg_out_i(s, label->u.value);
 469         assert(label->u.value);
 470     } else {
 471         tcg_out_reloc(s, s->code_ptr, sizeof(tcg_target_ulong), label, 0);
 472         s->code_ptr += sizeof(tcg_target_ulong);
 473     }
 474 }
 475
 476 static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
 477                        intptr_t arg2)
 478 {
 479     uint8_t *old_code_ptr = s->code_ptr;
 480     if (type == TCG_TYPE_I32) {
 481         tcg_out_op_t(s, INDEX_op_ld_i32);
 482         tcg_out_r(s, ret);
 483         tcg_out_r(s, arg1);
 484         tcg_out32(s, arg2);
 485     } else {
 486         assert(type == TCG_TYPE_I64);
 487 #if TCG_TARGET_REG_BITS == 64
 488         tcg_out_op_t(s, INDEX_op_ld_i64);
 489         tcg_out_r(s, ret);
 490         tcg_out_r(s, arg1);
 491         assert(arg2 == (int32_t)arg2);
 492         tcg_out32(s, arg2);
 493 #else
 494         TODO();
 495 #endif
 496     }
 497     old_code_ptr[1] = s->code_ptr - old_code_ptr;
 498 }
 499
 500 static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
 501 {
 502     uint8_t *old_code_ptr = s->code_ptr;
 503     assert(ret != arg);
 504 #if TCG_TARGET_REG_BITS == 32
 505     tcg_out_op_t(s, INDEX_op_mov_i32);
 506 #else
 507     tcg_out_op_t(s, INDEX_op_mov_i64);
 508 #endif
 509     tcg_out_r(s, ret);
 510     tcg_out_r(s, arg);
 511     old_code_ptr[1] = s->code_ptr - old_code_ptr;
 512 }
 513
 514 static void tcg_out_movi(TCGContext *s, TCGType type,
 515                          TCGReg t0, tcg_target_long arg)
 516 {
 517     uint8_t *old_code_ptr = s->code_ptr;
 518     uint32_t arg32 = arg;
 519     if (type == TCG_TYPE_I32 || arg == arg32) {
 520         tcg_out_op_t(s, INDEX_op_movi_i32);
 521         tcg_out_r(s, t0);
 522         tcg_out32(s, arg32);
 523     } else {
 524         assert(type == TCG_TYPE_I64);
 525 #if TCG_TARGET_REG_BITS == 64
 526         tcg_out_op_t(s, INDEX_op_movi_i64);
 527         tcg_out_r(s, t0);
 528         tcg_out64(s, arg);
 529 #else
 530         TODO();
 531 #endif
 532     }
 533     old_code_ptr[1] = s->code_ptr - old_code_ptr;
 534 }
 535
 536 static inline void tcg_out_call(TCGContext *s, tcg_insn_unit *arg)
 537 {
 538     uint8_t *old_code_ptr = s->code_ptr;
 539     tcg_out_op_t(s, INDEX_op_call);
 540     tcg_out_ri(s, 1, (uintptr_t)arg);
 541     old_code_ptr[1] = s->code_ptr - old_code_ptr;
 542 }
 543
 544 static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
 545                        const int *const_args)
 546 {
 547     uint8_t *old_code_ptr = s->code_ptr;
 548
 549     tcg_out_op_t(s, opc);
 550
 551     switch (opc) {
 552     case INDEX_op_exit_tb:
 553         tcg_out64(s, args[0]);
 554         break;
 555     case INDEX_op_goto_tb:
 556         if (s->tb_jmp_offset) {
 557             /* Direct jump method. */
 558             assert(args[0] < ARRAY_SIZE(s->tb_jmp_offset));
 559             s->tb_jmp_offset[args[0]] = tcg_current_code_size(s);
 560             tcg_out32(s, 0);
 561         } else {
 562             /* Indirect jump method. */
 563             TODO();
 564         }
 565         assert(args[0] < ARRAY_SIZE(s->tb_next_offset));
 566         s->tb_next_offset[args[0]] = tcg_current_code_size(s);
 567         break;
 568     case INDEX_op_br:
 569         tci_out_label(s, arg_label(args[0]));
 570         break;
 571     case INDEX_op_setcond_i32:
 572         tcg_out_r(s, args[0]);
 573         tcg_out_r(s, args[1]);
 574         tcg_out_ri32(s, const_args[2], args[2]);
 575         tcg_out8(s, args[3]);   /* condition */
 576         break;
 577 #if TCG_TARGET_REG_BITS == 32
 578     case INDEX_op_setcond2_i32:
 579         /* setcond2_i32 cond, t0, t1_low, t1_high, t2_low, t2_high */
 580         tcg_out_r(s, args[0]);
 581         tcg_out_r(s, args[1]);
 582         tcg_out_r(s, args[2]);
 583         tcg_out_ri32(s, const_args[3], args[3]);
 584         tcg_out_ri32(s, const_args[4], args[4]);
 585         tcg_out8(s, args[5]);   /* condition */
 586         break;
 587 #elif TCG_TARGET_REG_BITS == 64
 588     case INDEX_op_setcond_i64:
 589         tcg_out_r(s, args[0]);
 590         tcg_out_r(s, args[1]);
 591         tcg_out_ri64(s, const_args[2], args[2]);
 592         tcg_out8(s, args[3]);   /* condition */
 593         break;
 594 #endif
 595     case INDEX_op_ld8u_i32:
 596     case INDEX_op_ld8s_i32:
 597     case INDEX_op_ld16u_i32:
 598     case INDEX_op_ld16s_i32:
 599     case INDEX_op_ld_i32:
 600     case INDEX_op_st8_i32:
 601     case INDEX_op_st16_i32:
 602     case INDEX_op_st_i32:
 603     case INDEX_op_ld8u_i64:
 604     case INDEX_op_ld8s_i64:
 605     case INDEX_op_ld16u_i64:
 606     case INDEX_op_ld16s_i64:
 607     case INDEX_op_ld32u_i64:
 608     case INDEX_op_ld32s_i64:
 609     case INDEX_op_ld_i64:
 610     case INDEX_op_st8_i64:
 611     case INDEX_op_st16_i64:
 612     case INDEX_op_st32_i64:
 613     case INDEX_op_st_i64:
 614         tcg_out_r(s, args[0]);
 615         tcg_out_r(s, args[1]);
 616         assert(args[2] == (int32_t)args[2]);
 617         tcg_out32(s, args[2]);
 618         break;
 619     case INDEX_op_add_i32:
 620     case INDEX_op_sub_i32:
 621     case INDEX_op_mul_i32:
 622     case INDEX_op_and_i32:
 623     case INDEX_op_andc_i32:     /* Optional (TCG_TARGET_HAS_andc_i32). */
 624     case INDEX_op_eqv_i32:      /* Optional (TCG_TARGET_HAS_eqv_i32). */
 625     case INDEX_op_nand_i32:     /* Optional (TCG_TARGET_HAS_nand_i32). */
 626     case INDEX_op_nor_i32:      /* Optional (TCG_TARGET_HAS_nor_i32). */
 627     case INDEX_op_or_i32:
 628     case INDEX_op_orc_i32:      /* Optional (TCG_TARGET_HAS_orc_i32). */
 629     case INDEX_op_xor_i32:
 630     case INDEX_op_shl_i32:
 631     case INDEX_op_shr_i32:
 632     case INDEX_op_sar_i32:
 633     case INDEX_op_rotl_i32:     /* Optional (TCG_TARGET_HAS_rot_i32). */
 634     case INDEX_op_rotr_i32:     /* Optional (TCG_TARGET_HAS_rot_i32). */
 635         tcg_out_r(s, args[0]);
 636         tcg_out_ri32(s, const_args[1], args[1]);
 637         tcg_out_ri32(s, const_args[2], args[2]);
 638         break;
 639     case INDEX_op_deposit_i32:  /* Optional (TCG_TARGET_HAS_deposit_i32). */
 640         tcg_out_r(s, args[0]);
 641         tcg_out_r(s, args[1]);
 642         tcg_out_r(s, args[2]);
 643         assert(args[3] <= UINT8_MAX);
 644         tcg_out8(s, args[3]);
 645         assert(args[4] <= UINT8_MAX);
 646         tcg_out8(s, args[4]);
 647         break;
 648
 649 #if TCG_TARGET_REG_BITS == 64
 650     case INDEX_op_add_i64:
 651     case INDEX_op_sub_i64:
 652     case INDEX_op_mul_i64:
 653     case INDEX_op_and_i64:
 654     case INDEX_op_andc_i64:     /* Optional (TCG_TARGET_HAS_andc_i64). */
 655     case INDEX_op_eqv_i64:      /* Optional (TCG_TARGET_HAS_eqv_i64). */
 656     case INDEX_op_nand_i64:     /* Optional (TCG_TARGET_HAS_nand_i64). */
 657     case INDEX_op_nor_i64:      /* Optional (TCG_TARGET_HAS_nor_i64). */
 658     case INDEX_op_or_i64:
 659     case INDEX_op_orc_i64:      /* Optional (TCG_TARGET_HAS_orc_i64). */
 660     case INDEX_op_xor_i64:
 661     case INDEX_op_shl_i64:
 662     case INDEX_op_shr_i64:
 663     case INDEX_op_sar_i64:
 664     case INDEX_op_rotl_i64:     /* Optional (TCG_TARGET_HAS_rot_i64). */
 665     case INDEX_op_rotr_i64:     /* Optional (TCG_TARGET_HAS_rot_i64). */
 666         tcg_out_r(s, args[0]);
 667         tcg_out_ri64(s, const_args[1], args[1]);
 668         tcg_out_ri64(s, const_args[2], args[2]);
 669         break;
 670     case INDEX_op_deposit_i64:  /* Optional (TCG_TARGET_HAS_deposit_i64). */
 671         tcg_out_r(s, args[0]);
 672         tcg_out_r(s, args[1]);
 673         tcg_out_r(s, args[2]);
 674         assert(args[3] <= UINT8_MAX);
 675         tcg_out8(s, args[3]);
 676         assert(args[4] <= UINT8_MAX);
 677         tcg_out8(s, args[4]);
 678         break;
 679     case INDEX_op_div_i64:      /* Optional (TCG_TARGET_HAS_div_i64). */
 680     case INDEX_op_divu_i64:     /* Optional (TCG_TARGET_HAS_div_i64). */
 681     case INDEX_op_rem_i64:      /* Optional (TCG_TARGET_HAS_div_i64). */
 682     case INDEX_op_remu_i64:     /* Optional (TCG_TARGET_HAS_div_i64). */
 683         TODO();
 684         break;
 685     case INDEX_op_div2_i64:     /* Optional (TCG_TARGET_HAS_div2_i64). */
 686     case INDEX_op_divu2_i64:    /* Optional (TCG_TARGET_HAS_div2_i64). */
 687         TODO();
 688         break;
 689     case INDEX_op_brcond_i64:
 690         tcg_out_r(s, args[0]);
 691         tcg_out_ri64(s, const_args[1], args[1]);
 692         tcg_out8(s, args[2]);           /* condition */
 693         tci_out_label(s, arg_label(args[3]));
 694         break;
 695     case INDEX_op_bswap16_i64:  /* Optional (TCG_TARGET_HAS_bswap16_i64). */
 696     case INDEX_op_bswap32_i64:  /* Optional (TCG_TARGET_HAS_bswap32_i64). */
 697     case INDEX_op_bswap64_i64:  /* Optional (TCG_TARGET_HAS_bswap64_i64). */
 698     case INDEX_op_not_i64:      /* Optional (TCG_TARGET_HAS_not_i64). */
 699     case INDEX_op_neg_i64:      /* Optional (TCG_TARGET_HAS_neg_i64). */
 700     case INDEX_op_ext8s_i64:    /* Optional (TCG_TARGET_HAS_ext8s_i64). */
 701     case INDEX_op_ext8u_i64:    /* Optional (TCG_TARGET_HAS_ext8u_i64). */
 702     case INDEX_op_ext16s_i64:   /* Optional (TCG_TARGET_HAS_ext16s_i64). */
 703     case INDEX_op_ext16u_i64:   /* Optional (TCG_TARGET_HAS_ext16u_i64). */
 704     case INDEX_op_ext32s_i64:   /* Optional (TCG_TARGET_HAS_ext32s_i64). */
 705     case INDEX_op_ext32u_i64:   /* Optional (TCG_TARGET_HAS_ext32u_i64). */
 706     case INDEX_op_ext_i32_i64:
 707     case INDEX_op_extu_i32_i64:
 708 #endif /* TCG_TARGET_REG_BITS == 64 */
 709     case INDEX_op_neg_i32:      /* Optional (TCG_TARGET_HAS_neg_i32). */
 710     case INDEX_op_not_i32:      /* Optional (TCG_TARGET_HAS_not_i32). */
 711     case INDEX_op_ext8s_i32:    /* Optional (TCG_TARGET_HAS_ext8s_i32). */
 712     case INDEX_op_ext16s_i32:   /* Optional (TCG_TARGET_HAS_ext16s_i32). */
 713     case INDEX_op_ext8u_i32:    /* Optional (TCG_TARGET_HAS_ext8u_i32). */
 714     case INDEX_op_ext16u_i32:   /* Optional (TCG_TARGET_HAS_ext16u_i32). */
 715     case INDEX_op_bswap16_i32:  /* Optional (TCG_TARGET_HAS_bswap16_i32). */
 716     case INDEX_op_bswap32_i32:  /* Optional (TCG_TARGET_HAS_bswap32_i32). */
 717         tcg_out_r(s, args[0]);
 718         tcg_out_r(s, args[1]);
 719         break;
 720     case INDEX_op_div_i32:      /* Optional (TCG_TARGET_HAS_div_i32). */
 721     case INDEX_op_divu_i32:     /* Optional (TCG_TARGET_HAS_div_i32). */
 722     case INDEX_op_rem_i32:      /* Optional (TCG_TARGET_HAS_div_i32). */
 723     case INDEX_op_remu_i32:     /* Optional (TCG_TARGET_HAS_div_i32). */
 724         tcg_out_r(s, args[0]);
 725         tcg_out_ri32(s, const_args[1], args[1]);
 726         tcg_out_ri32(s, const_args[2], args[2]);
 727         break;
 728     case INDEX_op_div2_i32:     /* Optional (TCG_TARGET_HAS_div2_i32). */
 729     case INDEX_op_divu2_i32:    /* Optional (TCG_TARGET_HAS_div2_i32). */
 730         TODO();
 731         break;
 732 #if TCG_TARGET_REG_BITS == 32
 733     case INDEX_op_add2_i32:
 734     case INDEX_op_sub2_i32:
 735         tcg_out_r(s, args[0]);
 736         tcg_out_r(s, args[1]);
 737         tcg_out_r(s, args[2]);
 738         tcg_out_r(s, args[3]);
 739         tcg_out_r(s, args[4]);
 740         tcg_out_r(s, args[5]);
 741         break;
 742     case INDEX_op_brcond2_i32:
 743         tcg_out_r(s, args[0]);
 744         tcg_out_r(s, args[1]);
 745         tcg_out_ri32(s, const_args[2], args[2]);
 746         tcg_out_ri32(s, const_args[3], args[3]);
 747         tcg_out8(s, args[4]);           /* condition */
 748         tci_out_label(s, arg_label(args[5]));
 749         break;
 750     case INDEX_op_mulu2_i32:
 751         tcg_out_r(s, args[0]);
 752         tcg_out_r(s, args[1]);
 753         tcg_out_r(s, args[2]);
 754         tcg_out_r(s, args[3]);
 755         break;
 756 #endif
 757     case INDEX_op_brcond_i32:
 758         tcg_out_r(s, args[0]);
 759         tcg_out_ri32(s, const_args[1], args[1]);
 760         tcg_out8(s, args[2]);           /* condition */
 761         tci_out_label(s, arg_label(args[3]));
 762         break;
 763     case INDEX_op_qemu_ld_i32:
 764         tcg_out_r(s, *args++);
 765         tcg_out_r(s, *args++);
 766         if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
 767             tcg_out_r(s, *args++);
 768         }
 769         tcg_out_i(s, *args++);
 770         break;
 771     case INDEX_op_qemu_ld_i64:
 772         tcg_out_r(s, *args++);
 773         if (TCG_TARGET_REG_BITS == 32) {
 774             tcg_out_r(s, *args++);
 775         }
 776         tcg_out_r(s, *args++);
 777         if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
 778             tcg_out_r(s, *args++);
 779         }
 780         tcg_out_i(s, *args++);
 781         break;
 782     case INDEX_op_qemu_st_i32:
 783         tcg_out_r(s, *args++);
 784         tcg_out_r(s, *args++);
 785         if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
 786             tcg_out_r(s, *args++);
 787         }
 788         tcg_out_i(s, *args++);
 789         break;
 790     case INDEX_op_qemu_st_i64:
 791         tcg_out_r(s, *args++);
 792         if (TCG_TARGET_REG_BITS == 32) {
 793             tcg_out_r(s, *args++);
 794         }
 795         tcg_out_r(s, *args++);
 796         if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
 797             tcg_out_r(s, *args++);
 798         }
 799         tcg_out_i(s, *args++);
 800         break;
 801     case INDEX_op_mov_i32:  /* Always emitted via tcg_out_mov.  */
 802     case INDEX_op_mov_i64:
 803     case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi.  */
 804     case INDEX_op_movi_i64:
 805     case INDEX_op_call:     /* Always emitted via tcg_out_call.  */
 806     default:
 807         tcg_abort();
 808     }
 809     old_code_ptr[1] = s->code_ptr - old_code_ptr;
 810 }
 811
 812 static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1,
 813                        intptr_t arg2)
 814 {
 815     uint8_t *old_code_ptr = s->code_ptr;
 816     if (type == TCG_TYPE_I32) {
 817         tcg_out_op_t(s, INDEX_op_st_i32);
 818         tcg_out_r(s, arg);
 819         tcg_out_r(s, arg1);
 820         tcg_out32(s, arg2);
 821     } else {
 822         assert(type == TCG_TYPE_I64);
 823 #if TCG_TARGET_REG_BITS == 64
 824         tcg_out_op_t(s, INDEX_op_st_i64);
 825         tcg_out_r(s, arg);
 826         tcg_out_r(s, arg1);
 827         tcg_out32(s, arg2);
 828 #else
 829         TODO();
 830 #endif
 831     }
 832     old_code_ptr[1] = s->code_ptr - old_code_ptr;
 833 }
 834
 835 /* Test if a constant matches the constraint. */
 836 static int tcg_target_const_match(tcg_target_long val, TCGType type,
 837                                   const TCGArgConstraint *arg_ct)
 838 {
 839     /* No need to return 0 or 1, 0 or != 0 is good enough. */
 840     return arg_ct->ct & TCG_CT_CONST;
 841 }
 842
 843 static void tcg_target_init(TCGContext *s)
 844 {
 845 #if defined(CONFIG_DEBUG_TCG_INTERPRETER)
 846     const char *envval = getenv("DEBUG_TCG");
 847     if (envval) {
 848         qemu_set_log(strtol(envval, NULL, 0));
 849     }
 850 #endif
 851
 852     /* The current code uses uint8_t for tcg operations. */
 853     assert(ARRAY_SIZE(tcg_op_defs) <= UINT8_MAX);
 854
 855     /* Registers available for 32 bit operations. */
 856     tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0,
 857                      BIT(TCG_TARGET_NB_REGS) - 1);
 858     /* Registers available for 64 bit operations. */
 859     tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0,
 860                      BIT(TCG_TARGET_NB_REGS) - 1);
 861     /* TODO: Which registers should be set here? */
 862     tcg_regset_set32(tcg_target_call_clobber_regs, 0,
 863                      BIT(TCG_TARGET_NB_REGS) - 1);
 864
 865     tcg_regset_clear(s->reserved_regs);
 866     tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
 867     tcg_add_target_add_op_defs(tcg_target_op_defs);
 868
 869     /* We use negative offsets from "sp" so that we can distinguish
 870        stores that might pretend to be call arguments.  */
 871     tcg_set_frame(s, TCG_REG_CALL_STACK,
 872                   -CPU_TEMP_BUF_NLONGS * sizeof(long),
 873                   CPU_TEMP_BUF_NLONGS * sizeof(long));
 874 }
 875
 876 /* Generate global QEMU prologue and epilogue code. */
 877 static inline void tcg_target_qemu_prologue(TCGContext *s)
 878 {
 879 }