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target/m68k: rename M68K_FEATURE_M68000 to M68K_FEATURE_M68K
[qemu/ar7.git] / target / m68k / translate.c
blob0b618e8eb2bdc016c0729eced63df3f6e4f2ddf6
1 /*
2 * m68k translation
3 *
4 * Copyright (c) 2005-2007 CodeSourcery
5 * Written by Paul Brook
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
25 #include "tcg/tcg-op.h"
26 #include "qemu/log.h"
27 #include "qemu/qemu-print.h"
28 #include "exec/cpu_ldst.h"
29 #include "exec/translator.h"
30
31 #include "exec/helper-proto.h"
32 #include "exec/helper-gen.h"
33
34 #include "exec/log.h"
35 #include "fpu/softfloat.h"
36
37
38 //#define DEBUG_DISPATCH 1
39
40 #define DEFO32(name, offset) static TCGv QREG_##name;
41 #define DEFO64(name, offset) static TCGv_i64 QREG_##name;
42 #include "qregs.def"
43 #undef DEFO32
44 #undef DEFO64
45
46 static TCGv_i32 cpu_halted;
47 static TCGv_i32 cpu_exception_index;
48
49 static char cpu_reg_names[2 * 8 * 3 + 5 * 4];
50 static TCGv cpu_dregs[8];
51 static TCGv cpu_aregs[8];
52 static TCGv_i64 cpu_macc[4];
53
54 #define REG(insn, pos) (((insn) >> (pos)) & 7)
55 #define DREG(insn, pos) cpu_dregs[REG(insn, pos)]
56 #define AREG(insn, pos) get_areg(s, REG(insn, pos))
57 #define MACREG(acc) cpu_macc[acc]
58 #define QREG_SP get_areg(s, 7)
59
60 static TCGv NULL_QREG;
61 #define IS_NULL_QREG(t) (t == NULL_QREG)
62 /* Used to distinguish stores from bad addressing modes. */
63 static TCGv store_dummy;
64
65 #include "exec/gen-icount.h"
66
67 void m68k_tcg_init(void)
68 {
69 char *p;
70 int i;
71
72 #define DEFO32(name, offset) \
73 QREG_##name = tcg_global_mem_new_i32(cpu_env, \
74 offsetof(CPUM68KState, offset), #name);
75 #define DEFO64(name, offset) \
76 QREG_##name = tcg_global_mem_new_i64(cpu_env, \
77 offsetof(CPUM68KState, offset), #name);
78 #include "qregs.def"
79 #undef DEFO32
80 #undef DEFO64
81
82 cpu_halted = tcg_global_mem_new_i32(cpu_env,
83 -offsetof(M68kCPU, env) +
84 offsetof(CPUState, halted), "HALTED");
85 cpu_exception_index = tcg_global_mem_new_i32(cpu_env,
86 -offsetof(M68kCPU, env) +
87 offsetof(CPUState, exception_index),
88 "EXCEPTION");
89
90 p = cpu_reg_names;
91 for (i = 0; i < 8; i++) {
92 sprintf(p, "D%d", i);
93 cpu_dregs[i] = tcg_global_mem_new(cpu_env,
94 offsetof(CPUM68KState, dregs[i]), p);
95 p += 3;
96 sprintf(p, "A%d", i);
97 cpu_aregs[i] = tcg_global_mem_new(cpu_env,
98 offsetof(CPUM68KState, aregs[i]), p);
99 p += 3;
100 }
101 for (i = 0; i < 4; i++) {
102 sprintf(p, "ACC%d", i);
103 cpu_macc[i] = tcg_global_mem_new_i64(cpu_env,
104 offsetof(CPUM68KState, macc[i]), p);
105 p += 5;
106 }
107
108 NULL_QREG = tcg_global_mem_new(cpu_env, -4, "NULL");
109 store_dummy = tcg_global_mem_new(cpu_env, -8, "NULL");
110 }
111
112 /* internal defines */
113 typedef struct DisasContext {
114 DisasContextBase base;
115 CPUM68KState *env;
116 target_ulong pc;
117 target_ulong pc_prev;
118 CCOp cc_op; /* Current CC operation */
119 int cc_op_synced;
120 TCGv_i64 mactmp;
121 int done_mac;
122 int writeback_mask;
123 TCGv writeback[8];
124 #define MAX_TO_RELEASE 8
125 int release_count;
126 TCGv release[MAX_TO_RELEASE];
127 bool ss_active;
128 } DisasContext;
129
130 static void init_release_array(DisasContext *s)
131 {
132 #ifdef CONFIG_DEBUG_TCG
133 memset(s->release, 0, sizeof(s->release));
134 #endif
135 s->release_count = 0;
136 }
137
138 static void do_release(DisasContext *s)
139 {
140 int i;
141 for (i = 0; i < s->release_count; i++) {
142 tcg_temp_free(s->release[i]);
143 }
144 init_release_array(s);
145 }
146
147 static TCGv mark_to_release(DisasContext *s, TCGv tmp)
148 {
149 g_assert(s->release_count < MAX_TO_RELEASE);
150 return s->release[s->release_count++] = tmp;
151 }
152
153 static TCGv get_areg(DisasContext *s, unsigned regno)
154 {
155 if (s->writeback_mask & (1 << regno)) {
156 return s->writeback[regno];
157 } else {
158 return cpu_aregs[regno];
159 }
160 }
161
162 static void delay_set_areg(DisasContext *s, unsigned regno,
163 TCGv val, bool give_temp)
164 {
165 if (s->writeback_mask & (1 << regno)) {
166 if (give_temp) {
167 tcg_temp_free(s->writeback[regno]);
168 s->writeback[regno] = val;
169 } else {
170 tcg_gen_mov_i32(s->writeback[regno], val);
171 }
172 } else {
173 s->writeback_mask |= 1 << regno;
174 if (give_temp) {
175 s->writeback[regno] = val;
176 } else {
177 TCGv tmp = tcg_temp_new();
178 s->writeback[regno] = tmp;
179 tcg_gen_mov_i32(tmp, val);
180 }
181 }
182 }
183
184 static void do_writebacks(DisasContext *s)
185 {
186 unsigned mask = s->writeback_mask;
187 if (mask) {
188 s->writeback_mask = 0;
189 do {
190 unsigned regno = ctz32(mask);
191 tcg_gen_mov_i32(cpu_aregs[regno], s->writeback[regno]);
192 tcg_temp_free(s->writeback[regno]);
193 mask &= mask - 1;
194 } while (mask);
195 }
196 }
197
198 /* is_jmp field values */
199 #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
200 #define DISAS_EXIT DISAS_TARGET_1 /* cpu state was modified dynamically */
201
202 #if defined(CONFIG_USER_ONLY)
203 #define IS_USER(s) 1
204 #else
205 #define IS_USER(s) (!(s->base.tb->flags & TB_FLAGS_MSR_S))
206 #define SFC_INDEX(s) ((s->base.tb->flags & TB_FLAGS_SFC_S) ? \
207 MMU_KERNEL_IDX : MMU_USER_IDX)
208 #define DFC_INDEX(s) ((s->base.tb->flags & TB_FLAGS_DFC_S) ? \
209 MMU_KERNEL_IDX : MMU_USER_IDX)
210 #endif
211
212 typedef void (*disas_proc)(CPUM68KState *env, DisasContext *s, uint16_t insn);
213
214 #ifdef DEBUG_DISPATCH
215 #define DISAS_INSN(name) \
216 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
217 uint16_t insn); \
218 static void disas_##name(CPUM68KState *env, DisasContext *s, \
219 uint16_t insn) \
220 { \
221 qemu_log("Dispatch " #name "\n"); \
222 real_disas_##name(env, s, insn); \
223 } \
224 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
225 uint16_t insn)
226 #else
227 #define DISAS_INSN(name) \
228 static void disas_##name(CPUM68KState *env, DisasContext *s, \
229 uint16_t insn)
230 #endif
231
232 static const uint8_t cc_op_live[CC_OP_NB] = {
233 [CC_OP_DYNAMIC] = CCF_C | CCF_V | CCF_Z | CCF_N | CCF_X,
234 [CC_OP_FLAGS] = CCF_C | CCF_V | CCF_Z | CCF_N | CCF_X,
235 [CC_OP_ADDB ... CC_OP_ADDL] = CCF_X | CCF_N | CCF_V,
236 [CC_OP_SUBB ... CC_OP_SUBL] = CCF_X | CCF_N | CCF_V,
237 [CC_OP_CMPB ... CC_OP_CMPL] = CCF_X | CCF_N | CCF_V,
238 [CC_OP_LOGIC] = CCF_X | CCF_N
239 };
240
241 static void set_cc_op(DisasContext *s, CCOp op)
242 {
243 CCOp old_op = s->cc_op;
244 int dead;
245
246 if (old_op == op) {
247 return;
248 }
249 s->cc_op = op;
250 s->cc_op_synced = 0;
251
252 /*
253 * Discard CC computation that will no longer be used.
254 * Note that X and N are never dead.
255 */
256 dead = cc_op_live[old_op] & ~cc_op_live[op];
257 if (dead & CCF_C) {
258 tcg_gen_discard_i32(QREG_CC_C);
259 }
260 if (dead & CCF_Z) {
261 tcg_gen_discard_i32(QREG_CC_Z);
262 }
263 if (dead & CCF_V) {
264 tcg_gen_discard_i32(QREG_CC_V);
265 }
266 }
267
268 /* Update the CPU env CC_OP state. */
269 static void update_cc_op(DisasContext *s)
270 {
271 if (!s->cc_op_synced) {
272 s->cc_op_synced = 1;
273 tcg_gen_movi_i32(QREG_CC_OP, s->cc_op);
274 }
275 }
276
277 /* Generate a jump to an immediate address. */
278 static void gen_jmp_im(DisasContext *s, uint32_t dest)
279 {
280 update_cc_op(s);
281 tcg_gen_movi_i32(QREG_PC, dest);
282 s->base.is_jmp = DISAS_JUMP;
283 }
284
285 /* Generate a jump to the address in qreg DEST. */
286 static void gen_jmp(DisasContext *s, TCGv dest)
287 {
288 update_cc_op(s);
289 tcg_gen_mov_i32(QREG_PC, dest);
290 s->base.is_jmp = DISAS_JUMP;
291 }
292
293 static void gen_raise_exception(int nr)
294 {
295 TCGv_i32 tmp;
296
297 tmp = tcg_const_i32(nr);
298 gen_helper_raise_exception(cpu_env, tmp);
299 tcg_temp_free_i32(tmp);
300 }
301
302 static void gen_raise_exception_format2(DisasContext *s, int nr,
303 target_ulong this_pc)
304 {
305 /*
306 * Pass the address of the insn to the exception handler,
307 * for recording in the Format $2 (6-word) stack frame.
308 * Re-use mmu.ar for the purpose, since that's only valid
309 * after tlb_fill.
310 */
311 tcg_gen_st_i32(tcg_constant_i32(this_pc), cpu_env,
312 offsetof(CPUM68KState, mmu.ar));
313 gen_raise_exception(nr);
314 s->base.is_jmp = DISAS_NORETURN;
315 }
316
317 static void gen_exception(DisasContext *s, uint32_t dest, int nr)
318 {
319 update_cc_op(s);
320 tcg_gen_movi_i32(QREG_PC, dest);
321
322 gen_raise_exception(nr);
323
324 s->base.is_jmp = DISAS_NORETURN;
325 }
326
327 static inline void gen_addr_fault(DisasContext *s)
328 {
329 gen_exception(s, s->base.pc_next, EXCP_ADDRESS);
330 }
331
332 /*
333 * Generate a load from the specified address. Narrow values are
334 * sign extended to full register width.
335 */
336 static inline TCGv gen_load(DisasContext *s, int opsize, TCGv addr,
337 int sign, int index)
338 {
339 TCGv tmp;
340 tmp = tcg_temp_new_i32();
341 switch(opsize) {
342 case OS_BYTE:
343 if (sign)
344 tcg_gen_qemu_ld8s(tmp, addr, index);
345 else
346 tcg_gen_qemu_ld8u(tmp, addr, index);
347 break;
348 case OS_WORD:
349 if (sign)
350 tcg_gen_qemu_ld16s(tmp, addr, index);
351 else
352 tcg_gen_qemu_ld16u(tmp, addr, index);
353 break;
354 case OS_LONG:
355 tcg_gen_qemu_ld32u(tmp, addr, index);
356 break;
357 default:
358 g_assert_not_reached();
359 }
360 return tmp;
361 }
362
363 /* Generate a store. */
364 static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val,
365 int index)
366 {
367 switch(opsize) {
368 case OS_BYTE:
369 tcg_gen_qemu_st8(val, addr, index);
370 break;
371 case OS_WORD:
372 tcg_gen_qemu_st16(val, addr, index);
373 break;
374 case OS_LONG:
375 tcg_gen_qemu_st32(val, addr, index);
376 break;
377 default:
378 g_assert_not_reached();
379 }
380 }
381
382 typedef enum {
383 EA_STORE,
384 EA_LOADU,
385 EA_LOADS
386 } ea_what;
387
388 /*
389 * Generate an unsigned load if VAL is 0 a signed load if val is -1,
390 * otherwise generate a store.
391 */
392 static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val,
393 ea_what what, int index)
394 {
395 if (what == EA_STORE) {
396 gen_store(s, opsize, addr, val, index);
397 return store_dummy;
398 } else {
399 return mark_to_release(s, gen_load(s, opsize, addr,
400 what == EA_LOADS, index));
401 }
402 }
403
404 /* Read a 16-bit immediate constant */
405 static inline uint16_t read_im16(CPUM68KState *env, DisasContext *s)
406 {
407 uint16_t im;
408 im = translator_lduw(env, &s->base, s->pc);
409 s->pc += 2;
410 return im;
411 }
412
413 /* Read an 8-bit immediate constant */
414 static inline uint8_t read_im8(CPUM68KState *env, DisasContext *s)
415 {
416 return read_im16(env, s);
417 }
418
419 /* Read a 32-bit immediate constant. */
420 static inline uint32_t read_im32(CPUM68KState *env, DisasContext *s)
421 {
422 uint32_t im;
423 im = read_im16(env, s) << 16;
424 im |= 0xffff & read_im16(env, s);
425 return im;
426 }
427
428 /* Read a 64-bit immediate constant. */
429 static inline uint64_t read_im64(CPUM68KState *env, DisasContext *s)
430 {
431 uint64_t im;
432 im = (uint64_t)read_im32(env, s) << 32;
433 im |= (uint64_t)read_im32(env, s);
434 return im;
435 }
436
437 /* Calculate and address index. */
438 static TCGv gen_addr_index(DisasContext *s, uint16_t ext, TCGv tmp)
439 {
440 TCGv add;
441 int scale;
442
443 add = (ext & 0x8000) ? AREG(ext, 12) : DREG(ext, 12);
444 if ((ext & 0x800) == 0) {
445 tcg_gen_ext16s_i32(tmp, add);
446 add = tmp;
447 }
448 scale = (ext >> 9) & 3;
449 if (scale != 0) {
450 tcg_gen_shli_i32(tmp, add, scale);
451 add = tmp;
452 }
453 return add;
454 }
455
456 /*
457 * Handle a base + index + displacement effective address.
458 * A NULL_QREG base means pc-relative.
459 */
460 static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base)
461 {
462 uint32_t offset;
463 uint16_t ext;
464 TCGv add;
465 TCGv tmp;
466 uint32_t bd, od;
467
468 offset = s->pc;
469 ext = read_im16(env, s);
470
471 if ((ext & 0x800) == 0 && !m68k_feature(s->env, M68K_FEATURE_WORD_INDEX))
472 return NULL_QREG;
473
474 if (m68k_feature(s->env, M68K_FEATURE_M68K) &&
475 !m68k_feature(s->env, M68K_FEATURE_SCALED_INDEX)) {
476 ext &= ~(3 << 9);
477 }
478
479 if (ext & 0x100) {
480 /* full extension word format */
481 if (!m68k_feature(s->env, M68K_FEATURE_EXT_FULL))
482 return NULL_QREG;
483
484 if ((ext & 0x30) > 0x10) {
485 /* base displacement */
486 if ((ext & 0x30) == 0x20) {
487 bd = (int16_t)read_im16(env, s);
488 } else {
489 bd = read_im32(env, s);
490 }
491 } else {
492 bd = 0;
493 }
494 tmp = mark_to_release(s, tcg_temp_new());
495 if ((ext & 0x44) == 0) {
496 /* pre-index */
497 add = gen_addr_index(s, ext, tmp);
498 } else {
499 add = NULL_QREG;
500 }
501 if ((ext & 0x80) == 0) {
502 /* base not suppressed */
503 if (IS_NULL_QREG(base)) {
504 base = mark_to_release(s, tcg_const_i32(offset + bd));
505 bd = 0;
506 }
507 if (!IS_NULL_QREG(add)) {
508 tcg_gen_add_i32(tmp, add, base);
509 add = tmp;
510 } else {
511 add = base;
512 }
513 }
514 if (!IS_NULL_QREG(add)) {
515 if (bd != 0) {
516 tcg_gen_addi_i32(tmp, add, bd);
517 add = tmp;
518 }
519 } else {
520 add = mark_to_release(s, tcg_const_i32(bd));
521 }
522 if ((ext & 3) != 0) {
523 /* memory indirect */
524 base = mark_to_release(s, gen_load(s, OS_LONG, add, 0, IS_USER(s)));
525 if ((ext & 0x44) == 4) {
526 add = gen_addr_index(s, ext, tmp);
527 tcg_gen_add_i32(tmp, add, base);
528 add = tmp;
529 } else {
530 add = base;
531 }
532 if ((ext & 3) > 1) {
533 /* outer displacement */
534 if ((ext & 3) == 2) {
535 od = (int16_t)read_im16(env, s);
536 } else {
537 od = read_im32(env, s);
538 }
539 } else {
540 od = 0;
541 }
542 if (od != 0) {
543 tcg_gen_addi_i32(tmp, add, od);
544 add = tmp;
545 }
546 }
547 } else {
548 /* brief extension word format */
549 tmp = mark_to_release(s, tcg_temp_new());
550 add = gen_addr_index(s, ext, tmp);
551 if (!IS_NULL_QREG(base)) {
552 tcg_gen_add_i32(tmp, add, base);
553 if ((int8_t)ext)
554 tcg_gen_addi_i32(tmp, tmp, (int8_t)ext);
555 } else {
556 tcg_gen_addi_i32(tmp, add, offset + (int8_t)ext);
557 }
558 add = tmp;
559 }
560 return add;
561 }
562
563 /* Sign or zero extend a value. */
564
565 static inline void gen_ext(TCGv res, TCGv val, int opsize, int sign)
566 {
567 switch (opsize) {
568 case OS_BYTE:
569 if (sign) {
570 tcg_gen_ext8s_i32(res, val);
571 } else {
572 tcg_gen_ext8u_i32(res, val);
573 }
574 break;
575 case OS_WORD:
576 if (sign) {
577 tcg_gen_ext16s_i32(res, val);
578 } else {
579 tcg_gen_ext16u_i32(res, val);
580 }
581 break;
582 case OS_LONG:
583 tcg_gen_mov_i32(res, val);
584 break;
585 default:
586 g_assert_not_reached();
587 }
588 }
589
590 /* Evaluate all the CC flags. */
591
592 static void gen_flush_flags(DisasContext *s)
593 {
594 TCGv t0, t1;
595
596 switch (s->cc_op) {
597 case CC_OP_FLAGS:
598 return;
599
600 case CC_OP_ADDB:
601 case CC_OP_ADDW:
602 case CC_OP_ADDL:
603 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
604 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
605 /* Compute signed overflow for addition. */
606 t0 = tcg_temp_new();
607 t1 = tcg_temp_new();
608 tcg_gen_sub_i32(t0, QREG_CC_N, QREG_CC_V);
609 gen_ext(t0, t0, s->cc_op - CC_OP_ADDB, 1);
610 tcg_gen_xor_i32(t1, QREG_CC_N, QREG_CC_V);
611 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, t0);
612 tcg_temp_free(t0);
613 tcg_gen_andc_i32(QREG_CC_V, t1, QREG_CC_V);
614 tcg_temp_free(t1);
615 break;
616
617 case CC_OP_SUBB:
618 case CC_OP_SUBW:
619 case CC_OP_SUBL:
620 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
621 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
622 /* Compute signed overflow for subtraction. */
623 t0 = tcg_temp_new();
624 t1 = tcg_temp_new();
625 tcg_gen_add_i32(t0, QREG_CC_N, QREG_CC_V);
626 gen_ext(t0, t0, s->cc_op - CC_OP_SUBB, 1);
627 tcg_gen_xor_i32(t1, QREG_CC_N, t0);
628 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, t0);
629 tcg_temp_free(t0);
630 tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, t1);
631 tcg_temp_free(t1);
632 break;
633
634 case CC_OP_CMPB:
635 case CC_OP_CMPW:
636 case CC_OP_CMPL:
637 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_C, QREG_CC_N, QREG_CC_V);
638 tcg_gen_sub_i32(QREG_CC_Z, QREG_CC_N, QREG_CC_V);
639 gen_ext(QREG_CC_Z, QREG_CC_Z, s->cc_op - CC_OP_CMPB, 1);
640 /* Compute signed overflow for subtraction. */
641 t0 = tcg_temp_new();
642 tcg_gen_xor_i32(t0, QREG_CC_Z, QREG_CC_N);
643 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, QREG_CC_N);
644 tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, t0);
645 tcg_temp_free(t0);
646 tcg_gen_mov_i32(QREG_CC_N, QREG_CC_Z);
647 break;
648
649 case CC_OP_LOGIC:
650 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
651 tcg_gen_movi_i32(QREG_CC_C, 0);
652 tcg_gen_movi_i32(QREG_CC_V, 0);
653 break;
654
655 case CC_OP_DYNAMIC:
656 gen_helper_flush_flags(cpu_env, QREG_CC_OP);
657 s->cc_op_synced = 1;
658 break;
659
660 default:
661 t0 = tcg_const_i32(s->cc_op);
662 gen_helper_flush_flags(cpu_env, t0);
663 tcg_temp_free(t0);
664 s->cc_op_synced = 1;
665 break;
666 }
667
668 /* Note that flush_flags also assigned to env->cc_op. */
669 s->cc_op = CC_OP_FLAGS;
670 }
671
672 static inline TCGv gen_extend(DisasContext *s, TCGv val, int opsize, int sign)
673 {
674 TCGv tmp;
675
676 if (opsize == OS_LONG) {
677 tmp = val;
678 } else {
679 tmp = mark_to_release(s, tcg_temp_new());
680 gen_ext(tmp, val, opsize, sign);
681 }
682
683 return tmp;
684 }
685
686 static void gen_logic_cc(DisasContext *s, TCGv val, int opsize)
687 {
688 gen_ext(QREG_CC_N, val, opsize, 1);
689 set_cc_op(s, CC_OP_LOGIC);
690 }
691
692 static void gen_update_cc_cmp(DisasContext *s, TCGv dest, TCGv src, int opsize)
693 {
694 tcg_gen_mov_i32(QREG_CC_N, dest);
695 tcg_gen_mov_i32(QREG_CC_V, src);
696 set_cc_op(s, CC_OP_CMPB + opsize);
697 }
698
699 static void gen_update_cc_add(TCGv dest, TCGv src, int opsize)
700 {
701 gen_ext(QREG_CC_N, dest, opsize, 1);
702 tcg_gen_mov_i32(QREG_CC_V, src);
703 }
704
705 static inline int opsize_bytes(int opsize)
706 {
707 switch (opsize) {
708 case OS_BYTE: return 1;
709 case OS_WORD: return 2;
710 case OS_LONG: return 4;
711 case OS_SINGLE: return 4;
712 case OS_DOUBLE: return 8;
713 case OS_EXTENDED: return 12;
714 case OS_PACKED: return 12;
715 default:
716 g_assert_not_reached();
717 }
718 }
719
720 static inline int insn_opsize(int insn)
721 {
722 switch ((insn >> 6) & 3) {
723 case 0: return OS_BYTE;
724 case 1: return OS_WORD;
725 case 2: return OS_LONG;
726 default:
727 g_assert_not_reached();
728 }
729 }
730
731 static inline int ext_opsize(int ext, int pos)
732 {
733 switch ((ext >> pos) & 7) {
734 case 0: return OS_LONG;
735 case 1: return OS_SINGLE;
736 case 2: return OS_EXTENDED;
737 case 3: return OS_PACKED;
738 case 4: return OS_WORD;
739 case 5: return OS_DOUBLE;
740 case 6: return OS_BYTE;
741 default:
742 g_assert_not_reached();
743 }
744 }
745
746 /*
747 * Assign value to a register. If the width is less than the register width
748 * only the low part of the register is set.
749 */
750 static void gen_partset_reg(int opsize, TCGv reg, TCGv val)
751 {
752 TCGv tmp;
753 switch (opsize) {
754 case OS_BYTE:
755 tcg_gen_andi_i32(reg, reg, 0xffffff00);
756 tmp = tcg_temp_new();
757 tcg_gen_ext8u_i32(tmp, val);
758 tcg_gen_or_i32(reg, reg, tmp);
759 tcg_temp_free(tmp);
760 break;
761 case OS_WORD:
762 tcg_gen_andi_i32(reg, reg, 0xffff0000);
763 tmp = tcg_temp_new();
764 tcg_gen_ext16u_i32(tmp, val);
765 tcg_gen_or_i32(reg, reg, tmp);
766 tcg_temp_free(tmp);
767 break;
768 case OS_LONG:
769 case OS_SINGLE:
770 tcg_gen_mov_i32(reg, val);
771 break;
772 default:
773 g_assert_not_reached();
774 }
775 }
776
777 /*
778 * Generate code for an "effective address". Does not adjust the base
779 * register for autoincrement addressing modes.
780 */
781 static TCGv gen_lea_mode(CPUM68KState *env, DisasContext *s,
782 int mode, int reg0, int opsize)
783 {
784 TCGv reg;
785 TCGv tmp;
786 uint16_t ext;
787 uint32_t offset;
788
789 switch (mode) {
790 case 0: /* Data register direct. */
791 case 1: /* Address register direct. */
792 return NULL_QREG;
793 case 3: /* Indirect postincrement. */
794 if (opsize == OS_UNSIZED) {
795 return NULL_QREG;
796 }
797 /* fallthru */
798 case 2: /* Indirect register */
799 return get_areg(s, reg0);
800 case 4: /* Indirect predecrememnt. */
801 if (opsize == OS_UNSIZED) {
802 return NULL_QREG;
803 }
804 reg = get_areg(s, reg0);
805 tmp = mark_to_release(s, tcg_temp_new());
806 if (reg0 == 7 && opsize == OS_BYTE &&
807 m68k_feature(s->env, M68K_FEATURE_M68K)) {
808 tcg_gen_subi_i32(tmp, reg, 2);
809 } else {
810 tcg_gen_subi_i32(tmp, reg, opsize_bytes(opsize));
811 }
812 return tmp;
813 case 5: /* Indirect displacement. */
814 reg = get_areg(s, reg0);
815 tmp = mark_to_release(s, tcg_temp_new());
816 ext = read_im16(env, s);
817 tcg_gen_addi_i32(tmp, reg, (int16_t)ext);
818 return tmp;
819 case 6: /* Indirect index + displacement. */
820 reg = get_areg(s, reg0);
821 return gen_lea_indexed(env, s, reg);
822 case 7: /* Other */
823 switch (reg0) {
824 case 0: /* Absolute short. */
825 offset = (int16_t)read_im16(env, s);
826 return mark_to_release(s, tcg_const_i32(offset));
827 case 1: /* Absolute long. */
828 offset = read_im32(env, s);
829 return mark_to_release(s, tcg_const_i32(offset));
830 case 2: /* pc displacement */
831 offset = s->pc;
832 offset += (int16_t)read_im16(env, s);
833 return mark_to_release(s, tcg_const_i32(offset));
834 case 3: /* pc index+displacement. */
835 return gen_lea_indexed(env, s, NULL_QREG);
836 case 4: /* Immediate. */
837 default:
838 return NULL_QREG;
839 }
840 }
841 /* Should never happen. */
842 return NULL_QREG;
843 }
844
845 static TCGv gen_lea(CPUM68KState *env, DisasContext *s, uint16_t insn,
846 int opsize)
847 {
848 int mode = extract32(insn, 3, 3);
849 int reg0 = REG(insn, 0);
850 return gen_lea_mode(env, s, mode, reg0, opsize);
851 }
852
853 /*
854 * Generate code to load/store a value from/into an EA. If WHAT > 0 this is
855 * a write otherwise it is a read (0 == sign extend, -1 == zero extend).
856 * ADDRP is non-null for readwrite operands.
857 */
858 static TCGv gen_ea_mode(CPUM68KState *env, DisasContext *s, int mode, int reg0,
859 int opsize, TCGv val, TCGv *addrp, ea_what what,
860 int index)
861 {
862 TCGv reg, tmp, result;
863 int32_t offset;
864
865 switch (mode) {
866 case 0: /* Data register direct. */
867 reg = cpu_dregs[reg0];
868 if (what == EA_STORE) {
869 gen_partset_reg(opsize, reg, val);
870 return store_dummy;
871 } else {
872 return gen_extend(s, reg, opsize, what == EA_LOADS);
873 }
874 case 1: /* Address register direct. */
875 reg = get_areg(s, reg0);
876 if (what == EA_STORE) {
877 tcg_gen_mov_i32(reg, val);
878 return store_dummy;
879 } else {
880 return gen_extend(s, reg, opsize, what == EA_LOADS);
881 }
882 case 2: /* Indirect register */
883 reg = get_areg(s, reg0);
884 return gen_ldst(s, opsize, reg, val, what, index);
885 case 3: /* Indirect postincrement. */
886 reg = get_areg(s, reg0);
887 result = gen_ldst(s, opsize, reg, val, what, index);
888 if (what == EA_STORE || !addrp) {
889 TCGv tmp = tcg_temp_new();
890 if (reg0 == 7 && opsize == OS_BYTE &&
891 m68k_feature(s->env, M68K_FEATURE_M68K)) {
892 tcg_gen_addi_i32(tmp, reg, 2);
893 } else {
894 tcg_gen_addi_i32(tmp, reg, opsize_bytes(opsize));
895 }
896 delay_set_areg(s, reg0, tmp, true);
897 }
898 return result;
899 case 4: /* Indirect predecrememnt. */
900 if (addrp && what == EA_STORE) {
901 tmp = *addrp;
902 } else {
903 tmp = gen_lea_mode(env, s, mode, reg0, opsize);
904 if (IS_NULL_QREG(tmp)) {
905 return tmp;
906 }
907 if (addrp) {
908 *addrp = tmp;
909 }
910 }
911 result = gen_ldst(s, opsize, tmp, val, what, index);
912 if (what == EA_STORE || !addrp) {
913 delay_set_areg(s, reg0, tmp, false);
914 }
915 return result;
916 case 5: /* Indirect displacement. */
917 case 6: /* Indirect index + displacement. */
918 do_indirect:
919 if (addrp && what == EA_STORE) {
920 tmp = *addrp;
921 } else {
922 tmp = gen_lea_mode(env, s, mode, reg0, opsize);
923 if (IS_NULL_QREG(tmp)) {
924 return tmp;
925 }
926 if (addrp) {
927 *addrp = tmp;
928 }
929 }
930 return gen_ldst(s, opsize, tmp, val, what, index);
931 case 7: /* Other */
932 switch (reg0) {
933 case 0: /* Absolute short. */
934 case 1: /* Absolute long. */
935 case 2: /* pc displacement */
936 case 3: /* pc index+displacement. */
937 goto do_indirect;
938 case 4: /* Immediate. */
939 /* Sign extend values for consistency. */
940 switch (opsize) {
941 case OS_BYTE:
942 if (what == EA_LOADS) {
943 offset = (int8_t)read_im8(env, s);
944 } else {
945 offset = read_im8(env, s);
946 }
947 break;
948 case OS_WORD:
949 if (what == EA_LOADS) {
950 offset = (int16_t)read_im16(env, s);
951 } else {
952 offset = read_im16(env, s);
953 }
954 break;
955 case OS_LONG:
956 offset = read_im32(env, s);
957 break;
958 default:
959 g_assert_not_reached();
960 }
961 return mark_to_release(s, tcg_const_i32(offset));
962 default:
963 return NULL_QREG;
964 }
965 }
966 /* Should never happen. */
967 return NULL_QREG;
968 }
969
970 static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn,
971 int opsize, TCGv val, TCGv *addrp, ea_what what, int index)
972 {
973 int mode = extract32(insn, 3, 3);
974 int reg0 = REG(insn, 0);
975 return gen_ea_mode(env, s, mode, reg0, opsize, val, addrp, what, index);
976 }
977
978 static TCGv_ptr gen_fp_ptr(int freg)
979 {
980 TCGv_ptr fp = tcg_temp_new_ptr();
981 tcg_gen_addi_ptr(fp, cpu_env, offsetof(CPUM68KState, fregs[freg]));
982 return fp;
983 }
984
985 static TCGv_ptr gen_fp_result_ptr(void)
986 {
987 TCGv_ptr fp = tcg_temp_new_ptr();
988 tcg_gen_addi_ptr(fp, cpu_env, offsetof(CPUM68KState, fp_result));
989 return fp;
990 }
991
992 static void gen_fp_move(TCGv_ptr dest, TCGv_ptr src)
993 {
994 TCGv t32;
995 TCGv_i64 t64;
996
997 t32 = tcg_temp_new();
998 tcg_gen_ld16u_i32(t32, src, offsetof(FPReg, l.upper));
999 tcg_gen_st16_i32(t32, dest, offsetof(FPReg, l.upper));
1000 tcg_temp_free(t32);
1001
1002 t64 = tcg_temp_new_i64();
1003 tcg_gen_ld_i64(t64, src, offsetof(FPReg, l.lower));
1004 tcg_gen_st_i64(t64, dest, offsetof(FPReg, l.lower));
1005 tcg_temp_free_i64(t64);
1006 }
1007
1008 static void gen_load_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp,
1009 int index)
1010 {
1011 TCGv tmp;
1012 TCGv_i64 t64;
1013
1014 t64 = tcg_temp_new_i64();
1015 tmp = tcg_temp_new();
1016 switch (opsize) {
1017 case OS_BYTE:
1018 tcg_gen_qemu_ld8s(tmp, addr, index);
1019 gen_helper_exts32(cpu_env, fp, tmp);
1020 break;
1021 case OS_WORD:
1022 tcg_gen_qemu_ld16s(tmp, addr, index);
1023 gen_helper_exts32(cpu_env, fp, tmp);
1024 break;
1025 case OS_LONG:
1026 tcg_gen_qemu_ld32u(tmp, addr, index);
1027 gen_helper_exts32(cpu_env, fp, tmp);
1028 break;
1029 case OS_SINGLE:
1030 tcg_gen_qemu_ld32u(tmp, addr, index);
1031 gen_helper_extf32(cpu_env, fp, tmp);
1032 break;
1033 case OS_DOUBLE:
1034 tcg_gen_qemu_ld64(t64, addr, index);
1035 gen_helper_extf64(cpu_env, fp, t64);
1036 break;
1037 case OS_EXTENDED:
1038 if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) {
1039 gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP);
1040 break;
1041 }
1042 tcg_gen_qemu_ld32u(tmp, addr, index);
1043 tcg_gen_shri_i32(tmp, tmp, 16);
1044 tcg_gen_st16_i32(tmp, fp, offsetof(FPReg, l.upper));
1045 tcg_gen_addi_i32(tmp, addr, 4);
1046 tcg_gen_qemu_ld64(t64, tmp, index);
1047 tcg_gen_st_i64(t64, fp, offsetof(FPReg, l.lower));
1048 break;
1049 case OS_PACKED:
1050 /*
1051 * unimplemented data type on 68040/ColdFire
1052 * FIXME if needed for another FPU
1053 */
1054 gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP);
1055 break;
1056 default:
1057 g_assert_not_reached();
1058 }
1059 tcg_temp_free(tmp);
1060 tcg_temp_free_i64(t64);
1061 }
1062
1063 static void gen_store_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp,
1064 int index)
1065 {
1066 TCGv tmp;
1067 TCGv_i64 t64;
1068
1069 t64 = tcg_temp_new_i64();
1070 tmp = tcg_temp_new();
1071 switch (opsize) {
1072 case OS_BYTE:
1073 gen_helper_reds32(tmp, cpu_env, fp);
1074 tcg_gen_qemu_st8(tmp, addr, index);
1075 break;
1076 case OS_WORD:
1077 gen_helper_reds32(tmp, cpu_env, fp);
1078 tcg_gen_qemu_st16(tmp, addr, index);
1079 break;
1080 case OS_LONG:
1081 gen_helper_reds32(tmp, cpu_env, fp);
1082 tcg_gen_qemu_st32(tmp, addr, index);
1083 break;
1084 case OS_SINGLE:
1085 gen_helper_redf32(tmp, cpu_env, fp);
1086 tcg_gen_qemu_st32(tmp, addr, index);
1087 break;
1088 case OS_DOUBLE:
1089 gen_helper_redf64(t64, cpu_env, fp);
1090 tcg_gen_qemu_st64(t64, addr, index);
1091 break;
1092 case OS_EXTENDED:
1093 if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) {
1094 gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP);
1095 break;
1096 }
1097 tcg_gen_ld16u_i32(tmp, fp, offsetof(FPReg, l.upper));
1098 tcg_gen_shli_i32(tmp, tmp, 16);
1099 tcg_gen_qemu_st32(tmp, addr, index);
1100 tcg_gen_addi_i32(tmp, addr, 4);
1101 tcg_gen_ld_i64(t64, fp, offsetof(FPReg, l.lower));
1102 tcg_gen_qemu_st64(t64, tmp, index);
1103 break;
1104 case OS_PACKED:
1105 /*
1106 * unimplemented data type on 68040/ColdFire
1107 * FIXME if needed for another FPU
1108 */
1109 gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP);
1110 break;
1111 default:
1112 g_assert_not_reached();
1113 }
1114 tcg_temp_free(tmp);
1115 tcg_temp_free_i64(t64);
1116 }
1117
1118 static void gen_ldst_fp(DisasContext *s, int opsize, TCGv addr,
1119 TCGv_ptr fp, ea_what what, int index)
1120 {
1121 if (what == EA_STORE) {
1122 gen_store_fp(s, opsize, addr, fp, index);
1123 } else {
1124 gen_load_fp(s, opsize, addr, fp, index);
1125 }
1126 }
1127
1128 static int gen_ea_mode_fp(CPUM68KState *env, DisasContext *s, int mode,
1129 int reg0, int opsize, TCGv_ptr fp, ea_what what,
1130 int index)
1131 {
1132 TCGv reg, addr, tmp;
1133 TCGv_i64 t64;
1134
1135 switch (mode) {
1136 case 0: /* Data register direct. */
1137 reg = cpu_dregs[reg0];
1138 if (what == EA_STORE) {
1139 switch (opsize) {
1140 case OS_BYTE:
1141 case OS_WORD:
1142 case OS_LONG:
1143 gen_helper_reds32(reg, cpu_env, fp);
1144 break;
1145 case OS_SINGLE:
1146 gen_helper_redf32(reg, cpu_env, fp);
1147 break;
1148 default:
1149 g_assert_not_reached();
1150 }
1151 } else {
1152 tmp = tcg_temp_new();
1153 switch (opsize) {
1154 case OS_BYTE:
1155 tcg_gen_ext8s_i32(tmp, reg);
1156 gen_helper_exts32(cpu_env, fp, tmp);
1157 break;
1158 case OS_WORD:
1159 tcg_gen_ext16s_i32(tmp, reg);
1160 gen_helper_exts32(cpu_env, fp, tmp);
1161 break;
1162 case OS_LONG:
1163 gen_helper_exts32(cpu_env, fp, reg);
1164 break;
1165 case OS_SINGLE:
1166 gen_helper_extf32(cpu_env, fp, reg);
1167 break;
1168 default:
1169 g_assert_not_reached();
1170 }
1171 tcg_temp_free(tmp);
1172 }
1173 return 0;
1174 case 1: /* Address register direct. */
1175 return -1;
1176 case 2: /* Indirect register */
1177 addr = get_areg(s, reg0);
1178 gen_ldst_fp(s, opsize, addr, fp, what, index);
1179 return 0;
1180 case 3: /* Indirect postincrement. */
1181 addr = cpu_aregs[reg0];
1182 gen_ldst_fp(s, opsize, addr, fp, what, index);
1183 tcg_gen_addi_i32(addr, addr, opsize_bytes(opsize));
1184 return 0;
1185 case 4: /* Indirect predecrememnt. */
1186 addr = gen_lea_mode(env, s, mode, reg0, opsize);
1187 if (IS_NULL_QREG(addr)) {
1188 return -1;
1189 }
1190 gen_ldst_fp(s, opsize, addr, fp, what, index);
1191 tcg_gen_mov_i32(cpu_aregs[reg0], addr);
1192 return 0;
1193 case 5: /* Indirect displacement. */
1194 case 6: /* Indirect index + displacement. */
1195 do_indirect:
1196 addr = gen_lea_mode(env, s, mode, reg0, opsize);
1197 if (IS_NULL_QREG(addr)) {
1198 return -1;
1199 }
1200 gen_ldst_fp(s, opsize, addr, fp, what, index);
1201 return 0;
1202 case 7: /* Other */
1203 switch (reg0) {
1204 case 0: /* Absolute short. */
1205 case 1: /* Absolute long. */
1206 case 2: /* pc displacement */
1207 case 3: /* pc index+displacement. */
1208 goto do_indirect;
1209 case 4: /* Immediate. */
1210 if (what == EA_STORE) {
1211 return -1;
1212 }
1213 switch (opsize) {
1214 case OS_BYTE:
1215 tmp = tcg_const_i32((int8_t)read_im8(env, s));
1216 gen_helper_exts32(cpu_env, fp, tmp);
1217 tcg_temp_free(tmp);
1218 break;
1219 case OS_WORD:
1220 tmp = tcg_const_i32((int16_t)read_im16(env, s));
1221 gen_helper_exts32(cpu_env, fp, tmp);
1222 tcg_temp_free(tmp);
1223 break;
1224 case OS_LONG:
1225 tmp = tcg_const_i32(read_im32(env, s));
1226 gen_helper_exts32(cpu_env, fp, tmp);
1227 tcg_temp_free(tmp);
1228 break;
1229 case OS_SINGLE:
1230 tmp = tcg_const_i32(read_im32(env, s));
1231 gen_helper_extf32(cpu_env, fp, tmp);
1232 tcg_temp_free(tmp);
1233 break;
1234 case OS_DOUBLE:
1235 t64 = tcg_const_i64(read_im64(env, s));
1236 gen_helper_extf64(cpu_env, fp, t64);
1237 tcg_temp_free_i64(t64);
1238 break;
1239 case OS_EXTENDED:
1240 if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) {
1241 gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP);
1242 break;
1243 }
1244 tmp = tcg_const_i32(read_im32(env, s) >> 16);
1245 tcg_gen_st16_i32(tmp, fp, offsetof(FPReg, l.upper));
1246 tcg_temp_free(tmp);
1247 t64 = tcg_const_i64(read_im64(env, s));
1248 tcg_gen_st_i64(t64, fp, offsetof(FPReg, l.lower));
1249 tcg_temp_free_i64(t64);
1250 break;
1251 case OS_PACKED:
1252 /*
1253 * unimplemented data type on 68040/ColdFire
1254 * FIXME if needed for another FPU
1255 */
1256 gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP);
1257 break;
1258 default:
1259 g_assert_not_reached();
1260 }
1261 return 0;
1262 default:
1263 return -1;
1264 }
1265 }
1266 return -1;
1267 }
1268
1269 static int gen_ea_fp(CPUM68KState *env, DisasContext *s, uint16_t insn,
1270 int opsize, TCGv_ptr fp, ea_what what, int index)
1271 {
1272 int mode = extract32(insn, 3, 3);
1273 int reg0 = REG(insn, 0);
1274 return gen_ea_mode_fp(env, s, mode, reg0, opsize, fp, what, index);
1275 }
1276
1277 typedef struct {
1278 TCGCond tcond;
1279 bool g1;
1280 bool g2;
1281 TCGv v1;
1282 TCGv v2;
1283 } DisasCompare;
1284
1285 static void gen_cc_cond(DisasCompare *c, DisasContext *s, int cond)
1286 {
1287 TCGv tmp, tmp2;
1288 TCGCond tcond;
1289 CCOp op = s->cc_op;
1290
1291 /* The CC_OP_CMP form can handle most normal comparisons directly. */
1292 if (op == CC_OP_CMPB || op == CC_OP_CMPW || op == CC_OP_CMPL) {
1293 c->g1 = c->g2 = 1;
1294 c->v1 = QREG_CC_N;
1295 c->v2 = QREG_CC_V;
1296 switch (cond) {
1297 case 2: /* HI */
1298 case 3: /* LS */
1299 tcond = TCG_COND_LEU;
1300 goto done;
1301 case 4: /* CC */
1302 case 5: /* CS */
1303 tcond = TCG_COND_LTU;
1304 goto done;
1305 case 6: /* NE */
1306 case 7: /* EQ */
1307 tcond = TCG_COND_EQ;
1308 goto done;
1309 case 10: /* PL */
1310 case 11: /* MI */
1311 c->g1 = c->g2 = 0;
1312 c->v2 = tcg_const_i32(0);
1313 c->v1 = tmp = tcg_temp_new();
1314 tcg_gen_sub_i32(tmp, QREG_CC_N, QREG_CC_V);
1315 gen_ext(tmp, tmp, op - CC_OP_CMPB, 1);
1316 /* fallthru */
1317 case 12: /* GE */
1318 case 13: /* LT */
1319 tcond = TCG_COND_LT;
1320 goto done;
1321 case 14: /* GT */
1322 case 15: /* LE */
1323 tcond = TCG_COND_LE;
1324 goto done;
1325 }
1326 }
1327
1328 c->g1 = 1;
1329 c->g2 = 0;
1330 c->v2 = tcg_const_i32(0);
1331
1332 switch (cond) {
1333 case 0: /* T */
1334 case 1: /* F */
1335 c->v1 = c->v2;
1336 tcond = TCG_COND_NEVER;
1337 goto done;
1338 case 14: /* GT (!(Z || (N ^ V))) */
1339 case 15: /* LE (Z || (N ^ V)) */
1340 /*
1341 * Logic operations clear V, which simplifies LE to (Z || N),
1342 * and since Z and N are co-located, this becomes a normal
1343 * comparison vs N.
1344 */
1345 if (op == CC_OP_LOGIC) {
1346 c->v1 = QREG_CC_N;
1347 tcond = TCG_COND_LE;
1348 goto done;
1349 }
1350 break;
1351 case 12: /* GE (!(N ^ V)) */
1352 case 13: /* LT (N ^ V) */
1353 /* Logic operations clear V, which simplifies this to N. */
1354 if (op != CC_OP_LOGIC) {
1355 break;
1356 }
1357 /* fallthru */
1358 case 10: /* PL (!N) */
1359 case 11: /* MI (N) */
1360 /* Several cases represent N normally. */
1361 if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL ||
1362 op == CC_OP_SUBB || op == CC_OP_SUBW || op == CC_OP_SUBL ||
1363 op == CC_OP_LOGIC) {
1364 c->v1 = QREG_CC_N;
1365 tcond = TCG_COND_LT;
1366 goto done;
1367 }
1368 break;
1369 case 6: /* NE (!Z) */
1370 case 7: /* EQ (Z) */
1371 /* Some cases fold Z into N. */
1372 if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL ||
1373 op == CC_OP_SUBB || op == CC_OP_SUBW || op == CC_OP_SUBL ||
1374 op == CC_OP_LOGIC) {
1375 tcond = TCG_COND_EQ;
1376 c->v1 = QREG_CC_N;
1377 goto done;
1378 }
1379 break;
1380 case 4: /* CC (!C) */
1381 case 5: /* CS (C) */
1382 /* Some cases fold C into X. */
1383 if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL ||
1384 op == CC_OP_SUBB || op == CC_OP_SUBW || op == CC_OP_SUBL) {
1385 tcond = TCG_COND_NE;
1386 c->v1 = QREG_CC_X;
1387 goto done;
1388 }
1389 /* fallthru */
1390 case 8: /* VC (!V) */
1391 case 9: /* VS (V) */
1392 /* Logic operations clear V and C. */
1393 if (op == CC_OP_LOGIC) {
1394 tcond = TCG_COND_NEVER;
1395 c->v1 = c->v2;
1396 goto done;
1397 }
1398 break;
1399 }
1400
1401 /* Otherwise, flush flag state to CC_OP_FLAGS. */
1402 gen_flush_flags(s);
1403
1404 switch (cond) {
1405 case 0: /* T */
1406 case 1: /* F */
1407 default:
1408 /* Invalid, or handled above. */
1409 abort();
1410 case 2: /* HI (!C && !Z) -> !(C || Z)*/
1411 case 3: /* LS (C || Z) */
1412 c->v1 = tmp = tcg_temp_new();
1413 c->g1 = 0;
1414 tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2);
1415 tcg_gen_or_i32(tmp, tmp, QREG_CC_C);
1416 tcond = TCG_COND_NE;
1417 break;
1418 case 4: /* CC (!C) */
1419 case 5: /* CS (C) */
1420 c->v1 = QREG_CC_C;
1421 tcond = TCG_COND_NE;
1422 break;
1423 case 6: /* NE (!Z) */
1424 case 7: /* EQ (Z) */
1425 c->v1 = QREG_CC_Z;
1426 tcond = TCG_COND_EQ;
1427 break;
1428 case 8: /* VC (!V) */
1429 case 9: /* VS (V) */
1430 c->v1 = QREG_CC_V;
1431 tcond = TCG_COND_LT;
1432 break;
1433 case 10: /* PL (!N) */
1434 case 11: /* MI (N) */
1435 c->v1 = QREG_CC_N;
1436 tcond = TCG_COND_LT;
1437 break;
1438 case 12: /* GE (!(N ^ V)) */
1439 case 13: /* LT (N ^ V) */
1440 c->v1 = tmp = tcg_temp_new();
1441 c->g1 = 0;
1442 tcg_gen_xor_i32(tmp, QREG_CC_N, QREG_CC_V);
1443 tcond = TCG_COND_LT;
1444 break;
1445 case 14: /* GT (!(Z || (N ^ V))) */
1446 case 15: /* LE (Z || (N ^ V)) */
1447 c->v1 = tmp = tcg_temp_new();
1448 c->g1 = 0;
1449 tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2);
1450 tcg_gen_neg_i32(tmp, tmp);
1451 tmp2 = tcg_temp_new();
1452 tcg_gen_xor_i32(tmp2, QREG_CC_N, QREG_CC_V);
1453 tcg_gen_or_i32(tmp, tmp, tmp2);
1454 tcg_temp_free(tmp2);
1455 tcond = TCG_COND_LT;
1456 break;
1457 }
1458
1459 done:
1460 if ((cond & 1) == 0) {
1461 tcond = tcg_invert_cond(tcond);
1462 }
1463 c->tcond = tcond;
1464 }
1465
1466 static void free_cond(DisasCompare *c)
1467 {
1468 if (!c->g1) {
1469 tcg_temp_free(c->v1);
1470 }
1471 if (!c->g2) {
1472 tcg_temp_free(c->v2);
1473 }
1474 }
1475
1476 static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1)
1477 {
1478 DisasCompare c;
1479
1480 gen_cc_cond(&c, s, cond);
1481 update_cc_op(s);
1482 tcg_gen_brcond_i32(c.tcond, c.v1, c.v2, l1);
1483 free_cond(&c);
1484 }
1485
1486 /* Force a TB lookup after an instruction that changes the CPU state. */
1487 static void gen_exit_tb(DisasContext *s)
1488 {
1489 update_cc_op(s);
1490 tcg_gen_movi_i32(QREG_PC, s->pc);
1491 s->base.is_jmp = DISAS_EXIT;
1492 }
1493
1494 #define SRC_EA(env, result, opsize, op_sign, addrp) do { \
1495 result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \
1496 op_sign ? EA_LOADS : EA_LOADU, IS_USER(s)); \
1497 if (IS_NULL_QREG(result)) { \
1498 gen_addr_fault(s); \
1499 return; \
1500 } \
1501 } while (0)
1502
1503 #define DEST_EA(env, insn, opsize, val, addrp) do { \
1504 TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, \
1505 EA_STORE, IS_USER(s)); \
1506 if (IS_NULL_QREG(ea_result)) { \
1507 gen_addr_fault(s); \
1508 return; \
1509 } \
1510 } while (0)
1511
1512 /* Generate a jump to an immediate address. */
1513 static void gen_jmp_tb(DisasContext *s, int n, target_ulong dest,
1514 target_ulong src)
1515 {
1516 if (unlikely(s->ss_active)) {
1517 update_cc_op(s);
1518 tcg_gen_movi_i32(QREG_PC, dest);
1519 gen_raise_exception_format2(s, EXCP_TRACE, src);
1520 } else if (translator_use_goto_tb(&s->base, dest)) {
1521 tcg_gen_goto_tb(n);
1522 tcg_gen_movi_i32(QREG_PC, dest);
1523 tcg_gen_exit_tb(s->base.tb, n);
1524 } else {
1525 gen_jmp_im(s, dest);
1526 tcg_gen_exit_tb(NULL, 0);
1527 }
1528 s->base.is_jmp = DISAS_NORETURN;
1529 }
1530
1531 DISAS_INSN(scc)
1532 {
1533 DisasCompare c;
1534 int cond;
1535 TCGv tmp;
1536
1537 cond = (insn >> 8) & 0xf;
1538 gen_cc_cond(&c, s, cond);
1539
1540 tmp = tcg_temp_new();
1541 tcg_gen_setcond_i32(c.tcond, tmp, c.v1, c.v2);
1542 free_cond(&c);
1543
1544 tcg_gen_neg_i32(tmp, tmp);
1545 DEST_EA(env, insn, OS_BYTE, tmp, NULL);
1546 tcg_temp_free(tmp);
1547 }
1548
1549 DISAS_INSN(dbcc)
1550 {
1551 TCGLabel *l1;
1552 TCGv reg;
1553 TCGv tmp;
1554 int16_t offset;
1555 uint32_t base;
1556
1557 reg = DREG(insn, 0);
1558 base = s->pc;
1559 offset = (int16_t)read_im16(env, s);
1560 l1 = gen_new_label();
1561 gen_jmpcc(s, (insn >> 8) & 0xf, l1);
1562
1563 tmp = tcg_temp_new();
1564 tcg_gen_ext16s_i32(tmp, reg);
1565 tcg_gen_addi_i32(tmp, tmp, -1);
1566 gen_partset_reg(OS_WORD, reg, tmp);
1567 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, -1, l1);
1568 gen_jmp_tb(s, 1, base + offset, s->base.pc_next);
1569 gen_set_label(l1);
1570 gen_jmp_tb(s, 0, s->pc, s->base.pc_next);
1571 }
1572
1573 DISAS_INSN(undef_mac)
1574 {
1575 gen_exception(s, s->base.pc_next, EXCP_LINEA);
1576 }
1577
1578 DISAS_INSN(undef_fpu)
1579 {
1580 gen_exception(s, s->base.pc_next, EXCP_LINEF);
1581 }
1582
1583 DISAS_INSN(undef)
1584 {
1585 /*
1586 * ??? This is both instructions that are as yet unimplemented
1587 * for the 680x0 series, as well as those that are implemented
1588 * but actually illegal for CPU32 or pre-68020.
1589 */
1590 qemu_log_mask(LOG_UNIMP, "Illegal instruction: %04x @ %08x\n",
1591 insn, s->base.pc_next);
1592 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
1593 }
1594
1595 DISAS_INSN(mulw)
1596 {
1597 TCGv reg;
1598 TCGv tmp;
1599 TCGv src;
1600 int sign;
1601
1602 sign = (insn & 0x100) != 0;
1603 reg = DREG(insn, 9);
1604 tmp = tcg_temp_new();
1605 if (sign)
1606 tcg_gen_ext16s_i32(tmp, reg);
1607 else
1608 tcg_gen_ext16u_i32(tmp, reg);
1609 SRC_EA(env, src, OS_WORD, sign, NULL);
1610 tcg_gen_mul_i32(tmp, tmp, src);
1611 tcg_gen_mov_i32(reg, tmp);
1612 gen_logic_cc(s, tmp, OS_LONG);
1613 tcg_temp_free(tmp);
1614 }
1615
1616 DISAS_INSN(divw)
1617 {
1618 int sign;
1619 TCGv src;
1620 TCGv destr;
1621 TCGv ilen;
1622
1623 /* divX.w <EA>,Dn 32/16 -> 16r:16q */
1624
1625 sign = (insn & 0x100) != 0;
1626
1627 /* dest.l / src.w */
1628
1629 SRC_EA(env, src, OS_WORD, sign, NULL);
1630 destr = tcg_constant_i32(REG(insn, 9));
1631 ilen = tcg_constant_i32(s->pc - s->base.pc_next);
1632 if (sign) {
1633 gen_helper_divsw(cpu_env, destr, src, ilen);
1634 } else {
1635 gen_helper_divuw(cpu_env, destr, src, ilen);
1636 }
1637
1638 set_cc_op(s, CC_OP_FLAGS);
1639 }
1640
1641 DISAS_INSN(divl)
1642 {
1643 TCGv num, reg, den, ilen;
1644 int sign;
1645 uint16_t ext;
1646
1647 ext = read_im16(env, s);
1648
1649 sign = (ext & 0x0800) != 0;
1650
1651 if (ext & 0x400) {
1652 if (!m68k_feature(s->env, M68K_FEATURE_QUAD_MULDIV)) {
1653 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
1654 return;
1655 }
1656
1657 /* divX.l <EA>, Dr:Dq 64/32 -> 32r:32q */
1658
1659 SRC_EA(env, den, OS_LONG, 0, NULL);
1660 num = tcg_constant_i32(REG(ext, 12));
1661 reg = tcg_constant_i32(REG(ext, 0));
1662 ilen = tcg_constant_i32(s->pc - s->base.pc_next);
1663 if (sign) {
1664 gen_helper_divsll(cpu_env, num, reg, den, ilen);
1665 } else {
1666 gen_helper_divull(cpu_env, num, reg, den, ilen);
1667 }
1668 set_cc_op(s, CC_OP_FLAGS);
1669 return;
1670 }
1671
1672 /* divX.l <EA>, Dq 32/32 -> 32q */
1673 /* divXl.l <EA>, Dr:Dq 32/32 -> 32r:32q */
1674
1675 SRC_EA(env, den, OS_LONG, 0, NULL);
1676 num = tcg_constant_i32(REG(ext, 12));
1677 reg = tcg_constant_i32(REG(ext, 0));
1678 ilen = tcg_constant_i32(s->pc - s->base.pc_next);
1679 if (sign) {
1680 gen_helper_divsl(cpu_env, num, reg, den, ilen);
1681 } else {
1682 gen_helper_divul(cpu_env, num, reg, den, ilen);
1683 }
1684
1685 set_cc_op(s, CC_OP_FLAGS);
1686 }
1687
1688 static void bcd_add(TCGv dest, TCGv src)
1689 {
1690 TCGv t0, t1;
1691
1692 /*
1693 * dest10 = dest10 + src10 + X
1694 *
1695 * t1 = src
1696 * t2 = t1 + 0x066
1697 * t3 = t2 + dest + X
1698 * t4 = t2 ^ dest
1699 * t5 = t3 ^ t4
1700 * t6 = ~t5 & 0x110
1701 * t7 = (t6 >> 2) | (t6 >> 3)
1702 * return t3 - t7
1703 */
1704
1705 /*
1706 * t1 = (src + 0x066) + dest + X
1707 * = result with some possible exceeding 0x6
1708 */
1709
1710 t0 = tcg_const_i32(0x066);
1711 tcg_gen_add_i32(t0, t0, src);
1712
1713 t1 = tcg_temp_new();
1714 tcg_gen_add_i32(t1, t0, dest);
1715 tcg_gen_add_i32(t1, t1, QREG_CC_X);
1716
1717 /* we will remove exceeding 0x6 where there is no carry */
1718
1719 /*
1720 * t0 = (src + 0x0066) ^ dest
1721 * = t1 without carries
1722 */
1723
1724 tcg_gen_xor_i32(t0, t0, dest);
1725
1726 /*
1727 * extract the carries
1728 * t0 = t0 ^ t1
1729 * = only the carries
1730 */
1731
1732 tcg_gen_xor_i32(t0, t0, t1);
1733
1734 /*
1735 * generate 0x1 where there is no carry
1736 * and for each 0x10, generate a 0x6
1737 */
1738
1739 tcg_gen_shri_i32(t0, t0, 3);
1740 tcg_gen_not_i32(t0, t0);
1741 tcg_gen_andi_i32(t0, t0, 0x22);
1742 tcg_gen_add_i32(dest, t0, t0);
1743 tcg_gen_add_i32(dest, dest, t0);
1744 tcg_temp_free(t0);
1745
1746 /*
1747 * remove the exceeding 0x6
1748 * for digits that have not generated a carry
1749 */
1750
1751 tcg_gen_sub_i32(dest, t1, dest);
1752 tcg_temp_free(t1);
1753 }
1754
1755 static void bcd_sub(TCGv dest, TCGv src)
1756 {
1757 TCGv t0, t1, t2;
1758
1759 /*
1760 * dest10 = dest10 - src10 - X
1761 * = bcd_add(dest + 1 - X, 0x199 - src)
1762 */
1763
1764 /* t0 = 0x066 + (0x199 - src) */
1765
1766 t0 = tcg_temp_new();
1767 tcg_gen_subfi_i32(t0, 0x1ff, src);
1768
1769 /* t1 = t0 + dest + 1 - X*/
1770
1771 t1 = tcg_temp_new();
1772 tcg_gen_add_i32(t1, t0, dest);
1773 tcg_gen_addi_i32(t1, t1, 1);
1774 tcg_gen_sub_i32(t1, t1, QREG_CC_X);
1775
1776 /* t2 = t0 ^ dest */
1777
1778 t2 = tcg_temp_new();
1779 tcg_gen_xor_i32(t2, t0, dest);
1780
1781 /* t0 = t1 ^ t2 */
1782
1783 tcg_gen_xor_i32(t0, t1, t2);
1784
1785 /*
1786 * t2 = ~t0 & 0x110
1787 * t0 = (t2 >> 2) | (t2 >> 3)
1788 *
1789 * to fit on 8bit operands, changed in:
1790 *
1791 * t2 = ~(t0 >> 3) & 0x22
1792 * t0 = t2 + t2
1793 * t0 = t0 + t2
1794 */
1795
1796 tcg_gen_shri_i32(t2, t0, 3);
1797 tcg_gen_not_i32(t2, t2);
1798 tcg_gen_andi_i32(t2, t2, 0x22);
1799 tcg_gen_add_i32(t0, t2, t2);
1800 tcg_gen_add_i32(t0, t0, t2);
1801 tcg_temp_free(t2);
1802
1803 /* return t1 - t0 */
1804
1805 tcg_gen_sub_i32(dest, t1, t0);
1806 tcg_temp_free(t0);
1807 tcg_temp_free(t1);
1808 }
1809
1810 static void bcd_flags(TCGv val)
1811 {
1812 tcg_gen_andi_i32(QREG_CC_C, val, 0x0ff);
1813 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_C);
1814
1815 tcg_gen_extract_i32(QREG_CC_C, val, 8, 1);
1816
1817 tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C);
1818 }
1819
1820 DISAS_INSN(abcd_reg)
1821 {
1822 TCGv src;
1823 TCGv dest;
1824
1825 gen_flush_flags(s); /* !Z is sticky */
1826
1827 src = gen_extend(s, DREG(insn, 0), OS_BYTE, 0);
1828 dest = gen_extend(s, DREG(insn, 9), OS_BYTE, 0);
1829 bcd_add(dest, src);
1830 gen_partset_reg(OS_BYTE, DREG(insn, 9), dest);
1831
1832 bcd_flags(dest);
1833 }
1834
1835 DISAS_INSN(abcd_mem)
1836 {
1837 TCGv src, dest, addr;
1838
1839 gen_flush_flags(s); /* !Z is sticky */
1840
1841 /* Indirect pre-decrement load (mode 4) */
1842
1843 src = gen_ea_mode(env, s, 4, REG(insn, 0), OS_BYTE,
1844 NULL_QREG, NULL, EA_LOADU, IS_USER(s));
1845 dest = gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE,
1846 NULL_QREG, &addr, EA_LOADU, IS_USER(s));
1847
1848 bcd_add(dest, src);
1849
1850 gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, dest, &addr,
1851 EA_STORE, IS_USER(s));
1852
1853 bcd_flags(dest);
1854 }
1855
1856 DISAS_INSN(sbcd_reg)
1857 {
1858 TCGv src, dest;
1859
1860 gen_flush_flags(s); /* !Z is sticky */
1861
1862 src = gen_extend(s, DREG(insn, 0), OS_BYTE, 0);
1863 dest = gen_extend(s, DREG(insn, 9), OS_BYTE, 0);
1864
1865 bcd_sub(dest, src);
1866
1867 gen_partset_reg(OS_BYTE, DREG(insn, 9), dest);
1868
1869 bcd_flags(dest);
1870 }
1871
1872 DISAS_INSN(sbcd_mem)
1873 {
1874 TCGv src, dest, addr;
1875
1876 gen_flush_flags(s); /* !Z is sticky */
1877
1878 /* Indirect pre-decrement load (mode 4) */
1879
1880 src = gen_ea_mode(env, s, 4, REG(insn, 0), OS_BYTE,
1881 NULL_QREG, NULL, EA_LOADU, IS_USER(s));
1882 dest = gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE,
1883 NULL_QREG, &addr, EA_LOADU, IS_USER(s));
1884
1885 bcd_sub(dest, src);
1886
1887 gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, dest, &addr,
1888 EA_STORE, IS_USER(s));
1889
1890 bcd_flags(dest);
1891 }
1892
1893 DISAS_INSN(nbcd)
1894 {
1895 TCGv src, dest;
1896 TCGv addr;
1897
1898 gen_flush_flags(s); /* !Z is sticky */
1899
1900 SRC_EA(env, src, OS_BYTE, 0, &addr);
1901
1902 dest = tcg_const_i32(0);
1903 bcd_sub(dest, src);
1904
1905 DEST_EA(env, insn, OS_BYTE, dest, &addr);
1906
1907 bcd_flags(dest);
1908
1909 tcg_temp_free(dest);
1910 }
1911
1912 DISAS_INSN(addsub)
1913 {
1914 TCGv reg;
1915 TCGv dest;
1916 TCGv src;
1917 TCGv tmp;
1918 TCGv addr;
1919 int add;
1920 int opsize;
1921
1922 add = (insn & 0x4000) != 0;
1923 opsize = insn_opsize(insn);
1924 reg = gen_extend(s, DREG(insn, 9), opsize, 1);
1925 dest = tcg_temp_new();
1926 if (insn & 0x100) {
1927 SRC_EA(env, tmp, opsize, 1, &addr);
1928 src = reg;
1929 } else {
1930 tmp = reg;
1931 SRC_EA(env, src, opsize, 1, NULL);
1932 }
1933 if (add) {
1934 tcg_gen_add_i32(dest, tmp, src);
1935 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, src);
1936 set_cc_op(s, CC_OP_ADDB + opsize);
1937 } else {
1938 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, tmp, src);
1939 tcg_gen_sub_i32(dest, tmp, src);
1940 set_cc_op(s, CC_OP_SUBB + opsize);
1941 }
1942 gen_update_cc_add(dest, src, opsize);
1943 if (insn & 0x100) {
1944 DEST_EA(env, insn, opsize, dest, &addr);
1945 } else {
1946 gen_partset_reg(opsize, DREG(insn, 9), dest);
1947 }
1948 tcg_temp_free(dest);
1949 }
1950
1951 /* Reverse the order of the bits in REG. */
1952 DISAS_INSN(bitrev)
1953 {
1954 TCGv reg;
1955 reg = DREG(insn, 0);
1956 gen_helper_bitrev(reg, reg);
1957 }
1958
1959 DISAS_INSN(bitop_reg)
1960 {
1961 int opsize;
1962 int op;
1963 TCGv src1;
1964 TCGv src2;
1965 TCGv tmp;
1966 TCGv addr;
1967 TCGv dest;
1968
1969 if ((insn & 0x38) != 0)
1970 opsize = OS_BYTE;
1971 else
1972 opsize = OS_LONG;
1973 op = (insn >> 6) & 3;
1974 SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
1975
1976 gen_flush_flags(s);
1977 src2 = tcg_temp_new();
1978 if (opsize == OS_BYTE)
1979 tcg_gen_andi_i32(src2, DREG(insn, 9), 7);
1980 else
1981 tcg_gen_andi_i32(src2, DREG(insn, 9), 31);
1982
1983 tmp = tcg_const_i32(1);
1984 tcg_gen_shl_i32(tmp, tmp, src2);
1985 tcg_temp_free(src2);
1986
1987 tcg_gen_and_i32(QREG_CC_Z, src1, tmp);
1988
1989 dest = tcg_temp_new();
1990 switch (op) {
1991 case 1: /* bchg */
1992 tcg_gen_xor_i32(dest, src1, tmp);
1993 break;
1994 case 2: /* bclr */
1995 tcg_gen_andc_i32(dest, src1, tmp);
1996 break;
1997 case 3: /* bset */
1998 tcg_gen_or_i32(dest, src1, tmp);
1999 break;
2000 default: /* btst */
2001 break;
2002 }
2003 tcg_temp_free(tmp);
2004 if (op) {
2005 DEST_EA(env, insn, opsize, dest, &addr);
2006 }
2007 tcg_temp_free(dest);
2008 }
2009
2010 DISAS_INSN(sats)
2011 {
2012 TCGv reg;
2013 reg = DREG(insn, 0);
2014 gen_flush_flags(s);
2015 gen_helper_sats(reg, reg, QREG_CC_V);
2016 gen_logic_cc(s, reg, OS_LONG);
2017 }
2018
2019 static void gen_push(DisasContext *s, TCGv val)
2020 {
2021 TCGv tmp;
2022
2023 tmp = tcg_temp_new();
2024 tcg_gen_subi_i32(tmp, QREG_SP, 4);
2025 gen_store(s, OS_LONG, tmp, val, IS_USER(s));
2026 tcg_gen_mov_i32(QREG_SP, tmp);
2027 tcg_temp_free(tmp);
2028 }
2029
2030 static TCGv mreg(int reg)
2031 {
2032 if (reg < 8) {
2033 /* Dx */
2034 return cpu_dregs[reg];
2035 }
2036 /* Ax */
2037 return cpu_aregs[reg & 7];
2038 }
2039
2040 DISAS_INSN(movem)
2041 {
2042 TCGv addr, incr, tmp, r[16];
2043 int is_load = (insn & 0x0400) != 0;
2044 int opsize = (insn & 0x40) != 0 ? OS_LONG : OS_WORD;
2045 uint16_t mask = read_im16(env, s);
2046 int mode = extract32(insn, 3, 3);
2047 int reg0 = REG(insn, 0);
2048 int i;
2049
2050 tmp = cpu_aregs[reg0];
2051
2052 switch (mode) {
2053 case 0: /* data register direct */
2054 case 1: /* addr register direct */
2055 do_addr_fault:
2056 gen_addr_fault(s);
2057 return;
2058
2059 case 2: /* indirect */
2060 break;
2061
2062 case 3: /* indirect post-increment */
2063 if (!is_load) {
2064 /* post-increment is not allowed */
2065 goto do_addr_fault;
2066 }
2067 break;
2068
2069 case 4: /* indirect pre-decrement */
2070 if (is_load) {
2071 /* pre-decrement is not allowed */
2072 goto do_addr_fault;
2073 }
2074 /*
2075 * We want a bare copy of the address reg, without any pre-decrement
2076 * adjustment, as gen_lea would provide.
2077 */
2078 break;
2079
2080 default:
2081 tmp = gen_lea_mode(env, s, mode, reg0, opsize);
2082 if (IS_NULL_QREG(tmp)) {
2083 goto do_addr_fault;
2084 }
2085 break;
2086 }
2087
2088 addr = tcg_temp_new();
2089 tcg_gen_mov_i32(addr, tmp);
2090 incr = tcg_const_i32(opsize_bytes(opsize));
2091
2092 if (is_load) {
2093 /* memory to register */
2094 for (i = 0; i < 16; i++) {
2095 if (mask & (1 << i)) {
2096 r[i] = gen_load(s, opsize, addr, 1, IS_USER(s));
2097 tcg_gen_add_i32(addr, addr, incr);
2098 }
2099 }
2100 for (i = 0; i < 16; i++) {
2101 if (mask & (1 << i)) {
2102 tcg_gen_mov_i32(mreg(i), r[i]);
2103 tcg_temp_free(r[i]);
2104 }
2105 }
2106 if (mode == 3) {
2107 /* post-increment: movem (An)+,X */
2108 tcg_gen_mov_i32(cpu_aregs[reg0], addr);
2109 }
2110 } else {
2111 /* register to memory */
2112 if (mode == 4) {
2113 /* pre-decrement: movem X,-(An) */
2114 for (i = 15; i >= 0; i--) {
2115 if ((mask << i) & 0x8000) {
2116 tcg_gen_sub_i32(addr, addr, incr);
2117 if (reg0 + 8 == i &&
2118 m68k_feature(s->env, M68K_FEATURE_EXT_FULL)) {
2119 /*
2120 * M68020+: if the addressing register is the
2121 * register moved to memory, the value written
2122 * is the initial value decremented by the size of
2123 * the operation, regardless of how many actual
2124 * stores have been performed until this point.
2125 * M68000/M68010: the value is the initial value.
2126 */
2127 tmp = tcg_temp_new();
2128 tcg_gen_sub_i32(tmp, cpu_aregs[reg0], incr);
2129 gen_store(s, opsize, addr, tmp, IS_USER(s));
2130 tcg_temp_free(tmp);
2131 } else {
2132 gen_store(s, opsize, addr, mreg(i), IS_USER(s));
2133 }
2134 }
2135 }
2136 tcg_gen_mov_i32(cpu_aregs[reg0], addr);
2137 } else {
2138 for (i = 0; i < 16; i++) {
2139 if (mask & (1 << i)) {
2140 gen_store(s, opsize, addr, mreg(i), IS_USER(s));
2141 tcg_gen_add_i32(addr, addr, incr);
2142 }
2143 }
2144 }
2145 }
2146
2147 tcg_temp_free(incr);
2148 tcg_temp_free(addr);
2149 }
2150
2151 DISAS_INSN(movep)
2152 {
2153 uint8_t i;
2154 int16_t displ;
2155 TCGv reg;
2156 TCGv addr;
2157 TCGv abuf;
2158 TCGv dbuf;
2159
2160 displ = read_im16(env, s);
2161
2162 addr = AREG(insn, 0);
2163 reg = DREG(insn, 9);
2164
2165 abuf = tcg_temp_new();
2166 tcg_gen_addi_i32(abuf, addr, displ);
2167 dbuf = tcg_temp_new();
2168
2169 if (insn & 0x40) {
2170 i = 4;
2171 } else {
2172 i = 2;
2173 }
2174
2175 if (insn & 0x80) {
2176 for ( ; i > 0 ; i--) {
2177 tcg_gen_shri_i32(dbuf, reg, (i - 1) * 8);
2178 tcg_gen_qemu_st8(dbuf, abuf, IS_USER(s));
2179 if (i > 1) {
2180 tcg_gen_addi_i32(abuf, abuf, 2);
2181 }
2182 }
2183 } else {
2184 for ( ; i > 0 ; i--) {
2185 tcg_gen_qemu_ld8u(dbuf, abuf, IS_USER(s));
2186 tcg_gen_deposit_i32(reg, reg, dbuf, (i - 1) * 8, 8);
2187 if (i > 1) {
2188 tcg_gen_addi_i32(abuf, abuf, 2);
2189 }
2190 }
2191 }
2192 tcg_temp_free(abuf);
2193 tcg_temp_free(dbuf);
2194 }
2195
2196 DISAS_INSN(bitop_im)
2197 {
2198 int opsize;
2199 int op;
2200 TCGv src1;
2201 uint32_t mask;
2202 int bitnum;
2203 TCGv tmp;
2204 TCGv addr;
2205
2206 if ((insn & 0x38) != 0)
2207 opsize = OS_BYTE;
2208 else
2209 opsize = OS_LONG;
2210 op = (insn >> 6) & 3;
2211
2212 bitnum = read_im16(env, s);
2213 if (m68k_feature(s->env, M68K_FEATURE_M68K)) {
2214 if (bitnum & 0xfe00) {
2215 disas_undef(env, s, insn);
2216 return;
2217 }
2218 } else {
2219 if (bitnum & 0xff00) {
2220 disas_undef(env, s, insn);
2221 return;
2222 }
2223 }
2224
2225 SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
2226
2227 gen_flush_flags(s);
2228 if (opsize == OS_BYTE)
2229 bitnum &= 7;
2230 else
2231 bitnum &= 31;
2232 mask = 1 << bitnum;
2233
2234 tcg_gen_andi_i32(QREG_CC_Z, src1, mask);
2235
2236 if (op) {
2237 tmp = tcg_temp_new();
2238 switch (op) {
2239 case 1: /* bchg */
2240 tcg_gen_xori_i32(tmp, src1, mask);
2241 break;
2242 case 2: /* bclr */
2243 tcg_gen_andi_i32(tmp, src1, ~mask);
2244 break;
2245 case 3: /* bset */
2246 tcg_gen_ori_i32(tmp, src1, mask);
2247 break;
2248 default: /* btst */
2249 break;
2250 }
2251 DEST_EA(env, insn, opsize, tmp, &addr);
2252 tcg_temp_free(tmp);
2253 }
2254 }
2255
2256 static TCGv gen_get_ccr(DisasContext *s)
2257 {
2258 TCGv dest;
2259
2260 update_cc_op(s);
2261 dest = tcg_temp_new();
2262 gen_helper_get_ccr(dest, cpu_env);
2263 return dest;
2264 }
2265
2266 static TCGv gen_get_sr(DisasContext *s)
2267 {
2268 TCGv ccr;
2269 TCGv sr;
2270
2271 ccr = gen_get_ccr(s);
2272 sr = tcg_temp_new();
2273 tcg_gen_andi_i32(sr, QREG_SR, 0xffe0);
2274 tcg_gen_or_i32(sr, sr, ccr);
2275 tcg_temp_free(ccr);
2276 return sr;
2277 }
2278
2279 static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only)
2280 {
2281 if (ccr_only) {
2282 tcg_gen_movi_i32(QREG_CC_C, val & CCF_C ? 1 : 0);
2283 tcg_gen_movi_i32(QREG_CC_V, val & CCF_V ? -1 : 0);
2284 tcg_gen_movi_i32(QREG_CC_Z, val & CCF_Z ? 0 : 1);
2285 tcg_gen_movi_i32(QREG_CC_N, val & CCF_N ? -1 : 0);
2286 tcg_gen_movi_i32(QREG_CC_X, val & CCF_X ? 1 : 0);
2287 } else {
2288 /* Must writeback before changing security state. */
2289 do_writebacks(s);
2290 gen_helper_set_sr(cpu_env, tcg_constant_i32(val));
2291 }
2292 set_cc_op(s, CC_OP_FLAGS);
2293 }
2294
2295 static void gen_set_sr(DisasContext *s, TCGv val, int ccr_only)
2296 {
2297 if (ccr_only) {
2298 gen_helper_set_ccr(cpu_env, val);
2299 } else {
2300 /* Must writeback before changing security state. */
2301 do_writebacks(s);
2302 gen_helper_set_sr(cpu_env, val);
2303 }
2304 set_cc_op(s, CC_OP_FLAGS);
2305 }
2306
2307 static void gen_move_to_sr(CPUM68KState *env, DisasContext *s, uint16_t insn,
2308 bool ccr_only)
2309 {
2310 if ((insn & 0x3f) == 0x3c) {
2311 uint16_t val;
2312 val = read_im16(env, s);
2313 gen_set_sr_im(s, val, ccr_only);
2314 } else {
2315 TCGv src;
2316 SRC_EA(env, src, OS_WORD, 0, NULL);
2317 gen_set_sr(s, src, ccr_only);
2318 }
2319 }
2320
2321 DISAS_INSN(arith_im)
2322 {
2323 int op;
2324 TCGv im;
2325 TCGv src1;
2326 TCGv dest;
2327 TCGv addr;
2328 int opsize;
2329 bool with_SR = ((insn & 0x3f) == 0x3c);
2330
2331 op = (insn >> 9) & 7;
2332 opsize = insn_opsize(insn);
2333 switch (opsize) {
2334 case OS_BYTE:
2335 im = tcg_const_i32((int8_t)read_im8(env, s));
2336 break;
2337 case OS_WORD:
2338 im = tcg_const_i32((int16_t)read_im16(env, s));
2339 break;
2340 case OS_LONG:
2341 im = tcg_const_i32(read_im32(env, s));
2342 break;
2343 default:
2344 g_assert_not_reached();
2345 }
2346
2347 if (with_SR) {
2348 /* SR/CCR can only be used with andi/eori/ori */
2349 if (op == 2 || op == 3 || op == 6) {
2350 disas_undef(env, s, insn);
2351 return;
2352 }
2353 switch (opsize) {
2354 case OS_BYTE:
2355 src1 = gen_get_ccr(s);
2356 break;
2357 case OS_WORD:
2358 if (IS_USER(s)) {
2359 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
2360 return;
2361 }
2362 src1 = gen_get_sr(s);
2363 break;
2364 default:
2365 /* OS_LONG; others already g_assert_not_reached. */
2366 disas_undef(env, s, insn);
2367 return;
2368 }
2369 } else {
2370 SRC_EA(env, src1, opsize, 1, (op == 6) ? NULL : &addr);
2371 }
2372 dest = tcg_temp_new();
2373 switch (op) {
2374 case 0: /* ori */
2375 tcg_gen_or_i32(dest, src1, im);
2376 if (with_SR) {
2377 gen_set_sr(s, dest, opsize == OS_BYTE);
2378 } else {
2379 DEST_EA(env, insn, opsize, dest, &addr);
2380 gen_logic_cc(s, dest, opsize);
2381 }
2382 break;
2383 case 1: /* andi */
2384 tcg_gen_and_i32(dest, src1, im);
2385 if (with_SR) {
2386 gen_set_sr(s, dest, opsize == OS_BYTE);
2387 } else {
2388 DEST_EA(env, insn, opsize, dest, &addr);
2389 gen_logic_cc(s, dest, opsize);
2390 }
2391 break;
2392 case 2: /* subi */
2393 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, src1, im);
2394 tcg_gen_sub_i32(dest, src1, im);
2395 gen_update_cc_add(dest, im, opsize);
2396 set_cc_op(s, CC_OP_SUBB + opsize);
2397 DEST_EA(env, insn, opsize, dest, &addr);
2398 break;
2399 case 3: /* addi */
2400 tcg_gen_add_i32(dest, src1, im);
2401 gen_update_cc_add(dest, im, opsize);
2402 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, im);
2403 set_cc_op(s, CC_OP_ADDB + opsize);
2404 DEST_EA(env, insn, opsize, dest, &addr);
2405 break;
2406 case 5: /* eori */
2407 tcg_gen_xor_i32(dest, src1, im);
2408 if (with_SR) {
2409 gen_set_sr(s, dest, opsize == OS_BYTE);
2410 } else {
2411 DEST_EA(env, insn, opsize, dest, &addr);
2412 gen_logic_cc(s, dest, opsize);
2413 }
2414 break;
2415 case 6: /* cmpi */
2416 gen_update_cc_cmp(s, src1, im, opsize);
2417 break;
2418 default:
2419 abort();
2420 }
2421 tcg_temp_free(im);
2422 tcg_temp_free(dest);
2423 }
2424
2425 DISAS_INSN(cas)
2426 {
2427 int opsize;
2428 TCGv addr;
2429 uint16_t ext;
2430 TCGv load;
2431 TCGv cmp;
2432 MemOp opc;
2433
2434 switch ((insn >> 9) & 3) {
2435 case 1:
2436 opsize = OS_BYTE;
2437 opc = MO_SB;
2438 break;
2439 case 2:
2440 opsize = OS_WORD;
2441 opc = MO_TESW;
2442 break;
2443 case 3:
2444 opsize = OS_LONG;
2445 opc = MO_TESL;
2446 break;
2447 default:
2448 g_assert_not_reached();
2449 }
2450
2451 ext = read_im16(env, s);
2452
2453 /* cas Dc,Du,<EA> */
2454
2455 addr = gen_lea(env, s, insn, opsize);
2456 if (IS_NULL_QREG(addr)) {
2457 gen_addr_fault(s);
2458 return;
2459 }
2460
2461 cmp = gen_extend(s, DREG(ext, 0), opsize, 1);
2462
2463 /*
2464 * if <EA> == Dc then
2465 * <EA> = Du
2466 * Dc = <EA> (because <EA> == Dc)
2467 * else
2468 * Dc = <EA>
2469 */
2470
2471 load = tcg_temp_new();
2472 tcg_gen_atomic_cmpxchg_i32(load, addr, cmp, DREG(ext, 6),
2473 IS_USER(s), opc);
2474 /* update flags before setting cmp to load */
2475 gen_update_cc_cmp(s, load, cmp, opsize);
2476 gen_partset_reg(opsize, DREG(ext, 0), load);
2477
2478 tcg_temp_free(load);
2479
2480 switch (extract32(insn, 3, 3)) {
2481 case 3: /* Indirect postincrement. */
2482 tcg_gen_addi_i32(AREG(insn, 0), addr, opsize_bytes(opsize));
2483 break;
2484 case 4: /* Indirect predecrememnt. */
2485 tcg_gen_mov_i32(AREG(insn, 0), addr);
2486 break;
2487 }
2488 }
2489
2490 DISAS_INSN(cas2w)
2491 {
2492 uint16_t ext1, ext2;
2493 TCGv addr1, addr2;
2494 TCGv regs;
2495
2496 /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */
2497
2498 ext1 = read_im16(env, s);
2499
2500 if (ext1 & 0x8000) {
2501 /* Address Register */
2502 addr1 = AREG(ext1, 12);
2503 } else {
2504 /* Data Register */
2505 addr1 = DREG(ext1, 12);
2506 }
2507
2508 ext2 = read_im16(env, s);
2509 if (ext2 & 0x8000) {
2510 /* Address Register */
2511 addr2 = AREG(ext2, 12);
2512 } else {
2513 /* Data Register */
2514 addr2 = DREG(ext2, 12);
2515 }
2516
2517 /*
2518 * if (R1) == Dc1 && (R2) == Dc2 then
2519 * (R1) = Du1
2520 * (R2) = Du2
2521 * else
2522 * Dc1 = (R1)
2523 * Dc2 = (R2)
2524 */
2525
2526 regs = tcg_const_i32(REG(ext2, 6) |
2527 (REG(ext1, 6) << 3) |
2528 (REG(ext2, 0) << 6) |
2529 (REG(ext1, 0) << 9));
2530 if (tb_cflags(s->base.tb) & CF_PARALLEL) {
2531 gen_helper_exit_atomic(cpu_env);
2532 } else {
2533 gen_helper_cas2w(cpu_env, regs, addr1, addr2);
2534 }
2535 tcg_temp_free(regs);
2536
2537 /* Note that cas2w also assigned to env->cc_op. */
2538 s->cc_op = CC_OP_CMPW;
2539 s->cc_op_synced = 1;
2540 }
2541
2542 DISAS_INSN(cas2l)
2543 {
2544 uint16_t ext1, ext2;
2545 TCGv addr1, addr2, regs;
2546
2547 /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */
2548
2549 ext1 = read_im16(env, s);
2550
2551 if (ext1 & 0x8000) {
2552 /* Address Register */
2553 addr1 = AREG(ext1, 12);
2554 } else {
2555 /* Data Register */
2556 addr1 = DREG(ext1, 12);
2557 }
2558
2559 ext2 = read_im16(env, s);
2560 if (ext2 & 0x8000) {
2561 /* Address Register */
2562 addr2 = AREG(ext2, 12);
2563 } else {
2564 /* Data Register */
2565 addr2 = DREG(ext2, 12);
2566 }
2567
2568 /*
2569 * if (R1) == Dc1 && (R2) == Dc2 then
2570 * (R1) = Du1
2571 * (R2) = Du2
2572 * else
2573 * Dc1 = (R1)
2574 * Dc2 = (R2)
2575 */
2576
2577 regs = tcg_const_i32(REG(ext2, 6) |
2578 (REG(ext1, 6) << 3) |
2579 (REG(ext2, 0) << 6) |
2580 (REG(ext1, 0) << 9));
2581 if (tb_cflags(s->base.tb) & CF_PARALLEL) {
2582 gen_helper_cas2l_parallel(cpu_env, regs, addr1, addr2);
2583 } else {
2584 gen_helper_cas2l(cpu_env, regs, addr1, addr2);
2585 }
2586 tcg_temp_free(regs);
2587
2588 /* Note that cas2l also assigned to env->cc_op. */
2589 s->cc_op = CC_OP_CMPL;
2590 s->cc_op_synced = 1;
2591 }
2592
2593 DISAS_INSN(byterev)
2594 {
2595 TCGv reg;
2596
2597 reg = DREG(insn, 0);
2598 tcg_gen_bswap32_i32(reg, reg);
2599 }
2600
2601 DISAS_INSN(move)
2602 {
2603 TCGv src;
2604 TCGv dest;
2605 int op;
2606 int opsize;
2607
2608 switch (insn >> 12) {
2609 case 1: /* move.b */
2610 opsize = OS_BYTE;
2611 break;
2612 case 2: /* move.l */
2613 opsize = OS_LONG;
2614 break;
2615 case 3: /* move.w */
2616 opsize = OS_WORD;
2617 break;
2618 default:
2619 abort();
2620 }
2621 SRC_EA(env, src, opsize, 1, NULL);
2622 op = (insn >> 6) & 7;
2623 if (op == 1) {
2624 /* movea */
2625 /* The value will already have been sign extended. */
2626 dest = AREG(insn, 9);
2627 tcg_gen_mov_i32(dest, src);
2628 } else {
2629 /* normal move */
2630 uint16_t dest_ea;
2631 dest_ea = ((insn >> 9) & 7) | (op << 3);
2632 DEST_EA(env, dest_ea, opsize, src, NULL);
2633 /* This will be correct because loads sign extend. */
2634 gen_logic_cc(s, src, opsize);
2635 }
2636 }
2637
2638 DISAS_INSN(negx)
2639 {
2640 TCGv z;
2641 TCGv src;
2642 TCGv addr;
2643 int opsize;
2644
2645 opsize = insn_opsize(insn);
2646 SRC_EA(env, src, opsize, 1, &addr);
2647
2648 gen_flush_flags(s); /* compute old Z */
2649
2650 /*
2651 * Perform subtract with borrow.
2652 * (X, N) = -(src + X);
2653 */
2654
2655 z = tcg_const_i32(0);
2656 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, src, z, QREG_CC_X, z);
2657 tcg_gen_sub2_i32(QREG_CC_N, QREG_CC_X, z, z, QREG_CC_N, QREG_CC_X);
2658 tcg_temp_free(z);
2659 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
2660
2661 tcg_gen_andi_i32(QREG_CC_X, QREG_CC_X, 1);
2662
2663 /*
2664 * Compute signed-overflow for negation. The normal formula for
2665 * subtraction is (res ^ src) & (src ^ dest), but with dest==0
2666 * this simplifies to res & src.
2667 */
2668
2669 tcg_gen_and_i32(QREG_CC_V, QREG_CC_N, src);
2670
2671 /* Copy the rest of the results into place. */
2672 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */
2673 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
2674
2675 set_cc_op(s, CC_OP_FLAGS);
2676
2677 /* result is in QREG_CC_N */
2678
2679 DEST_EA(env, insn, opsize, QREG_CC_N, &addr);
2680 }
2681
2682 DISAS_INSN(lea)
2683 {
2684 TCGv reg;
2685 TCGv tmp;
2686
2687 reg = AREG(insn, 9);
2688 tmp = gen_lea(env, s, insn, OS_LONG);
2689 if (IS_NULL_QREG(tmp)) {
2690 gen_addr_fault(s);
2691 return;
2692 }
2693 tcg_gen_mov_i32(reg, tmp);
2694 }
2695
2696 DISAS_INSN(clr)
2697 {
2698 int opsize;
2699 TCGv zero;
2700
2701 zero = tcg_const_i32(0);
2702
2703 opsize = insn_opsize(insn);
2704 DEST_EA(env, insn, opsize, zero, NULL);
2705 gen_logic_cc(s, zero, opsize);
2706 tcg_temp_free(zero);
2707 }
2708
2709 DISAS_INSN(move_from_ccr)
2710 {
2711 TCGv ccr;
2712
2713 ccr = gen_get_ccr(s);
2714 DEST_EA(env, insn, OS_WORD, ccr, NULL);
2715 }
2716
2717 DISAS_INSN(neg)
2718 {
2719 TCGv src1;
2720 TCGv dest;
2721 TCGv addr;
2722 int opsize;
2723
2724 opsize = insn_opsize(insn);
2725 SRC_EA(env, src1, opsize, 1, &addr);
2726 dest = tcg_temp_new();
2727 tcg_gen_neg_i32(dest, src1);
2728 set_cc_op(s, CC_OP_SUBB + opsize);
2729 gen_update_cc_add(dest, src1, opsize);
2730 tcg_gen_setcondi_i32(TCG_COND_NE, QREG_CC_X, dest, 0);
2731 DEST_EA(env, insn, opsize, dest, &addr);
2732 tcg_temp_free(dest);
2733 }
2734
2735 DISAS_INSN(move_to_ccr)
2736 {
2737 gen_move_to_sr(env, s, insn, true);
2738 }
2739
2740 DISAS_INSN(not)
2741 {
2742 TCGv src1;
2743 TCGv dest;
2744 TCGv addr;
2745 int opsize;
2746
2747 opsize = insn_opsize(insn);
2748 SRC_EA(env, src1, opsize, 1, &addr);
2749 dest = tcg_temp_new();
2750 tcg_gen_not_i32(dest, src1);
2751 DEST_EA(env, insn, opsize, dest, &addr);
2752 gen_logic_cc(s, dest, opsize);
2753 }
2754
2755 DISAS_INSN(swap)
2756 {
2757 TCGv src1;
2758 TCGv src2;
2759 TCGv reg;
2760
2761 src1 = tcg_temp_new();
2762 src2 = tcg_temp_new();
2763 reg = DREG(insn, 0);
2764 tcg_gen_shli_i32(src1, reg, 16);
2765 tcg_gen_shri_i32(src2, reg, 16);
2766 tcg_gen_or_i32(reg, src1, src2);
2767 tcg_temp_free(src2);
2768 tcg_temp_free(src1);
2769 gen_logic_cc(s, reg, OS_LONG);
2770 }
2771
2772 DISAS_INSN(bkpt)
2773 {
2774 gen_exception(s, s->base.pc_next, EXCP_DEBUG);
2775 }
2776
2777 DISAS_INSN(pea)
2778 {
2779 TCGv tmp;
2780
2781 tmp = gen_lea(env, s, insn, OS_LONG);
2782 if (IS_NULL_QREG(tmp)) {
2783 gen_addr_fault(s);
2784 return;
2785 }
2786 gen_push(s, tmp);
2787 }
2788
2789 DISAS_INSN(ext)
2790 {
2791 int op;
2792 TCGv reg;
2793 TCGv tmp;
2794
2795 reg = DREG(insn, 0);
2796 op = (insn >> 6) & 7;
2797 tmp = tcg_temp_new();
2798 if (op == 3)
2799 tcg_gen_ext16s_i32(tmp, reg);
2800 else
2801 tcg_gen_ext8s_i32(tmp, reg);
2802 if (op == 2)
2803 gen_partset_reg(OS_WORD, reg, tmp);
2804 else
2805 tcg_gen_mov_i32(reg, tmp);
2806 gen_logic_cc(s, tmp, OS_LONG);
2807 tcg_temp_free(tmp);
2808 }
2809
2810 DISAS_INSN(tst)
2811 {
2812 int opsize;
2813 TCGv tmp;
2814
2815 opsize = insn_opsize(insn);
2816 SRC_EA(env, tmp, opsize, 1, NULL);
2817 gen_logic_cc(s, tmp, opsize);
2818 }
2819
2820 DISAS_INSN(pulse)
2821 {
2822 /* Implemented as a NOP. */
2823 }
2824
2825 DISAS_INSN(illegal)
2826 {
2827 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
2828 }
2829
2830 DISAS_INSN(tas)
2831 {
2832 int mode = extract32(insn, 3, 3);
2833 int reg0 = REG(insn, 0);
2834
2835 if (mode == 0) {
2836 /* data register direct */
2837 TCGv dest = cpu_dregs[reg0];
2838 gen_logic_cc(s, dest, OS_BYTE);
2839 tcg_gen_ori_tl(dest, dest, 0x80);
2840 } else {
2841 TCGv src1, addr;
2842
2843 addr = gen_lea_mode(env, s, mode, reg0, OS_BYTE);
2844 if (IS_NULL_QREG(addr)) {
2845 gen_addr_fault(s);
2846 return;
2847 }
2848 src1 = tcg_temp_new();
2849 tcg_gen_atomic_fetch_or_tl(src1, addr, tcg_constant_tl(0x80),
2850 IS_USER(s), MO_SB);
2851 gen_logic_cc(s, src1, OS_BYTE);
2852 tcg_temp_free(src1);
2853
2854 switch (mode) {
2855 case 3: /* Indirect postincrement. */
2856 tcg_gen_addi_i32(AREG(insn, 0), addr, 1);
2857 break;
2858 case 4: /* Indirect predecrememnt. */
2859 tcg_gen_mov_i32(AREG(insn, 0), addr);
2860 break;
2861 }
2862 }
2863 }
2864
2865 DISAS_INSN(mull)
2866 {
2867 uint16_t ext;
2868 TCGv src1;
2869 int sign;
2870
2871 ext = read_im16(env, s);
2872
2873 sign = ext & 0x800;
2874
2875 if (ext & 0x400) {
2876 if (!m68k_feature(s->env, M68K_FEATURE_QUAD_MULDIV)) {
2877 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
2878 return;
2879 }
2880
2881 SRC_EA(env, src1, OS_LONG, 0, NULL);
2882
2883 if (sign) {
2884 tcg_gen_muls2_i32(QREG_CC_Z, QREG_CC_N, src1, DREG(ext, 12));
2885 } else {
2886 tcg_gen_mulu2_i32(QREG_CC_Z, QREG_CC_N, src1, DREG(ext, 12));
2887 }
2888 /* if Dl == Dh, 68040 returns low word */
2889 tcg_gen_mov_i32(DREG(ext, 0), QREG_CC_N);
2890 tcg_gen_mov_i32(DREG(ext, 12), QREG_CC_Z);
2891 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N);
2892
2893 tcg_gen_movi_i32(QREG_CC_V, 0);
2894 tcg_gen_movi_i32(QREG_CC_C, 0);
2895
2896 set_cc_op(s, CC_OP_FLAGS);
2897 return;
2898 }
2899 SRC_EA(env, src1, OS_LONG, 0, NULL);
2900 if (m68k_feature(s->env, M68K_FEATURE_M68K)) {
2901 tcg_gen_movi_i32(QREG_CC_C, 0);
2902 if (sign) {
2903 tcg_gen_muls2_i32(QREG_CC_N, QREG_CC_V, src1, DREG(ext, 12));
2904 /* QREG_CC_V is -(QREG_CC_V != (QREG_CC_N >> 31)) */
2905 tcg_gen_sari_i32(QREG_CC_Z, QREG_CC_N, 31);
2906 tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, QREG_CC_Z);
2907 } else {
2908 tcg_gen_mulu2_i32(QREG_CC_N, QREG_CC_V, src1, DREG(ext, 12));
2909 /* QREG_CC_V is -(QREG_CC_V != 0), use QREG_CC_C as 0 */
2910 tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, QREG_CC_C);
2911 }
2912 tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V);
2913 tcg_gen_mov_i32(DREG(ext, 12), QREG_CC_N);
2914
2915 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
2916
2917 set_cc_op(s, CC_OP_FLAGS);
2918 } else {
2919 /*
2920 * The upper 32 bits of the product are discarded, so
2921 * muls.l and mulu.l are functionally equivalent.
2922 */
2923 tcg_gen_mul_i32(DREG(ext, 12), src1, DREG(ext, 12));
2924 gen_logic_cc(s, DREG(ext, 12), OS_LONG);
2925 }
2926 }
2927
2928 static void gen_link(DisasContext *s, uint16_t insn, int32_t offset)
2929 {
2930 TCGv reg;
2931 TCGv tmp;
2932
2933 reg = AREG(insn, 0);
2934 tmp = tcg_temp_new();
2935 tcg_gen_subi_i32(tmp, QREG_SP, 4);
2936 gen_store(s, OS_LONG, tmp, reg, IS_USER(s));
2937 if ((insn & 7) != 7) {
2938 tcg_gen_mov_i32(reg, tmp);
2939 }
2940 tcg_gen_addi_i32(QREG_SP, tmp, offset);
2941 tcg_temp_free(tmp);
2942 }
2943
2944 DISAS_INSN(link)
2945 {
2946 int16_t offset;
2947
2948 offset = read_im16(env, s);
2949 gen_link(s, insn, offset);
2950 }
2951
2952 DISAS_INSN(linkl)
2953 {
2954 int32_t offset;
2955
2956 offset = read_im32(env, s);
2957 gen_link(s, insn, offset);
2958 }
2959
2960 DISAS_INSN(unlk)
2961 {
2962 TCGv src;
2963 TCGv reg;
2964 TCGv tmp;
2965
2966 src = tcg_temp_new();
2967 reg = AREG(insn, 0);
2968 tcg_gen_mov_i32(src, reg);
2969 tmp = gen_load(s, OS_LONG, src, 0, IS_USER(s));
2970 tcg_gen_mov_i32(reg, tmp);
2971 tcg_gen_addi_i32(QREG_SP, src, 4);
2972 tcg_temp_free(src);
2973 tcg_temp_free(tmp);
2974 }
2975
2976 #if defined(CONFIG_SOFTMMU)
2977 DISAS_INSN(reset)
2978 {
2979 if (IS_USER(s)) {
2980 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
2981 return;
2982 }
2983
2984 gen_helper_reset(cpu_env);
2985 }
2986 #endif
2987
2988 DISAS_INSN(nop)
2989 {
2990 }
2991
2992 DISAS_INSN(rtd)
2993 {
2994 TCGv tmp;
2995 int16_t offset = read_im16(env, s);
2996
2997 tmp = gen_load(s, OS_LONG, QREG_SP, 0, IS_USER(s));
2998 tcg_gen_addi_i32(QREG_SP, QREG_SP, offset + 4);
2999 gen_jmp(s, tmp);
3000 }
3001
3002 DISAS_INSN(rtr)
3003 {
3004 TCGv tmp;
3005 TCGv ccr;
3006 TCGv sp;
3007
3008 sp = tcg_temp_new();
3009 ccr = gen_load(s, OS_WORD, QREG_SP, 0, IS_USER(s));
3010 tcg_gen_addi_i32(sp, QREG_SP, 2);
3011 tmp = gen_load(s, OS_LONG, sp, 0, IS_USER(s));
3012 tcg_gen_addi_i32(QREG_SP, sp, 4);
3013 tcg_temp_free(sp);
3014
3015 gen_set_sr(s, ccr, true);
3016 tcg_temp_free(ccr);
3017
3018 gen_jmp(s, tmp);
3019 }
3020
3021 DISAS_INSN(rts)
3022 {
3023 TCGv tmp;
3024
3025 tmp = gen_load(s, OS_LONG, QREG_SP, 0, IS_USER(s));
3026 tcg_gen_addi_i32(QREG_SP, QREG_SP, 4);
3027 gen_jmp(s, tmp);
3028 }
3029
3030 DISAS_INSN(jump)
3031 {
3032 TCGv tmp;
3033
3034 /*
3035 * Load the target address first to ensure correct exception
3036 * behavior.
3037 */
3038 tmp = gen_lea(env, s, insn, OS_LONG);
3039 if (IS_NULL_QREG(tmp)) {
3040 gen_addr_fault(s);
3041 return;
3042 }
3043 if ((insn & 0x40) == 0) {
3044 /* jsr */
3045 gen_push(s, tcg_const_i32(s->pc));
3046 }
3047 gen_jmp(s, tmp);
3048 }
3049
3050 DISAS_INSN(addsubq)
3051 {
3052 TCGv src;
3053 TCGv dest;
3054 TCGv val;
3055 int imm;
3056 TCGv addr;
3057 int opsize;
3058
3059 if ((insn & 070) == 010) {
3060 /* Operation on address register is always long. */
3061 opsize = OS_LONG;
3062 } else {
3063 opsize = insn_opsize(insn);
3064 }
3065 SRC_EA(env, src, opsize, 1, &addr);
3066 imm = (insn >> 9) & 7;
3067 if (imm == 0) {
3068 imm = 8;
3069 }
3070 val = tcg_const_i32(imm);
3071 dest = tcg_temp_new();
3072 tcg_gen_mov_i32(dest, src);
3073 if ((insn & 0x38) == 0x08) {
3074 /*
3075 * Don't update condition codes if the destination is an
3076 * address register.
3077 */
3078 if (insn & 0x0100) {
3079 tcg_gen_sub_i32(dest, dest, val);
3080 } else {
3081 tcg_gen_add_i32(dest, dest, val);
3082 }
3083 } else {
3084 if (insn & 0x0100) {
3085 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, val);
3086 tcg_gen_sub_i32(dest, dest, val);
3087 set_cc_op(s, CC_OP_SUBB + opsize);
3088 } else {
3089 tcg_gen_add_i32(dest, dest, val);
3090 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, val);
3091 set_cc_op(s, CC_OP_ADDB + opsize);
3092 }
3093 gen_update_cc_add(dest, val, opsize);
3094 }
3095 tcg_temp_free(val);
3096 DEST_EA(env, insn, opsize, dest, &addr);
3097 tcg_temp_free(dest);
3098 }
3099
3100 DISAS_INSN(branch)
3101 {
3102 int32_t offset;
3103 uint32_t base;
3104 int op;
3105
3106 base = s->pc;
3107 op = (insn >> 8) & 0xf;
3108 offset = (int8_t)insn;
3109 if (offset == 0) {
3110 offset = (int16_t)read_im16(env, s);
3111 } else if (offset == -1) {
3112 offset = read_im32(env, s);
3113 }
3114 if (op == 1) {
3115 /* bsr */
3116 gen_push(s, tcg_const_i32(s->pc));
3117 }
3118 if (op > 1) {
3119 /* Bcc */
3120 TCGLabel *l1 = gen_new_label();
3121 gen_jmpcc(s, ((insn >> 8) & 0xf) ^ 1, l1);
3122 gen_jmp_tb(s, 1, base + offset, s->base.pc_next);
3123 gen_set_label(l1);
3124 gen_jmp_tb(s, 0, s->pc, s->base.pc_next);
3125 } else {
3126 /* Unconditional branch. */
3127 update_cc_op(s);
3128 gen_jmp_tb(s, 0, base + offset, s->base.pc_next);
3129 }
3130 }
3131
3132 DISAS_INSN(moveq)
3133 {
3134 tcg_gen_movi_i32(DREG(insn, 9), (int8_t)insn);
3135 gen_logic_cc(s, DREG(insn, 9), OS_LONG);
3136 }
3137
3138 DISAS_INSN(mvzs)
3139 {
3140 int opsize;
3141 TCGv src;
3142 TCGv reg;
3143
3144 if (insn & 0x40)
3145 opsize = OS_WORD;
3146 else
3147 opsize = OS_BYTE;
3148 SRC_EA(env, src, opsize, (insn & 0x80) == 0, NULL);
3149 reg = DREG(insn, 9);
3150 tcg_gen_mov_i32(reg, src);
3151 gen_logic_cc(s, src, opsize);
3152 }
3153
3154 DISAS_INSN(or)
3155 {
3156 TCGv reg;
3157 TCGv dest;
3158 TCGv src;
3159 TCGv addr;
3160 int opsize;
3161
3162 opsize = insn_opsize(insn);
3163 reg = gen_extend(s, DREG(insn, 9), opsize, 0);
3164 dest = tcg_temp_new();
3165 if (insn & 0x100) {
3166 SRC_EA(env, src, opsize, 0, &addr);
3167 tcg_gen_or_i32(dest, src, reg);
3168 DEST_EA(env, insn, opsize, dest, &addr);
3169 } else {
3170 SRC_EA(env, src, opsize, 0, NULL);
3171 tcg_gen_or_i32(dest, src, reg);
3172 gen_partset_reg(opsize, DREG(insn, 9), dest);
3173 }
3174 gen_logic_cc(s, dest, opsize);
3175 tcg_temp_free(dest);
3176 }
3177
3178 DISAS_INSN(suba)
3179 {
3180 TCGv src;
3181 TCGv reg;
3182
3183 SRC_EA(env, src, (insn & 0x100) ? OS_LONG : OS_WORD, 1, NULL);
3184 reg = AREG(insn, 9);
3185 tcg_gen_sub_i32(reg, reg, src);
3186 }
3187
3188 static inline void gen_subx(DisasContext *s, TCGv src, TCGv dest, int opsize)
3189 {
3190 TCGv tmp;
3191
3192 gen_flush_flags(s); /* compute old Z */
3193
3194 /*
3195 * Perform subtract with borrow.
3196 * (X, N) = dest - (src + X);
3197 */
3198
3199 tmp = tcg_const_i32(0);
3200 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, src, tmp, QREG_CC_X, tmp);
3201 tcg_gen_sub2_i32(QREG_CC_N, QREG_CC_X, dest, tmp, QREG_CC_N, QREG_CC_X);
3202 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
3203 tcg_gen_andi_i32(QREG_CC_X, QREG_CC_X, 1);
3204
3205 /* Compute signed-overflow for subtract. */
3206
3207 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, dest);
3208 tcg_gen_xor_i32(tmp, dest, src);
3209 tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, tmp);
3210 tcg_temp_free(tmp);
3211
3212 /* Copy the rest of the results into place. */
3213 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */
3214 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
3215
3216 set_cc_op(s, CC_OP_FLAGS);
3217
3218 /* result is in QREG_CC_N */
3219 }
3220
3221 DISAS_INSN(subx_reg)
3222 {
3223 TCGv dest;
3224 TCGv src;
3225 int opsize;
3226
3227 opsize = insn_opsize(insn);
3228
3229 src = gen_extend(s, DREG(insn, 0), opsize, 1);
3230 dest = gen_extend(s, DREG(insn, 9), opsize, 1);
3231
3232 gen_subx(s, src, dest, opsize);
3233
3234 gen_partset_reg(opsize, DREG(insn, 9), QREG_CC_N);
3235 }
3236
3237 DISAS_INSN(subx_mem)
3238 {
3239 TCGv src;
3240 TCGv addr_src;
3241 TCGv dest;
3242 TCGv addr_dest;
3243 int opsize;
3244
3245 opsize = insn_opsize(insn);
3246
3247 addr_src = AREG(insn, 0);
3248 tcg_gen_subi_i32(addr_src, addr_src, opsize_bytes(opsize));
3249 src = gen_load(s, opsize, addr_src, 1, IS_USER(s));
3250
3251 addr_dest = AREG(insn, 9);
3252 tcg_gen_subi_i32(addr_dest, addr_dest, opsize_bytes(opsize));
3253 dest = gen_load(s, opsize, addr_dest, 1, IS_USER(s));
3254
3255 gen_subx(s, src, dest, opsize);
3256
3257 gen_store(s, opsize, addr_dest, QREG_CC_N, IS_USER(s));
3258
3259 tcg_temp_free(dest);
3260 tcg_temp_free(src);
3261 }
3262
3263 DISAS_INSN(mov3q)
3264 {
3265 TCGv src;
3266 int val;
3267
3268 val = (insn >> 9) & 7;
3269 if (val == 0)
3270 val = -1;
3271 src = tcg_const_i32(val);
3272 gen_logic_cc(s, src, OS_LONG);
3273 DEST_EA(env, insn, OS_LONG, src, NULL);
3274 tcg_temp_free(src);
3275 }
3276
3277 DISAS_INSN(cmp)
3278 {
3279 TCGv src;
3280 TCGv reg;
3281 int opsize;
3282
3283 opsize = insn_opsize(insn);
3284 SRC_EA(env, src, opsize, 1, NULL);
3285 reg = gen_extend(s, DREG(insn, 9), opsize, 1);
3286 gen_update_cc_cmp(s, reg, src, opsize);
3287 }
3288
3289 DISAS_INSN(cmpa)
3290 {
3291 int opsize;
3292 TCGv src;
3293 TCGv reg;
3294
3295 if (insn & 0x100) {
3296 opsize = OS_LONG;
3297 } else {
3298 opsize = OS_WORD;
3299 }
3300 SRC_EA(env, src, opsize, 1, NULL);
3301 reg = AREG(insn, 9);
3302 gen_update_cc_cmp(s, reg, src, OS_LONG);
3303 }
3304
3305 DISAS_INSN(cmpm)
3306 {
3307 int opsize = insn_opsize(insn);
3308 TCGv src, dst;
3309
3310 /* Post-increment load (mode 3) from Ay. */
3311 src = gen_ea_mode(env, s, 3, REG(insn, 0), opsize,
3312 NULL_QREG, NULL, EA_LOADS, IS_USER(s));
3313 /* Post-increment load (mode 3) from Ax. */
3314 dst = gen_ea_mode(env, s, 3, REG(insn, 9), opsize,
3315 NULL_QREG, NULL, EA_LOADS, IS_USER(s));
3316
3317 gen_update_cc_cmp(s, dst, src, opsize);
3318 }
3319
3320 DISAS_INSN(eor)
3321 {
3322 TCGv src;
3323 TCGv dest;
3324 TCGv addr;
3325 int opsize;
3326
3327 opsize = insn_opsize(insn);
3328
3329 SRC_EA(env, src, opsize, 0, &addr);
3330 dest = tcg_temp_new();
3331 tcg_gen_xor_i32(dest, src, DREG(insn, 9));
3332 gen_logic_cc(s, dest, opsize);
3333 DEST_EA(env, insn, opsize, dest, &addr);
3334 tcg_temp_free(dest);
3335 }
3336
3337 static void do_exg(TCGv reg1, TCGv reg2)
3338 {
3339 TCGv temp = tcg_temp_new();
3340 tcg_gen_mov_i32(temp, reg1);
3341 tcg_gen_mov_i32(reg1, reg2);
3342 tcg_gen_mov_i32(reg2, temp);
3343 tcg_temp_free(temp);
3344 }
3345
3346 DISAS_INSN(exg_dd)
3347 {
3348 /* exchange Dx and Dy */
3349 do_exg(DREG(insn, 9), DREG(insn, 0));
3350 }
3351
3352 DISAS_INSN(exg_aa)
3353 {
3354 /* exchange Ax and Ay */
3355 do_exg(AREG(insn, 9), AREG(insn, 0));
3356 }
3357
3358 DISAS_INSN(exg_da)
3359 {
3360 /* exchange Dx and Ay */
3361 do_exg(DREG(insn, 9), AREG(insn, 0));
3362 }
3363
3364 DISAS_INSN(and)
3365 {
3366 TCGv src;
3367 TCGv reg;
3368 TCGv dest;
3369 TCGv addr;
3370 int opsize;
3371
3372 dest = tcg_temp_new();
3373
3374 opsize = insn_opsize(insn);
3375 reg = DREG(insn, 9);
3376 if (insn & 0x100) {
3377 SRC_EA(env, src, opsize, 0, &addr);
3378 tcg_gen_and_i32(dest, src, reg);
3379 DEST_EA(env, insn, opsize, dest, &addr);
3380 } else {
3381 SRC_EA(env, src, opsize, 0, NULL);
3382 tcg_gen_and_i32(dest, src, reg);
3383 gen_partset_reg(opsize, reg, dest);
3384 }
3385 gen_logic_cc(s, dest, opsize);
3386 tcg_temp_free(dest);
3387 }
3388
3389 DISAS_INSN(adda)
3390 {
3391 TCGv src;
3392 TCGv reg;
3393
3394 SRC_EA(env, src, (insn & 0x100) ? OS_LONG : OS_WORD, 1, NULL);
3395 reg = AREG(insn, 9);
3396 tcg_gen_add_i32(reg, reg, src);
3397 }
3398
3399 static inline void gen_addx(DisasContext *s, TCGv src, TCGv dest, int opsize)
3400 {
3401 TCGv tmp;
3402
3403 gen_flush_flags(s); /* compute old Z */
3404
3405 /*
3406 * Perform addition with carry.
3407 * (X, N) = src + dest + X;
3408 */
3409
3410 tmp = tcg_const_i32(0);
3411 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_X, tmp, dest, tmp);
3412 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_N, QREG_CC_X, src, tmp);
3413 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
3414
3415 /* Compute signed-overflow for addition. */
3416
3417 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, src);
3418 tcg_gen_xor_i32(tmp, dest, src);
3419 tcg_gen_andc_i32(QREG_CC_V, QREG_CC_V, tmp);
3420 tcg_temp_free(tmp);
3421
3422 /* Copy the rest of the results into place. */
3423 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */
3424 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
3425
3426 set_cc_op(s, CC_OP_FLAGS);
3427
3428 /* result is in QREG_CC_N */
3429 }
3430
3431 DISAS_INSN(addx_reg)
3432 {
3433 TCGv dest;
3434 TCGv src;
3435 int opsize;
3436
3437 opsize = insn_opsize(insn);
3438
3439 dest = gen_extend(s, DREG(insn, 9), opsize, 1);
3440 src = gen_extend(s, DREG(insn, 0), opsize, 1);
3441
3442 gen_addx(s, src, dest, opsize);
3443
3444 gen_partset_reg(opsize, DREG(insn, 9), QREG_CC_N);
3445 }
3446
3447 DISAS_INSN(addx_mem)
3448 {
3449 TCGv src;
3450 TCGv addr_src;
3451 TCGv dest;
3452 TCGv addr_dest;
3453 int opsize;
3454
3455 opsize = insn_opsize(insn);
3456
3457 addr_src = AREG(insn, 0);
3458 tcg_gen_subi_i32(addr_src, addr_src, opsize_bytes(opsize));
3459 src = gen_load(s, opsize, addr_src, 1, IS_USER(s));
3460
3461 addr_dest = AREG(insn, 9);
3462 tcg_gen_subi_i32(addr_dest, addr_dest, opsize_bytes(opsize));
3463 dest = gen_load(s, opsize, addr_dest, 1, IS_USER(s));
3464
3465 gen_addx(s, src, dest, opsize);
3466
3467 gen_store(s, opsize, addr_dest, QREG_CC_N, IS_USER(s));
3468
3469 tcg_temp_free(dest);
3470 tcg_temp_free(src);
3471 }
3472
3473 static inline void shift_im(DisasContext *s, uint16_t insn, int opsize)
3474 {
3475 int count = (insn >> 9) & 7;
3476 int logical = insn & 8;
3477 int left = insn & 0x100;
3478 int bits = opsize_bytes(opsize) * 8;
3479 TCGv reg = gen_extend(s, DREG(insn, 0), opsize, !logical);
3480
3481 if (count == 0) {
3482 count = 8;
3483 }
3484
3485 tcg_gen_movi_i32(QREG_CC_V, 0);
3486 if (left) {
3487 tcg_gen_shri_i32(QREG_CC_C, reg, bits - count);
3488 tcg_gen_shli_i32(QREG_CC_N, reg, count);
3489
3490 /*
3491 * Note that ColdFire always clears V (done above),
3492 * while M68000 sets if the most significant bit is changed at
3493 * any time during the shift operation.
3494 */
3495 if (!logical && m68k_feature(s->env, M68K_FEATURE_M68K)) {
3496 /* if shift count >= bits, V is (reg != 0) */
3497 if (count >= bits) {
3498 tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, reg, QREG_CC_V);
3499 } else {
3500 TCGv t0 = tcg_temp_new();
3501 tcg_gen_sari_i32(QREG_CC_V, reg, bits - 1);
3502 tcg_gen_sari_i32(t0, reg, bits - count - 1);
3503 tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, t0);
3504 tcg_temp_free(t0);
3505 }
3506 tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V);
3507 }
3508 } else {
3509 tcg_gen_shri_i32(QREG_CC_C, reg, count - 1);
3510 if (logical) {
3511 tcg_gen_shri_i32(QREG_CC_N, reg, count);
3512 } else {
3513 tcg_gen_sari_i32(QREG_CC_N, reg, count);
3514 }
3515 }
3516
3517 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
3518 tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1);
3519 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
3520 tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C);
3521
3522 gen_partset_reg(opsize, DREG(insn, 0), QREG_CC_N);
3523 set_cc_op(s, CC_OP_FLAGS);
3524 }
3525
3526 static inline void shift_reg(DisasContext *s, uint16_t insn, int opsize)
3527 {
3528 int logical = insn & 8;
3529 int left = insn & 0x100;
3530 int bits = opsize_bytes(opsize) * 8;
3531 TCGv reg = gen_extend(s, DREG(insn, 0), opsize, !logical);
3532 TCGv s32;
3533 TCGv_i64 t64, s64;
3534
3535 t64 = tcg_temp_new_i64();
3536 s64 = tcg_temp_new_i64();
3537 s32 = tcg_temp_new();
3538
3539 /*
3540 * Note that m68k truncates the shift count modulo 64, not 32.
3541 * In addition, a 64-bit shift makes it easy to find "the last
3542 * bit shifted out", for the carry flag.
3543 */
3544 tcg_gen_andi_i32(s32, DREG(insn, 9), 63);
3545 tcg_gen_extu_i32_i64(s64, s32);
3546 tcg_gen_extu_i32_i64(t64, reg);
3547
3548 /* Optimistically set V=0. Also used as a zero source below. */
3549 tcg_gen_movi_i32(QREG_CC_V, 0);
3550 if (left) {
3551 tcg_gen_shl_i64(t64, t64, s64);
3552
3553 if (opsize == OS_LONG) {
3554 tcg_gen_extr_i64_i32(QREG_CC_N, QREG_CC_C, t64);
3555 /* Note that C=0 if shift count is 0, and we get that for free. */
3556 } else {
3557 TCGv zero = tcg_const_i32(0);
3558 tcg_gen_extrl_i64_i32(QREG_CC_N, t64);
3559 tcg_gen_shri_i32(QREG_CC_C, QREG_CC_N, bits);
3560 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C,
3561 s32, zero, zero, QREG_CC_C);
3562 tcg_temp_free(zero);
3563 }
3564 tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1);
3565
3566 /* X = C, but only if the shift count was non-zero. */
3567 tcg_gen_movcond_i32(TCG_COND_NE, QREG_CC_X, s32, QREG_CC_V,
3568 QREG_CC_C, QREG_CC_X);
3569
3570 /*
3571 * M68000 sets V if the most significant bit is changed at
3572 * any time during the shift operation. Do this via creating
3573 * an extension of the sign bit, comparing, and discarding
3574 * the bits below the sign bit. I.e.
3575 * int64_t s = (intN_t)reg;
3576 * int64_t t = (int64_t)(intN_t)reg << count;
3577 * V = ((s ^ t) & (-1 << (bits - 1))) != 0
3578 */
3579 if (!logical && m68k_feature(s->env, M68K_FEATURE_M68K)) {
3580 TCGv_i64 tt = tcg_const_i64(32);
3581 /* if shift is greater than 32, use 32 */
3582 tcg_gen_movcond_i64(TCG_COND_GT, s64, s64, tt, tt, s64);
3583 tcg_temp_free_i64(tt);
3584 /* Sign extend the input to 64 bits; re-do the shift. */
3585 tcg_gen_ext_i32_i64(t64, reg);
3586 tcg_gen_shl_i64(s64, t64, s64);
3587 /* Clear all bits that are unchanged. */
3588 tcg_gen_xor_i64(t64, t64, s64);
3589 /* Ignore the bits below the sign bit. */
3590 tcg_gen_andi_i64(t64, t64, -1ULL << (bits - 1));
3591 /* If any bits remain set, we have overflow. */
3592 tcg_gen_setcondi_i64(TCG_COND_NE, t64, t64, 0);
3593 tcg_gen_extrl_i64_i32(QREG_CC_V, t64);
3594 tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V);
3595 }
3596 } else {
3597 tcg_gen_shli_i64(t64, t64, 32);
3598 if (logical) {
3599 tcg_gen_shr_i64(t64, t64, s64);
3600 } else {
3601 tcg_gen_sar_i64(t64, t64, s64);
3602 }
3603 tcg_gen_extr_i64_i32(QREG_CC_C, QREG_CC_N, t64);
3604
3605 /* Note that C=0 if shift count is 0, and we get that for free. */
3606 tcg_gen_shri_i32(QREG_CC_C, QREG_CC_C, 31);
3607
3608 /* X = C, but only if the shift count was non-zero. */
3609 tcg_gen_movcond_i32(TCG_COND_NE, QREG_CC_X, s32, QREG_CC_V,
3610 QREG_CC_C, QREG_CC_X);
3611 }
3612 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
3613 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
3614
3615 tcg_temp_free(s32);
3616 tcg_temp_free_i64(s64);
3617 tcg_temp_free_i64(t64);
3618
3619 /* Write back the result. */
3620 gen_partset_reg(opsize, DREG(insn, 0), QREG_CC_N);
3621 set_cc_op(s, CC_OP_FLAGS);
3622 }
3623
3624 DISAS_INSN(shift8_im)
3625 {
3626 shift_im(s, insn, OS_BYTE);
3627 }
3628
3629 DISAS_INSN(shift16_im)
3630 {
3631 shift_im(s, insn, OS_WORD);
3632 }
3633
3634 DISAS_INSN(shift_im)
3635 {
3636 shift_im(s, insn, OS_LONG);
3637 }
3638
3639 DISAS_INSN(shift8_reg)
3640 {
3641 shift_reg(s, insn, OS_BYTE);
3642 }
3643
3644 DISAS_INSN(shift16_reg)
3645 {
3646 shift_reg(s, insn, OS_WORD);
3647 }
3648
3649 DISAS_INSN(shift_reg)
3650 {
3651 shift_reg(s, insn, OS_LONG);
3652 }
3653
3654 DISAS_INSN(shift_mem)
3655 {
3656 int logical = insn & 8;
3657 int left = insn & 0x100;
3658 TCGv src;
3659 TCGv addr;
3660
3661 SRC_EA(env, src, OS_WORD, !logical, &addr);
3662 tcg_gen_movi_i32(QREG_CC_V, 0);
3663 if (left) {
3664 tcg_gen_shri_i32(QREG_CC_C, src, 15);
3665 tcg_gen_shli_i32(QREG_CC_N, src, 1);
3666
3667 /*
3668 * Note that ColdFire always clears V,
3669 * while M68000 sets if the most significant bit is changed at
3670 * any time during the shift operation
3671 */
3672 if (!logical && m68k_feature(s->env, M68K_FEATURE_M68K)) {
3673 src = gen_extend(s, src, OS_WORD, 1);
3674 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, src);
3675 }
3676 } else {
3677 tcg_gen_mov_i32(QREG_CC_C, src);
3678 if (logical) {
3679 tcg_gen_shri_i32(QREG_CC_N, src, 1);
3680 } else {
3681 tcg_gen_sari_i32(QREG_CC_N, src, 1);
3682 }
3683 }
3684
3685 gen_ext(QREG_CC_N, QREG_CC_N, OS_WORD, 1);
3686 tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1);
3687 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
3688 tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C);
3689
3690 DEST_EA(env, insn, OS_WORD, QREG_CC_N, &addr);
3691 set_cc_op(s, CC_OP_FLAGS);
3692 }
3693
3694 static void rotate(TCGv reg, TCGv shift, int left, int size)
3695 {
3696 switch (size) {
3697 case 8:
3698 /* Replicate the 8-bit input so that a 32-bit rotate works. */
3699 tcg_gen_ext8u_i32(reg, reg);
3700 tcg_gen_muli_i32(reg, reg, 0x01010101);
3701 goto do_long;
3702 case 16:
3703 /* Replicate the 16-bit input so that a 32-bit rotate works. */
3704 tcg_gen_deposit_i32(reg, reg, reg, 16, 16);
3705 goto do_long;
3706 do_long:
3707 default:
3708 if (left) {
3709 tcg_gen_rotl_i32(reg, reg, shift);
3710 } else {
3711 tcg_gen_rotr_i32(reg, reg, shift);
3712 }
3713 }
3714
3715 /* compute flags */
3716
3717 switch (size) {
3718 case 8:
3719 tcg_gen_ext8s_i32(reg, reg);
3720 break;
3721 case 16:
3722 tcg_gen_ext16s_i32(reg, reg);
3723 break;
3724 default:
3725 break;
3726 }
3727
3728 /* QREG_CC_X is not affected */
3729
3730 tcg_gen_mov_i32(QREG_CC_N, reg);
3731 tcg_gen_mov_i32(QREG_CC_Z, reg);
3732
3733 if (left) {
3734 tcg_gen_andi_i32(QREG_CC_C, reg, 1);
3735 } else {
3736 tcg_gen_shri_i32(QREG_CC_C, reg, 31);
3737 }
3738
3739 tcg_gen_movi_i32(QREG_CC_V, 0); /* always cleared */
3740 }
3741
3742 static void rotate_x_flags(TCGv reg, TCGv X, int size)
3743 {
3744 switch (size) {
3745 case 8:
3746 tcg_gen_ext8s_i32(reg, reg);
3747 break;
3748 case 16:
3749 tcg_gen_ext16s_i32(reg, reg);
3750 break;
3751 default:
3752 break;
3753 }
3754 tcg_gen_mov_i32(QREG_CC_N, reg);
3755 tcg_gen_mov_i32(QREG_CC_Z, reg);
3756 tcg_gen_mov_i32(QREG_CC_X, X);
3757 tcg_gen_mov_i32(QREG_CC_C, X);
3758 tcg_gen_movi_i32(QREG_CC_V, 0);
3759 }
3760
3761 /* Result of rotate_x() is valid if 0 <= shift <= size */
3762 static TCGv rotate_x(TCGv reg, TCGv shift, int left, int size)
3763 {
3764 TCGv X, shl, shr, shx, sz, zero;
3765
3766 sz = tcg_const_i32(size);
3767
3768 shr = tcg_temp_new();
3769 shl = tcg_temp_new();
3770 shx = tcg_temp_new();
3771 if (left) {
3772 tcg_gen_mov_i32(shl, shift); /* shl = shift */
3773 tcg_gen_movi_i32(shr, size + 1);
3774 tcg_gen_sub_i32(shr, shr, shift); /* shr = size + 1 - shift */
3775 tcg_gen_subi_i32(shx, shift, 1); /* shx = shift - 1 */
3776 /* shx = shx < 0 ? size : shx; */
3777 zero = tcg_const_i32(0);
3778 tcg_gen_movcond_i32(TCG_COND_LT, shx, shx, zero, sz, shx);
3779 tcg_temp_free(zero);
3780 } else {
3781 tcg_gen_mov_i32(shr, shift); /* shr = shift */
3782 tcg_gen_movi_i32(shl, size + 1);
3783 tcg_gen_sub_i32(shl, shl, shift); /* shl = size + 1 - shift */
3784 tcg_gen_sub_i32(shx, sz, shift); /* shx = size - shift */
3785 }
3786 tcg_temp_free_i32(sz);
3787
3788 /* reg = (reg << shl) | (reg >> shr) | (x << shx); */
3789
3790 tcg_gen_shl_i32(shl, reg, shl);
3791 tcg_gen_shr_i32(shr, reg, shr);
3792 tcg_gen_or_i32(reg, shl, shr);
3793 tcg_temp_free(shl);
3794 tcg_temp_free(shr);
3795 tcg_gen_shl_i32(shx, QREG_CC_X, shx);
3796 tcg_gen_or_i32(reg, reg, shx);
3797 tcg_temp_free(shx);
3798
3799 /* X = (reg >> size) & 1 */
3800
3801 X = tcg_temp_new();
3802 tcg_gen_extract_i32(X, reg, size, 1);
3803
3804 return X;
3805 }
3806
3807 /* Result of rotate32_x() is valid if 0 <= shift < 33 */
3808 static TCGv rotate32_x(TCGv reg, TCGv shift, int left)
3809 {
3810 TCGv_i64 t0, shift64;
3811 TCGv X, lo, hi, zero;
3812
3813 shift64 = tcg_temp_new_i64();
3814 tcg_gen_extu_i32_i64(shift64, shift);
3815
3816 t0 = tcg_temp_new_i64();
3817
3818 X = tcg_temp_new();
3819 lo = tcg_temp_new();
3820 hi = tcg_temp_new();
3821
3822 if (left) {
3823 /* create [reg:X:..] */
3824
3825 tcg_gen_shli_i32(lo, QREG_CC_X, 31);
3826 tcg_gen_concat_i32_i64(t0, lo, reg);
3827
3828 /* rotate */
3829
3830 tcg_gen_rotl_i64(t0, t0, shift64);
3831 tcg_temp_free_i64(shift64);
3832
3833 /* result is [reg:..:reg:X] */
3834
3835 tcg_gen_extr_i64_i32(lo, hi, t0);
3836 tcg_gen_andi_i32(X, lo, 1);
3837
3838 tcg_gen_shri_i32(lo, lo, 1);
3839 } else {
3840 /* create [..:X:reg] */
3841
3842 tcg_gen_concat_i32_i64(t0, reg, QREG_CC_X);
3843
3844 tcg_gen_rotr_i64(t0, t0, shift64);
3845 tcg_temp_free_i64(shift64);
3846
3847 /* result is value: [X:reg:..:reg] */
3848
3849 tcg_gen_extr_i64_i32(lo, hi, t0);
3850
3851 /* extract X */
3852
3853 tcg_gen_shri_i32(X, hi, 31);
3854
3855 /* extract result */
3856
3857 tcg_gen_shli_i32(hi, hi, 1);
3858 }
3859 tcg_temp_free_i64(t0);
3860 tcg_gen_or_i32(lo, lo, hi);
3861 tcg_temp_free(hi);
3862
3863 /* if shift == 0, register and X are not affected */
3864
3865 zero = tcg_const_i32(0);
3866 tcg_gen_movcond_i32(TCG_COND_EQ, X, shift, zero, QREG_CC_X, X);
3867 tcg_gen_movcond_i32(TCG_COND_EQ, reg, shift, zero, reg, lo);
3868 tcg_temp_free(zero);
3869 tcg_temp_free(lo);
3870
3871 return X;
3872 }
3873
3874 DISAS_INSN(rotate_im)
3875 {
3876 TCGv shift;
3877 int tmp;
3878 int left = (insn & 0x100);
3879
3880 tmp = (insn >> 9) & 7;
3881 if (tmp == 0) {
3882 tmp = 8;
3883 }
3884
3885 shift = tcg_const_i32(tmp);
3886 if (insn & 8) {
3887 rotate(DREG(insn, 0), shift, left, 32);
3888 } else {
3889 TCGv X = rotate32_x(DREG(insn, 0), shift, left);
3890 rotate_x_flags(DREG(insn, 0), X, 32);
3891 tcg_temp_free(X);
3892 }
3893 tcg_temp_free(shift);
3894
3895 set_cc_op(s, CC_OP_FLAGS);
3896 }
3897
3898 DISAS_INSN(rotate8_im)
3899 {
3900 int left = (insn & 0x100);
3901 TCGv reg;
3902 TCGv shift;
3903 int tmp;
3904
3905 reg = gen_extend(s, DREG(insn, 0), OS_BYTE, 0);
3906
3907 tmp = (insn >> 9) & 7;
3908 if (tmp == 0) {
3909 tmp = 8;
3910 }
3911
3912 shift = tcg_const_i32(tmp);
3913 if (insn & 8) {
3914 rotate(reg, shift, left, 8);
3915 } else {
3916 TCGv X = rotate_x(reg, shift, left, 8);
3917 rotate_x_flags(reg, X, 8);
3918 tcg_temp_free(X);
3919 }
3920 tcg_temp_free(shift);
3921 gen_partset_reg(OS_BYTE, DREG(insn, 0), reg);
3922 set_cc_op(s, CC_OP_FLAGS);
3923 }
3924
3925 DISAS_INSN(rotate16_im)
3926 {
3927 int left = (insn & 0x100);
3928 TCGv reg;
3929 TCGv shift;
3930 int tmp;
3931
3932 reg = gen_extend(s, DREG(insn, 0), OS_WORD, 0);
3933 tmp = (insn >> 9) & 7;
3934 if (tmp == 0) {
3935 tmp = 8;
3936 }
3937
3938 shift = tcg_const_i32(tmp);
3939 if (insn & 8) {
3940 rotate(reg, shift, left, 16);
3941 } else {
3942 TCGv X = rotate_x(reg, shift, left, 16);
3943 rotate_x_flags(reg, X, 16);
3944 tcg_temp_free(X);
3945 }
3946 tcg_temp_free(shift);
3947 gen_partset_reg(OS_WORD, DREG(insn, 0), reg);
3948 set_cc_op(s, CC_OP_FLAGS);
3949 }
3950
3951 DISAS_INSN(rotate_reg)
3952 {
3953 TCGv reg;
3954 TCGv src;
3955 TCGv t0, t1;
3956 int left = (insn & 0x100);
3957
3958 reg = DREG(insn, 0);
3959 src = DREG(insn, 9);
3960 /* shift in [0..63] */
3961 t0 = tcg_temp_new();
3962 tcg_gen_andi_i32(t0, src, 63);
3963 t1 = tcg_temp_new_i32();
3964 if (insn & 8) {
3965 tcg_gen_andi_i32(t1, src, 31);
3966 rotate(reg, t1, left, 32);
3967 /* if shift == 0, clear C */
3968 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C,
3969 t0, QREG_CC_V /* 0 */,
3970 QREG_CC_V /* 0 */, QREG_CC_C);
3971 } else {
3972 TCGv X;
3973 /* modulo 33 */
3974 tcg_gen_movi_i32(t1, 33);
3975 tcg_gen_remu_i32(t1, t0, t1);
3976 X = rotate32_x(DREG(insn, 0), t1, left);
3977 rotate_x_flags(DREG(insn, 0), X, 32);
3978 tcg_temp_free(X);
3979 }
3980 tcg_temp_free(t1);
3981 tcg_temp_free(t0);
3982 set_cc_op(s, CC_OP_FLAGS);
3983 }
3984
3985 DISAS_INSN(rotate8_reg)
3986 {
3987 TCGv reg;
3988 TCGv src;
3989 TCGv t0, t1;
3990 int left = (insn & 0x100);
3991
3992 reg = gen_extend(s, DREG(insn, 0), OS_BYTE, 0);
3993 src = DREG(insn, 9);
3994 /* shift in [0..63] */
3995 t0 = tcg_temp_new_i32();
3996 tcg_gen_andi_i32(t0, src, 63);
3997 t1 = tcg_temp_new_i32();
3998 if (insn & 8) {
3999 tcg_gen_andi_i32(t1, src, 7);
4000 rotate(reg, t1, left, 8);
4001 /* if shift == 0, clear C */
4002 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C,
4003 t0, QREG_CC_V /* 0 */,
4004 QREG_CC_V /* 0 */, QREG_CC_C);
4005 } else {
4006 TCGv X;
4007 /* modulo 9 */
4008 tcg_gen_movi_i32(t1, 9);
4009 tcg_gen_remu_i32(t1, t0, t1);
4010 X = rotate_x(reg, t1, left, 8);
4011 rotate_x_flags(reg, X, 8);
4012 tcg_temp_free(X);
4013 }
4014 tcg_temp_free(t1);
4015 tcg_temp_free(t0);
4016 gen_partset_reg(OS_BYTE, DREG(insn, 0), reg);
4017 set_cc_op(s, CC_OP_FLAGS);
4018 }
4019
4020 DISAS_INSN(rotate16_reg)
4021 {
4022 TCGv reg;
4023 TCGv src;
4024 TCGv t0, t1;
4025 int left = (insn & 0x100);
4026
4027 reg = gen_extend(s, DREG(insn, 0), OS_WORD, 0);
4028 src = DREG(insn, 9);
4029 /* shift in [0..63] */
4030 t0 = tcg_temp_new_i32();
4031 tcg_gen_andi_i32(t0, src, 63);
4032 t1 = tcg_temp_new_i32();
4033 if (insn & 8) {
4034 tcg_gen_andi_i32(t1, src, 15);
4035 rotate(reg, t1, left, 16);
4036 /* if shift == 0, clear C */
4037 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C,
4038 t0, QREG_CC_V /* 0 */,
4039 QREG_CC_V /* 0 */, QREG_CC_C);
4040 } else {
4041 TCGv X;
4042 /* modulo 17 */
4043 tcg_gen_movi_i32(t1, 17);
4044 tcg_gen_remu_i32(t1, t0, t1);
4045 X = rotate_x(reg, t1, left, 16);
4046 rotate_x_flags(reg, X, 16);
4047 tcg_temp_free(X);
4048 }
4049 tcg_temp_free(t1);
4050 tcg_temp_free(t0);
4051 gen_partset_reg(OS_WORD, DREG(insn, 0), reg);
4052 set_cc_op(s, CC_OP_FLAGS);
4053 }
4054
4055 DISAS_INSN(rotate_mem)
4056 {
4057 TCGv src;
4058 TCGv addr;
4059 TCGv shift;
4060 int left = (insn & 0x100);
4061
4062 SRC_EA(env, src, OS_WORD, 0, &addr);
4063
4064 shift = tcg_const_i32(1);
4065 if (insn & 0x0200) {
4066 rotate(src, shift, left, 16);
4067 } else {
4068 TCGv X = rotate_x(src, shift, left, 16);
4069 rotate_x_flags(src, X, 16);
4070 tcg_temp_free(X);
4071 }
4072 tcg_temp_free(shift);
4073 DEST_EA(env, insn, OS_WORD, src, &addr);
4074 set_cc_op(s, CC_OP_FLAGS);
4075 }
4076
4077 DISAS_INSN(bfext_reg)
4078 {
4079 int ext = read_im16(env, s);
4080 int is_sign = insn & 0x200;
4081 TCGv src = DREG(insn, 0);
4082 TCGv dst = DREG(ext, 12);
4083 int len = ((extract32(ext, 0, 5) - 1) & 31) + 1;
4084 int ofs = extract32(ext, 6, 5); /* big bit-endian */
4085 int pos = 32 - ofs - len; /* little bit-endian */
4086 TCGv tmp = tcg_temp_new();
4087 TCGv shift;
4088
4089 /*
4090 * In general, we're going to rotate the field so that it's at the
4091 * top of the word and then right-shift by the complement of the
4092 * width to extend the field.
4093 */
4094 if (ext & 0x20) {
4095 /* Variable width. */
4096 if (ext & 0x800) {
4097 /* Variable offset. */
4098 tcg_gen_andi_i32(tmp, DREG(ext, 6), 31);
4099 tcg_gen_rotl_i32(tmp, src, tmp);
4100 } else {
4101 tcg_gen_rotli_i32(tmp, src, ofs);
4102 }
4103
4104 shift = tcg_temp_new();
4105 tcg_gen_neg_i32(shift, DREG(ext, 0));
4106 tcg_gen_andi_i32(shift, shift, 31);
4107 tcg_gen_sar_i32(QREG_CC_N, tmp, shift);
4108 if (is_sign) {
4109 tcg_gen_mov_i32(dst, QREG_CC_N);
4110 } else {
4111 tcg_gen_shr_i32(dst, tmp, shift);
4112 }
4113 tcg_temp_free(shift);
4114 } else {
4115 /* Immediate width. */
4116 if (ext & 0x800) {
4117 /* Variable offset */
4118 tcg_gen_andi_i32(tmp, DREG(ext, 6), 31);
4119 tcg_gen_rotl_i32(tmp, src, tmp);
4120 src = tmp;
4121 pos = 32 - len;
4122 } else {
4123 /*
4124 * Immediate offset. If the field doesn't wrap around the
4125 * end of the word, rely on (s)extract completely.
4126 */
4127 if (pos < 0) {
4128 tcg_gen_rotli_i32(tmp, src, ofs);
4129 src = tmp;
4130 pos = 32 - len;
4131 }
4132 }
4133
4134 tcg_gen_sextract_i32(QREG_CC_N, src, pos, len);
4135 if (is_sign) {
4136 tcg_gen_mov_i32(dst, QREG_CC_N);
4137 } else {
4138 tcg_gen_extract_i32(dst, src, pos, len);
4139 }
4140 }
4141
4142 tcg_temp_free(tmp);
4143 set_cc_op(s, CC_OP_LOGIC);
4144 }
4145
4146 DISAS_INSN(bfext_mem)
4147 {
4148 int ext = read_im16(env, s);
4149 int is_sign = insn & 0x200;
4150 TCGv dest = DREG(ext, 12);
4151 TCGv addr, len, ofs;
4152
4153 addr = gen_lea(env, s, insn, OS_UNSIZED);
4154 if (IS_NULL_QREG(addr)) {
4155 gen_addr_fault(s);
4156 return;
4157 }
4158
4159 if (ext & 0x20) {
4160 len = DREG(ext, 0);
4161 } else {
4162 len = tcg_const_i32(extract32(ext, 0, 5));
4163 }
4164 if (ext & 0x800) {
4165 ofs = DREG(ext, 6);
4166 } else {
4167 ofs = tcg_const_i32(extract32(ext, 6, 5));
4168 }
4169
4170 if (is_sign) {
4171 gen_helper_bfexts_mem(dest, cpu_env, addr, ofs, len);
4172 tcg_gen_mov_i32(QREG_CC_N, dest);
4173 } else {
4174 TCGv_i64 tmp = tcg_temp_new_i64();
4175 gen_helper_bfextu_mem(tmp, cpu_env, addr, ofs, len);
4176 tcg_gen_extr_i64_i32(dest, QREG_CC_N, tmp);
4177 tcg_temp_free_i64(tmp);
4178 }
4179 set_cc_op(s, CC_OP_LOGIC);
4180
4181 if (!(ext & 0x20)) {
4182 tcg_temp_free(len);
4183 }
4184 if (!(ext & 0x800)) {
4185 tcg_temp_free(ofs);
4186 }
4187 }
4188
4189 DISAS_INSN(bfop_reg)
4190 {
4191 int ext = read_im16(env, s);
4192 TCGv src = DREG(insn, 0);
4193 int len = ((extract32(ext, 0, 5) - 1) & 31) + 1;
4194 int ofs = extract32(ext, 6, 5); /* big bit-endian */
4195 TCGv mask, tofs, tlen;
4196
4197 tofs = NULL;
4198 tlen = NULL;
4199 if ((insn & 0x0f00) == 0x0d00) { /* bfffo */
4200 tofs = tcg_temp_new();
4201 tlen = tcg_temp_new();
4202 }
4203
4204 if ((ext & 0x820) == 0) {
4205 /* Immediate width and offset. */
4206 uint32_t maski = 0x7fffffffu >> (len - 1);
4207 if (ofs + len <= 32) {
4208 tcg_gen_shli_i32(QREG_CC_N, src, ofs);
4209 } else {
4210 tcg_gen_rotli_i32(QREG_CC_N, src, ofs);
4211 }
4212 tcg_gen_andi_i32(QREG_CC_N, QREG_CC_N, ~maski);
4213 mask = tcg_const_i32(ror32(maski, ofs));
4214 if (tofs) {
4215 tcg_gen_movi_i32(tofs, ofs);
4216 tcg_gen_movi_i32(tlen, len);
4217 }
4218 } else {
4219 TCGv tmp = tcg_temp_new();
4220 if (ext & 0x20) {
4221 /* Variable width */
4222 tcg_gen_subi_i32(tmp, DREG(ext, 0), 1);
4223 tcg_gen_andi_i32(tmp, tmp, 31);
4224 mask = tcg_const_i32(0x7fffffffu);
4225 tcg_gen_shr_i32(mask, mask, tmp);
4226 if (tlen) {
4227 tcg_gen_addi_i32(tlen, tmp, 1);
4228 }
4229 } else {
4230 /* Immediate width */
4231 mask = tcg_const_i32(0x7fffffffu >> (len - 1));
4232 if (tlen) {
4233 tcg_gen_movi_i32(tlen, len);
4234 }
4235 }
4236 if (ext & 0x800) {
4237 /* Variable offset */
4238 tcg_gen_andi_i32(tmp, DREG(ext, 6), 31);
4239 tcg_gen_rotl_i32(QREG_CC_N, src, tmp);
4240 tcg_gen_andc_i32(QREG_CC_N, QREG_CC_N, mask);
4241 tcg_gen_rotr_i32(mask, mask, tmp);
4242 if (tofs) {
4243 tcg_gen_mov_i32(tofs, tmp);
4244 }
4245 } else {
4246 /* Immediate offset (and variable width) */
4247 tcg_gen_rotli_i32(QREG_CC_N, src, ofs);
4248 tcg_gen_andc_i32(QREG_CC_N, QREG_CC_N, mask);
4249 tcg_gen_rotri_i32(mask, mask, ofs);
4250 if (tofs) {
4251 tcg_gen_movi_i32(tofs, ofs);
4252 }
4253 }
4254 tcg_temp_free(tmp);
4255 }
4256 set_cc_op(s, CC_OP_LOGIC);
4257
4258 switch (insn & 0x0f00) {
4259 case 0x0a00: /* bfchg */
4260 tcg_gen_eqv_i32(src, src, mask);
4261 break;
4262 case 0x0c00: /* bfclr */
4263 tcg_gen_and_i32(src, src, mask);
4264 break;
4265 case 0x0d00: /* bfffo */
4266 gen_helper_bfffo_reg(DREG(ext, 12), QREG_CC_N, tofs, tlen);
4267 tcg_temp_free(tlen);
4268 tcg_temp_free(tofs);
4269 break;
4270 case 0x0e00: /* bfset */
4271 tcg_gen_orc_i32(src, src, mask);
4272 break;
4273 case 0x0800: /* bftst */
4274 /* flags already set; no other work to do. */
4275 break;
4276 default:
4277 g_assert_not_reached();
4278 }
4279 tcg_temp_free(mask);
4280 }
4281
4282 DISAS_INSN(bfop_mem)
4283 {
4284 int ext = read_im16(env, s);
4285 TCGv addr, len, ofs;
4286 TCGv_i64 t64;
4287
4288 addr = gen_lea(env, s, insn, OS_UNSIZED);
4289 if (IS_NULL_QREG(addr)) {
4290 gen_addr_fault(s);
4291 return;
4292 }
4293
4294 if (ext & 0x20) {
4295 len = DREG(ext, 0);
4296 } else {
4297 len = tcg_const_i32(extract32(ext, 0, 5));
4298 }
4299 if (ext & 0x800) {
4300 ofs = DREG(ext, 6);
4301 } else {
4302 ofs = tcg_const_i32(extract32(ext, 6, 5));
4303 }
4304
4305 switch (insn & 0x0f00) {
4306 case 0x0a00: /* bfchg */
4307 gen_helper_bfchg_mem(QREG_CC_N, cpu_env, addr, ofs, len);
4308 break;
4309 case 0x0c00: /* bfclr */
4310 gen_helper_bfclr_mem(QREG_CC_N, cpu_env, addr, ofs, len);
4311 break;
4312 case 0x0d00: /* bfffo */
4313 t64 = tcg_temp_new_i64();
4314 gen_helper_bfffo_mem(t64, cpu_env, addr, ofs, len);
4315 tcg_gen_extr_i64_i32(DREG(ext, 12), QREG_CC_N, t64);
4316 tcg_temp_free_i64(t64);
4317 break;
4318 case 0x0e00: /* bfset */
4319 gen_helper_bfset_mem(QREG_CC_N, cpu_env, addr, ofs, len);
4320 break;
4321 case 0x0800: /* bftst */
4322 gen_helper_bfexts_mem(QREG_CC_N, cpu_env, addr, ofs, len);
4323 break;
4324 default:
4325 g_assert_not_reached();
4326 }
4327 set_cc_op(s, CC_OP_LOGIC);
4328
4329 if (!(ext & 0x20)) {
4330 tcg_temp_free(len);
4331 }
4332 if (!(ext & 0x800)) {
4333 tcg_temp_free(ofs);
4334 }
4335 }
4336
4337 DISAS_INSN(bfins_reg)
4338 {
4339 int ext = read_im16(env, s);
4340 TCGv dst = DREG(insn, 0);
4341 TCGv src = DREG(ext, 12);
4342 int len = ((extract32(ext, 0, 5) - 1) & 31) + 1;
4343 int ofs = extract32(ext, 6, 5); /* big bit-endian */
4344 int pos = 32 - ofs - len; /* little bit-endian */
4345 TCGv tmp;
4346
4347 tmp = tcg_temp_new();
4348
4349 if (ext & 0x20) {
4350 /* Variable width */
4351 tcg_gen_neg_i32(tmp, DREG(ext, 0));
4352 tcg_gen_andi_i32(tmp, tmp, 31);
4353 tcg_gen_shl_i32(QREG_CC_N, src, tmp);
4354 } else {
4355 /* Immediate width */
4356 tcg_gen_shli_i32(QREG_CC_N, src, 32 - len);
4357 }
4358 set_cc_op(s, CC_OP_LOGIC);
4359
4360 /* Immediate width and offset */
4361 if ((ext & 0x820) == 0) {
4362 /* Check for suitability for deposit. */
4363 if (pos >= 0) {
4364 tcg_gen_deposit_i32(dst, dst, src, pos, len);
4365 } else {
4366 uint32_t maski = -2U << (len - 1);
4367 uint32_t roti = (ofs + len) & 31;
4368 tcg_gen_andi_i32(tmp, src, ~maski);
4369 tcg_gen_rotri_i32(tmp, tmp, roti);
4370 tcg_gen_andi_i32(dst, dst, ror32(maski, roti));
4371 tcg_gen_or_i32(dst, dst, tmp);
4372 }
4373 } else {
4374 TCGv mask = tcg_temp_new();
4375 TCGv rot = tcg_temp_new();
4376
4377 if (ext & 0x20) {
4378 /* Variable width */
4379 tcg_gen_subi_i32(rot, DREG(ext, 0), 1);
4380 tcg_gen_andi_i32(rot, rot, 31);
4381 tcg_gen_movi_i32(mask, -2);
4382 tcg_gen_shl_i32(mask, mask, rot);
4383 tcg_gen_mov_i32(rot, DREG(ext, 0));
4384 tcg_gen_andc_i32(tmp, src, mask);
4385 } else {
4386 /* Immediate width (variable offset) */
4387 uint32_t maski = -2U << (len - 1);
4388 tcg_gen_andi_i32(tmp, src, ~maski);
4389 tcg_gen_movi_i32(mask, maski);
4390 tcg_gen_movi_i32(rot, len & 31);
4391 }
4392 if (ext & 0x800) {
4393 /* Variable offset */
4394 tcg_gen_add_i32(rot, rot, DREG(ext, 6));
4395 } else {
4396 /* Immediate offset (variable width) */
4397 tcg_gen_addi_i32(rot, rot, ofs);
4398 }
4399 tcg_gen_andi_i32(rot, rot, 31);
4400 tcg_gen_rotr_i32(mask, mask, rot);
4401 tcg_gen_rotr_i32(tmp, tmp, rot);
4402 tcg_gen_and_i32(dst, dst, mask);
4403 tcg_gen_or_i32(dst, dst, tmp);
4404
4405 tcg_temp_free(rot);
4406 tcg_temp_free(mask);
4407 }
4408 tcg_temp_free(tmp);
4409 }
4410
4411 DISAS_INSN(bfins_mem)
4412 {
4413 int ext = read_im16(env, s);
4414 TCGv src = DREG(ext, 12);
4415 TCGv addr, len, ofs;
4416
4417 addr = gen_lea(env, s, insn, OS_UNSIZED);
4418 if (IS_NULL_QREG(addr)) {
4419 gen_addr_fault(s);
4420 return;
4421 }
4422
4423 if (ext & 0x20) {
4424 len = DREG(ext, 0);
4425 } else {
4426 len = tcg_const_i32(extract32(ext, 0, 5));
4427 }
4428 if (ext & 0x800) {
4429 ofs = DREG(ext, 6);
4430 } else {
4431 ofs = tcg_const_i32(extract32(ext, 6, 5));
4432 }
4433
4434 gen_helper_bfins_mem(QREG_CC_N, cpu_env, addr, src, ofs, len);
4435 set_cc_op(s, CC_OP_LOGIC);
4436
4437 if (!(ext & 0x20)) {
4438 tcg_temp_free(len);
4439 }
4440 if (!(ext & 0x800)) {
4441 tcg_temp_free(ofs);
4442 }
4443 }
4444
4445 DISAS_INSN(ff1)
4446 {
4447 TCGv reg;
4448 reg = DREG(insn, 0);
4449 gen_logic_cc(s, reg, OS_LONG);
4450 gen_helper_ff1(reg, reg);
4451 }
4452
4453 DISAS_INSN(chk)
4454 {
4455 TCGv src, reg;
4456 int opsize;
4457
4458 switch ((insn >> 7) & 3) {
4459 case 3:
4460 opsize = OS_WORD;
4461 break;
4462 case 2:
4463 if (m68k_feature(env, M68K_FEATURE_CHK2)) {
4464 opsize = OS_LONG;
4465 break;
4466 }
4467 /* fallthru */
4468 default:
4469 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
4470 return;
4471 }
4472 SRC_EA(env, src, opsize, 1, NULL);
4473 reg = gen_extend(s, DREG(insn, 9), opsize, 1);
4474
4475 gen_flush_flags(s);
4476 gen_helper_chk(cpu_env, reg, src);
4477 }
4478
4479 DISAS_INSN(chk2)
4480 {
4481 uint16_t ext;
4482 TCGv addr1, addr2, bound1, bound2, reg;
4483 int opsize;
4484
4485 switch ((insn >> 9) & 3) {
4486 case 0:
4487 opsize = OS_BYTE;
4488 break;
4489 case 1:
4490 opsize = OS_WORD;
4491 break;
4492 case 2:
4493 opsize = OS_LONG;
4494 break;
4495 default:
4496 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
4497 return;
4498 }
4499
4500 ext = read_im16(env, s);
4501 if ((ext & 0x0800) == 0) {
4502 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
4503 return;
4504 }
4505
4506 addr1 = gen_lea(env, s, insn, OS_UNSIZED);
4507 addr2 = tcg_temp_new();
4508 tcg_gen_addi_i32(addr2, addr1, opsize_bytes(opsize));
4509
4510 bound1 = gen_load(s, opsize, addr1, 1, IS_USER(s));
4511 tcg_temp_free(addr1);
4512 bound2 = gen_load(s, opsize, addr2, 1, IS_USER(s));
4513 tcg_temp_free(addr2);
4514
4515 reg = tcg_temp_new();
4516 if (ext & 0x8000) {
4517 tcg_gen_mov_i32(reg, AREG(ext, 12));
4518 } else {
4519 gen_ext(reg, DREG(ext, 12), opsize, 1);
4520 }
4521
4522 gen_flush_flags(s);
4523 gen_helper_chk2(cpu_env, reg, bound1, bound2);
4524 tcg_temp_free(reg);
4525 tcg_temp_free(bound1);
4526 tcg_temp_free(bound2);
4527 }
4528
4529 static void m68k_copy_line(TCGv dst, TCGv src, int index)
4530 {
4531 TCGv addr;
4532 TCGv_i64 t0, t1;
4533
4534 addr = tcg_temp_new();
4535
4536 t0 = tcg_temp_new_i64();
4537 t1 = tcg_temp_new_i64();
4538
4539 tcg_gen_andi_i32(addr, src, ~15);
4540 tcg_gen_qemu_ld64(t0, addr, index);
4541 tcg_gen_addi_i32(addr, addr, 8);
4542 tcg_gen_qemu_ld64(t1, addr, index);
4543
4544 tcg_gen_andi_i32(addr, dst, ~15);
4545 tcg_gen_qemu_st64(t0, addr, index);
4546 tcg_gen_addi_i32(addr, addr, 8);
4547 tcg_gen_qemu_st64(t1, addr, index);
4548
4549 tcg_temp_free_i64(t0);
4550 tcg_temp_free_i64(t1);
4551 tcg_temp_free(addr);
4552 }
4553
4554 DISAS_INSN(move16_reg)
4555 {
4556 int index = IS_USER(s);
4557 TCGv tmp;
4558 uint16_t ext;
4559
4560 ext = read_im16(env, s);
4561 if ((ext & (1 << 15)) == 0) {
4562 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
4563 }
4564
4565 m68k_copy_line(AREG(ext, 12), AREG(insn, 0), index);
4566
4567 /* Ax can be Ay, so save Ay before incrementing Ax */
4568 tmp = tcg_temp_new();
4569 tcg_gen_mov_i32(tmp, AREG(ext, 12));
4570 tcg_gen_addi_i32(AREG(insn, 0), AREG(insn, 0), 16);
4571 tcg_gen_addi_i32(AREG(ext, 12), tmp, 16);
4572 tcg_temp_free(tmp);
4573 }
4574
4575 DISAS_INSN(move16_mem)
4576 {
4577 int index = IS_USER(s);
4578 TCGv reg, addr;
4579
4580 reg = AREG(insn, 0);
4581 addr = tcg_const_i32(read_im32(env, s));
4582
4583 if ((insn >> 3) & 1) {
4584 /* MOVE16 (xxx).L, (Ay) */
4585 m68k_copy_line(reg, addr, index);
4586 } else {
4587 /* MOVE16 (Ay), (xxx).L */
4588 m68k_copy_line(addr, reg, index);
4589 }
4590
4591 tcg_temp_free(addr);
4592
4593 if (((insn >> 3) & 2) == 0) {
4594 /* (Ay)+ */
4595 tcg_gen_addi_i32(reg, reg, 16);
4596 }
4597 }
4598
4599 DISAS_INSN(strldsr)
4600 {
4601 uint16_t ext;
4602 uint32_t addr;
4603
4604 addr = s->pc - 2;
4605 ext = read_im16(env, s);
4606 if (ext != 0x46FC) {
4607 gen_exception(s, addr, EXCP_ILLEGAL);
4608 return;
4609 }
4610 ext = read_im16(env, s);
4611 if (IS_USER(s) || (ext & SR_S) == 0) {
4612 gen_exception(s, addr, EXCP_PRIVILEGE);
4613 return;
4614 }
4615 gen_push(s, gen_get_sr(s));
4616 gen_set_sr_im(s, ext, 0);
4617 }
4618
4619 DISAS_INSN(move_from_sr)
4620 {
4621 TCGv sr;
4622
4623 if (IS_USER(s) && !m68k_feature(env, M68K_FEATURE_M68K)) {
4624 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4625 return;
4626 }
4627 sr = gen_get_sr(s);
4628 DEST_EA(env, insn, OS_WORD, sr, NULL);
4629 }
4630
4631 #if defined(CONFIG_SOFTMMU)
4632 DISAS_INSN(moves)
4633 {
4634 int opsize;
4635 uint16_t ext;
4636 TCGv reg;
4637 TCGv addr;
4638 int extend;
4639
4640 if (IS_USER(s)) {
4641 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4642 return;
4643 }
4644
4645 ext = read_im16(env, s);
4646
4647 opsize = insn_opsize(insn);
4648
4649 if (ext & 0x8000) {
4650 /* address register */
4651 reg = AREG(ext, 12);
4652 extend = 1;
4653 } else {
4654 /* data register */
4655 reg = DREG(ext, 12);
4656 extend = 0;
4657 }
4658
4659 addr = gen_lea(env, s, insn, opsize);
4660 if (IS_NULL_QREG(addr)) {
4661 gen_addr_fault(s);
4662 return;
4663 }
4664
4665 if (ext & 0x0800) {
4666 /* from reg to ea */
4667 gen_store(s, opsize, addr, reg, DFC_INDEX(s));
4668 } else {
4669 /* from ea to reg */
4670 TCGv tmp = gen_load(s, opsize, addr, 0, SFC_INDEX(s));
4671 if (extend) {
4672 gen_ext(reg, tmp, opsize, 1);
4673 } else {
4674 gen_partset_reg(opsize, reg, tmp);
4675 }
4676 tcg_temp_free(tmp);
4677 }
4678 switch (extract32(insn, 3, 3)) {
4679 case 3: /* Indirect postincrement. */
4680 tcg_gen_addi_i32(AREG(insn, 0), addr,
4681 REG(insn, 0) == 7 && opsize == OS_BYTE
4682 ? 2
4683 : opsize_bytes(opsize));
4684 break;
4685 case 4: /* Indirect predecrememnt. */
4686 tcg_gen_mov_i32(AREG(insn, 0), addr);
4687 break;
4688 }
4689 }
4690
4691 DISAS_INSN(move_to_sr)
4692 {
4693 if (IS_USER(s)) {
4694 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4695 return;
4696 }
4697 gen_move_to_sr(env, s, insn, false);
4698 gen_exit_tb(s);
4699 }
4700
4701 DISAS_INSN(move_from_usp)
4702 {
4703 if (IS_USER(s)) {
4704 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4705 return;
4706 }
4707 tcg_gen_ld_i32(AREG(insn, 0), cpu_env,
4708 offsetof(CPUM68KState, sp[M68K_USP]));
4709 }
4710
4711 DISAS_INSN(move_to_usp)
4712 {
4713 if (IS_USER(s)) {
4714 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4715 return;
4716 }
4717 tcg_gen_st_i32(AREG(insn, 0), cpu_env,
4718 offsetof(CPUM68KState, sp[M68K_USP]));
4719 }
4720
4721 DISAS_INSN(halt)
4722 {
4723 if (IS_USER(s)) {
4724 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4725 return;
4726 }
4727
4728 gen_exception(s, s->pc, EXCP_HALT_INSN);
4729 }
4730
4731 DISAS_INSN(stop)
4732 {
4733 uint16_t ext;
4734
4735 if (IS_USER(s)) {
4736 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4737 return;
4738 }
4739
4740 ext = read_im16(env, s);
4741
4742 gen_set_sr_im(s, ext, 0);
4743 tcg_gen_movi_i32(cpu_halted, 1);
4744 gen_exception(s, s->pc, EXCP_HLT);
4745 }
4746
4747 DISAS_INSN(rte)
4748 {
4749 if (IS_USER(s)) {
4750 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4751 return;
4752 }
4753 gen_exception(s, s->base.pc_next, EXCP_RTE);
4754 }
4755
4756 DISAS_INSN(cf_movec)
4757 {
4758 uint16_t ext;
4759 TCGv reg;
4760
4761 if (IS_USER(s)) {
4762 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4763 return;
4764 }
4765
4766 ext = read_im16(env, s);
4767
4768 if (ext & 0x8000) {
4769 reg = AREG(ext, 12);
4770 } else {
4771 reg = DREG(ext, 12);
4772 }
4773 gen_helper_cf_movec_to(cpu_env, tcg_const_i32(ext & 0xfff), reg);
4774 gen_exit_tb(s);
4775 }
4776
4777 DISAS_INSN(m68k_movec)
4778 {
4779 uint16_t ext;
4780 TCGv reg;
4781
4782 if (IS_USER(s)) {
4783 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4784 return;
4785 }
4786
4787 ext = read_im16(env, s);
4788
4789 if (ext & 0x8000) {
4790 reg = AREG(ext, 12);
4791 } else {
4792 reg = DREG(ext, 12);
4793 }
4794 if (insn & 1) {
4795 gen_helper_m68k_movec_to(cpu_env, tcg_const_i32(ext & 0xfff), reg);
4796 } else {
4797 gen_helper_m68k_movec_from(reg, cpu_env, tcg_const_i32(ext & 0xfff));
4798 }
4799 gen_exit_tb(s);
4800 }
4801
4802 DISAS_INSN(intouch)
4803 {
4804 if (IS_USER(s)) {
4805 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4806 return;
4807 }
4808 /* ICache fetch. Implement as no-op. */
4809 }
4810
4811 DISAS_INSN(cpushl)
4812 {
4813 if (IS_USER(s)) {
4814 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4815 return;
4816 }
4817 /* Cache push/invalidate. Implement as no-op. */
4818 }
4819
4820 DISAS_INSN(cpush)
4821 {
4822 if (IS_USER(s)) {
4823 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4824 return;
4825 }
4826 /* Cache push/invalidate. Implement as no-op. */
4827 }
4828
4829 DISAS_INSN(cinv)
4830 {
4831 if (IS_USER(s)) {
4832 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4833 return;
4834 }
4835 /* Invalidate cache line. Implement as no-op. */
4836 }
4837
4838 #if defined(CONFIG_SOFTMMU)
4839 DISAS_INSN(pflush)
4840 {
4841 TCGv opmode;
4842
4843 if (IS_USER(s)) {
4844 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4845 return;
4846 }
4847
4848 opmode = tcg_const_i32((insn >> 3) & 3);
4849 gen_helper_pflush(cpu_env, AREG(insn, 0), opmode);
4850 tcg_temp_free(opmode);
4851 }
4852
4853 DISAS_INSN(ptest)
4854 {
4855 TCGv is_read;
4856
4857 if (IS_USER(s)) {
4858 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4859 return;
4860 }
4861 is_read = tcg_const_i32((insn >> 5) & 1);
4862 gen_helper_ptest(cpu_env, AREG(insn, 0), is_read);
4863 tcg_temp_free(is_read);
4864 }
4865 #endif
4866
4867 DISAS_INSN(wddata)
4868 {
4869 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4870 }
4871
4872 DISAS_INSN(wdebug)
4873 {
4874 if (IS_USER(s)) {
4875 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4876 return;
4877 }
4878 /* TODO: Implement wdebug. */
4879 cpu_abort(env_cpu(env), "WDEBUG not implemented");
4880 }
4881 #endif
4882
4883 DISAS_INSN(trap)
4884 {
4885 gen_exception(s, s->pc, EXCP_TRAP0 + (insn & 0xf));
4886 }
4887
4888 static void do_trapcc(DisasContext *s, DisasCompare *c)
4889 {
4890 if (c->tcond != TCG_COND_NEVER) {
4891 TCGLabel *over = NULL;
4892
4893 update_cc_op(s);
4894
4895 if (c->tcond != TCG_COND_ALWAYS) {
4896 /* Jump over if !c. */
4897 over = gen_new_label();
4898 tcg_gen_brcond_i32(tcg_invert_cond(c->tcond), c->v1, c->v2, over);
4899 }
4900
4901 tcg_gen_movi_i32(QREG_PC, s->pc);
4902 gen_raise_exception_format2(s, EXCP_TRAPCC, s->base.pc_next);
4903
4904 if (over != NULL) {
4905 gen_set_label(over);
4906 s->base.is_jmp = DISAS_NEXT;
4907 }
4908 }
4909 free_cond(c);
4910 }
4911
4912 DISAS_INSN(trapcc)
4913 {
4914 DisasCompare c;
4915
4916 /* Consume and discard the immediate operand. */
4917 switch (extract32(insn, 0, 3)) {
4918 case 2: /* trapcc.w */
4919 (void)read_im16(env, s);
4920 break;
4921 case 3: /* trapcc.l */
4922 (void)read_im32(env, s);
4923 break;
4924 case 4: /* trapcc (no operand) */
4925 break;
4926 default:
4927 /* trapcc registered with only valid opmodes */
4928 g_assert_not_reached();
4929 }
4930
4931 gen_cc_cond(&c, s, extract32(insn, 8, 4));
4932 do_trapcc(s, &c);
4933 }
4934
4935 DISAS_INSN(trapv)
4936 {
4937 DisasCompare c;
4938
4939 gen_cc_cond(&c, s, 9); /* V set */
4940 do_trapcc(s, &c);
4941 }
4942
4943 static void gen_load_fcr(DisasContext *s, TCGv res, int reg)
4944 {
4945 switch (reg) {
4946 case M68K_FPIAR:
4947 tcg_gen_movi_i32(res, 0);
4948 break;
4949 case M68K_FPSR:
4950 tcg_gen_ld_i32(res, cpu_env, offsetof(CPUM68KState, fpsr));
4951 break;
4952 case M68K_FPCR:
4953 tcg_gen_ld_i32(res, cpu_env, offsetof(CPUM68KState, fpcr));
4954 break;
4955 }
4956 }
4957
4958 static void gen_store_fcr(DisasContext *s, TCGv val, int reg)
4959 {
4960 switch (reg) {
4961 case M68K_FPIAR:
4962 break;
4963 case M68K_FPSR:
4964 tcg_gen_st_i32(val, cpu_env, offsetof(CPUM68KState, fpsr));
4965 break;
4966 case M68K_FPCR:
4967 gen_helper_set_fpcr(cpu_env, val);
4968 break;
4969 }
4970 }
4971
4972 static void gen_qemu_store_fcr(DisasContext *s, TCGv addr, int reg)
4973 {
4974 int index = IS_USER(s);
4975 TCGv tmp;
4976
4977 tmp = tcg_temp_new();
4978 gen_load_fcr(s, tmp, reg);
4979 tcg_gen_qemu_st32(tmp, addr, index);
4980 tcg_temp_free(tmp);
4981 }
4982
4983 static void gen_qemu_load_fcr(DisasContext *s, TCGv addr, int reg)
4984 {
4985 int index = IS_USER(s);
4986 TCGv tmp;
4987
4988 tmp = tcg_temp_new();
4989 tcg_gen_qemu_ld32u(tmp, addr, index);
4990 gen_store_fcr(s, tmp, reg);
4991 tcg_temp_free(tmp);
4992 }
4993
4994
4995 static void gen_op_fmove_fcr(CPUM68KState *env, DisasContext *s,
4996 uint32_t insn, uint32_t ext)
4997 {
4998 int mask = (ext >> 10) & 7;
4999 int is_write = (ext >> 13) & 1;
5000 int mode = extract32(insn, 3, 3);
5001 int i;
5002 TCGv addr, tmp;
5003
5004 switch (mode) {
5005 case 0: /* Dn */
5006 if (mask != M68K_FPIAR && mask != M68K_FPSR && mask != M68K_FPCR) {
5007 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
5008 return;
5009 }
5010 if (is_write) {
5011 gen_load_fcr(s, DREG(insn, 0), mask);
5012 } else {
5013 gen_store_fcr(s, DREG(insn, 0), mask);
5014 }
5015 return;
5016 case 1: /* An, only with FPIAR */
5017 if (mask != M68K_FPIAR) {
5018 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
5019 return;
5020 }
5021 if (is_write) {
5022 gen_load_fcr(s, AREG(insn, 0), mask);
5023 } else {
5024 gen_store_fcr(s, AREG(insn, 0), mask);
5025 }
5026 return;
5027 case 7: /* Immediate */
5028 if (REG(insn, 0) == 4) {
5029 if (is_write ||
5030 (mask != M68K_FPIAR && mask != M68K_FPSR &&
5031 mask != M68K_FPCR)) {
5032 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
5033 return;
5034 }
5035 tmp = tcg_const_i32(read_im32(env, s));
5036 gen_store_fcr(s, tmp, mask);
5037 tcg_temp_free(tmp);
5038 return;
5039 }
5040 break;
5041 default:
5042 break;
5043 }
5044
5045 tmp = gen_lea(env, s, insn, OS_LONG);
5046 if (IS_NULL_QREG(tmp)) {
5047 gen_addr_fault(s);
5048 return;
5049 }
5050
5051 addr = tcg_temp_new();
5052 tcg_gen_mov_i32(addr, tmp);
5053
5054 /*
5055 * mask:
5056 *
5057 * 0b100 Floating-Point Control Register
5058 * 0b010 Floating-Point Status Register
5059 * 0b001 Floating-Point Instruction Address Register
5060 *
5061 */
5062
5063 if (is_write && mode == 4) {
5064 for (i = 2; i >= 0; i--, mask >>= 1) {
5065 if (mask & 1) {
5066 gen_qemu_store_fcr(s, addr, 1 << i);
5067 if (mask != 1) {
5068 tcg_gen_subi_i32(addr, addr, opsize_bytes(OS_LONG));
5069 }
5070 }
5071 }
5072 tcg_gen_mov_i32(AREG(insn, 0), addr);
5073 } else {
5074 for (i = 0; i < 3; i++, mask >>= 1) {
5075 if (mask & 1) {
5076 if (is_write) {
5077 gen_qemu_store_fcr(s, addr, 1 << i);
5078 } else {
5079 gen_qemu_load_fcr(s, addr, 1 << i);
5080 }
5081 if (mask != 1 || mode == 3) {
5082 tcg_gen_addi_i32(addr, addr, opsize_bytes(OS_LONG));
5083 }
5084 }
5085 }
5086 if (mode == 3) {
5087 tcg_gen_mov_i32(AREG(insn, 0), addr);
5088 }
5089 }
5090 tcg_temp_free_i32(addr);
5091 }
5092
5093 static void gen_op_fmovem(CPUM68KState *env, DisasContext *s,
5094 uint32_t insn, uint32_t ext)
5095 {
5096 int opsize;
5097 TCGv addr, tmp;
5098 int mode = (ext >> 11) & 0x3;
5099 int is_load = ((ext & 0x2000) == 0);
5100
5101 if (m68k_feature(s->env, M68K_FEATURE_FPU)) {
5102 opsize = OS_EXTENDED;
5103 } else {
5104 opsize = OS_DOUBLE; /* FIXME */
5105 }
5106
5107 addr = gen_lea(env, s, insn, opsize);
5108 if (IS_NULL_QREG(addr)) {
5109 gen_addr_fault(s);
5110 return;
5111 }
5112
5113 tmp = tcg_temp_new();
5114 if (mode & 0x1) {
5115 /* Dynamic register list */
5116 tcg_gen_ext8u_i32(tmp, DREG(ext, 4));
5117 } else {
5118 /* Static register list */
5119 tcg_gen_movi_i32(tmp, ext & 0xff);
5120 }
5121
5122 if (!is_load && (mode & 2) == 0) {
5123 /*
5124 * predecrement addressing mode
5125 * only available to store register to memory
5126 */
5127 if (opsize == OS_EXTENDED) {
5128 gen_helper_fmovemx_st_predec(tmp, cpu_env, addr, tmp);
5129 } else {
5130 gen_helper_fmovemd_st_predec(tmp, cpu_env, addr, tmp);
5131 }
5132 } else {
5133 /* postincrement addressing mode */
5134 if (opsize == OS_EXTENDED) {
5135 if (is_load) {
5136 gen_helper_fmovemx_ld_postinc(tmp, cpu_env, addr, tmp);
5137 } else {
5138 gen_helper_fmovemx_st_postinc(tmp, cpu_env, addr, tmp);
5139 }
5140 } else {
5141 if (is_load) {
5142 gen_helper_fmovemd_ld_postinc(tmp, cpu_env, addr, tmp);
5143 } else {
5144 gen_helper_fmovemd_st_postinc(tmp, cpu_env, addr, tmp);
5145 }
5146 }
5147 }
5148 if ((insn & 070) == 030 || (insn & 070) == 040) {
5149 tcg_gen_mov_i32(AREG(insn, 0), tmp);
5150 }
5151 tcg_temp_free(tmp);
5152 }
5153
5154 /*
5155 * ??? FP exceptions are not implemented. Most exceptions are deferred until
5156 * immediately before the next FP instruction is executed.
5157 */
5158 DISAS_INSN(fpu)
5159 {
5160 uint16_t ext;
5161 int opmode;
5162 int opsize;
5163 TCGv_ptr cpu_src, cpu_dest;
5164
5165 ext = read_im16(env, s);
5166 opmode = ext & 0x7f;
5167 switch ((ext >> 13) & 7) {
5168 case 0:
5169 break;
5170 case 1:
5171 goto undef;
5172 case 2:
5173 if (insn == 0xf200 && (ext & 0xfc00) == 0x5c00) {
5174 /* fmovecr */
5175 TCGv rom_offset = tcg_const_i32(opmode);
5176 cpu_dest = gen_fp_ptr(REG(ext, 7));
5177 gen_helper_fconst(cpu_env, cpu_dest, rom_offset);
5178 tcg_temp_free_ptr(cpu_dest);
5179 tcg_temp_free(rom_offset);
5180 return;
5181 }
5182 break;
5183 case 3: /* fmove out */
5184 cpu_src = gen_fp_ptr(REG(ext, 7));
5185 opsize = ext_opsize(ext, 10);
5186 if (gen_ea_fp(env, s, insn, opsize, cpu_src,
5187 EA_STORE, IS_USER(s)) == -1) {
5188 gen_addr_fault(s);
5189 }
5190 gen_helper_ftst(cpu_env, cpu_src);
5191 tcg_temp_free_ptr(cpu_src);
5192 return;
5193 case 4: /* fmove to control register. */
5194 case 5: /* fmove from control register. */
5195 gen_op_fmove_fcr(env, s, insn, ext);
5196 return;
5197 case 6: /* fmovem */
5198 case 7:
5199 if ((ext & 0x1000) == 0 && !m68k_feature(s->env, M68K_FEATURE_FPU)) {
5200 goto undef;
5201 }
5202 gen_op_fmovem(env, s, insn, ext);
5203 return;
5204 }
5205 if (ext & (1 << 14)) {
5206 /* Source effective address. */
5207 opsize = ext_opsize(ext, 10);
5208 cpu_src = gen_fp_result_ptr();
5209 if (gen_ea_fp(env, s, insn, opsize, cpu_src,
5210 EA_LOADS, IS_USER(s)) == -1) {
5211 gen_addr_fault(s);
5212 return;
5213 }
5214 } else {
5215 /* Source register. */
5216 opsize = OS_EXTENDED;
5217 cpu_src = gen_fp_ptr(REG(ext, 10));
5218 }
5219 cpu_dest = gen_fp_ptr(REG(ext, 7));
5220 switch (opmode) {
5221 case 0: /* fmove */
5222 gen_fp_move(cpu_dest, cpu_src);
5223 break;
5224 case 0x40: /* fsmove */
5225 gen_helper_fsround(cpu_env, cpu_dest, cpu_src);
5226 break;
5227 case 0x44: /* fdmove */
5228 gen_helper_fdround(cpu_env, cpu_dest, cpu_src);
5229 break;
5230 case 1: /* fint */
5231 gen_helper_firound(cpu_env, cpu_dest, cpu_src);
5232 break;
5233 case 2: /* fsinh */
5234 gen_helper_fsinh(cpu_env, cpu_dest, cpu_src);
5235 break;
5236 case 3: /* fintrz */
5237 gen_helper_fitrunc(cpu_env, cpu_dest, cpu_src);
5238 break;
5239 case 4: /* fsqrt */
5240 gen_helper_fsqrt(cpu_env, cpu_dest, cpu_src);
5241 break;
5242 case 0x41: /* fssqrt */
5243 gen_helper_fssqrt(cpu_env, cpu_dest, cpu_src);
5244 break;
5245 case 0x45: /* fdsqrt */
5246 gen_helper_fdsqrt(cpu_env, cpu_dest, cpu_src);
5247 break;
5248 case 0x06: /* flognp1 */
5249 gen_helper_flognp1(cpu_env, cpu_dest, cpu_src);
5250 break;
5251 case 0x08: /* fetoxm1 */
5252 gen_helper_fetoxm1(cpu_env, cpu_dest, cpu_src);
5253 break;
5254 case 0x09: /* ftanh */
5255 gen_helper_ftanh(cpu_env, cpu_dest, cpu_src);
5256 break;
5257 case 0x0a: /* fatan */
5258 gen_helper_fatan(cpu_env, cpu_dest, cpu_src);
5259 break;
5260 case 0x0c: /* fasin */
5261 gen_helper_fasin(cpu_env, cpu_dest, cpu_src);
5262 break;
5263 case 0x0d: /* fatanh */
5264 gen_helper_fatanh(cpu_env, cpu_dest, cpu_src);
5265 break;
5266 case 0x0e: /* fsin */
5267 gen_helper_fsin(cpu_env, cpu_dest, cpu_src);
5268 break;
5269 case 0x0f: /* ftan */
5270 gen_helper_ftan(cpu_env, cpu_dest, cpu_src);
5271 break;
5272 case 0x10: /* fetox */
5273 gen_helper_fetox(cpu_env, cpu_dest, cpu_src);
5274 break;
5275 case 0x11: /* ftwotox */
5276 gen_helper_ftwotox(cpu_env, cpu_dest, cpu_src);
5277 break;
5278 case 0x12: /* ftentox */
5279 gen_helper_ftentox(cpu_env, cpu_dest, cpu_src);
5280 break;
5281 case 0x14: /* flogn */
5282 gen_helper_flogn(cpu_env, cpu_dest, cpu_src);
5283 break;
5284 case 0x15: /* flog10 */
5285 gen_helper_flog10(cpu_env, cpu_dest, cpu_src);
5286 break;
5287 case 0x16: /* flog2 */
5288 gen_helper_flog2(cpu_env, cpu_dest, cpu_src);
5289 break;
5290 case 0x18: /* fabs */
5291 gen_helper_fabs(cpu_env, cpu_dest, cpu_src);
5292 break;
5293 case 0x58: /* fsabs */
5294 gen_helper_fsabs(cpu_env, cpu_dest, cpu_src);
5295 break;
5296 case 0x5c: /* fdabs */
5297 gen_helper_fdabs(cpu_env, cpu_dest, cpu_src);
5298 break;
5299 case 0x19: /* fcosh */
5300 gen_helper_fcosh(cpu_env, cpu_dest, cpu_src);
5301 break;
5302 case 0x1a: /* fneg */
5303 gen_helper_fneg(cpu_env, cpu_dest, cpu_src);
5304 break;
5305 case 0x5a: /* fsneg */
5306 gen_helper_fsneg(cpu_env, cpu_dest, cpu_src);
5307 break;
5308 case 0x5e: /* fdneg */
5309 gen_helper_fdneg(cpu_env, cpu_dest, cpu_src);
5310 break;
5311 case 0x1c: /* facos */
5312 gen_helper_facos(cpu_env, cpu_dest, cpu_src);
5313 break;
5314 case 0x1d: /* fcos */
5315 gen_helper_fcos(cpu_env, cpu_dest, cpu_src);
5316 break;
5317 case 0x1e: /* fgetexp */
5318 gen_helper_fgetexp(cpu_env, cpu_dest, cpu_src);
5319 break;
5320 case 0x1f: /* fgetman */
5321 gen_helper_fgetman(cpu_env, cpu_dest, cpu_src);
5322 break;
5323 case 0x20: /* fdiv */
5324 gen_helper_fdiv(cpu_env, cpu_dest, cpu_src, cpu_dest);
5325 break;
5326 case 0x60: /* fsdiv */
5327 gen_helper_fsdiv(cpu_env, cpu_dest, cpu_src, cpu_dest);
5328 break;
5329 case 0x64: /* fddiv */
5330 gen_helper_fddiv(cpu_env, cpu_dest, cpu_src, cpu_dest);
5331 break;
5332 case 0x21: /* fmod */
5333 gen_helper_fmod(cpu_env, cpu_dest, cpu_src, cpu_dest);
5334 break;
5335 case 0x22: /* fadd */
5336 gen_helper_fadd(cpu_env, cpu_dest, cpu_src, cpu_dest);
5337 break;
5338 case 0x62: /* fsadd */
5339 gen_helper_fsadd(cpu_env, cpu_dest, cpu_src, cpu_dest);
5340 break;
5341 case 0x66: /* fdadd */
5342 gen_helper_fdadd(cpu_env, cpu_dest, cpu_src, cpu_dest);
5343 break;
5344 case 0x23: /* fmul */
5345 gen_helper_fmul(cpu_env, cpu_dest, cpu_src, cpu_dest);
5346 break;
5347 case 0x63: /* fsmul */
5348 gen_helper_fsmul(cpu_env, cpu_dest, cpu_src, cpu_dest);
5349 break;
5350 case 0x67: /* fdmul */
5351 gen_helper_fdmul(cpu_env, cpu_dest, cpu_src, cpu_dest);
5352 break;
5353 case 0x24: /* fsgldiv */
5354 gen_helper_fsgldiv(cpu_env, cpu_dest, cpu_src, cpu_dest);
5355 break;
5356 case 0x25: /* frem */
5357 gen_helper_frem(cpu_env, cpu_dest, cpu_src, cpu_dest);
5358 break;
5359 case 0x26: /* fscale */
5360 gen_helper_fscale(cpu_env, cpu_dest, cpu_src, cpu_dest);
5361 break;
5362 case 0x27: /* fsglmul */
5363 gen_helper_fsglmul(cpu_env, cpu_dest, cpu_src, cpu_dest);
5364 break;
5365 case 0x28: /* fsub */
5366 gen_helper_fsub(cpu_env, cpu_dest, cpu_src, cpu_dest);
5367 break;
5368 case 0x68: /* fssub */
5369 gen_helper_fssub(cpu_env, cpu_dest, cpu_src, cpu_dest);
5370 break;
5371 case 0x6c: /* fdsub */
5372 gen_helper_fdsub(cpu_env, cpu_dest, cpu_src, cpu_dest);
5373 break;
5374 case 0x30: case 0x31: case 0x32:
5375 case 0x33: case 0x34: case 0x35:
5376 case 0x36: case 0x37: {
5377 TCGv_ptr cpu_dest2 = gen_fp_ptr(REG(ext, 0));
5378 gen_helper_fsincos(cpu_env, cpu_dest, cpu_dest2, cpu_src);
5379 tcg_temp_free_ptr(cpu_dest2);
5380 }
5381 break;
5382 case 0x38: /* fcmp */
5383 gen_helper_fcmp(cpu_env, cpu_src, cpu_dest);
5384 return;
5385 case 0x3a: /* ftst */
5386 gen_helper_ftst(cpu_env, cpu_src);
5387 return;
5388 default:
5389 goto undef;
5390 }
5391 tcg_temp_free_ptr(cpu_src);
5392 gen_helper_ftst(cpu_env, cpu_dest);
5393 tcg_temp_free_ptr(cpu_dest);
5394 return;
5395 undef:
5396 /* FIXME: Is this right for offset addressing modes? */
5397 s->pc -= 2;
5398 disas_undef_fpu(env, s, insn);
5399 }
5400
5401 static void gen_fcc_cond(DisasCompare *c, DisasContext *s, int cond)
5402 {
5403 TCGv fpsr;
5404
5405 c->g1 = 1;
5406 c->v2 = tcg_const_i32(0);
5407 c->g2 = 0;
5408 /* TODO: Raise BSUN exception. */
5409 fpsr = tcg_temp_new();
5410 gen_load_fcr(s, fpsr, M68K_FPSR);
5411 switch (cond) {
5412 case 0: /* False */
5413 case 16: /* Signaling False */
5414 c->v1 = c->v2;
5415 c->tcond = TCG_COND_NEVER;
5416 break;
5417 case 1: /* EQual Z */
5418 case 17: /* Signaling EQual Z */
5419 c->v1 = tcg_temp_new();
5420 c->g1 = 0;
5421 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
5422 c->tcond = TCG_COND_NE;
5423 break;
5424 case 2: /* Ordered Greater Than !(A || Z || N) */
5425 case 18: /* Greater Than !(A || Z || N) */
5426 c->v1 = tcg_temp_new();
5427 c->g1 = 0;
5428 tcg_gen_andi_i32(c->v1, fpsr,
5429 FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N);
5430 c->tcond = TCG_COND_EQ;
5431 break;
5432 case 3: /* Ordered Greater than or Equal Z || !(A || N) */
5433 case 19: /* Greater than or Equal Z || !(A || N) */
5434 c->v1 = tcg_temp_new();
5435 c->g1 = 0;
5436 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
5437 tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_A));
5438 tcg_gen_andi_i32(fpsr, fpsr, FPSR_CC_Z | FPSR_CC_N);
5439 tcg_gen_or_i32(c->v1, c->v1, fpsr);
5440 tcg_gen_xori_i32(c->v1, c->v1, FPSR_CC_N);
5441 c->tcond = TCG_COND_NE;
5442 break;
5443 case 4: /* Ordered Less Than !(!N || A || Z); */
5444 case 20: /* Less Than !(!N || A || Z); */
5445 c->v1 = tcg_temp_new();
5446 c->g1 = 0;
5447 tcg_gen_xori_i32(c->v1, fpsr, FPSR_CC_N);
5448 tcg_gen_andi_i32(c->v1, c->v1, FPSR_CC_N | FPSR_CC_A | FPSR_CC_Z);
5449 c->tcond = TCG_COND_EQ;
5450 break;
5451 case 5: /* Ordered Less than or Equal Z || (N && !A) */
5452 case 21: /* Less than or Equal Z || (N && !A) */
5453 c->v1 = tcg_temp_new();
5454 c->g1 = 0;
5455 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
5456 tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_A));
5457 tcg_gen_andc_i32(c->v1, fpsr, c->v1);
5458 tcg_gen_andi_i32(c->v1, c->v1, FPSR_CC_Z | FPSR_CC_N);
5459 c->tcond = TCG_COND_NE;
5460 break;
5461 case 6: /* Ordered Greater or Less than !(A || Z) */
5462 case 22: /* Greater or Less than !(A || Z) */
5463 c->v1 = tcg_temp_new();
5464 c->g1 = 0;
5465 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z);
5466 c->tcond = TCG_COND_EQ;
5467 break;
5468 case 7: /* Ordered !A */
5469 case 23: /* Greater, Less or Equal !A */
5470 c->v1 = tcg_temp_new();
5471 c->g1 = 0;
5472 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
5473 c->tcond = TCG_COND_EQ;
5474 break;
5475 case 8: /* Unordered A */
5476 case 24: /* Not Greater, Less or Equal A */
5477 c->v1 = tcg_temp_new();
5478 c->g1 = 0;
5479 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
5480 c->tcond = TCG_COND_NE;
5481 break;
5482 case 9: /* Unordered or Equal A || Z */
5483 case 25: /* Not Greater or Less then A || Z */
5484 c->v1 = tcg_temp_new();
5485 c->g1 = 0;
5486 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z);
5487 c->tcond = TCG_COND_NE;
5488 break;
5489 case 10: /* Unordered or Greater Than A || !(N || Z)) */
5490 case 26: /* Not Less or Equal A || !(N || Z)) */
5491 c->v1 = tcg_temp_new();
5492 c->g1 = 0;
5493 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
5494 tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_Z));
5495 tcg_gen_andi_i32(fpsr, fpsr, FPSR_CC_A | FPSR_CC_N);
5496 tcg_gen_or_i32(c->v1, c->v1, fpsr);
5497 tcg_gen_xori_i32(c->v1, c->v1, FPSR_CC_N);
5498 c->tcond = TCG_COND_NE;
5499 break;
5500 case 11: /* Unordered or Greater or Equal A || Z || !N */
5501 case 27: /* Not Less Than A || Z || !N */
5502 c->v1 = tcg_temp_new();
5503 c->g1 = 0;
5504 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N);
5505 tcg_gen_xori_i32(c->v1, c->v1, FPSR_CC_N);
5506 c->tcond = TCG_COND_NE;
5507 break;
5508 case 12: /* Unordered or Less Than A || (N && !Z) */
5509 case 28: /* Not Greater than or Equal A || (N && !Z) */
5510 c->v1 = tcg_temp_new();
5511 c->g1 = 0;
5512 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
5513 tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_Z));
5514 tcg_gen_andc_i32(c->v1, fpsr, c->v1);
5515 tcg_gen_andi_i32(c->v1, c->v1, FPSR_CC_A | FPSR_CC_N);
5516 c->tcond = TCG_COND_NE;
5517 break;
5518 case 13: /* Unordered or Less or Equal A || Z || N */
5519 case 29: /* Not Greater Than A || Z || N */
5520 c->v1 = tcg_temp_new();
5521 c->g1 = 0;
5522 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N);
5523 c->tcond = TCG_COND_NE;
5524 break;
5525 case 14: /* Not Equal !Z */
5526 case 30: /* Signaling Not Equal !Z */
5527 c->v1 = tcg_temp_new();
5528 c->g1 = 0;
5529 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
5530 c->tcond = TCG_COND_EQ;
5531 break;
5532 case 15: /* True */
5533 case 31: /* Signaling True */
5534 c->v1 = c->v2;
5535 c->tcond = TCG_COND_ALWAYS;
5536 break;
5537 }
5538 tcg_temp_free(fpsr);
5539 }
5540
5541 static void gen_fjmpcc(DisasContext *s, int cond, TCGLabel *l1)
5542 {
5543 DisasCompare c;
5544
5545 gen_fcc_cond(&c, s, cond);
5546 update_cc_op(s);
5547 tcg_gen_brcond_i32(c.tcond, c.v1, c.v2, l1);
5548 free_cond(&c);
5549 }
5550
5551 DISAS_INSN(fbcc)
5552 {
5553 uint32_t offset;
5554 uint32_t base;
5555 TCGLabel *l1;
5556
5557 base = s->pc;
5558 offset = (int16_t)read_im16(env, s);
5559 if (insn & (1 << 6)) {
5560 offset = (offset << 16) | read_im16(env, s);
5561 }
5562
5563 l1 = gen_new_label();
5564 update_cc_op(s);
5565 gen_fjmpcc(s, insn & 0x3f, l1);
5566 gen_jmp_tb(s, 0, s->pc, s->base.pc_next);
5567 gen_set_label(l1);
5568 gen_jmp_tb(s, 1, base + offset, s->base.pc_next);
5569 }
5570
5571 DISAS_INSN(fscc)
5572 {
5573 DisasCompare c;
5574 int cond;
5575 TCGv tmp;
5576 uint16_t ext;
5577
5578 ext = read_im16(env, s);
5579 cond = ext & 0x3f;
5580 gen_fcc_cond(&c, s, cond);
5581
5582 tmp = tcg_temp_new();
5583 tcg_gen_setcond_i32(c.tcond, tmp, c.v1, c.v2);
5584 free_cond(&c);
5585
5586 tcg_gen_neg_i32(tmp, tmp);
5587 DEST_EA(env, insn, OS_BYTE, tmp, NULL);
5588 tcg_temp_free(tmp);
5589 }
5590
5591 DISAS_INSN(ftrapcc)
5592 {
5593 DisasCompare c;
5594 uint16_t ext;
5595 int cond;
5596
5597 ext = read_im16(env, s);
5598 cond = ext & 0x3f;
5599
5600 /* Consume and discard the immediate operand. */
5601 switch (extract32(insn, 0, 3)) {
5602 case 2: /* ftrapcc.w */
5603 (void)read_im16(env, s);
5604 break;
5605 case 3: /* ftrapcc.l */
5606 (void)read_im32(env, s);
5607 break;
5608 case 4: /* ftrapcc (no operand) */
5609 break;
5610 default:
5611 /* ftrapcc registered with only valid opmodes */
5612 g_assert_not_reached();
5613 }
5614
5615 gen_fcc_cond(&c, s, cond);
5616 do_trapcc(s, &c);
5617 }
5618
5619 #if defined(CONFIG_SOFTMMU)
5620 DISAS_INSN(frestore)
5621 {
5622 TCGv addr;
5623
5624 if (IS_USER(s)) {
5625 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
5626 return;
5627 }
5628 if (m68k_feature(s->env, M68K_FEATURE_M68040)) {
5629 SRC_EA(env, addr, OS_LONG, 0, NULL);
5630 /* FIXME: check the state frame */
5631 } else {
5632 disas_undef(env, s, insn);
5633 }
5634 }
5635
5636 DISAS_INSN(fsave)
5637 {
5638 if (IS_USER(s)) {
5639 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
5640 return;
5641 }
5642
5643 if (m68k_feature(s->env, M68K_FEATURE_M68040)) {
5644 /* always write IDLE */
5645 TCGv idle = tcg_const_i32(0x41000000);
5646 DEST_EA(env, insn, OS_LONG, idle, NULL);
5647 tcg_temp_free(idle);
5648 } else {
5649 disas_undef(env, s, insn);
5650 }
5651 }
5652 #endif
5653
5654 static inline TCGv gen_mac_extract_word(DisasContext *s, TCGv val, int upper)
5655 {
5656 TCGv tmp = tcg_temp_new();
5657 if (s->env->macsr & MACSR_FI) {
5658 if (upper)
5659 tcg_gen_andi_i32(tmp, val, 0xffff0000);
5660 else
5661 tcg_gen_shli_i32(tmp, val, 16);
5662 } else if (s->env->macsr & MACSR_SU) {
5663 if (upper)
5664 tcg_gen_sari_i32(tmp, val, 16);
5665 else
5666 tcg_gen_ext16s_i32(tmp, val);
5667 } else {
5668 if (upper)
5669 tcg_gen_shri_i32(tmp, val, 16);
5670 else
5671 tcg_gen_ext16u_i32(tmp, val);
5672 }
5673 return tmp;
5674 }
5675
5676 static void gen_mac_clear_flags(void)
5677 {
5678 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR,
5679 ~(MACSR_V | MACSR_Z | MACSR_N | MACSR_EV));
5680 }
5681
5682 DISAS_INSN(mac)
5683 {
5684 TCGv rx;
5685 TCGv ry;
5686 uint16_t ext;
5687 int acc;
5688 TCGv tmp;
5689 TCGv addr;
5690 TCGv loadval;
5691 int dual;
5692 TCGv saved_flags;
5693
5694 if (!s->done_mac) {
5695 s->mactmp = tcg_temp_new_i64();
5696 s->done_mac = 1;
5697 }
5698
5699 ext = read_im16(env, s);
5700
5701 acc = ((insn >> 7) & 1) | ((ext >> 3) & 2);
5702 dual = ((insn & 0x30) != 0 && (ext & 3) != 0);
5703 if (dual && !m68k_feature(s->env, M68K_FEATURE_CF_EMAC_B)) {
5704 disas_undef(env, s, insn);
5705 return;
5706 }
5707 if (insn & 0x30) {
5708 /* MAC with load. */
5709 tmp = gen_lea(env, s, insn, OS_LONG);
5710 addr = tcg_temp_new();
5711 tcg_gen_and_i32(addr, tmp, QREG_MAC_MASK);
5712 /*
5713 * Load the value now to ensure correct exception behavior.
5714 * Perform writeback after reading the MAC inputs.
5715 */
5716 loadval = gen_load(s, OS_LONG, addr, 0, IS_USER(s));
5717
5718 acc ^= 1;
5719 rx = (ext & 0x8000) ? AREG(ext, 12) : DREG(insn, 12);
5720 ry = (ext & 8) ? AREG(ext, 0) : DREG(ext, 0);
5721 } else {
5722 loadval = addr = NULL_QREG;
5723 rx = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9);
5724 ry = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
5725 }
5726
5727 gen_mac_clear_flags();
5728 #if 0
5729 l1 = -1;
5730 /* Disabled because conditional branches clobber temporary vars. */
5731 if ((s->env->macsr & MACSR_OMC) != 0 && !dual) {
5732 /* Skip the multiply if we know we will ignore it. */
5733 l1 = gen_new_label();
5734 tmp = tcg_temp_new();
5735 tcg_gen_andi_i32(tmp, QREG_MACSR, 1 << (acc + 8));
5736 gen_op_jmp_nz32(tmp, l1);
5737 }
5738 #endif
5739
5740 if ((ext & 0x0800) == 0) {
5741 /* Word. */
5742 rx = gen_mac_extract_word(s, rx, (ext & 0x80) != 0);
5743 ry = gen_mac_extract_word(s, ry, (ext & 0x40) != 0);
5744 }
5745 if (s->env->macsr & MACSR_FI) {
5746 gen_helper_macmulf(s->mactmp, cpu_env, rx, ry);
5747 } else {
5748 if (s->env->macsr & MACSR_SU)
5749 gen_helper_macmuls(s->mactmp, cpu_env, rx, ry);
5750 else
5751 gen_helper_macmulu(s->mactmp, cpu_env, rx, ry);
5752 switch ((ext >> 9) & 3) {
5753 case 1:
5754 tcg_gen_shli_i64(s->mactmp, s->mactmp, 1);
5755 break;
5756 case 3:
5757 tcg_gen_shri_i64(s->mactmp, s->mactmp, 1);
5758 break;
5759 }
5760 }
5761
5762 if (dual) {
5763 /* Save the overflow flag from the multiply. */
5764 saved_flags = tcg_temp_new();
5765 tcg_gen_mov_i32(saved_flags, QREG_MACSR);
5766 } else {
5767 saved_flags = NULL_QREG;
5768 }
5769
5770 #if 0
5771 /* Disabled because conditional branches clobber temporary vars. */
5772 if ((s->env->macsr & MACSR_OMC) != 0 && dual) {
5773 /* Skip the accumulate if the value is already saturated. */
5774 l1 = gen_new_label();
5775 tmp = tcg_temp_new();
5776 gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
5777 gen_op_jmp_nz32(tmp, l1);
5778 }
5779 #endif
5780
5781 if (insn & 0x100)
5782 tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp);
5783 else
5784 tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
5785
5786 if (s->env->macsr & MACSR_FI)
5787 gen_helper_macsatf(cpu_env, tcg_const_i32(acc));
5788 else if (s->env->macsr & MACSR_SU)
5789 gen_helper_macsats(cpu_env, tcg_const_i32(acc));
5790 else
5791 gen_helper_macsatu(cpu_env, tcg_const_i32(acc));
5792
5793 #if 0
5794 /* Disabled because conditional branches clobber temporary vars. */
5795 if (l1 != -1)
5796 gen_set_label(l1);
5797 #endif
5798
5799 if (dual) {
5800 /* Dual accumulate variant. */
5801 acc = (ext >> 2) & 3;
5802 /* Restore the overflow flag from the multiplier. */
5803 tcg_gen_mov_i32(QREG_MACSR, saved_flags);
5804 #if 0
5805 /* Disabled because conditional branches clobber temporary vars. */
5806 if ((s->env->macsr & MACSR_OMC) != 0) {
5807 /* Skip the accumulate if the value is already saturated. */
5808 l1 = gen_new_label();
5809 tmp = tcg_temp_new();
5810 gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
5811 gen_op_jmp_nz32(tmp, l1);
5812 }
5813 #endif
5814 if (ext & 2)
5815 tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp);
5816 else
5817 tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
5818 if (s->env->macsr & MACSR_FI)
5819 gen_helper_macsatf(cpu_env, tcg_const_i32(acc));
5820 else if (s->env->macsr & MACSR_SU)
5821 gen_helper_macsats(cpu_env, tcg_const_i32(acc));
5822 else
5823 gen_helper_macsatu(cpu_env, tcg_const_i32(acc));
5824 #if 0
5825 /* Disabled because conditional branches clobber temporary vars. */
5826 if (l1 != -1)
5827 gen_set_label(l1);
5828 #endif
5829 }
5830 gen_helper_mac_set_flags(cpu_env, tcg_const_i32(acc));
5831
5832 if (insn & 0x30) {
5833 TCGv rw;
5834 rw = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9);
5835 tcg_gen_mov_i32(rw, loadval);
5836 /*
5837 * FIXME: Should address writeback happen with the masked or
5838 * unmasked value?
5839 */
5840 switch ((insn >> 3) & 7) {
5841 case 3: /* Post-increment. */
5842 tcg_gen_addi_i32(AREG(insn, 0), addr, 4);
5843 break;
5844 case 4: /* Pre-decrement. */
5845 tcg_gen_mov_i32(AREG(insn, 0), addr);
5846 }
5847 tcg_temp_free(loadval);
5848 }
5849 }
5850
5851 DISAS_INSN(from_mac)
5852 {
5853 TCGv rx;
5854 TCGv_i64 acc;
5855 int accnum;
5856
5857 rx = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
5858 accnum = (insn >> 9) & 3;
5859 acc = MACREG(accnum);
5860 if (s->env->macsr & MACSR_FI) {
5861 gen_helper_get_macf(rx, cpu_env, acc);
5862 } else if ((s->env->macsr & MACSR_OMC) == 0) {
5863 tcg_gen_extrl_i64_i32(rx, acc);
5864 } else if (s->env->macsr & MACSR_SU) {
5865 gen_helper_get_macs(rx, acc);
5866 } else {
5867 gen_helper_get_macu(rx, acc);
5868 }
5869 if (insn & 0x40) {
5870 tcg_gen_movi_i64(acc, 0);
5871 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum));
5872 }
5873 }
5874
5875 DISAS_INSN(move_mac)
5876 {
5877 /* FIXME: This can be done without a helper. */
5878 int src;
5879 TCGv dest;
5880 src = insn & 3;
5881 dest = tcg_const_i32((insn >> 9) & 3);
5882 gen_helper_mac_move(cpu_env, dest, tcg_const_i32(src));
5883 gen_mac_clear_flags();
5884 gen_helper_mac_set_flags(cpu_env, dest);
5885 }
5886
5887 DISAS_INSN(from_macsr)
5888 {
5889 TCGv reg;
5890
5891 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
5892 tcg_gen_mov_i32(reg, QREG_MACSR);
5893 }
5894
5895 DISAS_INSN(from_mask)
5896 {
5897 TCGv reg;
5898 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
5899 tcg_gen_mov_i32(reg, QREG_MAC_MASK);
5900 }
5901
5902 DISAS_INSN(from_mext)
5903 {
5904 TCGv reg;
5905 TCGv acc;
5906 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
5907 acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
5908 if (s->env->macsr & MACSR_FI)
5909 gen_helper_get_mac_extf(reg, cpu_env, acc);
5910 else
5911 gen_helper_get_mac_exti(reg, cpu_env, acc);
5912 }
5913
5914 DISAS_INSN(macsr_to_ccr)
5915 {
5916 TCGv tmp = tcg_temp_new();
5917
5918 /* Note that X and C are always cleared. */
5919 tcg_gen_andi_i32(tmp, QREG_MACSR, CCF_N | CCF_Z | CCF_V);
5920 gen_helper_set_ccr(cpu_env, tmp);
5921 tcg_temp_free(tmp);
5922 set_cc_op(s, CC_OP_FLAGS);
5923 }
5924
5925 DISAS_INSN(to_mac)
5926 {
5927 TCGv_i64 acc;
5928 TCGv val;
5929 int accnum;
5930 accnum = (insn >> 9) & 3;
5931 acc = MACREG(accnum);
5932 SRC_EA(env, val, OS_LONG, 0, NULL);
5933 if (s->env->macsr & MACSR_FI) {
5934 tcg_gen_ext_i32_i64(acc, val);
5935 tcg_gen_shli_i64(acc, acc, 8);
5936 } else if (s->env->macsr & MACSR_SU) {
5937 tcg_gen_ext_i32_i64(acc, val);
5938 } else {
5939 tcg_gen_extu_i32_i64(acc, val);
5940 }
5941 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum));
5942 gen_mac_clear_flags();
5943 gen_helper_mac_set_flags(cpu_env, tcg_const_i32(accnum));
5944 }
5945
5946 DISAS_INSN(to_macsr)
5947 {
5948 TCGv val;
5949 SRC_EA(env, val, OS_LONG, 0, NULL);
5950 gen_helper_set_macsr(cpu_env, val);
5951 gen_exit_tb(s);
5952 }
5953
5954 DISAS_INSN(to_mask)
5955 {
5956 TCGv val;
5957 SRC_EA(env, val, OS_LONG, 0, NULL);
5958 tcg_gen_ori_i32(QREG_MAC_MASK, val, 0xffff0000);
5959 }
5960
5961 DISAS_INSN(to_mext)
5962 {
5963 TCGv val;
5964 TCGv acc;
5965 SRC_EA(env, val, OS_LONG, 0, NULL);
5966 acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
5967 if (s->env->macsr & MACSR_FI)
5968 gen_helper_set_mac_extf(cpu_env, val, acc);
5969 else if (s->env->macsr & MACSR_SU)
5970 gen_helper_set_mac_exts(cpu_env, val, acc);
5971 else
5972 gen_helper_set_mac_extu(cpu_env, val, acc);
5973 }
5974
5975 static disas_proc opcode_table[65536];
5976
5977 static void
5978 register_opcode (disas_proc proc, uint16_t opcode, uint16_t mask)
5979 {
5980 int i;
5981 int from;
5982 int to;
5983
5984 /* Sanity check. All set bits must be included in the mask. */
5985 if (opcode & ~mask) {
5986 fprintf(stderr,
5987 "qemu internal error: bogus opcode definition %04x/%04x\n",
5988 opcode, mask);
5989 abort();
5990 }
5991 /*
5992 * This could probably be cleverer. For now just optimize the case where
5993 * the top bits are known.
5994 */
5995 /* Find the first zero bit in the mask. */
5996 i = 0x8000;
5997 while ((i & mask) != 0)
5998 i >>= 1;
5999 /* Iterate over all combinations of this and lower bits. */
6000 if (i == 0)
6001 i = 1;
6002 else
6003 i <<= 1;
6004 from = opcode & ~(i - 1);
6005 to = from + i;
6006 for (i = from; i < to; i++) {
6007 if ((i & mask) == opcode)
6008 opcode_table[i] = proc;
6009 }
6010 }
6011
6012 /*
6013 * Register m68k opcode handlers. Order is important.
6014 * Later insn override earlier ones.
6015 */
6016 void register_m68k_insns (CPUM68KState *env)
6017 {
6018 /*
6019 * Build the opcode table only once to avoid
6020 * multithreading issues.
6021 */
6022 if (opcode_table[0] != NULL) {
6023 return;
6024 }
6025
6026 /*
6027 * use BASE() for instruction available
6028 * for CF_ISA_A and M68000.
6029 */
6030 #define BASE(name, opcode, mask) \
6031 register_opcode(disas_##name, 0x##opcode, 0x##mask)
6032 #define INSN(name, opcode, mask, feature) do { \
6033 if (m68k_feature(env, M68K_FEATURE_##feature)) \
6034 BASE(name, opcode, mask); \
6035 } while(0)
6036 BASE(undef, 0000, 0000);
6037 INSN(arith_im, 0080, fff8, CF_ISA_A);
6038 INSN(arith_im, 0000, ff00, M68K);
6039 INSN(chk2, 00c0, f9c0, CHK2);
6040 INSN(bitrev, 00c0, fff8, CF_ISA_APLUSC);
6041 BASE(bitop_reg, 0100, f1c0);
6042 BASE(bitop_reg, 0140, f1c0);
6043 BASE(bitop_reg, 0180, f1c0);
6044 BASE(bitop_reg, 01c0, f1c0);
6045 INSN(movep, 0108, f138, MOVEP);
6046 INSN(arith_im, 0280, fff8, CF_ISA_A);
6047 INSN(arith_im, 0200, ff00, M68K);
6048 INSN(undef, 02c0, ffc0, M68K);
6049 INSN(byterev, 02c0, fff8, CF_ISA_APLUSC);
6050 INSN(arith_im, 0480, fff8, CF_ISA_A);
6051 INSN(arith_im, 0400, ff00, M68K);
6052 INSN(undef, 04c0, ffc0, M68K);
6053 INSN(arith_im, 0600, ff00, M68K);
6054 INSN(undef, 06c0, ffc0, M68K);
6055 INSN(ff1, 04c0, fff8, CF_ISA_APLUSC);
6056 INSN(arith_im, 0680, fff8, CF_ISA_A);
6057 INSN(arith_im, 0c00, ff38, CF_ISA_A);
6058 INSN(arith_im, 0c00, ff00, M68K);
6059 BASE(bitop_im, 0800, ffc0);
6060 BASE(bitop_im, 0840, ffc0);
6061 BASE(bitop_im, 0880, ffc0);
6062 BASE(bitop_im, 08c0, ffc0);
6063 INSN(arith_im, 0a80, fff8, CF_ISA_A);
6064 INSN(arith_im, 0a00, ff00, M68K);
6065 #if defined(CONFIG_SOFTMMU)
6066 INSN(moves, 0e00, ff00, M68K);
6067 #endif
6068 INSN(cas, 0ac0, ffc0, CAS);
6069 INSN(cas, 0cc0, ffc0, CAS);
6070 INSN(cas, 0ec0, ffc0, CAS);
6071 INSN(cas2w, 0cfc, ffff, CAS);
6072 INSN(cas2l, 0efc, ffff, CAS);
6073 BASE(move, 1000, f000);
6074 BASE(move, 2000, f000);
6075 BASE(move, 3000, f000);
6076 INSN(chk, 4000, f040, M68K);
6077 INSN(strldsr, 40e7, ffff, CF_ISA_APLUSC);
6078 INSN(negx, 4080, fff8, CF_ISA_A);
6079 INSN(negx, 4000, ff00, M68K);
6080 INSN(undef, 40c0, ffc0, M68K);
6081 INSN(move_from_sr, 40c0, fff8, CF_ISA_A);
6082 INSN(move_from_sr, 40c0, ffc0, M68K);
6083 BASE(lea, 41c0, f1c0);
6084 BASE(clr, 4200, ff00);
6085 BASE(undef, 42c0, ffc0);
6086 INSN(move_from_ccr, 42c0, fff8, CF_ISA_A);
6087 INSN(move_from_ccr, 42c0, ffc0, M68K);
6088 INSN(neg, 4480, fff8, CF_ISA_A);
6089 INSN(neg, 4400, ff00, M68K);
6090 INSN(undef, 44c0, ffc0, M68K);
6091 BASE(move_to_ccr, 44c0, ffc0);
6092 INSN(not, 4680, fff8, CF_ISA_A);
6093 INSN(not, 4600, ff00, M68K);
6094 #if defined(CONFIG_SOFTMMU)
6095 BASE(move_to_sr, 46c0, ffc0);
6096 #endif
6097 INSN(nbcd, 4800, ffc0, M68K);
6098 INSN(linkl, 4808, fff8, M68K);
6099 BASE(pea, 4840, ffc0);
6100 BASE(swap, 4840, fff8);
6101 INSN(bkpt, 4848, fff8, BKPT);
6102 INSN(movem, 48d0, fbf8, CF_ISA_A);
6103 INSN(movem, 48e8, fbf8, CF_ISA_A);
6104 INSN(movem, 4880, fb80, M68K);
6105 BASE(ext, 4880, fff8);
6106 BASE(ext, 48c0, fff8);
6107 BASE(ext, 49c0, fff8);
6108 BASE(tst, 4a00, ff00);
6109 INSN(tas, 4ac0, ffc0, CF_ISA_B);
6110 INSN(tas, 4ac0, ffc0, M68K);
6111 #if defined(CONFIG_SOFTMMU)
6112 INSN(halt, 4ac8, ffff, CF_ISA_A);
6113 INSN(halt, 4ac8, ffff, M68K);
6114 #endif
6115 INSN(pulse, 4acc, ffff, CF_ISA_A);
6116 BASE(illegal, 4afc, ffff);
6117 INSN(mull, 4c00, ffc0, CF_ISA_A);
6118 INSN(mull, 4c00, ffc0, LONG_MULDIV);
6119 INSN(divl, 4c40, ffc0, CF_ISA_A);
6120 INSN(divl, 4c40, ffc0, LONG_MULDIV);
6121 INSN(sats, 4c80, fff8, CF_ISA_B);
6122 BASE(trap, 4e40, fff0);
6123 BASE(link, 4e50, fff8);
6124 BASE(unlk, 4e58, fff8);
6125 #if defined(CONFIG_SOFTMMU)
6126 INSN(move_to_usp, 4e60, fff8, USP);
6127 INSN(move_from_usp, 4e68, fff8, USP);
6128 INSN(reset, 4e70, ffff, M68K);
6129 BASE(stop, 4e72, ffff);
6130 BASE(rte, 4e73, ffff);
6131 INSN(cf_movec, 4e7b, ffff, CF_ISA_A);
6132 INSN(m68k_movec, 4e7a, fffe, MOVEC);
6133 #endif
6134 BASE(nop, 4e71, ffff);
6135 INSN(rtd, 4e74, ffff, RTD);
6136 BASE(rts, 4e75, ffff);
6137 INSN(trapv, 4e76, ffff, M68K);
6138 INSN(rtr, 4e77, ffff, M68K);
6139 BASE(jump, 4e80, ffc0);
6140 BASE(jump, 4ec0, ffc0);
6141 INSN(addsubq, 5000, f080, M68K);
6142 BASE(addsubq, 5080, f0c0);
6143 INSN(scc, 50c0, f0f8, CF_ISA_A); /* Scc.B Dx */
6144 INSN(scc, 50c0, f0c0, M68K); /* Scc.B <EA> */
6145 INSN(dbcc, 50c8, f0f8, M68K);
6146 INSN(trapcc, 50fa, f0fe, TRAPCC); /* opmode 010, 011 */
6147 INSN(trapcc, 50fc, f0ff, TRAPCC); /* opmode 100 */
6148 INSN(trapcc, 51fa, fffe, CF_ISA_A); /* TPF (trapf) opmode 010, 011 */
6149 INSN(trapcc, 51fc, ffff, CF_ISA_A); /* TPF (trapf) opmode 100 */
6150
6151 /* Branch instructions. */
6152 BASE(branch, 6000, f000);
6153 /* Disable long branch instructions, then add back the ones we want. */
6154 BASE(undef, 60ff, f0ff); /* All long branches. */
6155 INSN(branch, 60ff, f0ff, CF_ISA_B);
6156 INSN(undef, 60ff, ffff, CF_ISA_B); /* bra.l */
6157 INSN(branch, 60ff, ffff, BRAL);
6158 INSN(branch, 60ff, f0ff, BCCL);
6159
6160 BASE(moveq, 7000, f100);
6161 INSN(mvzs, 7100, f100, CF_ISA_B);
6162 BASE(or, 8000, f000);
6163 BASE(divw, 80c0, f0c0);
6164 INSN(sbcd_reg, 8100, f1f8, M68K);
6165 INSN(sbcd_mem, 8108, f1f8, M68K);
6166 BASE(addsub, 9000, f000);
6167 INSN(undef, 90c0, f0c0, CF_ISA_A);
6168 INSN(subx_reg, 9180, f1f8, CF_ISA_A);
6169 INSN(subx_reg, 9100, f138, M68K);
6170 INSN(subx_mem, 9108, f138, M68K);
6171 INSN(suba, 91c0, f1c0, CF_ISA_A);
6172 INSN(suba, 90c0, f0c0, M68K);
6173
6174 BASE(undef_mac, a000, f000);
6175 INSN(mac, a000, f100, CF_EMAC);
6176 INSN(from_mac, a180, f9b0, CF_EMAC);
6177 INSN(move_mac, a110, f9fc, CF_EMAC);
6178 INSN(from_macsr,a980, f9f0, CF_EMAC);
6179 INSN(from_mask, ad80, fff0, CF_EMAC);
6180 INSN(from_mext, ab80, fbf0, CF_EMAC);
6181 INSN(macsr_to_ccr, a9c0, ffff, CF_EMAC);
6182 INSN(to_mac, a100, f9c0, CF_EMAC);
6183 INSN(to_macsr, a900, ffc0, CF_EMAC);
6184 INSN(to_mext, ab00, fbc0, CF_EMAC);
6185 INSN(to_mask, ad00, ffc0, CF_EMAC);
6186
6187 INSN(mov3q, a140, f1c0, CF_ISA_B);
6188 INSN(cmp, b000, f1c0, CF_ISA_B); /* cmp.b */
6189 INSN(cmp, b040, f1c0, CF_ISA_B); /* cmp.w */
6190 INSN(cmpa, b0c0, f1c0, CF_ISA_B); /* cmpa.w */
6191 INSN(cmp, b080, f1c0, CF_ISA_A);
6192 INSN(cmpa, b1c0, f1c0, CF_ISA_A);
6193 INSN(cmp, b000, f100, M68K);
6194 INSN(eor, b100, f100, M68K);
6195 INSN(cmpm, b108, f138, M68K);
6196 INSN(cmpa, b0c0, f0c0, M68K);
6197 INSN(eor, b180, f1c0, CF_ISA_A);
6198 BASE(and, c000, f000);
6199 INSN(exg_dd, c140, f1f8, M68K);
6200 INSN(exg_aa, c148, f1f8, M68K);
6201 INSN(exg_da, c188, f1f8, M68K);
6202 BASE(mulw, c0c0, f0c0);
6203 INSN(abcd_reg, c100, f1f8, M68K);
6204 INSN(abcd_mem, c108, f1f8, M68K);
6205 BASE(addsub, d000, f000);
6206 INSN(undef, d0c0, f0c0, CF_ISA_A);
6207 INSN(addx_reg, d180, f1f8, CF_ISA_A);
6208 INSN(addx_reg, d100, f138, M68K);
6209 INSN(addx_mem, d108, f138, M68K);
6210 INSN(adda, d1c0, f1c0, CF_ISA_A);
6211 INSN(adda, d0c0, f0c0, M68K);
6212 INSN(shift_im, e080, f0f0, CF_ISA_A);
6213 INSN(shift_reg, e0a0, f0f0, CF_ISA_A);
6214 INSN(shift8_im, e000, f0f0, M68K);
6215 INSN(shift16_im, e040, f0f0, M68K);
6216 INSN(shift_im, e080, f0f0, M68K);
6217 INSN(shift8_reg, e020, f0f0, M68K);
6218 INSN(shift16_reg, e060, f0f0, M68K);
6219 INSN(shift_reg, e0a0, f0f0, M68K);
6220 INSN(shift_mem, e0c0, fcc0, M68K);
6221 INSN(rotate_im, e090, f0f0, M68K);
6222 INSN(rotate8_im, e010, f0f0, M68K);
6223 INSN(rotate16_im, e050, f0f0, M68K);
6224 INSN(rotate_reg, e0b0, f0f0, M68K);
6225 INSN(rotate8_reg, e030, f0f0, M68K);
6226 INSN(rotate16_reg, e070, f0f0, M68K);
6227 INSN(rotate_mem, e4c0, fcc0, M68K);
6228 INSN(bfext_mem, e9c0, fdc0, BITFIELD); /* bfextu & bfexts */
6229 INSN(bfext_reg, e9c0, fdf8, BITFIELD);
6230 INSN(bfins_mem, efc0, ffc0, BITFIELD);
6231 INSN(bfins_reg, efc0, fff8, BITFIELD);
6232 INSN(bfop_mem, eac0, ffc0, BITFIELD); /* bfchg */
6233 INSN(bfop_reg, eac0, fff8, BITFIELD); /* bfchg */
6234 INSN(bfop_mem, ecc0, ffc0, BITFIELD); /* bfclr */
6235 INSN(bfop_reg, ecc0, fff8, BITFIELD); /* bfclr */
6236 INSN(bfop_mem, edc0, ffc0, BITFIELD); /* bfffo */
6237 INSN(bfop_reg, edc0, fff8, BITFIELD); /* bfffo */
6238 INSN(bfop_mem, eec0, ffc0, BITFIELD); /* bfset */
6239 INSN(bfop_reg, eec0, fff8, BITFIELD); /* bfset */
6240 INSN(bfop_mem, e8c0, ffc0, BITFIELD); /* bftst */
6241 INSN(bfop_reg, e8c0, fff8, BITFIELD); /* bftst */
6242 BASE(undef_fpu, f000, f000);
6243 INSN(fpu, f200, ffc0, CF_FPU);
6244 INSN(fbcc, f280, ffc0, CF_FPU);
6245 INSN(fpu, f200, ffc0, FPU);
6246 INSN(fscc, f240, ffc0, FPU);
6247 INSN(ftrapcc, f27a, fffe, FPU); /* opmode 010, 011 */
6248 INSN(ftrapcc, f27c, ffff, FPU); /* opmode 100 */
6249 INSN(fbcc, f280, ff80, FPU);
6250 #if defined(CONFIG_SOFTMMU)
6251 INSN(frestore, f340, ffc0, CF_FPU);
6252 INSN(fsave, f300, ffc0, CF_FPU);
6253 INSN(frestore, f340, ffc0, FPU);
6254 INSN(fsave, f300, ffc0, FPU);
6255 INSN(intouch, f340, ffc0, CF_ISA_A);
6256 INSN(cpushl, f428, ff38, CF_ISA_A);
6257 INSN(cpush, f420, ff20, M68040);
6258 INSN(cinv, f400, ff20, M68040);
6259 INSN(pflush, f500, ffe0, M68040);
6260 INSN(ptest, f548, ffd8, M68040);
6261 INSN(wddata, fb00, ff00, CF_ISA_A);
6262 INSN(wdebug, fbc0, ffc0, CF_ISA_A);
6263 #endif
6264 INSN(move16_mem, f600, ffe0, M68040);
6265 INSN(move16_reg, f620, fff8, M68040);
6266 #undef INSN
6267 }
6268
6269 static void m68k_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
6270 {
6271 DisasContext *dc = container_of(dcbase, DisasContext, base);
6272 CPUM68KState *env = cpu->env_ptr;
6273
6274 dc->env = env;
6275 dc->pc = dc->base.pc_first;
6276 /* This value will always be filled in properly before m68k_tr_tb_stop. */
6277 dc->pc_prev = 0xdeadbeef;
6278 dc->cc_op = CC_OP_DYNAMIC;
6279 dc->cc_op_synced = 1;
6280 dc->done_mac = 0;
6281 dc->writeback_mask = 0;
6282 init_release_array(dc);
6283
6284 dc->ss_active = (M68K_SR_TRACE(env->sr) == M68K_SR_TRACE_ANY_INS);
6285 /* If architectural single step active, limit to 1 */
6286 if (dc->ss_active) {
6287 dc->base.max_insns = 1;
6288 }
6289 }
6290
6291 static void m68k_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu)
6292 {
6293 }
6294
6295 static void m68k_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
6296 {
6297 DisasContext *dc = container_of(dcbase, DisasContext, base);
6298 tcg_gen_insn_start(dc->base.pc_next, dc->cc_op);
6299 }
6300
6301 static void m68k_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
6302 {
6303 DisasContext *dc = container_of(dcbase, DisasContext, base);
6304 CPUM68KState *env = cpu->env_ptr;
6305 uint16_t insn = read_im16(env, dc);
6306
6307 opcode_table[insn](env, dc, insn);
6308 do_writebacks(dc);
6309 do_release(dc);
6310
6311 dc->pc_prev = dc->base.pc_next;
6312 dc->base.pc_next = dc->pc;
6313
6314 if (dc->base.is_jmp == DISAS_NEXT) {
6315 /*
6316 * Stop translation when the next insn might touch a new page.
6317 * This ensures that prefetch aborts at the right place.
6318 *
6319 * We cannot determine the size of the next insn without
6320 * completely decoding it. However, the maximum insn size
6321 * is 32 bytes, so end if we do not have that much remaining.
6322 * This may produce several small TBs at the end of each page,
6323 * but they will all be linked with goto_tb.
6324 *
6325 * ??? ColdFire maximum is 4 bytes; MC68000's maximum is also
6326 * smaller than MC68020's.
6327 */
6328 target_ulong start_page_offset
6329 = dc->pc - (dc->base.pc_first & TARGET_PAGE_MASK);
6330
6331 if (start_page_offset >= TARGET_PAGE_SIZE - 32) {
6332 dc->base.is_jmp = DISAS_TOO_MANY;
6333 }
6334 }
6335 }
6336
6337 static void m68k_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
6338 {
6339 DisasContext *dc = container_of(dcbase, DisasContext, base);
6340
6341 switch (dc->base.is_jmp) {
6342 case DISAS_NORETURN:
6343 break;
6344 case DISAS_TOO_MANY:
6345 update_cc_op(dc);
6346 gen_jmp_tb(dc, 0, dc->pc, dc->pc_prev);
6347 break;
6348 case DISAS_JUMP:
6349 /* We updated CC_OP and PC in gen_jmp/gen_jmp_im. */
6350 if (dc->ss_active) {
6351 gen_raise_exception_format2(dc, EXCP_TRACE, dc->pc_prev);
6352 } else {
6353 tcg_gen_lookup_and_goto_ptr();
6354 }
6355 break;
6356 case DISAS_EXIT:
6357 /*
6358 * We updated CC_OP and PC in gen_exit_tb, but also modified
6359 * other state that may require returning to the main loop.
6360 */
6361 if (dc->ss_active) {
6362 gen_raise_exception_format2(dc, EXCP_TRACE, dc->pc_prev);
6363 } else {
6364 tcg_gen_exit_tb(NULL, 0);
6365 }
6366 break;
6367 default:
6368 g_assert_not_reached();
6369 }
6370 }
6371
6372 static void m68k_tr_disas_log(const DisasContextBase *dcbase,
6373 CPUState *cpu, FILE *logfile)
6374 {
6375 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first));
6376 target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size);
6377 }
6378
6379 static const TranslatorOps m68k_tr_ops = {
6380 .init_disas_context = m68k_tr_init_disas_context,
6381 .tb_start = m68k_tr_tb_start,
6382 .insn_start = m68k_tr_insn_start,
6383 .translate_insn = m68k_tr_translate_insn,
6384 .tb_stop = m68k_tr_tb_stop,
6385 .disas_log = m68k_tr_disas_log,
6386 };
6387
6388 void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns,
6389 target_ulong pc, void *host_pc)
6390 {
6391 DisasContext dc;
6392 translator_loop(cpu, tb, max_insns, pc, host_pc, &m68k_tr_ops, &dc.base);
6393 }
6394
6395 static double floatx80_to_double(CPUM68KState *env, uint16_t high, uint64_t low)
6396 {
6397 floatx80 a = { .high = high, .low = low };
6398 union {
6399 float64 f64;
6400 double d;
6401 } u;
6402
6403 u.f64 = floatx80_to_float64(a, &env->fp_status);
6404 return u.d;
6405 }
6406
6407 void m68k_cpu_dump_state(CPUState *cs, FILE *f, int flags)
6408 {
6409 M68kCPU *cpu = M68K_CPU(cs);
6410 CPUM68KState *env = &cpu->env;
6411 int i;
6412 uint16_t sr;
6413 for (i = 0; i < 8; i++) {
6414 qemu_fprintf(f, "D%d = %08x A%d = %08x "
6415 "F%d = %04x %016"PRIx64" (%12g)\n",
6416 i, env->dregs[i], i, env->aregs[i],
6417 i, env->fregs[i].l.upper, env->fregs[i].l.lower,
6418 floatx80_to_double(env, env->fregs[i].l.upper,
6419 env->fregs[i].l.lower));
6420 }
6421 qemu_fprintf(f, "PC = %08x ", env->pc);
6422 sr = env->sr | cpu_m68k_get_ccr(env);
6423 qemu_fprintf(f, "SR = %04x T:%x I:%x %c%c %c%c%c%c%c\n",
6424 sr, (sr & SR_T) >> SR_T_SHIFT, (sr & SR_I) >> SR_I_SHIFT,
6425 (sr & SR_S) ? 'S' : 'U', (sr & SR_M) ? '%' : 'I',
6426 (sr & CCF_X) ? 'X' : '-', (sr & CCF_N) ? 'N' : '-',
6427 (sr & CCF_Z) ? 'Z' : '-', (sr & CCF_V) ? 'V' : '-',
6428 (sr & CCF_C) ? 'C' : '-');
6429 qemu_fprintf(f, "FPSR = %08x %c%c%c%c ", env->fpsr,
6430 (env->fpsr & FPSR_CC_A) ? 'A' : '-',
6431 (env->fpsr & FPSR_CC_I) ? 'I' : '-',
6432 (env->fpsr & FPSR_CC_Z) ? 'Z' : '-',
6433 (env->fpsr & FPSR_CC_N) ? 'N' : '-');
6434 qemu_fprintf(f, "\n "
6435 "FPCR = %04x ", env->fpcr);
6436 switch (env->fpcr & FPCR_PREC_MASK) {
6437 case FPCR_PREC_X:
6438 qemu_fprintf(f, "X ");
6439 break;
6440 case FPCR_PREC_S:
6441 qemu_fprintf(f, "S ");
6442 break;
6443 case FPCR_PREC_D:
6444 qemu_fprintf(f, "D ");
6445 break;
6446 }
6447 switch (env->fpcr & FPCR_RND_MASK) {
6448 case FPCR_RND_N:
6449 qemu_fprintf(f, "RN ");
6450 break;
6451 case FPCR_RND_Z:
6452 qemu_fprintf(f, "RZ ");
6453 break;
6454 case FPCR_RND_M:
6455 qemu_fprintf(f, "RM ");
6456 break;
6457 case FPCR_RND_P:
6458 qemu_fprintf(f, "RP ");
6459 break;
6460 }
6461 qemu_fprintf(f, "\n");
6462 #ifdef CONFIG_SOFTMMU
6463 qemu_fprintf(f, "%sA7(MSP) = %08x %sA7(USP) = %08x %sA7(ISP) = %08x\n",
6464 env->current_sp == M68K_SSP ? "->" : " ", env->sp[M68K_SSP],
6465 env->current_sp == M68K_USP ? "->" : " ", env->sp[M68K_USP],
6466 env->current_sp == M68K_ISP ? "->" : " ", env->sp[M68K_ISP]);
6467 qemu_fprintf(f, "VBR = 0x%08x\n", env->vbr);
6468 qemu_fprintf(f, "SFC = %x DFC %x\n", env->sfc, env->dfc);
6469 qemu_fprintf(f, "SSW %08x TCR %08x URP %08x SRP %08x\n",
6470 env->mmu.ssw, env->mmu.tcr, env->mmu.urp, env->mmu.srp);
6471 qemu_fprintf(f, "DTTR0/1: %08x/%08x ITTR0/1: %08x/%08x\n",
6472 env->mmu.ttr[M68K_DTTR0], env->mmu.ttr[M68K_DTTR1],
6473 env->mmu.ttr[M68K_ITTR0], env->mmu.ttr[M68K_ITTR1]);
6474 qemu_fprintf(f, "MMUSR %08x, fault at %08x\n",
6475 env->mmu.mmusr, env->mmu.ar);
6476 #endif
6477 }
6478
6479 void restore_state_to_opc(CPUM68KState *env, TranslationBlock *tb,
6480 target_ulong *data)
6481 {
6482 int cc_op = data[1];
6483 env->pc = data[0];
6484 if (cc_op != CC_OP_DYNAMIC) {
6485 env->cc_op = cc_op;
6486 }
6487 }
AR7 emulation for QEMU