4 * Copyright (c) 2005-2007 CodeSourcery
5 * Written by Paul Brook
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
25 #include "tcg/tcg-op.h"
27 #include "qemu/qemu-print.h"
28 #include "exec/cpu_ldst.h"
29 #include "exec/translator.h"
31 #include "exec/helper-proto.h"
32 #include "exec/helper-gen.h"
35 #include "fpu/softfloat.h"
38 //#define DEBUG_DISPATCH 1
40 #define DEFO32(name, offset) static TCGv QREG_##name;
41 #define DEFO64(name, offset) static TCGv_i64 QREG_##name;
46 static TCGv_i32 cpu_halted
;
47 static TCGv_i32 cpu_exception_index
;
49 static char cpu_reg_names
[2 * 8 * 3 + 5 * 4];
50 static TCGv cpu_dregs
[8];
51 static TCGv cpu_aregs
[8];
52 static TCGv_i64 cpu_macc
[4];
54 #define REG(insn, pos) (((insn) >> (pos)) & 7)
55 #define DREG(insn, pos) cpu_dregs[REG(insn, pos)]
56 #define AREG(insn, pos) get_areg(s, REG(insn, pos))
57 #define MACREG(acc) cpu_macc[acc]
58 #define QREG_SP get_areg(s, 7)
60 static TCGv NULL_QREG
;
61 #define IS_NULL_QREG(t) (t == NULL_QREG)
62 /* Used to distinguish stores from bad addressing modes. */
63 static TCGv store_dummy
;
65 #include "exec/gen-icount.h"
67 void m68k_tcg_init(void)
72 #define DEFO32(name, offset) \
73 QREG_##name = tcg_global_mem_new_i32(cpu_env, \
74 offsetof(CPUM68KState, offset), #name);
75 #define DEFO64(name, offset) \
76 QREG_##name = tcg_global_mem_new_i64(cpu_env, \
77 offsetof(CPUM68KState, offset), #name);
82 cpu_halted
= tcg_global_mem_new_i32(cpu_env
,
83 -offsetof(M68kCPU
, env
) +
84 offsetof(CPUState
, halted
), "HALTED");
85 cpu_exception_index
= tcg_global_mem_new_i32(cpu_env
,
86 -offsetof(M68kCPU
, env
) +
87 offsetof(CPUState
, exception_index
),
91 for (i
= 0; i
< 8; i
++) {
93 cpu_dregs
[i
] = tcg_global_mem_new(cpu_env
,
94 offsetof(CPUM68KState
, dregs
[i
]), p
);
97 cpu_aregs
[i
] = tcg_global_mem_new(cpu_env
,
98 offsetof(CPUM68KState
, aregs
[i
]), p
);
101 for (i
= 0; i
< 4; i
++) {
102 sprintf(p
, "ACC%d", i
);
103 cpu_macc
[i
] = tcg_global_mem_new_i64(cpu_env
,
104 offsetof(CPUM68KState
, macc
[i
]), p
);
108 NULL_QREG
= tcg_global_mem_new(cpu_env
, -4, "NULL");
109 store_dummy
= tcg_global_mem_new(cpu_env
, -8, "NULL");
112 /* internal defines */
113 typedef struct DisasContext
{
114 DisasContextBase base
;
117 target_ulong pc_prev
;
118 CCOp cc_op
; /* Current CC operation */
124 #define MAX_TO_RELEASE 8
126 TCGv release
[MAX_TO_RELEASE
];
130 static void init_release_array(DisasContext
*s
)
132 #ifdef CONFIG_DEBUG_TCG
133 memset(s
->release
, 0, sizeof(s
->release
));
135 s
->release_count
= 0;
138 static void do_release(DisasContext
*s
)
141 for (i
= 0; i
< s
->release_count
; i
++) {
142 tcg_temp_free(s
->release
[i
]);
144 init_release_array(s
);
147 static TCGv
mark_to_release(DisasContext
*s
, TCGv tmp
)
149 g_assert(s
->release_count
< MAX_TO_RELEASE
);
150 return s
->release
[s
->release_count
++] = tmp
;
153 static TCGv
get_areg(DisasContext
*s
, unsigned regno
)
155 if (s
->writeback_mask
& (1 << regno
)) {
156 return s
->writeback
[regno
];
158 return cpu_aregs
[regno
];
162 static void delay_set_areg(DisasContext
*s
, unsigned regno
,
163 TCGv val
, bool give_temp
)
165 if (s
->writeback_mask
& (1 << regno
)) {
167 tcg_temp_free(s
->writeback
[regno
]);
168 s
->writeback
[regno
] = val
;
170 tcg_gen_mov_i32(s
->writeback
[regno
], val
);
173 s
->writeback_mask
|= 1 << regno
;
175 s
->writeback
[regno
] = val
;
177 TCGv tmp
= tcg_temp_new();
178 s
->writeback
[regno
] = tmp
;
179 tcg_gen_mov_i32(tmp
, val
);
184 static void do_writebacks(DisasContext
*s
)
186 unsigned mask
= s
->writeback_mask
;
188 s
->writeback_mask
= 0;
190 unsigned regno
= ctz32(mask
);
191 tcg_gen_mov_i32(cpu_aregs
[regno
], s
->writeback
[regno
]);
192 tcg_temp_free(s
->writeback
[regno
]);
198 /* is_jmp field values */
199 #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
200 #define DISAS_EXIT DISAS_TARGET_1 /* cpu state was modified dynamically */
202 #if defined(CONFIG_USER_ONLY)
205 #define IS_USER(s) (!(s->base.tb->flags & TB_FLAGS_MSR_S))
206 #define SFC_INDEX(s) ((s->base.tb->flags & TB_FLAGS_SFC_S) ? \
207 MMU_KERNEL_IDX : MMU_USER_IDX)
208 #define DFC_INDEX(s) ((s->base.tb->flags & TB_FLAGS_DFC_S) ? \
209 MMU_KERNEL_IDX : MMU_USER_IDX)
212 typedef void (*disas_proc
)(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
);
214 #ifdef DEBUG_DISPATCH
215 #define DISAS_INSN(name) \
216 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
218 static void disas_##name(CPUM68KState *env, DisasContext *s, \
221 qemu_log("Dispatch " #name "\n"); \
222 real_disas_##name(env, s, insn); \
224 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
227 #define DISAS_INSN(name) \
228 static void disas_##name(CPUM68KState *env, DisasContext *s, \
232 static const uint8_t cc_op_live
[CC_OP_NB
] = {
233 [CC_OP_DYNAMIC
] = CCF_C
| CCF_V
| CCF_Z
| CCF_N
| CCF_X
,
234 [CC_OP_FLAGS
] = CCF_C
| CCF_V
| CCF_Z
| CCF_N
| CCF_X
,
235 [CC_OP_ADDB
... CC_OP_ADDL
] = CCF_X
| CCF_N
| CCF_V
,
236 [CC_OP_SUBB
... CC_OP_SUBL
] = CCF_X
| CCF_N
| CCF_V
,
237 [CC_OP_CMPB
... CC_OP_CMPL
] = CCF_X
| CCF_N
| CCF_V
,
238 [CC_OP_LOGIC
] = CCF_X
| CCF_N
241 static void set_cc_op(DisasContext
*s
, CCOp op
)
243 CCOp old_op
= s
->cc_op
;
253 * Discard CC computation that will no longer be used.
254 * Note that X and N are never dead.
256 dead
= cc_op_live
[old_op
] & ~cc_op_live
[op
];
258 tcg_gen_discard_i32(QREG_CC_C
);
261 tcg_gen_discard_i32(QREG_CC_Z
);
264 tcg_gen_discard_i32(QREG_CC_V
);
268 /* Update the CPU env CC_OP state. */
269 static void update_cc_op(DisasContext
*s
)
271 if (!s
->cc_op_synced
) {
273 tcg_gen_movi_i32(QREG_CC_OP
, s
->cc_op
);
277 /* Generate a jump to an immediate address. */
278 static void gen_jmp_im(DisasContext
*s
, uint32_t dest
)
281 tcg_gen_movi_i32(QREG_PC
, dest
);
282 s
->base
.is_jmp
= DISAS_JUMP
;
285 /* Generate a jump to the address in qreg DEST. */
286 static void gen_jmp(DisasContext
*s
, TCGv dest
)
289 tcg_gen_mov_i32(QREG_PC
, dest
);
290 s
->base
.is_jmp
= DISAS_JUMP
;
293 static void gen_raise_exception(int nr
)
297 tmp
= tcg_const_i32(nr
);
298 gen_helper_raise_exception(cpu_env
, tmp
);
299 tcg_temp_free_i32(tmp
);
302 static void gen_raise_exception_format2(DisasContext
*s
, int nr
,
303 target_ulong this_pc
)
306 * Pass the address of the insn to the exception handler,
307 * for recording in the Format $2 (6-word) stack frame.
308 * Re-use mmu.ar for the purpose, since that's only valid
311 tcg_gen_st_i32(tcg_constant_i32(this_pc
), cpu_env
,
312 offsetof(CPUM68KState
, mmu
.ar
));
313 gen_raise_exception(nr
);
314 s
->base
.is_jmp
= DISAS_NORETURN
;
317 static void gen_exception(DisasContext
*s
, uint32_t dest
, int nr
)
320 tcg_gen_movi_i32(QREG_PC
, dest
);
322 gen_raise_exception(nr
);
324 s
->base
.is_jmp
= DISAS_NORETURN
;
327 static inline void gen_addr_fault(DisasContext
*s
)
329 gen_exception(s
, s
->base
.pc_next
, EXCP_ADDRESS
);
333 * Generate a load from the specified address. Narrow values are
334 * sign extended to full register width.
336 static inline TCGv
gen_load(DisasContext
*s
, int opsize
, TCGv addr
,
340 tmp
= tcg_temp_new_i32();
344 tcg_gen_qemu_ld8s(tmp
, addr
, index
);
346 tcg_gen_qemu_ld8u(tmp
, addr
, index
);
350 tcg_gen_qemu_ld16s(tmp
, addr
, index
);
352 tcg_gen_qemu_ld16u(tmp
, addr
, index
);
355 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
358 g_assert_not_reached();
363 /* Generate a store. */
364 static inline void gen_store(DisasContext
*s
, int opsize
, TCGv addr
, TCGv val
,
369 tcg_gen_qemu_st8(val
, addr
, index
);
372 tcg_gen_qemu_st16(val
, addr
, index
);
375 tcg_gen_qemu_st32(val
, addr
, index
);
378 g_assert_not_reached();
389 * Generate an unsigned load if VAL is 0 a signed load if val is -1,
390 * otherwise generate a store.
392 static TCGv
gen_ldst(DisasContext
*s
, int opsize
, TCGv addr
, TCGv val
,
393 ea_what what
, int index
)
395 if (what
== EA_STORE
) {
396 gen_store(s
, opsize
, addr
, val
, index
);
399 return mark_to_release(s
, gen_load(s
, opsize
, addr
,
400 what
== EA_LOADS
, index
));
404 /* Read a 16-bit immediate constant */
405 static inline uint16_t read_im16(CPUM68KState
*env
, DisasContext
*s
)
408 im
= translator_lduw(env
, &s
->base
, s
->pc
);
413 /* Read an 8-bit immediate constant */
414 static inline uint8_t read_im8(CPUM68KState
*env
, DisasContext
*s
)
416 return read_im16(env
, s
);
419 /* Read a 32-bit immediate constant. */
420 static inline uint32_t read_im32(CPUM68KState
*env
, DisasContext
*s
)
423 im
= read_im16(env
, s
) << 16;
424 im
|= 0xffff & read_im16(env
, s
);
428 /* Read a 64-bit immediate constant. */
429 static inline uint64_t read_im64(CPUM68KState
*env
, DisasContext
*s
)
432 im
= (uint64_t)read_im32(env
, s
) << 32;
433 im
|= (uint64_t)read_im32(env
, s
);
437 /* Calculate and address index. */
438 static TCGv
gen_addr_index(DisasContext
*s
, uint16_t ext
, TCGv tmp
)
443 add
= (ext
& 0x8000) ? AREG(ext
, 12) : DREG(ext
, 12);
444 if ((ext
& 0x800) == 0) {
445 tcg_gen_ext16s_i32(tmp
, add
);
448 scale
= (ext
>> 9) & 3;
450 tcg_gen_shli_i32(tmp
, add
, scale
);
457 * Handle a base + index + displacement effective address.
458 * A NULL_QREG base means pc-relative.
460 static TCGv
gen_lea_indexed(CPUM68KState
*env
, DisasContext
*s
, TCGv base
)
469 ext
= read_im16(env
, s
);
471 if ((ext
& 0x800) == 0 && !m68k_feature(s
->env
, M68K_FEATURE_WORD_INDEX
))
474 if (m68k_feature(s
->env
, M68K_FEATURE_M68K
) &&
475 !m68k_feature(s
->env
, M68K_FEATURE_SCALED_INDEX
)) {
480 /* full extension word format */
481 if (!m68k_feature(s
->env
, M68K_FEATURE_EXT_FULL
))
484 if ((ext
& 0x30) > 0x10) {
485 /* base displacement */
486 if ((ext
& 0x30) == 0x20) {
487 bd
= (int16_t)read_im16(env
, s
);
489 bd
= read_im32(env
, s
);
494 tmp
= mark_to_release(s
, tcg_temp_new());
495 if ((ext
& 0x44) == 0) {
497 add
= gen_addr_index(s
, ext
, tmp
);
501 if ((ext
& 0x80) == 0) {
502 /* base not suppressed */
503 if (IS_NULL_QREG(base
)) {
504 base
= mark_to_release(s
, tcg_const_i32(offset
+ bd
));
507 if (!IS_NULL_QREG(add
)) {
508 tcg_gen_add_i32(tmp
, add
, base
);
514 if (!IS_NULL_QREG(add
)) {
516 tcg_gen_addi_i32(tmp
, add
, bd
);
520 add
= mark_to_release(s
, tcg_const_i32(bd
));
522 if ((ext
& 3) != 0) {
523 /* memory indirect */
524 base
= mark_to_release(s
, gen_load(s
, OS_LONG
, add
, 0, IS_USER(s
)));
525 if ((ext
& 0x44) == 4) {
526 add
= gen_addr_index(s
, ext
, tmp
);
527 tcg_gen_add_i32(tmp
, add
, base
);
533 /* outer displacement */
534 if ((ext
& 3) == 2) {
535 od
= (int16_t)read_im16(env
, s
);
537 od
= read_im32(env
, s
);
543 tcg_gen_addi_i32(tmp
, add
, od
);
548 /* brief extension word format */
549 tmp
= mark_to_release(s
, tcg_temp_new());
550 add
= gen_addr_index(s
, ext
, tmp
);
551 if (!IS_NULL_QREG(base
)) {
552 tcg_gen_add_i32(tmp
, add
, base
);
554 tcg_gen_addi_i32(tmp
, tmp
, (int8_t)ext
);
556 tcg_gen_addi_i32(tmp
, add
, offset
+ (int8_t)ext
);
563 /* Sign or zero extend a value. */
565 static inline void gen_ext(TCGv res
, TCGv val
, int opsize
, int sign
)
570 tcg_gen_ext8s_i32(res
, val
);
572 tcg_gen_ext8u_i32(res
, val
);
577 tcg_gen_ext16s_i32(res
, val
);
579 tcg_gen_ext16u_i32(res
, val
);
583 tcg_gen_mov_i32(res
, val
);
586 g_assert_not_reached();
590 /* Evaluate all the CC flags. */
592 static void gen_flush_flags(DisasContext
*s
)
603 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
604 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
605 /* Compute signed overflow for addition. */
608 tcg_gen_sub_i32(t0
, QREG_CC_N
, QREG_CC_V
);
609 gen_ext(t0
, t0
, s
->cc_op
- CC_OP_ADDB
, 1);
610 tcg_gen_xor_i32(t1
, QREG_CC_N
, QREG_CC_V
);
611 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_V
, t0
);
613 tcg_gen_andc_i32(QREG_CC_V
, t1
, QREG_CC_V
);
620 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
621 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
622 /* Compute signed overflow for subtraction. */
625 tcg_gen_add_i32(t0
, QREG_CC_N
, QREG_CC_V
);
626 gen_ext(t0
, t0
, s
->cc_op
- CC_OP_SUBB
, 1);
627 tcg_gen_xor_i32(t1
, QREG_CC_N
, t0
);
628 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_V
, t0
);
630 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_V
, t1
);
637 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_C
, QREG_CC_N
, QREG_CC_V
);
638 tcg_gen_sub_i32(QREG_CC_Z
, QREG_CC_N
, QREG_CC_V
);
639 gen_ext(QREG_CC_Z
, QREG_CC_Z
, s
->cc_op
- CC_OP_CMPB
, 1);
640 /* Compute signed overflow for subtraction. */
642 tcg_gen_xor_i32(t0
, QREG_CC_Z
, QREG_CC_N
);
643 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_V
, QREG_CC_N
);
644 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_V
, t0
);
646 tcg_gen_mov_i32(QREG_CC_N
, QREG_CC_Z
);
650 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
651 tcg_gen_movi_i32(QREG_CC_C
, 0);
652 tcg_gen_movi_i32(QREG_CC_V
, 0);
656 gen_helper_flush_flags(cpu_env
, QREG_CC_OP
);
661 t0
= tcg_const_i32(s
->cc_op
);
662 gen_helper_flush_flags(cpu_env
, t0
);
668 /* Note that flush_flags also assigned to env->cc_op. */
669 s
->cc_op
= CC_OP_FLAGS
;
672 static inline TCGv
gen_extend(DisasContext
*s
, TCGv val
, int opsize
, int sign
)
676 if (opsize
== OS_LONG
) {
679 tmp
= mark_to_release(s
, tcg_temp_new());
680 gen_ext(tmp
, val
, opsize
, sign
);
686 static void gen_logic_cc(DisasContext
*s
, TCGv val
, int opsize
)
688 gen_ext(QREG_CC_N
, val
, opsize
, 1);
689 set_cc_op(s
, CC_OP_LOGIC
);
692 static void gen_update_cc_cmp(DisasContext
*s
, TCGv dest
, TCGv src
, int opsize
)
694 tcg_gen_mov_i32(QREG_CC_N
, dest
);
695 tcg_gen_mov_i32(QREG_CC_V
, src
);
696 set_cc_op(s
, CC_OP_CMPB
+ opsize
);
699 static void gen_update_cc_add(TCGv dest
, TCGv src
, int opsize
)
701 gen_ext(QREG_CC_N
, dest
, opsize
, 1);
702 tcg_gen_mov_i32(QREG_CC_V
, src
);
705 static inline int opsize_bytes(int opsize
)
708 case OS_BYTE
: return 1;
709 case OS_WORD
: return 2;
710 case OS_LONG
: return 4;
711 case OS_SINGLE
: return 4;
712 case OS_DOUBLE
: return 8;
713 case OS_EXTENDED
: return 12;
714 case OS_PACKED
: return 12;
716 g_assert_not_reached();
720 static inline int insn_opsize(int insn
)
722 switch ((insn
>> 6) & 3) {
723 case 0: return OS_BYTE
;
724 case 1: return OS_WORD
;
725 case 2: return OS_LONG
;
727 g_assert_not_reached();
731 static inline int ext_opsize(int ext
, int pos
)
733 switch ((ext
>> pos
) & 7) {
734 case 0: return OS_LONG
;
735 case 1: return OS_SINGLE
;
736 case 2: return OS_EXTENDED
;
737 case 3: return OS_PACKED
;
738 case 4: return OS_WORD
;
739 case 5: return OS_DOUBLE
;
740 case 6: return OS_BYTE
;
742 g_assert_not_reached();
747 * Assign value to a register. If the width is less than the register width
748 * only the low part of the register is set.
750 static void gen_partset_reg(int opsize
, TCGv reg
, TCGv val
)
755 tcg_gen_andi_i32(reg
, reg
, 0xffffff00);
756 tmp
= tcg_temp_new();
757 tcg_gen_ext8u_i32(tmp
, val
);
758 tcg_gen_or_i32(reg
, reg
, tmp
);
762 tcg_gen_andi_i32(reg
, reg
, 0xffff0000);
763 tmp
= tcg_temp_new();
764 tcg_gen_ext16u_i32(tmp
, val
);
765 tcg_gen_or_i32(reg
, reg
, tmp
);
770 tcg_gen_mov_i32(reg
, val
);
773 g_assert_not_reached();
778 * Generate code for an "effective address". Does not adjust the base
779 * register for autoincrement addressing modes.
781 static TCGv
gen_lea_mode(CPUM68KState
*env
, DisasContext
*s
,
782 int mode
, int reg0
, int opsize
)
790 case 0: /* Data register direct. */
791 case 1: /* Address register direct. */
793 case 3: /* Indirect postincrement. */
794 if (opsize
== OS_UNSIZED
) {
798 case 2: /* Indirect register */
799 return get_areg(s
, reg0
);
800 case 4: /* Indirect predecrememnt. */
801 if (opsize
== OS_UNSIZED
) {
804 reg
= get_areg(s
, reg0
);
805 tmp
= mark_to_release(s
, tcg_temp_new());
806 if (reg0
== 7 && opsize
== OS_BYTE
&&
807 m68k_feature(s
->env
, M68K_FEATURE_M68K
)) {
808 tcg_gen_subi_i32(tmp
, reg
, 2);
810 tcg_gen_subi_i32(tmp
, reg
, opsize_bytes(opsize
));
813 case 5: /* Indirect displacement. */
814 reg
= get_areg(s
, reg0
);
815 tmp
= mark_to_release(s
, tcg_temp_new());
816 ext
= read_im16(env
, s
);
817 tcg_gen_addi_i32(tmp
, reg
, (int16_t)ext
);
819 case 6: /* Indirect index + displacement. */
820 reg
= get_areg(s
, reg0
);
821 return gen_lea_indexed(env
, s
, reg
);
824 case 0: /* Absolute short. */
825 offset
= (int16_t)read_im16(env
, s
);
826 return mark_to_release(s
, tcg_const_i32(offset
));
827 case 1: /* Absolute long. */
828 offset
= read_im32(env
, s
);
829 return mark_to_release(s
, tcg_const_i32(offset
));
830 case 2: /* pc displacement */
832 offset
+= (int16_t)read_im16(env
, s
);
833 return mark_to_release(s
, tcg_const_i32(offset
));
834 case 3: /* pc index+displacement. */
835 return gen_lea_indexed(env
, s
, NULL_QREG
);
836 case 4: /* Immediate. */
841 /* Should never happen. */
845 static TCGv
gen_lea(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
848 int mode
= extract32(insn
, 3, 3);
849 int reg0
= REG(insn
, 0);
850 return gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
854 * Generate code to load/store a value from/into an EA. If WHAT > 0 this is
855 * a write otherwise it is a read (0 == sign extend, -1 == zero extend).
856 * ADDRP is non-null for readwrite operands.
858 static TCGv
gen_ea_mode(CPUM68KState
*env
, DisasContext
*s
, int mode
, int reg0
,
859 int opsize
, TCGv val
, TCGv
*addrp
, ea_what what
,
862 TCGv reg
, tmp
, result
;
866 case 0: /* Data register direct. */
867 reg
= cpu_dregs
[reg0
];
868 if (what
== EA_STORE
) {
869 gen_partset_reg(opsize
, reg
, val
);
872 return gen_extend(s
, reg
, opsize
, what
== EA_LOADS
);
874 case 1: /* Address register direct. */
875 reg
= get_areg(s
, reg0
);
876 if (what
== EA_STORE
) {
877 tcg_gen_mov_i32(reg
, val
);
880 return gen_extend(s
, reg
, opsize
, what
== EA_LOADS
);
882 case 2: /* Indirect register */
883 reg
= get_areg(s
, reg0
);
884 return gen_ldst(s
, opsize
, reg
, val
, what
, index
);
885 case 3: /* Indirect postincrement. */
886 reg
= get_areg(s
, reg0
);
887 result
= gen_ldst(s
, opsize
, reg
, val
, what
, index
);
888 if (what
== EA_STORE
|| !addrp
) {
889 TCGv tmp
= tcg_temp_new();
890 if (reg0
== 7 && opsize
== OS_BYTE
&&
891 m68k_feature(s
->env
, M68K_FEATURE_M68K
)) {
892 tcg_gen_addi_i32(tmp
, reg
, 2);
894 tcg_gen_addi_i32(tmp
, reg
, opsize_bytes(opsize
));
896 delay_set_areg(s
, reg0
, tmp
, true);
899 case 4: /* Indirect predecrememnt. */
900 if (addrp
&& what
== EA_STORE
) {
903 tmp
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
904 if (IS_NULL_QREG(tmp
)) {
911 result
= gen_ldst(s
, opsize
, tmp
, val
, what
, index
);
912 if (what
== EA_STORE
|| !addrp
) {
913 delay_set_areg(s
, reg0
, tmp
, false);
916 case 5: /* Indirect displacement. */
917 case 6: /* Indirect index + displacement. */
919 if (addrp
&& what
== EA_STORE
) {
922 tmp
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
923 if (IS_NULL_QREG(tmp
)) {
930 return gen_ldst(s
, opsize
, tmp
, val
, what
, index
);
933 case 0: /* Absolute short. */
934 case 1: /* Absolute long. */
935 case 2: /* pc displacement */
936 case 3: /* pc index+displacement. */
938 case 4: /* Immediate. */
939 /* Sign extend values for consistency. */
942 if (what
== EA_LOADS
) {
943 offset
= (int8_t)read_im8(env
, s
);
945 offset
= read_im8(env
, s
);
949 if (what
== EA_LOADS
) {
950 offset
= (int16_t)read_im16(env
, s
);
952 offset
= read_im16(env
, s
);
956 offset
= read_im32(env
, s
);
959 g_assert_not_reached();
961 return mark_to_release(s
, tcg_const_i32(offset
));
966 /* Should never happen. */
970 static TCGv
gen_ea(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
971 int opsize
, TCGv val
, TCGv
*addrp
, ea_what what
, int index
)
973 int mode
= extract32(insn
, 3, 3);
974 int reg0
= REG(insn
, 0);
975 return gen_ea_mode(env
, s
, mode
, reg0
, opsize
, val
, addrp
, what
, index
);
978 static TCGv_ptr
gen_fp_ptr(int freg
)
980 TCGv_ptr fp
= tcg_temp_new_ptr();
981 tcg_gen_addi_ptr(fp
, cpu_env
, offsetof(CPUM68KState
, fregs
[freg
]));
985 static TCGv_ptr
gen_fp_result_ptr(void)
987 TCGv_ptr fp
= tcg_temp_new_ptr();
988 tcg_gen_addi_ptr(fp
, cpu_env
, offsetof(CPUM68KState
, fp_result
));
992 static void gen_fp_move(TCGv_ptr dest
, TCGv_ptr src
)
997 t32
= tcg_temp_new();
998 tcg_gen_ld16u_i32(t32
, src
, offsetof(FPReg
, l
.upper
));
999 tcg_gen_st16_i32(t32
, dest
, offsetof(FPReg
, l
.upper
));
1002 t64
= tcg_temp_new_i64();
1003 tcg_gen_ld_i64(t64
, src
, offsetof(FPReg
, l
.lower
));
1004 tcg_gen_st_i64(t64
, dest
, offsetof(FPReg
, l
.lower
));
1005 tcg_temp_free_i64(t64
);
1008 static void gen_load_fp(DisasContext
*s
, int opsize
, TCGv addr
, TCGv_ptr fp
,
1014 t64
= tcg_temp_new_i64();
1015 tmp
= tcg_temp_new();
1018 tcg_gen_qemu_ld8s(tmp
, addr
, index
);
1019 gen_helper_exts32(cpu_env
, fp
, tmp
);
1022 tcg_gen_qemu_ld16s(tmp
, addr
, index
);
1023 gen_helper_exts32(cpu_env
, fp
, tmp
);
1026 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
1027 gen_helper_exts32(cpu_env
, fp
, tmp
);
1030 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
1031 gen_helper_extf32(cpu_env
, fp
, tmp
);
1034 tcg_gen_qemu_ld64(t64
, addr
, index
);
1035 gen_helper_extf64(cpu_env
, fp
, t64
);
1038 if (m68k_feature(s
->env
, M68K_FEATURE_CF_FPU
)) {
1039 gen_exception(s
, s
->base
.pc_next
, EXCP_FP_UNIMP
);
1042 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
1043 tcg_gen_shri_i32(tmp
, tmp
, 16);
1044 tcg_gen_st16_i32(tmp
, fp
, offsetof(FPReg
, l
.upper
));
1045 tcg_gen_addi_i32(tmp
, addr
, 4);
1046 tcg_gen_qemu_ld64(t64
, tmp
, index
);
1047 tcg_gen_st_i64(t64
, fp
, offsetof(FPReg
, l
.lower
));
1051 * unimplemented data type on 68040/ColdFire
1052 * FIXME if needed for another FPU
1054 gen_exception(s
, s
->base
.pc_next
, EXCP_FP_UNIMP
);
1057 g_assert_not_reached();
1060 tcg_temp_free_i64(t64
);
1063 static void gen_store_fp(DisasContext
*s
, int opsize
, TCGv addr
, TCGv_ptr fp
,
1069 t64
= tcg_temp_new_i64();
1070 tmp
= tcg_temp_new();
1073 gen_helper_reds32(tmp
, cpu_env
, fp
);
1074 tcg_gen_qemu_st8(tmp
, addr
, index
);
1077 gen_helper_reds32(tmp
, cpu_env
, fp
);
1078 tcg_gen_qemu_st16(tmp
, addr
, index
);
1081 gen_helper_reds32(tmp
, cpu_env
, fp
);
1082 tcg_gen_qemu_st32(tmp
, addr
, index
);
1085 gen_helper_redf32(tmp
, cpu_env
, fp
);
1086 tcg_gen_qemu_st32(tmp
, addr
, index
);
1089 gen_helper_redf64(t64
, cpu_env
, fp
);
1090 tcg_gen_qemu_st64(t64
, addr
, index
);
1093 if (m68k_feature(s
->env
, M68K_FEATURE_CF_FPU
)) {
1094 gen_exception(s
, s
->base
.pc_next
, EXCP_FP_UNIMP
);
1097 tcg_gen_ld16u_i32(tmp
, fp
, offsetof(FPReg
, l
.upper
));
1098 tcg_gen_shli_i32(tmp
, tmp
, 16);
1099 tcg_gen_qemu_st32(tmp
, addr
, index
);
1100 tcg_gen_addi_i32(tmp
, addr
, 4);
1101 tcg_gen_ld_i64(t64
, fp
, offsetof(FPReg
, l
.lower
));
1102 tcg_gen_qemu_st64(t64
, tmp
, index
);
1106 * unimplemented data type on 68040/ColdFire
1107 * FIXME if needed for another FPU
1109 gen_exception(s
, s
->base
.pc_next
, EXCP_FP_UNIMP
);
1112 g_assert_not_reached();
1115 tcg_temp_free_i64(t64
);
1118 static void gen_ldst_fp(DisasContext
*s
, int opsize
, TCGv addr
,
1119 TCGv_ptr fp
, ea_what what
, int index
)
1121 if (what
== EA_STORE
) {
1122 gen_store_fp(s
, opsize
, addr
, fp
, index
);
1124 gen_load_fp(s
, opsize
, addr
, fp
, index
);
1128 static int gen_ea_mode_fp(CPUM68KState
*env
, DisasContext
*s
, int mode
,
1129 int reg0
, int opsize
, TCGv_ptr fp
, ea_what what
,
1132 TCGv reg
, addr
, tmp
;
1136 case 0: /* Data register direct. */
1137 reg
= cpu_dregs
[reg0
];
1138 if (what
== EA_STORE
) {
1143 gen_helper_reds32(reg
, cpu_env
, fp
);
1146 gen_helper_redf32(reg
, cpu_env
, fp
);
1149 g_assert_not_reached();
1152 tmp
= tcg_temp_new();
1155 tcg_gen_ext8s_i32(tmp
, reg
);
1156 gen_helper_exts32(cpu_env
, fp
, tmp
);
1159 tcg_gen_ext16s_i32(tmp
, reg
);
1160 gen_helper_exts32(cpu_env
, fp
, tmp
);
1163 gen_helper_exts32(cpu_env
, fp
, reg
);
1166 gen_helper_extf32(cpu_env
, fp
, reg
);
1169 g_assert_not_reached();
1174 case 1: /* Address register direct. */
1176 case 2: /* Indirect register */
1177 addr
= get_areg(s
, reg0
);
1178 gen_ldst_fp(s
, opsize
, addr
, fp
, what
, index
);
1180 case 3: /* Indirect postincrement. */
1181 addr
= cpu_aregs
[reg0
];
1182 gen_ldst_fp(s
, opsize
, addr
, fp
, what
, index
);
1183 tcg_gen_addi_i32(addr
, addr
, opsize_bytes(opsize
));
1185 case 4: /* Indirect predecrememnt. */
1186 addr
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
1187 if (IS_NULL_QREG(addr
)) {
1190 gen_ldst_fp(s
, opsize
, addr
, fp
, what
, index
);
1191 tcg_gen_mov_i32(cpu_aregs
[reg0
], addr
);
1193 case 5: /* Indirect displacement. */
1194 case 6: /* Indirect index + displacement. */
1196 addr
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
1197 if (IS_NULL_QREG(addr
)) {
1200 gen_ldst_fp(s
, opsize
, addr
, fp
, what
, index
);
1204 case 0: /* Absolute short. */
1205 case 1: /* Absolute long. */
1206 case 2: /* pc displacement */
1207 case 3: /* pc index+displacement. */
1209 case 4: /* Immediate. */
1210 if (what
== EA_STORE
) {
1215 tmp
= tcg_const_i32((int8_t)read_im8(env
, s
));
1216 gen_helper_exts32(cpu_env
, fp
, tmp
);
1220 tmp
= tcg_const_i32((int16_t)read_im16(env
, s
));
1221 gen_helper_exts32(cpu_env
, fp
, tmp
);
1225 tmp
= tcg_const_i32(read_im32(env
, s
));
1226 gen_helper_exts32(cpu_env
, fp
, tmp
);
1230 tmp
= tcg_const_i32(read_im32(env
, s
));
1231 gen_helper_extf32(cpu_env
, fp
, tmp
);
1235 t64
= tcg_const_i64(read_im64(env
, s
));
1236 gen_helper_extf64(cpu_env
, fp
, t64
);
1237 tcg_temp_free_i64(t64
);
1240 if (m68k_feature(s
->env
, M68K_FEATURE_CF_FPU
)) {
1241 gen_exception(s
, s
->base
.pc_next
, EXCP_FP_UNIMP
);
1244 tmp
= tcg_const_i32(read_im32(env
, s
) >> 16);
1245 tcg_gen_st16_i32(tmp
, fp
, offsetof(FPReg
, l
.upper
));
1247 t64
= tcg_const_i64(read_im64(env
, s
));
1248 tcg_gen_st_i64(t64
, fp
, offsetof(FPReg
, l
.lower
));
1249 tcg_temp_free_i64(t64
);
1253 * unimplemented data type on 68040/ColdFire
1254 * FIXME if needed for another FPU
1256 gen_exception(s
, s
->base
.pc_next
, EXCP_FP_UNIMP
);
1259 g_assert_not_reached();
1269 static int gen_ea_fp(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
1270 int opsize
, TCGv_ptr fp
, ea_what what
, int index
)
1272 int mode
= extract32(insn
, 3, 3);
1273 int reg0
= REG(insn
, 0);
1274 return gen_ea_mode_fp(env
, s
, mode
, reg0
, opsize
, fp
, what
, index
);
1285 static void gen_cc_cond(DisasCompare
*c
, DisasContext
*s
, int cond
)
1291 /* The CC_OP_CMP form can handle most normal comparisons directly. */
1292 if (op
== CC_OP_CMPB
|| op
== CC_OP_CMPW
|| op
== CC_OP_CMPL
) {
1299 tcond
= TCG_COND_LEU
;
1303 tcond
= TCG_COND_LTU
;
1307 tcond
= TCG_COND_EQ
;
1312 c
->v2
= tcg_const_i32(0);
1313 c
->v1
= tmp
= tcg_temp_new();
1314 tcg_gen_sub_i32(tmp
, QREG_CC_N
, QREG_CC_V
);
1315 gen_ext(tmp
, tmp
, op
- CC_OP_CMPB
, 1);
1319 tcond
= TCG_COND_LT
;
1323 tcond
= TCG_COND_LE
;
1330 c
->v2
= tcg_const_i32(0);
1336 tcond
= TCG_COND_NEVER
;
1338 case 14: /* GT (!(Z || (N ^ V))) */
1339 case 15: /* LE (Z || (N ^ V)) */
1341 * Logic operations clear V, which simplifies LE to (Z || N),
1342 * and since Z and N are co-located, this becomes a normal
1345 if (op
== CC_OP_LOGIC
) {
1347 tcond
= TCG_COND_LE
;
1351 case 12: /* GE (!(N ^ V)) */
1352 case 13: /* LT (N ^ V) */
1353 /* Logic operations clear V, which simplifies this to N. */
1354 if (op
!= CC_OP_LOGIC
) {
1358 case 10: /* PL (!N) */
1359 case 11: /* MI (N) */
1360 /* Several cases represent N normally. */
1361 if (op
== CC_OP_ADDB
|| op
== CC_OP_ADDW
|| op
== CC_OP_ADDL
||
1362 op
== CC_OP_SUBB
|| op
== CC_OP_SUBW
|| op
== CC_OP_SUBL
||
1363 op
== CC_OP_LOGIC
) {
1365 tcond
= TCG_COND_LT
;
1369 case 6: /* NE (!Z) */
1370 case 7: /* EQ (Z) */
1371 /* Some cases fold Z into N. */
1372 if (op
== CC_OP_ADDB
|| op
== CC_OP_ADDW
|| op
== CC_OP_ADDL
||
1373 op
== CC_OP_SUBB
|| op
== CC_OP_SUBW
|| op
== CC_OP_SUBL
||
1374 op
== CC_OP_LOGIC
) {
1375 tcond
= TCG_COND_EQ
;
1380 case 4: /* CC (!C) */
1381 case 5: /* CS (C) */
1382 /* Some cases fold C into X. */
1383 if (op
== CC_OP_ADDB
|| op
== CC_OP_ADDW
|| op
== CC_OP_ADDL
||
1384 op
== CC_OP_SUBB
|| op
== CC_OP_SUBW
|| op
== CC_OP_SUBL
) {
1385 tcond
= TCG_COND_NE
;
1390 case 8: /* VC (!V) */
1391 case 9: /* VS (V) */
1392 /* Logic operations clear V and C. */
1393 if (op
== CC_OP_LOGIC
) {
1394 tcond
= TCG_COND_NEVER
;
1401 /* Otherwise, flush flag state to CC_OP_FLAGS. */
1408 /* Invalid, or handled above. */
1410 case 2: /* HI (!C && !Z) -> !(C || Z)*/
1411 case 3: /* LS (C || Z) */
1412 c
->v1
= tmp
= tcg_temp_new();
1414 tcg_gen_setcond_i32(TCG_COND_EQ
, tmp
, QREG_CC_Z
, c
->v2
);
1415 tcg_gen_or_i32(tmp
, tmp
, QREG_CC_C
);
1416 tcond
= TCG_COND_NE
;
1418 case 4: /* CC (!C) */
1419 case 5: /* CS (C) */
1421 tcond
= TCG_COND_NE
;
1423 case 6: /* NE (!Z) */
1424 case 7: /* EQ (Z) */
1426 tcond
= TCG_COND_EQ
;
1428 case 8: /* VC (!V) */
1429 case 9: /* VS (V) */
1431 tcond
= TCG_COND_LT
;
1433 case 10: /* PL (!N) */
1434 case 11: /* MI (N) */
1436 tcond
= TCG_COND_LT
;
1438 case 12: /* GE (!(N ^ V)) */
1439 case 13: /* LT (N ^ V) */
1440 c
->v1
= tmp
= tcg_temp_new();
1442 tcg_gen_xor_i32(tmp
, QREG_CC_N
, QREG_CC_V
);
1443 tcond
= TCG_COND_LT
;
1445 case 14: /* GT (!(Z || (N ^ V))) */
1446 case 15: /* LE (Z || (N ^ V)) */
1447 c
->v1
= tmp
= tcg_temp_new();
1449 tcg_gen_setcond_i32(TCG_COND_EQ
, tmp
, QREG_CC_Z
, c
->v2
);
1450 tcg_gen_neg_i32(tmp
, tmp
);
1451 tmp2
= tcg_temp_new();
1452 tcg_gen_xor_i32(tmp2
, QREG_CC_N
, QREG_CC_V
);
1453 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
1454 tcg_temp_free(tmp2
);
1455 tcond
= TCG_COND_LT
;
1460 if ((cond
& 1) == 0) {
1461 tcond
= tcg_invert_cond(tcond
);
1466 static void free_cond(DisasCompare
*c
)
1469 tcg_temp_free(c
->v1
);
1472 tcg_temp_free(c
->v2
);
1476 static void gen_jmpcc(DisasContext
*s
, int cond
, TCGLabel
*l1
)
1480 gen_cc_cond(&c
, s
, cond
);
1482 tcg_gen_brcond_i32(c
.tcond
, c
.v1
, c
.v2
, l1
);
1486 /* Force a TB lookup after an instruction that changes the CPU state. */
1487 static void gen_exit_tb(DisasContext
*s
)
1490 tcg_gen_movi_i32(QREG_PC
, s
->pc
);
1491 s
->base
.is_jmp
= DISAS_EXIT
;
1494 #define SRC_EA(env, result, opsize, op_sign, addrp) do { \
1495 result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \
1496 op_sign ? EA_LOADS : EA_LOADU, IS_USER(s)); \
1497 if (IS_NULL_QREG(result)) { \
1498 gen_addr_fault(s); \
1503 #define DEST_EA(env, insn, opsize, val, addrp) do { \
1504 TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, \
1505 EA_STORE, IS_USER(s)); \
1506 if (IS_NULL_QREG(ea_result)) { \
1507 gen_addr_fault(s); \
1512 /* Generate a jump to an immediate address. */
1513 static void gen_jmp_tb(DisasContext
*s
, int n
, target_ulong dest
,
1516 if (unlikely(s
->ss_active
)) {
1518 tcg_gen_movi_i32(QREG_PC
, dest
);
1519 gen_raise_exception_format2(s
, EXCP_TRACE
, src
);
1520 } else if (translator_use_goto_tb(&s
->base
, dest
)) {
1522 tcg_gen_movi_i32(QREG_PC
, dest
);
1523 tcg_gen_exit_tb(s
->base
.tb
, n
);
1525 gen_jmp_im(s
, dest
);
1526 tcg_gen_exit_tb(NULL
, 0);
1528 s
->base
.is_jmp
= DISAS_NORETURN
;
1537 cond
= (insn
>> 8) & 0xf;
1538 gen_cc_cond(&c
, s
, cond
);
1540 tmp
= tcg_temp_new();
1541 tcg_gen_setcond_i32(c
.tcond
, tmp
, c
.v1
, c
.v2
);
1544 tcg_gen_neg_i32(tmp
, tmp
);
1545 DEST_EA(env
, insn
, OS_BYTE
, tmp
, NULL
);
1557 reg
= DREG(insn
, 0);
1559 offset
= (int16_t)read_im16(env
, s
);
1560 l1
= gen_new_label();
1561 gen_jmpcc(s
, (insn
>> 8) & 0xf, l1
);
1563 tmp
= tcg_temp_new();
1564 tcg_gen_ext16s_i32(tmp
, reg
);
1565 tcg_gen_addi_i32(tmp
, tmp
, -1);
1566 gen_partset_reg(OS_WORD
, reg
, tmp
);
1567 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, -1, l1
);
1568 gen_jmp_tb(s
, 1, base
+ offset
, s
->base
.pc_next
);
1570 gen_jmp_tb(s
, 0, s
->pc
, s
->base
.pc_next
);
1573 DISAS_INSN(undef_mac
)
1575 gen_exception(s
, s
->base
.pc_next
, EXCP_LINEA
);
1578 DISAS_INSN(undef_fpu
)
1580 gen_exception(s
, s
->base
.pc_next
, EXCP_LINEF
);
1586 * ??? This is both instructions that are as yet unimplemented
1587 * for the 680x0 series, as well as those that are implemented
1588 * but actually illegal for CPU32 or pre-68020.
1590 qemu_log_mask(LOG_UNIMP
, "Illegal instruction: %04x @ %08x\n",
1591 insn
, s
->base
.pc_next
);
1592 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
1602 sign
= (insn
& 0x100) != 0;
1603 reg
= DREG(insn
, 9);
1604 tmp
= tcg_temp_new();
1606 tcg_gen_ext16s_i32(tmp
, reg
);
1608 tcg_gen_ext16u_i32(tmp
, reg
);
1609 SRC_EA(env
, src
, OS_WORD
, sign
, NULL
);
1610 tcg_gen_mul_i32(tmp
, tmp
, src
);
1611 tcg_gen_mov_i32(reg
, tmp
);
1612 gen_logic_cc(s
, tmp
, OS_LONG
);
1623 /* divX.w <EA>,Dn 32/16 -> 16r:16q */
1625 sign
= (insn
& 0x100) != 0;
1627 /* dest.l / src.w */
1629 SRC_EA(env
, src
, OS_WORD
, sign
, NULL
);
1630 destr
= tcg_constant_i32(REG(insn
, 9));
1631 ilen
= tcg_constant_i32(s
->pc
- s
->base
.pc_next
);
1633 gen_helper_divsw(cpu_env
, destr
, src
, ilen
);
1635 gen_helper_divuw(cpu_env
, destr
, src
, ilen
);
1638 set_cc_op(s
, CC_OP_FLAGS
);
1643 TCGv num
, reg
, den
, ilen
;
1647 ext
= read_im16(env
, s
);
1649 sign
= (ext
& 0x0800) != 0;
1652 if (!m68k_feature(s
->env
, M68K_FEATURE_QUAD_MULDIV
)) {
1653 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
1657 /* divX.l <EA>, Dr:Dq 64/32 -> 32r:32q */
1659 SRC_EA(env
, den
, OS_LONG
, 0, NULL
);
1660 num
= tcg_constant_i32(REG(ext
, 12));
1661 reg
= tcg_constant_i32(REG(ext
, 0));
1662 ilen
= tcg_constant_i32(s
->pc
- s
->base
.pc_next
);
1664 gen_helper_divsll(cpu_env
, num
, reg
, den
, ilen
);
1666 gen_helper_divull(cpu_env
, num
, reg
, den
, ilen
);
1668 set_cc_op(s
, CC_OP_FLAGS
);
1672 /* divX.l <EA>, Dq 32/32 -> 32q */
1673 /* divXl.l <EA>, Dr:Dq 32/32 -> 32r:32q */
1675 SRC_EA(env
, den
, OS_LONG
, 0, NULL
);
1676 num
= tcg_constant_i32(REG(ext
, 12));
1677 reg
= tcg_constant_i32(REG(ext
, 0));
1678 ilen
= tcg_constant_i32(s
->pc
- s
->base
.pc_next
);
1680 gen_helper_divsl(cpu_env
, num
, reg
, den
, ilen
);
1682 gen_helper_divul(cpu_env
, num
, reg
, den
, ilen
);
1685 set_cc_op(s
, CC_OP_FLAGS
);
1688 static void bcd_add(TCGv dest
, TCGv src
)
1693 * dest10 = dest10 + src10 + X
1697 * t3 = t2 + dest + X
1701 * t7 = (t6 >> 2) | (t6 >> 3)
1706 * t1 = (src + 0x066) + dest + X
1707 * = result with some possible exceeding 0x6
1710 t0
= tcg_const_i32(0x066);
1711 tcg_gen_add_i32(t0
, t0
, src
);
1713 t1
= tcg_temp_new();
1714 tcg_gen_add_i32(t1
, t0
, dest
);
1715 tcg_gen_add_i32(t1
, t1
, QREG_CC_X
);
1717 /* we will remove exceeding 0x6 where there is no carry */
1720 * t0 = (src + 0x0066) ^ dest
1721 * = t1 without carries
1724 tcg_gen_xor_i32(t0
, t0
, dest
);
1727 * extract the carries
1729 * = only the carries
1732 tcg_gen_xor_i32(t0
, t0
, t1
);
1735 * generate 0x1 where there is no carry
1736 * and for each 0x10, generate a 0x6
1739 tcg_gen_shri_i32(t0
, t0
, 3);
1740 tcg_gen_not_i32(t0
, t0
);
1741 tcg_gen_andi_i32(t0
, t0
, 0x22);
1742 tcg_gen_add_i32(dest
, t0
, t0
);
1743 tcg_gen_add_i32(dest
, dest
, t0
);
1747 * remove the exceeding 0x6
1748 * for digits that have not generated a carry
1751 tcg_gen_sub_i32(dest
, t1
, dest
);
1755 static void bcd_sub(TCGv dest
, TCGv src
)
1760 * dest10 = dest10 - src10 - X
1761 * = bcd_add(dest + 1 - X, 0x199 - src)
1764 /* t0 = 0x066 + (0x199 - src) */
1766 t0
= tcg_temp_new();
1767 tcg_gen_subfi_i32(t0
, 0x1ff, src
);
1769 /* t1 = t0 + dest + 1 - X*/
1771 t1
= tcg_temp_new();
1772 tcg_gen_add_i32(t1
, t0
, dest
);
1773 tcg_gen_addi_i32(t1
, t1
, 1);
1774 tcg_gen_sub_i32(t1
, t1
, QREG_CC_X
);
1776 /* t2 = t0 ^ dest */
1778 t2
= tcg_temp_new();
1779 tcg_gen_xor_i32(t2
, t0
, dest
);
1783 tcg_gen_xor_i32(t0
, t1
, t2
);
1787 * t0 = (t2 >> 2) | (t2 >> 3)
1789 * to fit on 8bit operands, changed in:
1791 * t2 = ~(t0 >> 3) & 0x22
1796 tcg_gen_shri_i32(t2
, t0
, 3);
1797 tcg_gen_not_i32(t2
, t2
);
1798 tcg_gen_andi_i32(t2
, t2
, 0x22);
1799 tcg_gen_add_i32(t0
, t2
, t2
);
1800 tcg_gen_add_i32(t0
, t0
, t2
);
1803 /* return t1 - t0 */
1805 tcg_gen_sub_i32(dest
, t1
, t0
);
1810 static void bcd_flags(TCGv val
)
1812 tcg_gen_andi_i32(QREG_CC_C
, val
, 0x0ff);
1813 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_C
);
1815 tcg_gen_extract_i32(QREG_CC_C
, val
, 8, 1);
1817 tcg_gen_mov_i32(QREG_CC_X
, QREG_CC_C
);
1820 DISAS_INSN(abcd_reg
)
1825 gen_flush_flags(s
); /* !Z is sticky */
1827 src
= gen_extend(s
, DREG(insn
, 0), OS_BYTE
, 0);
1828 dest
= gen_extend(s
, DREG(insn
, 9), OS_BYTE
, 0);
1830 gen_partset_reg(OS_BYTE
, DREG(insn
, 9), dest
);
1835 DISAS_INSN(abcd_mem
)
1837 TCGv src
, dest
, addr
;
1839 gen_flush_flags(s
); /* !Z is sticky */
1841 /* Indirect pre-decrement load (mode 4) */
1843 src
= gen_ea_mode(env
, s
, 4, REG(insn
, 0), OS_BYTE
,
1844 NULL_QREG
, NULL
, EA_LOADU
, IS_USER(s
));
1845 dest
= gen_ea_mode(env
, s
, 4, REG(insn
, 9), OS_BYTE
,
1846 NULL_QREG
, &addr
, EA_LOADU
, IS_USER(s
));
1850 gen_ea_mode(env
, s
, 4, REG(insn
, 9), OS_BYTE
, dest
, &addr
,
1851 EA_STORE
, IS_USER(s
));
1856 DISAS_INSN(sbcd_reg
)
1860 gen_flush_flags(s
); /* !Z is sticky */
1862 src
= gen_extend(s
, DREG(insn
, 0), OS_BYTE
, 0);
1863 dest
= gen_extend(s
, DREG(insn
, 9), OS_BYTE
, 0);
1867 gen_partset_reg(OS_BYTE
, DREG(insn
, 9), dest
);
1872 DISAS_INSN(sbcd_mem
)
1874 TCGv src
, dest
, addr
;
1876 gen_flush_flags(s
); /* !Z is sticky */
1878 /* Indirect pre-decrement load (mode 4) */
1880 src
= gen_ea_mode(env
, s
, 4, REG(insn
, 0), OS_BYTE
,
1881 NULL_QREG
, NULL
, EA_LOADU
, IS_USER(s
));
1882 dest
= gen_ea_mode(env
, s
, 4, REG(insn
, 9), OS_BYTE
,
1883 NULL_QREG
, &addr
, EA_LOADU
, IS_USER(s
));
1887 gen_ea_mode(env
, s
, 4, REG(insn
, 9), OS_BYTE
, dest
, &addr
,
1888 EA_STORE
, IS_USER(s
));
1898 gen_flush_flags(s
); /* !Z is sticky */
1900 SRC_EA(env
, src
, OS_BYTE
, 0, &addr
);
1902 dest
= tcg_const_i32(0);
1905 DEST_EA(env
, insn
, OS_BYTE
, dest
, &addr
);
1909 tcg_temp_free(dest
);
1922 add
= (insn
& 0x4000) != 0;
1923 opsize
= insn_opsize(insn
);
1924 reg
= gen_extend(s
, DREG(insn
, 9), opsize
, 1);
1925 dest
= tcg_temp_new();
1927 SRC_EA(env
, tmp
, opsize
, 1, &addr
);
1931 SRC_EA(env
, src
, opsize
, 1, NULL
);
1934 tcg_gen_add_i32(dest
, tmp
, src
);
1935 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, src
);
1936 set_cc_op(s
, CC_OP_ADDB
+ opsize
);
1938 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, tmp
, src
);
1939 tcg_gen_sub_i32(dest
, tmp
, src
);
1940 set_cc_op(s
, CC_OP_SUBB
+ opsize
);
1942 gen_update_cc_add(dest
, src
, opsize
);
1944 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
1946 gen_partset_reg(opsize
, DREG(insn
, 9), dest
);
1948 tcg_temp_free(dest
);
1951 /* Reverse the order of the bits in REG. */
1955 reg
= DREG(insn
, 0);
1956 gen_helper_bitrev(reg
, reg
);
1959 DISAS_INSN(bitop_reg
)
1969 if ((insn
& 0x38) != 0)
1973 op
= (insn
>> 6) & 3;
1974 SRC_EA(env
, src1
, opsize
, 0, op
? &addr
: NULL
);
1977 src2
= tcg_temp_new();
1978 if (opsize
== OS_BYTE
)
1979 tcg_gen_andi_i32(src2
, DREG(insn
, 9), 7);
1981 tcg_gen_andi_i32(src2
, DREG(insn
, 9), 31);
1983 tmp
= tcg_const_i32(1);
1984 tcg_gen_shl_i32(tmp
, tmp
, src2
);
1985 tcg_temp_free(src2
);
1987 tcg_gen_and_i32(QREG_CC_Z
, src1
, tmp
);
1989 dest
= tcg_temp_new();
1992 tcg_gen_xor_i32(dest
, src1
, tmp
);
1995 tcg_gen_andc_i32(dest
, src1
, tmp
);
1998 tcg_gen_or_i32(dest
, src1
, tmp
);
2005 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2007 tcg_temp_free(dest
);
2013 reg
= DREG(insn
, 0);
2015 gen_helper_sats(reg
, reg
, QREG_CC_V
);
2016 gen_logic_cc(s
, reg
, OS_LONG
);
2019 static void gen_push(DisasContext
*s
, TCGv val
)
2023 tmp
= tcg_temp_new();
2024 tcg_gen_subi_i32(tmp
, QREG_SP
, 4);
2025 gen_store(s
, OS_LONG
, tmp
, val
, IS_USER(s
));
2026 tcg_gen_mov_i32(QREG_SP
, tmp
);
2030 static TCGv
mreg(int reg
)
2034 return cpu_dregs
[reg
];
2037 return cpu_aregs
[reg
& 7];
2042 TCGv addr
, incr
, tmp
, r
[16];
2043 int is_load
= (insn
& 0x0400) != 0;
2044 int opsize
= (insn
& 0x40) != 0 ? OS_LONG
: OS_WORD
;
2045 uint16_t mask
= read_im16(env
, s
);
2046 int mode
= extract32(insn
, 3, 3);
2047 int reg0
= REG(insn
, 0);
2050 tmp
= cpu_aregs
[reg0
];
2053 case 0: /* data register direct */
2054 case 1: /* addr register direct */
2059 case 2: /* indirect */
2062 case 3: /* indirect post-increment */
2064 /* post-increment is not allowed */
2069 case 4: /* indirect pre-decrement */
2071 /* pre-decrement is not allowed */
2075 * We want a bare copy of the address reg, without any pre-decrement
2076 * adjustment, as gen_lea would provide.
2081 tmp
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
2082 if (IS_NULL_QREG(tmp
)) {
2088 addr
= tcg_temp_new();
2089 tcg_gen_mov_i32(addr
, tmp
);
2090 incr
= tcg_const_i32(opsize_bytes(opsize
));
2093 /* memory to register */
2094 for (i
= 0; i
< 16; i
++) {
2095 if (mask
& (1 << i
)) {
2096 r
[i
] = gen_load(s
, opsize
, addr
, 1, IS_USER(s
));
2097 tcg_gen_add_i32(addr
, addr
, incr
);
2100 for (i
= 0; i
< 16; i
++) {
2101 if (mask
& (1 << i
)) {
2102 tcg_gen_mov_i32(mreg(i
), r
[i
]);
2103 tcg_temp_free(r
[i
]);
2107 /* post-increment: movem (An)+,X */
2108 tcg_gen_mov_i32(cpu_aregs
[reg0
], addr
);
2111 /* register to memory */
2113 /* pre-decrement: movem X,-(An) */
2114 for (i
= 15; i
>= 0; i
--) {
2115 if ((mask
<< i
) & 0x8000) {
2116 tcg_gen_sub_i32(addr
, addr
, incr
);
2117 if (reg0
+ 8 == i
&&
2118 m68k_feature(s
->env
, M68K_FEATURE_EXT_FULL
)) {
2120 * M68020+: if the addressing register is the
2121 * register moved to memory, the value written
2122 * is the initial value decremented by the size of
2123 * the operation, regardless of how many actual
2124 * stores have been performed until this point.
2125 * M68000/M68010: the value is the initial value.
2127 tmp
= tcg_temp_new();
2128 tcg_gen_sub_i32(tmp
, cpu_aregs
[reg0
], incr
);
2129 gen_store(s
, opsize
, addr
, tmp
, IS_USER(s
));
2132 gen_store(s
, opsize
, addr
, mreg(i
), IS_USER(s
));
2136 tcg_gen_mov_i32(cpu_aregs
[reg0
], addr
);
2138 for (i
= 0; i
< 16; i
++) {
2139 if (mask
& (1 << i
)) {
2140 gen_store(s
, opsize
, addr
, mreg(i
), IS_USER(s
));
2141 tcg_gen_add_i32(addr
, addr
, incr
);
2147 tcg_temp_free(incr
);
2148 tcg_temp_free(addr
);
2160 displ
= read_im16(env
, s
);
2162 addr
= AREG(insn
, 0);
2163 reg
= DREG(insn
, 9);
2165 abuf
= tcg_temp_new();
2166 tcg_gen_addi_i32(abuf
, addr
, displ
);
2167 dbuf
= tcg_temp_new();
2176 for ( ; i
> 0 ; i
--) {
2177 tcg_gen_shri_i32(dbuf
, reg
, (i
- 1) * 8);
2178 tcg_gen_qemu_st8(dbuf
, abuf
, IS_USER(s
));
2180 tcg_gen_addi_i32(abuf
, abuf
, 2);
2184 for ( ; i
> 0 ; i
--) {
2185 tcg_gen_qemu_ld8u(dbuf
, abuf
, IS_USER(s
));
2186 tcg_gen_deposit_i32(reg
, reg
, dbuf
, (i
- 1) * 8, 8);
2188 tcg_gen_addi_i32(abuf
, abuf
, 2);
2192 tcg_temp_free(abuf
);
2193 tcg_temp_free(dbuf
);
2196 DISAS_INSN(bitop_im
)
2206 if ((insn
& 0x38) != 0)
2210 op
= (insn
>> 6) & 3;
2212 bitnum
= read_im16(env
, s
);
2213 if (m68k_feature(s
->env
, M68K_FEATURE_M68K
)) {
2214 if (bitnum
& 0xfe00) {
2215 disas_undef(env
, s
, insn
);
2219 if (bitnum
& 0xff00) {
2220 disas_undef(env
, s
, insn
);
2225 SRC_EA(env
, src1
, opsize
, 0, op
? &addr
: NULL
);
2228 if (opsize
== OS_BYTE
)
2234 tcg_gen_andi_i32(QREG_CC_Z
, src1
, mask
);
2237 tmp
= tcg_temp_new();
2240 tcg_gen_xori_i32(tmp
, src1
, mask
);
2243 tcg_gen_andi_i32(tmp
, src1
, ~mask
);
2246 tcg_gen_ori_i32(tmp
, src1
, mask
);
2251 DEST_EA(env
, insn
, opsize
, tmp
, &addr
);
2256 static TCGv
gen_get_ccr(DisasContext
*s
)
2261 dest
= tcg_temp_new();
2262 gen_helper_get_ccr(dest
, cpu_env
);
2266 static TCGv
gen_get_sr(DisasContext
*s
)
2271 ccr
= gen_get_ccr(s
);
2272 sr
= tcg_temp_new();
2273 tcg_gen_andi_i32(sr
, QREG_SR
, 0xffe0);
2274 tcg_gen_or_i32(sr
, sr
, ccr
);
2279 static void gen_set_sr_im(DisasContext
*s
, uint16_t val
, int ccr_only
)
2282 tcg_gen_movi_i32(QREG_CC_C
, val
& CCF_C
? 1 : 0);
2283 tcg_gen_movi_i32(QREG_CC_V
, val
& CCF_V
? -1 : 0);
2284 tcg_gen_movi_i32(QREG_CC_Z
, val
& CCF_Z
? 0 : 1);
2285 tcg_gen_movi_i32(QREG_CC_N
, val
& CCF_N
? -1 : 0);
2286 tcg_gen_movi_i32(QREG_CC_X
, val
& CCF_X
? 1 : 0);
2288 /* Must writeback before changing security state. */
2290 gen_helper_set_sr(cpu_env
, tcg_constant_i32(val
));
2292 set_cc_op(s
, CC_OP_FLAGS
);
2295 static void gen_set_sr(DisasContext
*s
, TCGv val
, int ccr_only
)
2298 gen_helper_set_ccr(cpu_env
, val
);
2300 /* Must writeback before changing security state. */
2302 gen_helper_set_sr(cpu_env
, val
);
2304 set_cc_op(s
, CC_OP_FLAGS
);
2307 static void gen_move_to_sr(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
2310 if ((insn
& 0x3f) == 0x3c) {
2312 val
= read_im16(env
, s
);
2313 gen_set_sr_im(s
, val
, ccr_only
);
2316 SRC_EA(env
, src
, OS_WORD
, 0, NULL
);
2317 gen_set_sr(s
, src
, ccr_only
);
2321 DISAS_INSN(arith_im
)
2329 bool with_SR
= ((insn
& 0x3f) == 0x3c);
2331 op
= (insn
>> 9) & 7;
2332 opsize
= insn_opsize(insn
);
2335 im
= tcg_const_i32((int8_t)read_im8(env
, s
));
2338 im
= tcg_const_i32((int16_t)read_im16(env
, s
));
2341 im
= tcg_const_i32(read_im32(env
, s
));
2344 g_assert_not_reached();
2348 /* SR/CCR can only be used with andi/eori/ori */
2349 if (op
== 2 || op
== 3 || op
== 6) {
2350 disas_undef(env
, s
, insn
);
2355 src1
= gen_get_ccr(s
);
2359 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
2362 src1
= gen_get_sr(s
);
2365 /* OS_LONG; others already g_assert_not_reached. */
2366 disas_undef(env
, s
, insn
);
2370 SRC_EA(env
, src1
, opsize
, 1, (op
== 6) ? NULL
: &addr
);
2372 dest
= tcg_temp_new();
2375 tcg_gen_or_i32(dest
, src1
, im
);
2377 gen_set_sr(s
, dest
, opsize
== OS_BYTE
);
2379 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2380 gen_logic_cc(s
, dest
, opsize
);
2384 tcg_gen_and_i32(dest
, src1
, im
);
2386 gen_set_sr(s
, dest
, opsize
== OS_BYTE
);
2388 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2389 gen_logic_cc(s
, dest
, opsize
);
2393 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, src1
, im
);
2394 tcg_gen_sub_i32(dest
, src1
, im
);
2395 gen_update_cc_add(dest
, im
, opsize
);
2396 set_cc_op(s
, CC_OP_SUBB
+ opsize
);
2397 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2400 tcg_gen_add_i32(dest
, src1
, im
);
2401 gen_update_cc_add(dest
, im
, opsize
);
2402 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, im
);
2403 set_cc_op(s
, CC_OP_ADDB
+ opsize
);
2404 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2407 tcg_gen_xor_i32(dest
, src1
, im
);
2409 gen_set_sr(s
, dest
, opsize
== OS_BYTE
);
2411 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2412 gen_logic_cc(s
, dest
, opsize
);
2416 gen_update_cc_cmp(s
, src1
, im
, opsize
);
2422 tcg_temp_free(dest
);
2434 switch ((insn
>> 9) & 3) {
2448 g_assert_not_reached();
2451 ext
= read_im16(env
, s
);
2453 /* cas Dc,Du,<EA> */
2455 addr
= gen_lea(env
, s
, insn
, opsize
);
2456 if (IS_NULL_QREG(addr
)) {
2461 cmp
= gen_extend(s
, DREG(ext
, 0), opsize
, 1);
2464 * if <EA> == Dc then
2466 * Dc = <EA> (because <EA> == Dc)
2471 load
= tcg_temp_new();
2472 tcg_gen_atomic_cmpxchg_i32(load
, addr
, cmp
, DREG(ext
, 6),
2474 /* update flags before setting cmp to load */
2475 gen_update_cc_cmp(s
, load
, cmp
, opsize
);
2476 gen_partset_reg(opsize
, DREG(ext
, 0), load
);
2478 tcg_temp_free(load
);
2480 switch (extract32(insn
, 3, 3)) {
2481 case 3: /* Indirect postincrement. */
2482 tcg_gen_addi_i32(AREG(insn
, 0), addr
, opsize_bytes(opsize
));
2484 case 4: /* Indirect predecrememnt. */
2485 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
2492 uint16_t ext1
, ext2
;
2496 /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */
2498 ext1
= read_im16(env
, s
);
2500 if (ext1
& 0x8000) {
2501 /* Address Register */
2502 addr1
= AREG(ext1
, 12);
2505 addr1
= DREG(ext1
, 12);
2508 ext2
= read_im16(env
, s
);
2509 if (ext2
& 0x8000) {
2510 /* Address Register */
2511 addr2
= AREG(ext2
, 12);
2514 addr2
= DREG(ext2
, 12);
2518 * if (R1) == Dc1 && (R2) == Dc2 then
2526 regs
= tcg_const_i32(REG(ext2
, 6) |
2527 (REG(ext1
, 6) << 3) |
2528 (REG(ext2
, 0) << 6) |
2529 (REG(ext1
, 0) << 9));
2530 if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2531 gen_helper_exit_atomic(cpu_env
);
2533 gen_helper_cas2w(cpu_env
, regs
, addr1
, addr2
);
2535 tcg_temp_free(regs
);
2537 /* Note that cas2w also assigned to env->cc_op. */
2538 s
->cc_op
= CC_OP_CMPW
;
2539 s
->cc_op_synced
= 1;
2544 uint16_t ext1
, ext2
;
2545 TCGv addr1
, addr2
, regs
;
2547 /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */
2549 ext1
= read_im16(env
, s
);
2551 if (ext1
& 0x8000) {
2552 /* Address Register */
2553 addr1
= AREG(ext1
, 12);
2556 addr1
= DREG(ext1
, 12);
2559 ext2
= read_im16(env
, s
);
2560 if (ext2
& 0x8000) {
2561 /* Address Register */
2562 addr2
= AREG(ext2
, 12);
2565 addr2
= DREG(ext2
, 12);
2569 * if (R1) == Dc1 && (R2) == Dc2 then
2577 regs
= tcg_const_i32(REG(ext2
, 6) |
2578 (REG(ext1
, 6) << 3) |
2579 (REG(ext2
, 0) << 6) |
2580 (REG(ext1
, 0) << 9));
2581 if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2582 gen_helper_cas2l_parallel(cpu_env
, regs
, addr1
, addr2
);
2584 gen_helper_cas2l(cpu_env
, regs
, addr1
, addr2
);
2586 tcg_temp_free(regs
);
2588 /* Note that cas2l also assigned to env->cc_op. */
2589 s
->cc_op
= CC_OP_CMPL
;
2590 s
->cc_op_synced
= 1;
2597 reg
= DREG(insn
, 0);
2598 tcg_gen_bswap32_i32(reg
, reg
);
2608 switch (insn
>> 12) {
2609 case 1: /* move.b */
2612 case 2: /* move.l */
2615 case 3: /* move.w */
2621 SRC_EA(env
, src
, opsize
, 1, NULL
);
2622 op
= (insn
>> 6) & 7;
2625 /* The value will already have been sign extended. */
2626 dest
= AREG(insn
, 9);
2627 tcg_gen_mov_i32(dest
, src
);
2631 dest_ea
= ((insn
>> 9) & 7) | (op
<< 3);
2632 DEST_EA(env
, dest_ea
, opsize
, src
, NULL
);
2633 /* This will be correct because loads sign extend. */
2634 gen_logic_cc(s
, src
, opsize
);
2645 opsize
= insn_opsize(insn
);
2646 SRC_EA(env
, src
, opsize
, 1, &addr
);
2648 gen_flush_flags(s
); /* compute old Z */
2651 * Perform subtract with borrow.
2652 * (X, N) = -(src + X);
2655 z
= tcg_const_i32(0);
2656 tcg_gen_add2_i32(QREG_CC_N
, QREG_CC_X
, src
, z
, QREG_CC_X
, z
);
2657 tcg_gen_sub2_i32(QREG_CC_N
, QREG_CC_X
, z
, z
, QREG_CC_N
, QREG_CC_X
);
2659 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
2661 tcg_gen_andi_i32(QREG_CC_X
, QREG_CC_X
, 1);
2664 * Compute signed-overflow for negation. The normal formula for
2665 * subtraction is (res ^ src) & (src ^ dest), but with dest==0
2666 * this simplifies to res & src.
2669 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_N
, src
);
2671 /* Copy the rest of the results into place. */
2672 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_N
); /* !Z is sticky */
2673 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
2675 set_cc_op(s
, CC_OP_FLAGS
);
2677 /* result is in QREG_CC_N */
2679 DEST_EA(env
, insn
, opsize
, QREG_CC_N
, &addr
);
2687 reg
= AREG(insn
, 9);
2688 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
2689 if (IS_NULL_QREG(tmp
)) {
2693 tcg_gen_mov_i32(reg
, tmp
);
2701 zero
= tcg_const_i32(0);
2703 opsize
= insn_opsize(insn
);
2704 DEST_EA(env
, insn
, opsize
, zero
, NULL
);
2705 gen_logic_cc(s
, zero
, opsize
);
2706 tcg_temp_free(zero
);
2709 DISAS_INSN(move_from_ccr
)
2713 ccr
= gen_get_ccr(s
);
2714 DEST_EA(env
, insn
, OS_WORD
, ccr
, NULL
);
2724 opsize
= insn_opsize(insn
);
2725 SRC_EA(env
, src1
, opsize
, 1, &addr
);
2726 dest
= tcg_temp_new();
2727 tcg_gen_neg_i32(dest
, src1
);
2728 set_cc_op(s
, CC_OP_SUBB
+ opsize
);
2729 gen_update_cc_add(dest
, src1
, opsize
);
2730 tcg_gen_setcondi_i32(TCG_COND_NE
, QREG_CC_X
, dest
, 0);
2731 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2732 tcg_temp_free(dest
);
2735 DISAS_INSN(move_to_ccr
)
2737 gen_move_to_sr(env
, s
, insn
, true);
2747 opsize
= insn_opsize(insn
);
2748 SRC_EA(env
, src1
, opsize
, 1, &addr
);
2749 dest
= tcg_temp_new();
2750 tcg_gen_not_i32(dest
, src1
);
2751 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2752 gen_logic_cc(s
, dest
, opsize
);
2761 src1
= tcg_temp_new();
2762 src2
= tcg_temp_new();
2763 reg
= DREG(insn
, 0);
2764 tcg_gen_shli_i32(src1
, reg
, 16);
2765 tcg_gen_shri_i32(src2
, reg
, 16);
2766 tcg_gen_or_i32(reg
, src1
, src2
);
2767 tcg_temp_free(src2
);
2768 tcg_temp_free(src1
);
2769 gen_logic_cc(s
, reg
, OS_LONG
);
2774 gen_exception(s
, s
->base
.pc_next
, EXCP_DEBUG
);
2781 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
2782 if (IS_NULL_QREG(tmp
)) {
2795 reg
= DREG(insn
, 0);
2796 op
= (insn
>> 6) & 7;
2797 tmp
= tcg_temp_new();
2799 tcg_gen_ext16s_i32(tmp
, reg
);
2801 tcg_gen_ext8s_i32(tmp
, reg
);
2803 gen_partset_reg(OS_WORD
, reg
, tmp
);
2805 tcg_gen_mov_i32(reg
, tmp
);
2806 gen_logic_cc(s
, tmp
, OS_LONG
);
2815 opsize
= insn_opsize(insn
);
2816 SRC_EA(env
, tmp
, opsize
, 1, NULL
);
2817 gen_logic_cc(s
, tmp
, opsize
);
2822 /* Implemented as a NOP. */
2827 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
2832 int mode
= extract32(insn
, 3, 3);
2833 int reg0
= REG(insn
, 0);
2836 /* data register direct */
2837 TCGv dest
= cpu_dregs
[reg0
];
2838 gen_logic_cc(s
, dest
, OS_BYTE
);
2839 tcg_gen_ori_tl(dest
, dest
, 0x80);
2843 addr
= gen_lea_mode(env
, s
, mode
, reg0
, OS_BYTE
);
2844 if (IS_NULL_QREG(addr
)) {
2848 src1
= tcg_temp_new();
2849 tcg_gen_atomic_fetch_or_tl(src1
, addr
, tcg_constant_tl(0x80),
2851 gen_logic_cc(s
, src1
, OS_BYTE
);
2852 tcg_temp_free(src1
);
2855 case 3: /* Indirect postincrement. */
2856 tcg_gen_addi_i32(AREG(insn
, 0), addr
, 1);
2858 case 4: /* Indirect predecrememnt. */
2859 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
2871 ext
= read_im16(env
, s
);
2876 if (!m68k_feature(s
->env
, M68K_FEATURE_QUAD_MULDIV
)) {
2877 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
2881 SRC_EA(env
, src1
, OS_LONG
, 0, NULL
);
2884 tcg_gen_muls2_i32(QREG_CC_Z
, QREG_CC_N
, src1
, DREG(ext
, 12));
2886 tcg_gen_mulu2_i32(QREG_CC_Z
, QREG_CC_N
, src1
, DREG(ext
, 12));
2888 /* if Dl == Dh, 68040 returns low word */
2889 tcg_gen_mov_i32(DREG(ext
, 0), QREG_CC_N
);
2890 tcg_gen_mov_i32(DREG(ext
, 12), QREG_CC_Z
);
2891 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_N
);
2893 tcg_gen_movi_i32(QREG_CC_V
, 0);
2894 tcg_gen_movi_i32(QREG_CC_C
, 0);
2896 set_cc_op(s
, CC_OP_FLAGS
);
2899 SRC_EA(env
, src1
, OS_LONG
, 0, NULL
);
2900 if (m68k_feature(s
->env
, M68K_FEATURE_M68K
)) {
2901 tcg_gen_movi_i32(QREG_CC_C
, 0);
2903 tcg_gen_muls2_i32(QREG_CC_N
, QREG_CC_V
, src1
, DREG(ext
, 12));
2904 /* QREG_CC_V is -(QREG_CC_V != (QREG_CC_N >> 31)) */
2905 tcg_gen_sari_i32(QREG_CC_Z
, QREG_CC_N
, 31);
2906 tcg_gen_setcond_i32(TCG_COND_NE
, QREG_CC_V
, QREG_CC_V
, QREG_CC_Z
);
2908 tcg_gen_mulu2_i32(QREG_CC_N
, QREG_CC_V
, src1
, DREG(ext
, 12));
2909 /* QREG_CC_V is -(QREG_CC_V != 0), use QREG_CC_C as 0 */
2910 tcg_gen_setcond_i32(TCG_COND_NE
, QREG_CC_V
, QREG_CC_V
, QREG_CC_C
);
2912 tcg_gen_neg_i32(QREG_CC_V
, QREG_CC_V
);
2913 tcg_gen_mov_i32(DREG(ext
, 12), QREG_CC_N
);
2915 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
2917 set_cc_op(s
, CC_OP_FLAGS
);
2920 * The upper 32 bits of the product are discarded, so
2921 * muls.l and mulu.l are functionally equivalent.
2923 tcg_gen_mul_i32(DREG(ext
, 12), src1
, DREG(ext
, 12));
2924 gen_logic_cc(s
, DREG(ext
, 12), OS_LONG
);
2928 static void gen_link(DisasContext
*s
, uint16_t insn
, int32_t offset
)
2933 reg
= AREG(insn
, 0);
2934 tmp
= tcg_temp_new();
2935 tcg_gen_subi_i32(tmp
, QREG_SP
, 4);
2936 gen_store(s
, OS_LONG
, tmp
, reg
, IS_USER(s
));
2937 if ((insn
& 7) != 7) {
2938 tcg_gen_mov_i32(reg
, tmp
);
2940 tcg_gen_addi_i32(QREG_SP
, tmp
, offset
);
2948 offset
= read_im16(env
, s
);
2949 gen_link(s
, insn
, offset
);
2956 offset
= read_im32(env
, s
);
2957 gen_link(s
, insn
, offset
);
2966 src
= tcg_temp_new();
2967 reg
= AREG(insn
, 0);
2968 tcg_gen_mov_i32(src
, reg
);
2969 tmp
= gen_load(s
, OS_LONG
, src
, 0, IS_USER(s
));
2970 tcg_gen_mov_i32(reg
, tmp
);
2971 tcg_gen_addi_i32(QREG_SP
, src
, 4);
2976 #if defined(CONFIG_SOFTMMU)
2980 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
2984 gen_helper_reset(cpu_env
);
2995 int16_t offset
= read_im16(env
, s
);
2997 tmp
= gen_load(s
, OS_LONG
, QREG_SP
, 0, IS_USER(s
));
2998 tcg_gen_addi_i32(QREG_SP
, QREG_SP
, offset
+ 4);
3008 sp
= tcg_temp_new();
3009 ccr
= gen_load(s
, OS_WORD
, QREG_SP
, 0, IS_USER(s
));
3010 tcg_gen_addi_i32(sp
, QREG_SP
, 2);
3011 tmp
= gen_load(s
, OS_LONG
, sp
, 0, IS_USER(s
));
3012 tcg_gen_addi_i32(QREG_SP
, sp
, 4);
3015 gen_set_sr(s
, ccr
, true);
3025 tmp
= gen_load(s
, OS_LONG
, QREG_SP
, 0, IS_USER(s
));
3026 tcg_gen_addi_i32(QREG_SP
, QREG_SP
, 4);
3035 * Load the target address first to ensure correct exception
3038 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
3039 if (IS_NULL_QREG(tmp
)) {
3043 if ((insn
& 0x40) == 0) {
3045 gen_push(s
, tcg_const_i32(s
->pc
));
3059 if ((insn
& 070) == 010) {
3060 /* Operation on address register is always long. */
3063 opsize
= insn_opsize(insn
);
3065 SRC_EA(env
, src
, opsize
, 1, &addr
);
3066 imm
= (insn
>> 9) & 7;
3070 val
= tcg_const_i32(imm
);
3071 dest
= tcg_temp_new();
3072 tcg_gen_mov_i32(dest
, src
);
3073 if ((insn
& 0x38) == 0x08) {
3075 * Don't update condition codes if the destination is an
3078 if (insn
& 0x0100) {
3079 tcg_gen_sub_i32(dest
, dest
, val
);
3081 tcg_gen_add_i32(dest
, dest
, val
);
3084 if (insn
& 0x0100) {
3085 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, val
);
3086 tcg_gen_sub_i32(dest
, dest
, val
);
3087 set_cc_op(s
, CC_OP_SUBB
+ opsize
);
3089 tcg_gen_add_i32(dest
, dest
, val
);
3090 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, val
);
3091 set_cc_op(s
, CC_OP_ADDB
+ opsize
);
3093 gen_update_cc_add(dest
, val
, opsize
);
3096 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
3097 tcg_temp_free(dest
);
3107 op
= (insn
>> 8) & 0xf;
3108 offset
= (int8_t)insn
;
3110 offset
= (int16_t)read_im16(env
, s
);
3111 } else if (offset
== -1) {
3112 offset
= read_im32(env
, s
);
3116 gen_push(s
, tcg_const_i32(s
->pc
));
3120 TCGLabel
*l1
= gen_new_label();
3121 gen_jmpcc(s
, ((insn
>> 8) & 0xf) ^ 1, l1
);
3122 gen_jmp_tb(s
, 1, base
+ offset
, s
->base
.pc_next
);
3124 gen_jmp_tb(s
, 0, s
->pc
, s
->base
.pc_next
);
3126 /* Unconditional branch. */
3128 gen_jmp_tb(s
, 0, base
+ offset
, s
->base
.pc_next
);
3134 tcg_gen_movi_i32(DREG(insn
, 9), (int8_t)insn
);
3135 gen_logic_cc(s
, DREG(insn
, 9), OS_LONG
);
3148 SRC_EA(env
, src
, opsize
, (insn
& 0x80) == 0, NULL
);
3149 reg
= DREG(insn
, 9);
3150 tcg_gen_mov_i32(reg
, src
);
3151 gen_logic_cc(s
, src
, opsize
);
3162 opsize
= insn_opsize(insn
);
3163 reg
= gen_extend(s
, DREG(insn
, 9), opsize
, 0);
3164 dest
= tcg_temp_new();
3166 SRC_EA(env
, src
, opsize
, 0, &addr
);
3167 tcg_gen_or_i32(dest
, src
, reg
);
3168 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
3170 SRC_EA(env
, src
, opsize
, 0, NULL
);
3171 tcg_gen_or_i32(dest
, src
, reg
);
3172 gen_partset_reg(opsize
, DREG(insn
, 9), dest
);
3174 gen_logic_cc(s
, dest
, opsize
);
3175 tcg_temp_free(dest
);
3183 SRC_EA(env
, src
, (insn
& 0x100) ? OS_LONG
: OS_WORD
, 1, NULL
);
3184 reg
= AREG(insn
, 9);
3185 tcg_gen_sub_i32(reg
, reg
, src
);
3188 static inline void gen_subx(DisasContext
*s
, TCGv src
, TCGv dest
, int opsize
)
3192 gen_flush_flags(s
); /* compute old Z */
3195 * Perform subtract with borrow.
3196 * (X, N) = dest - (src + X);
3199 tmp
= tcg_const_i32(0);
3200 tcg_gen_add2_i32(QREG_CC_N
, QREG_CC_X
, src
, tmp
, QREG_CC_X
, tmp
);
3201 tcg_gen_sub2_i32(QREG_CC_N
, QREG_CC_X
, dest
, tmp
, QREG_CC_N
, QREG_CC_X
);
3202 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
3203 tcg_gen_andi_i32(QREG_CC_X
, QREG_CC_X
, 1);
3205 /* Compute signed-overflow for subtract. */
3207 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_N
, dest
);
3208 tcg_gen_xor_i32(tmp
, dest
, src
);
3209 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_V
, tmp
);
3212 /* Copy the rest of the results into place. */
3213 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_N
); /* !Z is sticky */
3214 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
3216 set_cc_op(s
, CC_OP_FLAGS
);
3218 /* result is in QREG_CC_N */
3221 DISAS_INSN(subx_reg
)
3227 opsize
= insn_opsize(insn
);
3229 src
= gen_extend(s
, DREG(insn
, 0), opsize
, 1);
3230 dest
= gen_extend(s
, DREG(insn
, 9), opsize
, 1);
3232 gen_subx(s
, src
, dest
, opsize
);
3234 gen_partset_reg(opsize
, DREG(insn
, 9), QREG_CC_N
);
3237 DISAS_INSN(subx_mem
)
3245 opsize
= insn_opsize(insn
);
3247 addr_src
= AREG(insn
, 0);
3248 tcg_gen_subi_i32(addr_src
, addr_src
, opsize_bytes(opsize
));
3249 src
= gen_load(s
, opsize
, addr_src
, 1, IS_USER(s
));
3251 addr_dest
= AREG(insn
, 9);
3252 tcg_gen_subi_i32(addr_dest
, addr_dest
, opsize_bytes(opsize
));
3253 dest
= gen_load(s
, opsize
, addr_dest
, 1, IS_USER(s
));
3255 gen_subx(s
, src
, dest
, opsize
);
3257 gen_store(s
, opsize
, addr_dest
, QREG_CC_N
, IS_USER(s
));
3259 tcg_temp_free(dest
);
3268 val
= (insn
>> 9) & 7;
3271 src
= tcg_const_i32(val
);
3272 gen_logic_cc(s
, src
, OS_LONG
);
3273 DEST_EA(env
, insn
, OS_LONG
, src
, NULL
);
3283 opsize
= insn_opsize(insn
);
3284 SRC_EA(env
, src
, opsize
, 1, NULL
);
3285 reg
= gen_extend(s
, DREG(insn
, 9), opsize
, 1);
3286 gen_update_cc_cmp(s
, reg
, src
, opsize
);
3300 SRC_EA(env
, src
, opsize
, 1, NULL
);
3301 reg
= AREG(insn
, 9);
3302 gen_update_cc_cmp(s
, reg
, src
, OS_LONG
);
3307 int opsize
= insn_opsize(insn
);
3310 /* Post-increment load (mode 3) from Ay. */
3311 src
= gen_ea_mode(env
, s
, 3, REG(insn
, 0), opsize
,
3312 NULL_QREG
, NULL
, EA_LOADS
, IS_USER(s
));
3313 /* Post-increment load (mode 3) from Ax. */
3314 dst
= gen_ea_mode(env
, s
, 3, REG(insn
, 9), opsize
,
3315 NULL_QREG
, NULL
, EA_LOADS
, IS_USER(s
));
3317 gen_update_cc_cmp(s
, dst
, src
, opsize
);
3327 opsize
= insn_opsize(insn
);
3329 SRC_EA(env
, src
, opsize
, 0, &addr
);
3330 dest
= tcg_temp_new();
3331 tcg_gen_xor_i32(dest
, src
, DREG(insn
, 9));
3332 gen_logic_cc(s
, dest
, opsize
);
3333 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
3334 tcg_temp_free(dest
);
3337 static void do_exg(TCGv reg1
, TCGv reg2
)
3339 TCGv temp
= tcg_temp_new();
3340 tcg_gen_mov_i32(temp
, reg1
);
3341 tcg_gen_mov_i32(reg1
, reg2
);
3342 tcg_gen_mov_i32(reg2
, temp
);
3343 tcg_temp_free(temp
);
3348 /* exchange Dx and Dy */
3349 do_exg(DREG(insn
, 9), DREG(insn
, 0));
3354 /* exchange Ax and Ay */
3355 do_exg(AREG(insn
, 9), AREG(insn
, 0));
3360 /* exchange Dx and Ay */
3361 do_exg(DREG(insn
, 9), AREG(insn
, 0));
3372 dest
= tcg_temp_new();
3374 opsize
= insn_opsize(insn
);
3375 reg
= DREG(insn
, 9);
3377 SRC_EA(env
, src
, opsize
, 0, &addr
);
3378 tcg_gen_and_i32(dest
, src
, reg
);
3379 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
3381 SRC_EA(env
, src
, opsize
, 0, NULL
);
3382 tcg_gen_and_i32(dest
, src
, reg
);
3383 gen_partset_reg(opsize
, reg
, dest
);
3385 gen_logic_cc(s
, dest
, opsize
);
3386 tcg_temp_free(dest
);
3394 SRC_EA(env
, src
, (insn
& 0x100) ? OS_LONG
: OS_WORD
, 1, NULL
);
3395 reg
= AREG(insn
, 9);
3396 tcg_gen_add_i32(reg
, reg
, src
);
3399 static inline void gen_addx(DisasContext
*s
, TCGv src
, TCGv dest
, int opsize
)
3403 gen_flush_flags(s
); /* compute old Z */
3406 * Perform addition with carry.
3407 * (X, N) = src + dest + X;
3410 tmp
= tcg_const_i32(0);
3411 tcg_gen_add2_i32(QREG_CC_N
, QREG_CC_X
, QREG_CC_X
, tmp
, dest
, tmp
);
3412 tcg_gen_add2_i32(QREG_CC_N
, QREG_CC_X
, QREG_CC_N
, QREG_CC_X
, src
, tmp
);
3413 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
3415 /* Compute signed-overflow for addition. */
3417 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_N
, src
);
3418 tcg_gen_xor_i32(tmp
, dest
, src
);
3419 tcg_gen_andc_i32(QREG_CC_V
, QREG_CC_V
, tmp
);
3422 /* Copy the rest of the results into place. */
3423 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_N
); /* !Z is sticky */
3424 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
3426 set_cc_op(s
, CC_OP_FLAGS
);
3428 /* result is in QREG_CC_N */
3431 DISAS_INSN(addx_reg
)
3437 opsize
= insn_opsize(insn
);
3439 dest
= gen_extend(s
, DREG(insn
, 9), opsize
, 1);
3440 src
= gen_extend(s
, DREG(insn
, 0), opsize
, 1);
3442 gen_addx(s
, src
, dest
, opsize
);
3444 gen_partset_reg(opsize
, DREG(insn
, 9), QREG_CC_N
);
3447 DISAS_INSN(addx_mem
)
3455 opsize
= insn_opsize(insn
);
3457 addr_src
= AREG(insn
, 0);
3458 tcg_gen_subi_i32(addr_src
, addr_src
, opsize_bytes(opsize
));
3459 src
= gen_load(s
, opsize
, addr_src
, 1, IS_USER(s
));
3461 addr_dest
= AREG(insn
, 9);
3462 tcg_gen_subi_i32(addr_dest
, addr_dest
, opsize_bytes(opsize
));
3463 dest
= gen_load(s
, opsize
, addr_dest
, 1, IS_USER(s
));
3465 gen_addx(s
, src
, dest
, opsize
);
3467 gen_store(s
, opsize
, addr_dest
, QREG_CC_N
, IS_USER(s
));
3469 tcg_temp_free(dest
);
3473 static inline void shift_im(DisasContext
*s
, uint16_t insn
, int opsize
)
3475 int count
= (insn
>> 9) & 7;
3476 int logical
= insn
& 8;
3477 int left
= insn
& 0x100;
3478 int bits
= opsize_bytes(opsize
) * 8;
3479 TCGv reg
= gen_extend(s
, DREG(insn
, 0), opsize
, !logical
);
3485 tcg_gen_movi_i32(QREG_CC_V
, 0);
3487 tcg_gen_shri_i32(QREG_CC_C
, reg
, bits
- count
);
3488 tcg_gen_shli_i32(QREG_CC_N
, reg
, count
);
3491 * Note that ColdFire always clears V (done above),
3492 * while M68000 sets if the most significant bit is changed at
3493 * any time during the shift operation.
3495 if (!logical
&& m68k_feature(s
->env
, M68K_FEATURE_M68K
)) {
3496 /* if shift count >= bits, V is (reg != 0) */
3497 if (count
>= bits
) {
3498 tcg_gen_setcond_i32(TCG_COND_NE
, QREG_CC_V
, reg
, QREG_CC_V
);
3500 TCGv t0
= tcg_temp_new();
3501 tcg_gen_sari_i32(QREG_CC_V
, reg
, bits
- 1);
3502 tcg_gen_sari_i32(t0
, reg
, bits
- count
- 1);
3503 tcg_gen_setcond_i32(TCG_COND_NE
, QREG_CC_V
, QREG_CC_V
, t0
);
3506 tcg_gen_neg_i32(QREG_CC_V
, QREG_CC_V
);
3509 tcg_gen_shri_i32(QREG_CC_C
, reg
, count
- 1);
3511 tcg_gen_shri_i32(QREG_CC_N
, reg
, count
);
3513 tcg_gen_sari_i32(QREG_CC_N
, reg
, count
);
3517 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
3518 tcg_gen_andi_i32(QREG_CC_C
, QREG_CC_C
, 1);
3519 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
3520 tcg_gen_mov_i32(QREG_CC_X
, QREG_CC_C
);
3522 gen_partset_reg(opsize
, DREG(insn
, 0), QREG_CC_N
);
3523 set_cc_op(s
, CC_OP_FLAGS
);
3526 static inline void shift_reg(DisasContext
*s
, uint16_t insn
, int opsize
)
3528 int logical
= insn
& 8;
3529 int left
= insn
& 0x100;
3530 int bits
= opsize_bytes(opsize
) * 8;
3531 TCGv reg
= gen_extend(s
, DREG(insn
, 0), opsize
, !logical
);
3535 t64
= tcg_temp_new_i64();
3536 s64
= tcg_temp_new_i64();
3537 s32
= tcg_temp_new();
3540 * Note that m68k truncates the shift count modulo 64, not 32.
3541 * In addition, a 64-bit shift makes it easy to find "the last
3542 * bit shifted out", for the carry flag.
3544 tcg_gen_andi_i32(s32
, DREG(insn
, 9), 63);
3545 tcg_gen_extu_i32_i64(s64
, s32
);
3546 tcg_gen_extu_i32_i64(t64
, reg
);
3548 /* Optimistically set V=0. Also used as a zero source below. */
3549 tcg_gen_movi_i32(QREG_CC_V
, 0);
3551 tcg_gen_shl_i64(t64
, t64
, s64
);
3553 if (opsize
== OS_LONG
) {
3554 tcg_gen_extr_i64_i32(QREG_CC_N
, QREG_CC_C
, t64
);
3555 /* Note that C=0 if shift count is 0, and we get that for free. */
3557 TCGv zero
= tcg_const_i32(0);
3558 tcg_gen_extrl_i64_i32(QREG_CC_N
, t64
);
3559 tcg_gen_shri_i32(QREG_CC_C
, QREG_CC_N
, bits
);
3560 tcg_gen_movcond_i32(TCG_COND_EQ
, QREG_CC_C
,
3561 s32
, zero
, zero
, QREG_CC_C
);
3562 tcg_temp_free(zero
);
3564 tcg_gen_andi_i32(QREG_CC_C
, QREG_CC_C
, 1);
3566 /* X = C, but only if the shift count was non-zero. */
3567 tcg_gen_movcond_i32(TCG_COND_NE
, QREG_CC_X
, s32
, QREG_CC_V
,
3568 QREG_CC_C
, QREG_CC_X
);
3571 * M68000 sets V if the most significant bit is changed at
3572 * any time during the shift operation. Do this via creating
3573 * an extension of the sign bit, comparing, and discarding
3574 * the bits below the sign bit. I.e.
3575 * int64_t s = (intN_t)reg;
3576 * int64_t t = (int64_t)(intN_t)reg << count;
3577 * V = ((s ^ t) & (-1 << (bits - 1))) != 0
3579 if (!logical
&& m68k_feature(s
->env
, M68K_FEATURE_M68K
)) {
3580 TCGv_i64 tt
= tcg_const_i64(32);
3581 /* if shift is greater than 32, use 32 */
3582 tcg_gen_movcond_i64(TCG_COND_GT
, s64
, s64
, tt
, tt
, s64
);
3583 tcg_temp_free_i64(tt
);
3584 /* Sign extend the input to 64 bits; re-do the shift. */
3585 tcg_gen_ext_i32_i64(t64
, reg
);
3586 tcg_gen_shl_i64(s64
, t64
, s64
);
3587 /* Clear all bits that are unchanged. */
3588 tcg_gen_xor_i64(t64
, t64
, s64
);
3589 /* Ignore the bits below the sign bit. */
3590 tcg_gen_andi_i64(t64
, t64
, -1ULL << (bits
- 1));
3591 /* If any bits remain set, we have overflow. */
3592 tcg_gen_setcondi_i64(TCG_COND_NE
, t64
, t64
, 0);
3593 tcg_gen_extrl_i64_i32(QREG_CC_V
, t64
);
3594 tcg_gen_neg_i32(QREG_CC_V
, QREG_CC_V
);
3597 tcg_gen_shli_i64(t64
, t64
, 32);
3599 tcg_gen_shr_i64(t64
, t64
, s64
);
3601 tcg_gen_sar_i64(t64
, t64
, s64
);
3603 tcg_gen_extr_i64_i32(QREG_CC_C
, QREG_CC_N
, t64
);
3605 /* Note that C=0 if shift count is 0, and we get that for free. */
3606 tcg_gen_shri_i32(QREG_CC_C
, QREG_CC_C
, 31);
3608 /* X = C, but only if the shift count was non-zero. */
3609 tcg_gen_movcond_i32(TCG_COND_NE
, QREG_CC_X
, s32
, QREG_CC_V
,
3610 QREG_CC_C
, QREG_CC_X
);
3612 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
3613 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
3616 tcg_temp_free_i64(s64
);
3617 tcg_temp_free_i64(t64
);
3619 /* Write back the result. */
3620 gen_partset_reg(opsize
, DREG(insn
, 0), QREG_CC_N
);
3621 set_cc_op(s
, CC_OP_FLAGS
);
3624 DISAS_INSN(shift8_im
)
3626 shift_im(s
, insn
, OS_BYTE
);
3629 DISAS_INSN(shift16_im
)
3631 shift_im(s
, insn
, OS_WORD
);
3634 DISAS_INSN(shift_im
)
3636 shift_im(s
, insn
, OS_LONG
);
3639 DISAS_INSN(shift8_reg
)
3641 shift_reg(s
, insn
, OS_BYTE
);
3644 DISAS_INSN(shift16_reg
)
3646 shift_reg(s
, insn
, OS_WORD
);
3649 DISAS_INSN(shift_reg
)
3651 shift_reg(s
, insn
, OS_LONG
);
3654 DISAS_INSN(shift_mem
)
3656 int logical
= insn
& 8;
3657 int left
= insn
& 0x100;
3661 SRC_EA(env
, src
, OS_WORD
, !logical
, &addr
);
3662 tcg_gen_movi_i32(QREG_CC_V
, 0);
3664 tcg_gen_shri_i32(QREG_CC_C
, src
, 15);
3665 tcg_gen_shli_i32(QREG_CC_N
, src
, 1);
3668 * Note that ColdFire always clears V,
3669 * while M68000 sets if the most significant bit is changed at
3670 * any time during the shift operation
3672 if (!logical
&& m68k_feature(s
->env
, M68K_FEATURE_M68K
)) {
3673 src
= gen_extend(s
, src
, OS_WORD
, 1);
3674 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_N
, src
);
3677 tcg_gen_mov_i32(QREG_CC_C
, src
);
3679 tcg_gen_shri_i32(QREG_CC_N
, src
, 1);
3681 tcg_gen_sari_i32(QREG_CC_N
, src
, 1);
3685 gen_ext(QREG_CC_N
, QREG_CC_N
, OS_WORD
, 1);
3686 tcg_gen_andi_i32(QREG_CC_C
, QREG_CC_C
, 1);
3687 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
3688 tcg_gen_mov_i32(QREG_CC_X
, QREG_CC_C
);
3690 DEST_EA(env
, insn
, OS_WORD
, QREG_CC_N
, &addr
);
3691 set_cc_op(s
, CC_OP_FLAGS
);
3694 static void rotate(TCGv reg
, TCGv shift
, int left
, int size
)
3698 /* Replicate the 8-bit input so that a 32-bit rotate works. */
3699 tcg_gen_ext8u_i32(reg
, reg
);
3700 tcg_gen_muli_i32(reg
, reg
, 0x01010101);
3703 /* Replicate the 16-bit input so that a 32-bit rotate works. */
3704 tcg_gen_deposit_i32(reg
, reg
, reg
, 16, 16);
3709 tcg_gen_rotl_i32(reg
, reg
, shift
);
3711 tcg_gen_rotr_i32(reg
, reg
, shift
);
3719 tcg_gen_ext8s_i32(reg
, reg
);
3722 tcg_gen_ext16s_i32(reg
, reg
);
3728 /* QREG_CC_X is not affected */
3730 tcg_gen_mov_i32(QREG_CC_N
, reg
);
3731 tcg_gen_mov_i32(QREG_CC_Z
, reg
);
3734 tcg_gen_andi_i32(QREG_CC_C
, reg
, 1);
3736 tcg_gen_shri_i32(QREG_CC_C
, reg
, 31);
3739 tcg_gen_movi_i32(QREG_CC_V
, 0); /* always cleared */
3742 static void rotate_x_flags(TCGv reg
, TCGv X
, int size
)
3746 tcg_gen_ext8s_i32(reg
, reg
);
3749 tcg_gen_ext16s_i32(reg
, reg
);
3754 tcg_gen_mov_i32(QREG_CC_N
, reg
);
3755 tcg_gen_mov_i32(QREG_CC_Z
, reg
);
3756 tcg_gen_mov_i32(QREG_CC_X
, X
);
3757 tcg_gen_mov_i32(QREG_CC_C
, X
);
3758 tcg_gen_movi_i32(QREG_CC_V
, 0);
3761 /* Result of rotate_x() is valid if 0 <= shift <= size */
3762 static TCGv
rotate_x(TCGv reg
, TCGv shift
, int left
, int size
)
3764 TCGv X
, shl
, shr
, shx
, sz
, zero
;
3766 sz
= tcg_const_i32(size
);
3768 shr
= tcg_temp_new();
3769 shl
= tcg_temp_new();
3770 shx
= tcg_temp_new();
3772 tcg_gen_mov_i32(shl
, shift
); /* shl = shift */
3773 tcg_gen_movi_i32(shr
, size
+ 1);
3774 tcg_gen_sub_i32(shr
, shr
, shift
); /* shr = size + 1 - shift */
3775 tcg_gen_subi_i32(shx
, shift
, 1); /* shx = shift - 1 */
3776 /* shx = shx < 0 ? size : shx; */
3777 zero
= tcg_const_i32(0);
3778 tcg_gen_movcond_i32(TCG_COND_LT
, shx
, shx
, zero
, sz
, shx
);
3779 tcg_temp_free(zero
);
3781 tcg_gen_mov_i32(shr
, shift
); /* shr = shift */
3782 tcg_gen_movi_i32(shl
, size
+ 1);
3783 tcg_gen_sub_i32(shl
, shl
, shift
); /* shl = size + 1 - shift */
3784 tcg_gen_sub_i32(shx
, sz
, shift
); /* shx = size - shift */
3786 tcg_temp_free_i32(sz
);
3788 /* reg = (reg << shl) | (reg >> shr) | (x << shx); */
3790 tcg_gen_shl_i32(shl
, reg
, shl
);
3791 tcg_gen_shr_i32(shr
, reg
, shr
);
3792 tcg_gen_or_i32(reg
, shl
, shr
);
3795 tcg_gen_shl_i32(shx
, QREG_CC_X
, shx
);
3796 tcg_gen_or_i32(reg
, reg
, shx
);
3799 /* X = (reg >> size) & 1 */
3802 tcg_gen_extract_i32(X
, reg
, size
, 1);
3807 /* Result of rotate32_x() is valid if 0 <= shift < 33 */
3808 static TCGv
rotate32_x(TCGv reg
, TCGv shift
, int left
)
3810 TCGv_i64 t0
, shift64
;
3811 TCGv X
, lo
, hi
, zero
;
3813 shift64
= tcg_temp_new_i64();
3814 tcg_gen_extu_i32_i64(shift64
, shift
);
3816 t0
= tcg_temp_new_i64();
3819 lo
= tcg_temp_new();
3820 hi
= tcg_temp_new();
3823 /* create [reg:X:..] */
3825 tcg_gen_shli_i32(lo
, QREG_CC_X
, 31);
3826 tcg_gen_concat_i32_i64(t0
, lo
, reg
);
3830 tcg_gen_rotl_i64(t0
, t0
, shift64
);
3831 tcg_temp_free_i64(shift64
);
3833 /* result is [reg:..:reg:X] */
3835 tcg_gen_extr_i64_i32(lo
, hi
, t0
);
3836 tcg_gen_andi_i32(X
, lo
, 1);
3838 tcg_gen_shri_i32(lo
, lo
, 1);
3840 /* create [..:X:reg] */
3842 tcg_gen_concat_i32_i64(t0
, reg
, QREG_CC_X
);
3844 tcg_gen_rotr_i64(t0
, t0
, shift64
);
3845 tcg_temp_free_i64(shift64
);
3847 /* result is value: [X:reg:..:reg] */
3849 tcg_gen_extr_i64_i32(lo
, hi
, t0
);
3853 tcg_gen_shri_i32(X
, hi
, 31);
3855 /* extract result */
3857 tcg_gen_shli_i32(hi
, hi
, 1);
3859 tcg_temp_free_i64(t0
);
3860 tcg_gen_or_i32(lo
, lo
, hi
);
3863 /* if shift == 0, register and X are not affected */
3865 zero
= tcg_const_i32(0);
3866 tcg_gen_movcond_i32(TCG_COND_EQ
, X
, shift
, zero
, QREG_CC_X
, X
);
3867 tcg_gen_movcond_i32(TCG_COND_EQ
, reg
, shift
, zero
, reg
, lo
);
3868 tcg_temp_free(zero
);
3874 DISAS_INSN(rotate_im
)
3878 int left
= (insn
& 0x100);
3880 tmp
= (insn
>> 9) & 7;
3885 shift
= tcg_const_i32(tmp
);
3887 rotate(DREG(insn
, 0), shift
, left
, 32);
3889 TCGv X
= rotate32_x(DREG(insn
, 0), shift
, left
);
3890 rotate_x_flags(DREG(insn
, 0), X
, 32);
3893 tcg_temp_free(shift
);
3895 set_cc_op(s
, CC_OP_FLAGS
);
3898 DISAS_INSN(rotate8_im
)
3900 int left
= (insn
& 0x100);
3905 reg
= gen_extend(s
, DREG(insn
, 0), OS_BYTE
, 0);
3907 tmp
= (insn
>> 9) & 7;
3912 shift
= tcg_const_i32(tmp
);
3914 rotate(reg
, shift
, left
, 8);
3916 TCGv X
= rotate_x(reg
, shift
, left
, 8);
3917 rotate_x_flags(reg
, X
, 8);
3920 tcg_temp_free(shift
);
3921 gen_partset_reg(OS_BYTE
, DREG(insn
, 0), reg
);
3922 set_cc_op(s
, CC_OP_FLAGS
);
3925 DISAS_INSN(rotate16_im
)
3927 int left
= (insn
& 0x100);
3932 reg
= gen_extend(s
, DREG(insn
, 0), OS_WORD
, 0);
3933 tmp
= (insn
>> 9) & 7;
3938 shift
= tcg_const_i32(tmp
);
3940 rotate(reg
, shift
, left
, 16);
3942 TCGv X
= rotate_x(reg
, shift
, left
, 16);
3943 rotate_x_flags(reg
, X
, 16);
3946 tcg_temp_free(shift
);
3947 gen_partset_reg(OS_WORD
, DREG(insn
, 0), reg
);
3948 set_cc_op(s
, CC_OP_FLAGS
);
3951 DISAS_INSN(rotate_reg
)
3956 int left
= (insn
& 0x100);
3958 reg
= DREG(insn
, 0);
3959 src
= DREG(insn
, 9);
3960 /* shift in [0..63] */
3961 t0
= tcg_temp_new();
3962 tcg_gen_andi_i32(t0
, src
, 63);
3963 t1
= tcg_temp_new_i32();
3965 tcg_gen_andi_i32(t1
, src
, 31);
3966 rotate(reg
, t1
, left
, 32);
3967 /* if shift == 0, clear C */
3968 tcg_gen_movcond_i32(TCG_COND_EQ
, QREG_CC_C
,
3969 t0
, QREG_CC_V
/* 0 */,
3970 QREG_CC_V
/* 0 */, QREG_CC_C
);
3974 tcg_gen_movi_i32(t1
, 33);
3975 tcg_gen_remu_i32(t1
, t0
, t1
);
3976 X
= rotate32_x(DREG(insn
, 0), t1
, left
);
3977 rotate_x_flags(DREG(insn
, 0), X
, 32);
3982 set_cc_op(s
, CC_OP_FLAGS
);
3985 DISAS_INSN(rotate8_reg
)
3990 int left
= (insn
& 0x100);
3992 reg
= gen_extend(s
, DREG(insn
, 0), OS_BYTE
, 0);
3993 src
= DREG(insn
, 9);
3994 /* shift in [0..63] */
3995 t0
= tcg_temp_new_i32();
3996 tcg_gen_andi_i32(t0
, src
, 63);
3997 t1
= tcg_temp_new_i32();
3999 tcg_gen_andi_i32(t1
, src
, 7);
4000 rotate(reg
, t1
, left
, 8);
4001 /* if shift == 0, clear C */
4002 tcg_gen_movcond_i32(TCG_COND_EQ
, QREG_CC_C
,
4003 t0
, QREG_CC_V
/* 0 */,
4004 QREG_CC_V
/* 0 */, QREG_CC_C
);
4008 tcg_gen_movi_i32(t1
, 9);
4009 tcg_gen_remu_i32(t1
, t0
, t1
);
4010 X
= rotate_x(reg
, t1
, left
, 8);
4011 rotate_x_flags(reg
, X
, 8);
4016 gen_partset_reg(OS_BYTE
, DREG(insn
, 0), reg
);
4017 set_cc_op(s
, CC_OP_FLAGS
);
4020 DISAS_INSN(rotate16_reg
)
4025 int left
= (insn
& 0x100);
4027 reg
= gen_extend(s
, DREG(insn
, 0), OS_WORD
, 0);
4028 src
= DREG(insn
, 9);
4029 /* shift in [0..63] */
4030 t0
= tcg_temp_new_i32();
4031 tcg_gen_andi_i32(t0
, src
, 63);
4032 t1
= tcg_temp_new_i32();
4034 tcg_gen_andi_i32(t1
, src
, 15);
4035 rotate(reg
, t1
, left
, 16);
4036 /* if shift == 0, clear C */
4037 tcg_gen_movcond_i32(TCG_COND_EQ
, QREG_CC_C
,
4038 t0
, QREG_CC_V
/* 0 */,
4039 QREG_CC_V
/* 0 */, QREG_CC_C
);
4043 tcg_gen_movi_i32(t1
, 17);
4044 tcg_gen_remu_i32(t1
, t0
, t1
);
4045 X
= rotate_x(reg
, t1
, left
, 16);
4046 rotate_x_flags(reg
, X
, 16);
4051 gen_partset_reg(OS_WORD
, DREG(insn
, 0), reg
);
4052 set_cc_op(s
, CC_OP_FLAGS
);
4055 DISAS_INSN(rotate_mem
)
4060 int left
= (insn
& 0x100);
4062 SRC_EA(env
, src
, OS_WORD
, 0, &addr
);
4064 shift
= tcg_const_i32(1);
4065 if (insn
& 0x0200) {
4066 rotate(src
, shift
, left
, 16);
4068 TCGv X
= rotate_x(src
, shift
, left
, 16);
4069 rotate_x_flags(src
, X
, 16);
4072 tcg_temp_free(shift
);
4073 DEST_EA(env
, insn
, OS_WORD
, src
, &addr
);
4074 set_cc_op(s
, CC_OP_FLAGS
);
4077 DISAS_INSN(bfext_reg
)
4079 int ext
= read_im16(env
, s
);
4080 int is_sign
= insn
& 0x200;
4081 TCGv src
= DREG(insn
, 0);
4082 TCGv dst
= DREG(ext
, 12);
4083 int len
= ((extract32(ext
, 0, 5) - 1) & 31) + 1;
4084 int ofs
= extract32(ext
, 6, 5); /* big bit-endian */
4085 int pos
= 32 - ofs
- len
; /* little bit-endian */
4086 TCGv tmp
= tcg_temp_new();
4090 * In general, we're going to rotate the field so that it's at the
4091 * top of the word and then right-shift by the complement of the
4092 * width to extend the field.
4095 /* Variable width. */
4097 /* Variable offset. */
4098 tcg_gen_andi_i32(tmp
, DREG(ext
, 6), 31);
4099 tcg_gen_rotl_i32(tmp
, src
, tmp
);
4101 tcg_gen_rotli_i32(tmp
, src
, ofs
);
4104 shift
= tcg_temp_new();
4105 tcg_gen_neg_i32(shift
, DREG(ext
, 0));
4106 tcg_gen_andi_i32(shift
, shift
, 31);
4107 tcg_gen_sar_i32(QREG_CC_N
, tmp
, shift
);
4109 tcg_gen_mov_i32(dst
, QREG_CC_N
);
4111 tcg_gen_shr_i32(dst
, tmp
, shift
);
4113 tcg_temp_free(shift
);
4115 /* Immediate width. */
4117 /* Variable offset */
4118 tcg_gen_andi_i32(tmp
, DREG(ext
, 6), 31);
4119 tcg_gen_rotl_i32(tmp
, src
, tmp
);
4124 * Immediate offset. If the field doesn't wrap around the
4125 * end of the word, rely on (s)extract completely.
4128 tcg_gen_rotli_i32(tmp
, src
, ofs
);
4134 tcg_gen_sextract_i32(QREG_CC_N
, src
, pos
, len
);
4136 tcg_gen_mov_i32(dst
, QREG_CC_N
);
4138 tcg_gen_extract_i32(dst
, src
, pos
, len
);
4143 set_cc_op(s
, CC_OP_LOGIC
);
4146 DISAS_INSN(bfext_mem
)
4148 int ext
= read_im16(env
, s
);
4149 int is_sign
= insn
& 0x200;
4150 TCGv dest
= DREG(ext
, 12);
4151 TCGv addr
, len
, ofs
;
4153 addr
= gen_lea(env
, s
, insn
, OS_UNSIZED
);
4154 if (IS_NULL_QREG(addr
)) {
4162 len
= tcg_const_i32(extract32(ext
, 0, 5));
4167 ofs
= tcg_const_i32(extract32(ext
, 6, 5));
4171 gen_helper_bfexts_mem(dest
, cpu_env
, addr
, ofs
, len
);
4172 tcg_gen_mov_i32(QREG_CC_N
, dest
);
4174 TCGv_i64 tmp
= tcg_temp_new_i64();
4175 gen_helper_bfextu_mem(tmp
, cpu_env
, addr
, ofs
, len
);
4176 tcg_gen_extr_i64_i32(dest
, QREG_CC_N
, tmp
);
4177 tcg_temp_free_i64(tmp
);
4179 set_cc_op(s
, CC_OP_LOGIC
);
4181 if (!(ext
& 0x20)) {
4184 if (!(ext
& 0x800)) {
4189 DISAS_INSN(bfop_reg
)
4191 int ext
= read_im16(env
, s
);
4192 TCGv src
= DREG(insn
, 0);
4193 int len
= ((extract32(ext
, 0, 5) - 1) & 31) + 1;
4194 int ofs
= extract32(ext
, 6, 5); /* big bit-endian */
4195 TCGv mask
, tofs
, tlen
;
4199 if ((insn
& 0x0f00) == 0x0d00) { /* bfffo */
4200 tofs
= tcg_temp_new();
4201 tlen
= tcg_temp_new();
4204 if ((ext
& 0x820) == 0) {
4205 /* Immediate width and offset. */
4206 uint32_t maski
= 0x7fffffffu
>> (len
- 1);
4207 if (ofs
+ len
<= 32) {
4208 tcg_gen_shli_i32(QREG_CC_N
, src
, ofs
);
4210 tcg_gen_rotli_i32(QREG_CC_N
, src
, ofs
);
4212 tcg_gen_andi_i32(QREG_CC_N
, QREG_CC_N
, ~maski
);
4213 mask
= tcg_const_i32(ror32(maski
, ofs
));
4215 tcg_gen_movi_i32(tofs
, ofs
);
4216 tcg_gen_movi_i32(tlen
, len
);
4219 TCGv tmp
= tcg_temp_new();
4221 /* Variable width */
4222 tcg_gen_subi_i32(tmp
, DREG(ext
, 0), 1);
4223 tcg_gen_andi_i32(tmp
, tmp
, 31);
4224 mask
= tcg_const_i32(0x7fffffffu
);
4225 tcg_gen_shr_i32(mask
, mask
, tmp
);
4227 tcg_gen_addi_i32(tlen
, tmp
, 1);
4230 /* Immediate width */
4231 mask
= tcg_const_i32(0x7fffffffu
>> (len
- 1));
4233 tcg_gen_movi_i32(tlen
, len
);
4237 /* Variable offset */
4238 tcg_gen_andi_i32(tmp
, DREG(ext
, 6), 31);
4239 tcg_gen_rotl_i32(QREG_CC_N
, src
, tmp
);
4240 tcg_gen_andc_i32(QREG_CC_N
, QREG_CC_N
, mask
);
4241 tcg_gen_rotr_i32(mask
, mask
, tmp
);
4243 tcg_gen_mov_i32(tofs
, tmp
);
4246 /* Immediate offset (and variable width) */
4247 tcg_gen_rotli_i32(QREG_CC_N
, src
, ofs
);
4248 tcg_gen_andc_i32(QREG_CC_N
, QREG_CC_N
, mask
);
4249 tcg_gen_rotri_i32(mask
, mask
, ofs
);
4251 tcg_gen_movi_i32(tofs
, ofs
);
4256 set_cc_op(s
, CC_OP_LOGIC
);
4258 switch (insn
& 0x0f00) {
4259 case 0x0a00: /* bfchg */
4260 tcg_gen_eqv_i32(src
, src
, mask
);
4262 case 0x0c00: /* bfclr */
4263 tcg_gen_and_i32(src
, src
, mask
);
4265 case 0x0d00: /* bfffo */
4266 gen_helper_bfffo_reg(DREG(ext
, 12), QREG_CC_N
, tofs
, tlen
);
4267 tcg_temp_free(tlen
);
4268 tcg_temp_free(tofs
);
4270 case 0x0e00: /* bfset */
4271 tcg_gen_orc_i32(src
, src
, mask
);
4273 case 0x0800: /* bftst */
4274 /* flags already set; no other work to do. */
4277 g_assert_not_reached();
4279 tcg_temp_free(mask
);
4282 DISAS_INSN(bfop_mem
)
4284 int ext
= read_im16(env
, s
);
4285 TCGv addr
, len
, ofs
;
4288 addr
= gen_lea(env
, s
, insn
, OS_UNSIZED
);
4289 if (IS_NULL_QREG(addr
)) {
4297 len
= tcg_const_i32(extract32(ext
, 0, 5));
4302 ofs
= tcg_const_i32(extract32(ext
, 6, 5));
4305 switch (insn
& 0x0f00) {
4306 case 0x0a00: /* bfchg */
4307 gen_helper_bfchg_mem(QREG_CC_N
, cpu_env
, addr
, ofs
, len
);
4309 case 0x0c00: /* bfclr */
4310 gen_helper_bfclr_mem(QREG_CC_N
, cpu_env
, addr
, ofs
, len
);
4312 case 0x0d00: /* bfffo */
4313 t64
= tcg_temp_new_i64();
4314 gen_helper_bfffo_mem(t64
, cpu_env
, addr
, ofs
, len
);
4315 tcg_gen_extr_i64_i32(DREG(ext
, 12), QREG_CC_N
, t64
);
4316 tcg_temp_free_i64(t64
);
4318 case 0x0e00: /* bfset */
4319 gen_helper_bfset_mem(QREG_CC_N
, cpu_env
, addr
, ofs
, len
);
4321 case 0x0800: /* bftst */
4322 gen_helper_bfexts_mem(QREG_CC_N
, cpu_env
, addr
, ofs
, len
);
4325 g_assert_not_reached();
4327 set_cc_op(s
, CC_OP_LOGIC
);
4329 if (!(ext
& 0x20)) {
4332 if (!(ext
& 0x800)) {
4337 DISAS_INSN(bfins_reg
)
4339 int ext
= read_im16(env
, s
);
4340 TCGv dst
= DREG(insn
, 0);
4341 TCGv src
= DREG(ext
, 12);
4342 int len
= ((extract32(ext
, 0, 5) - 1) & 31) + 1;
4343 int ofs
= extract32(ext
, 6, 5); /* big bit-endian */
4344 int pos
= 32 - ofs
- len
; /* little bit-endian */
4347 tmp
= tcg_temp_new();
4350 /* Variable width */
4351 tcg_gen_neg_i32(tmp
, DREG(ext
, 0));
4352 tcg_gen_andi_i32(tmp
, tmp
, 31);
4353 tcg_gen_shl_i32(QREG_CC_N
, src
, tmp
);
4355 /* Immediate width */
4356 tcg_gen_shli_i32(QREG_CC_N
, src
, 32 - len
);
4358 set_cc_op(s
, CC_OP_LOGIC
);
4360 /* Immediate width and offset */
4361 if ((ext
& 0x820) == 0) {
4362 /* Check for suitability for deposit. */
4364 tcg_gen_deposit_i32(dst
, dst
, src
, pos
, len
);
4366 uint32_t maski
= -2U << (len
- 1);
4367 uint32_t roti
= (ofs
+ len
) & 31;
4368 tcg_gen_andi_i32(tmp
, src
, ~maski
);
4369 tcg_gen_rotri_i32(tmp
, tmp
, roti
);
4370 tcg_gen_andi_i32(dst
, dst
, ror32(maski
, roti
));
4371 tcg_gen_or_i32(dst
, dst
, tmp
);
4374 TCGv mask
= tcg_temp_new();
4375 TCGv rot
= tcg_temp_new();
4378 /* Variable width */
4379 tcg_gen_subi_i32(rot
, DREG(ext
, 0), 1);
4380 tcg_gen_andi_i32(rot
, rot
, 31);
4381 tcg_gen_movi_i32(mask
, -2);
4382 tcg_gen_shl_i32(mask
, mask
, rot
);
4383 tcg_gen_mov_i32(rot
, DREG(ext
, 0));
4384 tcg_gen_andc_i32(tmp
, src
, mask
);
4386 /* Immediate width (variable offset) */
4387 uint32_t maski
= -2U << (len
- 1);
4388 tcg_gen_andi_i32(tmp
, src
, ~maski
);
4389 tcg_gen_movi_i32(mask
, maski
);
4390 tcg_gen_movi_i32(rot
, len
& 31);
4393 /* Variable offset */
4394 tcg_gen_add_i32(rot
, rot
, DREG(ext
, 6));
4396 /* Immediate offset (variable width) */
4397 tcg_gen_addi_i32(rot
, rot
, ofs
);
4399 tcg_gen_andi_i32(rot
, rot
, 31);
4400 tcg_gen_rotr_i32(mask
, mask
, rot
);
4401 tcg_gen_rotr_i32(tmp
, tmp
, rot
);
4402 tcg_gen_and_i32(dst
, dst
, mask
);
4403 tcg_gen_or_i32(dst
, dst
, tmp
);
4406 tcg_temp_free(mask
);
4411 DISAS_INSN(bfins_mem
)
4413 int ext
= read_im16(env
, s
);
4414 TCGv src
= DREG(ext
, 12);
4415 TCGv addr
, len
, ofs
;
4417 addr
= gen_lea(env
, s
, insn
, OS_UNSIZED
);
4418 if (IS_NULL_QREG(addr
)) {
4426 len
= tcg_const_i32(extract32(ext
, 0, 5));
4431 ofs
= tcg_const_i32(extract32(ext
, 6, 5));
4434 gen_helper_bfins_mem(QREG_CC_N
, cpu_env
, addr
, src
, ofs
, len
);
4435 set_cc_op(s
, CC_OP_LOGIC
);
4437 if (!(ext
& 0x20)) {
4440 if (!(ext
& 0x800)) {
4448 reg
= DREG(insn
, 0);
4449 gen_logic_cc(s
, reg
, OS_LONG
);
4450 gen_helper_ff1(reg
, reg
);
4458 switch ((insn
>> 7) & 3) {
4463 if (m68k_feature(env
, M68K_FEATURE_CHK2
)) {
4469 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
4472 SRC_EA(env
, src
, opsize
, 1, NULL
);
4473 reg
= gen_extend(s
, DREG(insn
, 9), opsize
, 1);
4476 gen_helper_chk(cpu_env
, reg
, src
);
4482 TCGv addr1
, addr2
, bound1
, bound2
, reg
;
4485 switch ((insn
>> 9) & 3) {
4496 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
4500 ext
= read_im16(env
, s
);
4501 if ((ext
& 0x0800) == 0) {
4502 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
4506 addr1
= gen_lea(env
, s
, insn
, OS_UNSIZED
);
4507 addr2
= tcg_temp_new();
4508 tcg_gen_addi_i32(addr2
, addr1
, opsize_bytes(opsize
));
4510 bound1
= gen_load(s
, opsize
, addr1
, 1, IS_USER(s
));
4511 tcg_temp_free(addr1
);
4512 bound2
= gen_load(s
, opsize
, addr2
, 1, IS_USER(s
));
4513 tcg_temp_free(addr2
);
4515 reg
= tcg_temp_new();
4517 tcg_gen_mov_i32(reg
, AREG(ext
, 12));
4519 gen_ext(reg
, DREG(ext
, 12), opsize
, 1);
4523 gen_helper_chk2(cpu_env
, reg
, bound1
, bound2
);
4525 tcg_temp_free(bound1
);
4526 tcg_temp_free(bound2
);
4529 static void m68k_copy_line(TCGv dst
, TCGv src
, int index
)
4534 addr
= tcg_temp_new();
4536 t0
= tcg_temp_new_i64();
4537 t1
= tcg_temp_new_i64();
4539 tcg_gen_andi_i32(addr
, src
, ~15);
4540 tcg_gen_qemu_ld64(t0
, addr
, index
);
4541 tcg_gen_addi_i32(addr
, addr
, 8);
4542 tcg_gen_qemu_ld64(t1
, addr
, index
);
4544 tcg_gen_andi_i32(addr
, dst
, ~15);
4545 tcg_gen_qemu_st64(t0
, addr
, index
);
4546 tcg_gen_addi_i32(addr
, addr
, 8);
4547 tcg_gen_qemu_st64(t1
, addr
, index
);
4549 tcg_temp_free_i64(t0
);
4550 tcg_temp_free_i64(t1
);
4551 tcg_temp_free(addr
);
4554 DISAS_INSN(move16_reg
)
4556 int index
= IS_USER(s
);
4560 ext
= read_im16(env
, s
);
4561 if ((ext
& (1 << 15)) == 0) {
4562 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
4565 m68k_copy_line(AREG(ext
, 12), AREG(insn
, 0), index
);
4567 /* Ax can be Ay, so save Ay before incrementing Ax */
4568 tmp
= tcg_temp_new();
4569 tcg_gen_mov_i32(tmp
, AREG(ext
, 12));
4570 tcg_gen_addi_i32(AREG(insn
, 0), AREG(insn
, 0), 16);
4571 tcg_gen_addi_i32(AREG(ext
, 12), tmp
, 16);
4575 DISAS_INSN(move16_mem
)
4577 int index
= IS_USER(s
);
4580 reg
= AREG(insn
, 0);
4581 addr
= tcg_const_i32(read_im32(env
, s
));
4583 if ((insn
>> 3) & 1) {
4584 /* MOVE16 (xxx).L, (Ay) */
4585 m68k_copy_line(reg
, addr
, index
);
4587 /* MOVE16 (Ay), (xxx).L */
4588 m68k_copy_line(addr
, reg
, index
);
4591 tcg_temp_free(addr
);
4593 if (((insn
>> 3) & 2) == 0) {
4595 tcg_gen_addi_i32(reg
, reg
, 16);
4605 ext
= read_im16(env
, s
);
4606 if (ext
!= 0x46FC) {
4607 gen_exception(s
, addr
, EXCP_ILLEGAL
);
4610 ext
= read_im16(env
, s
);
4611 if (IS_USER(s
) || (ext
& SR_S
) == 0) {
4612 gen_exception(s
, addr
, EXCP_PRIVILEGE
);
4615 gen_push(s
, gen_get_sr(s
));
4616 gen_set_sr_im(s
, ext
, 0);
4619 DISAS_INSN(move_from_sr
)
4623 if (IS_USER(s
) && !m68k_feature(env
, M68K_FEATURE_M68K
)) {
4624 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4628 DEST_EA(env
, insn
, OS_WORD
, sr
, NULL
);
4631 #if defined(CONFIG_SOFTMMU)
4641 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4645 ext
= read_im16(env
, s
);
4647 opsize
= insn_opsize(insn
);
4650 /* address register */
4651 reg
= AREG(ext
, 12);
4655 reg
= DREG(ext
, 12);
4659 addr
= gen_lea(env
, s
, insn
, opsize
);
4660 if (IS_NULL_QREG(addr
)) {
4666 /* from reg to ea */
4667 gen_store(s
, opsize
, addr
, reg
, DFC_INDEX(s
));
4669 /* from ea to reg */
4670 TCGv tmp
= gen_load(s
, opsize
, addr
, 0, SFC_INDEX(s
));
4672 gen_ext(reg
, tmp
, opsize
, 1);
4674 gen_partset_reg(opsize
, reg
, tmp
);
4678 switch (extract32(insn
, 3, 3)) {
4679 case 3: /* Indirect postincrement. */
4680 tcg_gen_addi_i32(AREG(insn
, 0), addr
,
4681 REG(insn
, 0) == 7 && opsize
== OS_BYTE
4683 : opsize_bytes(opsize
));
4685 case 4: /* Indirect predecrememnt. */
4686 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
4691 DISAS_INSN(move_to_sr
)
4694 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4697 gen_move_to_sr(env
, s
, insn
, false);
4701 DISAS_INSN(move_from_usp
)
4704 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4707 tcg_gen_ld_i32(AREG(insn
, 0), cpu_env
,
4708 offsetof(CPUM68KState
, sp
[M68K_USP
]));
4711 DISAS_INSN(move_to_usp
)
4714 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4717 tcg_gen_st_i32(AREG(insn
, 0), cpu_env
,
4718 offsetof(CPUM68KState
, sp
[M68K_USP
]));
4724 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4728 gen_exception(s
, s
->pc
, EXCP_HALT_INSN
);
4736 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4740 ext
= read_im16(env
, s
);
4742 gen_set_sr_im(s
, ext
, 0);
4743 tcg_gen_movi_i32(cpu_halted
, 1);
4744 gen_exception(s
, s
->pc
, EXCP_HLT
);
4750 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4753 gen_exception(s
, s
->base
.pc_next
, EXCP_RTE
);
4756 DISAS_INSN(cf_movec
)
4762 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4766 ext
= read_im16(env
, s
);
4769 reg
= AREG(ext
, 12);
4771 reg
= DREG(ext
, 12);
4773 gen_helper_cf_movec_to(cpu_env
, tcg_const_i32(ext
& 0xfff), reg
);
4777 DISAS_INSN(m68k_movec
)
4783 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4787 ext
= read_im16(env
, s
);
4790 reg
= AREG(ext
, 12);
4792 reg
= DREG(ext
, 12);
4795 gen_helper_m68k_movec_to(cpu_env
, tcg_const_i32(ext
& 0xfff), reg
);
4797 gen_helper_m68k_movec_from(reg
, cpu_env
, tcg_const_i32(ext
& 0xfff));
4805 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4808 /* ICache fetch. Implement as no-op. */
4814 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4817 /* Cache push/invalidate. Implement as no-op. */
4823 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4826 /* Cache push/invalidate. Implement as no-op. */
4832 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4835 /* Invalidate cache line. Implement as no-op. */
4838 #if defined(CONFIG_SOFTMMU)
4844 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4848 opmode
= tcg_const_i32((insn
>> 3) & 3);
4849 gen_helper_pflush(cpu_env
, AREG(insn
, 0), opmode
);
4850 tcg_temp_free(opmode
);
4858 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4861 is_read
= tcg_const_i32((insn
>> 5) & 1);
4862 gen_helper_ptest(cpu_env
, AREG(insn
, 0), is_read
);
4863 tcg_temp_free(is_read
);
4869 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4875 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4878 /* TODO: Implement wdebug. */
4879 cpu_abort(env_cpu(env
), "WDEBUG not implemented");
4885 gen_exception(s
, s
->pc
, EXCP_TRAP0
+ (insn
& 0xf));
4888 static void do_trapcc(DisasContext
*s
, DisasCompare
*c
)
4890 if (c
->tcond
!= TCG_COND_NEVER
) {
4891 TCGLabel
*over
= NULL
;
4895 if (c
->tcond
!= TCG_COND_ALWAYS
) {
4896 /* Jump over if !c. */
4897 over
= gen_new_label();
4898 tcg_gen_brcond_i32(tcg_invert_cond(c
->tcond
), c
->v1
, c
->v2
, over
);
4901 tcg_gen_movi_i32(QREG_PC
, s
->pc
);
4902 gen_raise_exception_format2(s
, EXCP_TRAPCC
, s
->base
.pc_next
);
4905 gen_set_label(over
);
4906 s
->base
.is_jmp
= DISAS_NEXT
;
4916 /* Consume and discard the immediate operand. */
4917 switch (extract32(insn
, 0, 3)) {
4918 case 2: /* trapcc.w */
4919 (void)read_im16(env
, s
);
4921 case 3: /* trapcc.l */
4922 (void)read_im32(env
, s
);
4924 case 4: /* trapcc (no operand) */
4927 /* trapcc registered with only valid opmodes */
4928 g_assert_not_reached();
4931 gen_cc_cond(&c
, s
, extract32(insn
, 8, 4));
4939 gen_cc_cond(&c
, s
, 9); /* V set */
4943 static void gen_load_fcr(DisasContext
*s
, TCGv res
, int reg
)
4947 tcg_gen_movi_i32(res
, 0);
4950 tcg_gen_ld_i32(res
, cpu_env
, offsetof(CPUM68KState
, fpsr
));
4953 tcg_gen_ld_i32(res
, cpu_env
, offsetof(CPUM68KState
, fpcr
));
4958 static void gen_store_fcr(DisasContext
*s
, TCGv val
, int reg
)
4964 tcg_gen_st_i32(val
, cpu_env
, offsetof(CPUM68KState
, fpsr
));
4967 gen_helper_set_fpcr(cpu_env
, val
);
4972 static void gen_qemu_store_fcr(DisasContext
*s
, TCGv addr
, int reg
)
4974 int index
= IS_USER(s
);
4977 tmp
= tcg_temp_new();
4978 gen_load_fcr(s
, tmp
, reg
);
4979 tcg_gen_qemu_st32(tmp
, addr
, index
);
4983 static void gen_qemu_load_fcr(DisasContext
*s
, TCGv addr
, int reg
)
4985 int index
= IS_USER(s
);
4988 tmp
= tcg_temp_new();
4989 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
4990 gen_store_fcr(s
, tmp
, reg
);
4995 static void gen_op_fmove_fcr(CPUM68KState
*env
, DisasContext
*s
,
4996 uint32_t insn
, uint32_t ext
)
4998 int mask
= (ext
>> 10) & 7;
4999 int is_write
= (ext
>> 13) & 1;
5000 int mode
= extract32(insn
, 3, 3);
5006 if (mask
!= M68K_FPIAR
&& mask
!= M68K_FPSR
&& mask
!= M68K_FPCR
) {
5007 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
5011 gen_load_fcr(s
, DREG(insn
, 0), mask
);
5013 gen_store_fcr(s
, DREG(insn
, 0), mask
);
5016 case 1: /* An, only with FPIAR */
5017 if (mask
!= M68K_FPIAR
) {
5018 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
5022 gen_load_fcr(s
, AREG(insn
, 0), mask
);
5024 gen_store_fcr(s
, AREG(insn
, 0), mask
);
5027 case 7: /* Immediate */
5028 if (REG(insn
, 0) == 4) {
5030 (mask
!= M68K_FPIAR
&& mask
!= M68K_FPSR
&&
5031 mask
!= M68K_FPCR
)) {
5032 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
5035 tmp
= tcg_const_i32(read_im32(env
, s
));
5036 gen_store_fcr(s
, tmp
, mask
);
5045 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
5046 if (IS_NULL_QREG(tmp
)) {
5051 addr
= tcg_temp_new();
5052 tcg_gen_mov_i32(addr
, tmp
);
5057 * 0b100 Floating-Point Control Register
5058 * 0b010 Floating-Point Status Register
5059 * 0b001 Floating-Point Instruction Address Register
5063 if (is_write
&& mode
== 4) {
5064 for (i
= 2; i
>= 0; i
--, mask
>>= 1) {
5066 gen_qemu_store_fcr(s
, addr
, 1 << i
);
5068 tcg_gen_subi_i32(addr
, addr
, opsize_bytes(OS_LONG
));
5072 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
5074 for (i
= 0; i
< 3; i
++, mask
>>= 1) {
5077 gen_qemu_store_fcr(s
, addr
, 1 << i
);
5079 gen_qemu_load_fcr(s
, addr
, 1 << i
);
5081 if (mask
!= 1 || mode
== 3) {
5082 tcg_gen_addi_i32(addr
, addr
, opsize_bytes(OS_LONG
));
5087 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
5090 tcg_temp_free_i32(addr
);
5093 static void gen_op_fmovem(CPUM68KState
*env
, DisasContext
*s
,
5094 uint32_t insn
, uint32_t ext
)
5098 int mode
= (ext
>> 11) & 0x3;
5099 int is_load
= ((ext
& 0x2000) == 0);
5101 if (m68k_feature(s
->env
, M68K_FEATURE_FPU
)) {
5102 opsize
= OS_EXTENDED
;
5104 opsize
= OS_DOUBLE
; /* FIXME */
5107 addr
= gen_lea(env
, s
, insn
, opsize
);
5108 if (IS_NULL_QREG(addr
)) {
5113 tmp
= tcg_temp_new();
5115 /* Dynamic register list */
5116 tcg_gen_ext8u_i32(tmp
, DREG(ext
, 4));
5118 /* Static register list */
5119 tcg_gen_movi_i32(tmp
, ext
& 0xff);
5122 if (!is_load
&& (mode
& 2) == 0) {
5124 * predecrement addressing mode
5125 * only available to store register to memory
5127 if (opsize
== OS_EXTENDED
) {
5128 gen_helper_fmovemx_st_predec(tmp
, cpu_env
, addr
, tmp
);
5130 gen_helper_fmovemd_st_predec(tmp
, cpu_env
, addr
, tmp
);
5133 /* postincrement addressing mode */
5134 if (opsize
== OS_EXTENDED
) {
5136 gen_helper_fmovemx_ld_postinc(tmp
, cpu_env
, addr
, tmp
);
5138 gen_helper_fmovemx_st_postinc(tmp
, cpu_env
, addr
, tmp
);
5142 gen_helper_fmovemd_ld_postinc(tmp
, cpu_env
, addr
, tmp
);
5144 gen_helper_fmovemd_st_postinc(tmp
, cpu_env
, addr
, tmp
);
5148 if ((insn
& 070) == 030 || (insn
& 070) == 040) {
5149 tcg_gen_mov_i32(AREG(insn
, 0), tmp
);
5155 * ??? FP exceptions are not implemented. Most exceptions are deferred until
5156 * immediately before the next FP instruction is executed.
5163 TCGv_ptr cpu_src
, cpu_dest
;
5165 ext
= read_im16(env
, s
);
5166 opmode
= ext
& 0x7f;
5167 switch ((ext
>> 13) & 7) {
5173 if (insn
== 0xf200 && (ext
& 0xfc00) == 0x5c00) {
5175 TCGv rom_offset
= tcg_const_i32(opmode
);
5176 cpu_dest
= gen_fp_ptr(REG(ext
, 7));
5177 gen_helper_fconst(cpu_env
, cpu_dest
, rom_offset
);
5178 tcg_temp_free_ptr(cpu_dest
);
5179 tcg_temp_free(rom_offset
);
5183 case 3: /* fmove out */
5184 cpu_src
= gen_fp_ptr(REG(ext
, 7));
5185 opsize
= ext_opsize(ext
, 10);
5186 if (gen_ea_fp(env
, s
, insn
, opsize
, cpu_src
,
5187 EA_STORE
, IS_USER(s
)) == -1) {
5190 gen_helper_ftst(cpu_env
, cpu_src
);
5191 tcg_temp_free_ptr(cpu_src
);
5193 case 4: /* fmove to control register. */
5194 case 5: /* fmove from control register. */
5195 gen_op_fmove_fcr(env
, s
, insn
, ext
);
5197 case 6: /* fmovem */
5199 if ((ext
& 0x1000) == 0 && !m68k_feature(s
->env
, M68K_FEATURE_FPU
)) {
5202 gen_op_fmovem(env
, s
, insn
, ext
);
5205 if (ext
& (1 << 14)) {
5206 /* Source effective address. */
5207 opsize
= ext_opsize(ext
, 10);
5208 cpu_src
= gen_fp_result_ptr();
5209 if (gen_ea_fp(env
, s
, insn
, opsize
, cpu_src
,
5210 EA_LOADS
, IS_USER(s
)) == -1) {
5215 /* Source register. */
5216 opsize
= OS_EXTENDED
;
5217 cpu_src
= gen_fp_ptr(REG(ext
, 10));
5219 cpu_dest
= gen_fp_ptr(REG(ext
, 7));
5222 gen_fp_move(cpu_dest
, cpu_src
);
5224 case 0x40: /* fsmove */
5225 gen_helper_fsround(cpu_env
, cpu_dest
, cpu_src
);
5227 case 0x44: /* fdmove */
5228 gen_helper_fdround(cpu_env
, cpu_dest
, cpu_src
);
5231 gen_helper_firound(cpu_env
, cpu_dest
, cpu_src
);
5234 gen_helper_fsinh(cpu_env
, cpu_dest
, cpu_src
);
5236 case 3: /* fintrz */
5237 gen_helper_fitrunc(cpu_env
, cpu_dest
, cpu_src
);
5240 gen_helper_fsqrt(cpu_env
, cpu_dest
, cpu_src
);
5242 case 0x41: /* fssqrt */
5243 gen_helper_fssqrt(cpu_env
, cpu_dest
, cpu_src
);
5245 case 0x45: /* fdsqrt */
5246 gen_helper_fdsqrt(cpu_env
, cpu_dest
, cpu_src
);
5248 case 0x06: /* flognp1 */
5249 gen_helper_flognp1(cpu_env
, cpu_dest
, cpu_src
);
5251 case 0x08: /* fetoxm1 */
5252 gen_helper_fetoxm1(cpu_env
, cpu_dest
, cpu_src
);
5254 case 0x09: /* ftanh */
5255 gen_helper_ftanh(cpu_env
, cpu_dest
, cpu_src
);
5257 case 0x0a: /* fatan */
5258 gen_helper_fatan(cpu_env
, cpu_dest
, cpu_src
);
5260 case 0x0c: /* fasin */
5261 gen_helper_fasin(cpu_env
, cpu_dest
, cpu_src
);
5263 case 0x0d: /* fatanh */
5264 gen_helper_fatanh(cpu_env
, cpu_dest
, cpu_src
);
5266 case 0x0e: /* fsin */
5267 gen_helper_fsin(cpu_env
, cpu_dest
, cpu_src
);
5269 case 0x0f: /* ftan */
5270 gen_helper_ftan(cpu_env
, cpu_dest
, cpu_src
);
5272 case 0x10: /* fetox */
5273 gen_helper_fetox(cpu_env
, cpu_dest
, cpu_src
);
5275 case 0x11: /* ftwotox */
5276 gen_helper_ftwotox(cpu_env
, cpu_dest
, cpu_src
);
5278 case 0x12: /* ftentox */
5279 gen_helper_ftentox(cpu_env
, cpu_dest
, cpu_src
);
5281 case 0x14: /* flogn */
5282 gen_helper_flogn(cpu_env
, cpu_dest
, cpu_src
);
5284 case 0x15: /* flog10 */
5285 gen_helper_flog10(cpu_env
, cpu_dest
, cpu_src
);
5287 case 0x16: /* flog2 */
5288 gen_helper_flog2(cpu_env
, cpu_dest
, cpu_src
);
5290 case 0x18: /* fabs */
5291 gen_helper_fabs(cpu_env
, cpu_dest
, cpu_src
);
5293 case 0x58: /* fsabs */
5294 gen_helper_fsabs(cpu_env
, cpu_dest
, cpu_src
);
5296 case 0x5c: /* fdabs */
5297 gen_helper_fdabs(cpu_env
, cpu_dest
, cpu_src
);
5299 case 0x19: /* fcosh */
5300 gen_helper_fcosh(cpu_env
, cpu_dest
, cpu_src
);
5302 case 0x1a: /* fneg */
5303 gen_helper_fneg(cpu_env
, cpu_dest
, cpu_src
);
5305 case 0x5a: /* fsneg */
5306 gen_helper_fsneg(cpu_env
, cpu_dest
, cpu_src
);
5308 case 0x5e: /* fdneg */
5309 gen_helper_fdneg(cpu_env
, cpu_dest
, cpu_src
);
5311 case 0x1c: /* facos */
5312 gen_helper_facos(cpu_env
, cpu_dest
, cpu_src
);
5314 case 0x1d: /* fcos */
5315 gen_helper_fcos(cpu_env
, cpu_dest
, cpu_src
);
5317 case 0x1e: /* fgetexp */
5318 gen_helper_fgetexp(cpu_env
, cpu_dest
, cpu_src
);
5320 case 0x1f: /* fgetman */
5321 gen_helper_fgetman(cpu_env
, cpu_dest
, cpu_src
);
5323 case 0x20: /* fdiv */
5324 gen_helper_fdiv(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5326 case 0x60: /* fsdiv */
5327 gen_helper_fsdiv(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5329 case 0x64: /* fddiv */
5330 gen_helper_fddiv(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5332 case 0x21: /* fmod */
5333 gen_helper_fmod(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5335 case 0x22: /* fadd */
5336 gen_helper_fadd(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5338 case 0x62: /* fsadd */
5339 gen_helper_fsadd(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5341 case 0x66: /* fdadd */
5342 gen_helper_fdadd(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5344 case 0x23: /* fmul */
5345 gen_helper_fmul(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5347 case 0x63: /* fsmul */
5348 gen_helper_fsmul(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5350 case 0x67: /* fdmul */
5351 gen_helper_fdmul(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5353 case 0x24: /* fsgldiv */
5354 gen_helper_fsgldiv(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5356 case 0x25: /* frem */
5357 gen_helper_frem(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5359 case 0x26: /* fscale */
5360 gen_helper_fscale(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5362 case 0x27: /* fsglmul */
5363 gen_helper_fsglmul(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5365 case 0x28: /* fsub */
5366 gen_helper_fsub(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5368 case 0x68: /* fssub */
5369 gen_helper_fssub(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5371 case 0x6c: /* fdsub */
5372 gen_helper_fdsub(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5374 case 0x30: case 0x31: case 0x32:
5375 case 0x33: case 0x34: case 0x35:
5376 case 0x36: case 0x37: {
5377 TCGv_ptr cpu_dest2
= gen_fp_ptr(REG(ext
, 0));
5378 gen_helper_fsincos(cpu_env
, cpu_dest
, cpu_dest2
, cpu_src
);
5379 tcg_temp_free_ptr(cpu_dest2
);
5382 case 0x38: /* fcmp */
5383 gen_helper_fcmp(cpu_env
, cpu_src
, cpu_dest
);
5385 case 0x3a: /* ftst */
5386 gen_helper_ftst(cpu_env
, cpu_src
);
5391 tcg_temp_free_ptr(cpu_src
);
5392 gen_helper_ftst(cpu_env
, cpu_dest
);
5393 tcg_temp_free_ptr(cpu_dest
);
5396 /* FIXME: Is this right for offset addressing modes? */
5398 disas_undef_fpu(env
, s
, insn
);
5401 static void gen_fcc_cond(DisasCompare
*c
, DisasContext
*s
, int cond
)
5406 c
->v2
= tcg_const_i32(0);
5408 /* TODO: Raise BSUN exception. */
5409 fpsr
= tcg_temp_new();
5410 gen_load_fcr(s
, fpsr
, M68K_FPSR
);
5413 case 16: /* Signaling False */
5415 c
->tcond
= TCG_COND_NEVER
;
5417 case 1: /* EQual Z */
5418 case 17: /* Signaling EQual Z */
5419 c
->v1
= tcg_temp_new();
5421 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_Z
);
5422 c
->tcond
= TCG_COND_NE
;
5424 case 2: /* Ordered Greater Than !(A || Z || N) */
5425 case 18: /* Greater Than !(A || Z || N) */
5426 c
->v1
= tcg_temp_new();
5428 tcg_gen_andi_i32(c
->v1
, fpsr
,
5429 FPSR_CC_A
| FPSR_CC_Z
| FPSR_CC_N
);
5430 c
->tcond
= TCG_COND_EQ
;
5432 case 3: /* Ordered Greater than or Equal Z || !(A || N) */
5433 case 19: /* Greater than or Equal Z || !(A || N) */
5434 c
->v1
= tcg_temp_new();
5436 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
);
5437 tcg_gen_shli_i32(c
->v1
, c
->v1
, ctz32(FPSR_CC_N
) - ctz32(FPSR_CC_A
));
5438 tcg_gen_andi_i32(fpsr
, fpsr
, FPSR_CC_Z
| FPSR_CC_N
);
5439 tcg_gen_or_i32(c
->v1
, c
->v1
, fpsr
);
5440 tcg_gen_xori_i32(c
->v1
, c
->v1
, FPSR_CC_N
);
5441 c
->tcond
= TCG_COND_NE
;
5443 case 4: /* Ordered Less Than !(!N || A || Z); */
5444 case 20: /* Less Than !(!N || A || Z); */
5445 c
->v1
= tcg_temp_new();
5447 tcg_gen_xori_i32(c
->v1
, fpsr
, FPSR_CC_N
);
5448 tcg_gen_andi_i32(c
->v1
, c
->v1
, FPSR_CC_N
| FPSR_CC_A
| FPSR_CC_Z
);
5449 c
->tcond
= TCG_COND_EQ
;
5451 case 5: /* Ordered Less than or Equal Z || (N && !A) */
5452 case 21: /* Less than or Equal Z || (N && !A) */
5453 c
->v1
= tcg_temp_new();
5455 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
);
5456 tcg_gen_shli_i32(c
->v1
, c
->v1
, ctz32(FPSR_CC_N
) - ctz32(FPSR_CC_A
));
5457 tcg_gen_andc_i32(c
->v1
, fpsr
, c
->v1
);
5458 tcg_gen_andi_i32(c
->v1
, c
->v1
, FPSR_CC_Z
| FPSR_CC_N
);
5459 c
->tcond
= TCG_COND_NE
;
5461 case 6: /* Ordered Greater or Less than !(A || Z) */
5462 case 22: /* Greater or Less than !(A || Z) */
5463 c
->v1
= tcg_temp_new();
5465 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
| FPSR_CC_Z
);
5466 c
->tcond
= TCG_COND_EQ
;
5468 case 7: /* Ordered !A */
5469 case 23: /* Greater, Less or Equal !A */
5470 c
->v1
= tcg_temp_new();
5472 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
);
5473 c
->tcond
= TCG_COND_EQ
;
5475 case 8: /* Unordered A */
5476 case 24: /* Not Greater, Less or Equal A */
5477 c
->v1
= tcg_temp_new();
5479 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
);
5480 c
->tcond
= TCG_COND_NE
;
5482 case 9: /* Unordered or Equal A || Z */
5483 case 25: /* Not Greater or Less then A || Z */
5484 c
->v1
= tcg_temp_new();
5486 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
| FPSR_CC_Z
);
5487 c
->tcond
= TCG_COND_NE
;
5489 case 10: /* Unordered or Greater Than A || !(N || Z)) */
5490 case 26: /* Not Less or Equal A || !(N || Z)) */
5491 c
->v1
= tcg_temp_new();
5493 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_Z
);
5494 tcg_gen_shli_i32(c
->v1
, c
->v1
, ctz32(FPSR_CC_N
) - ctz32(FPSR_CC_Z
));
5495 tcg_gen_andi_i32(fpsr
, fpsr
, FPSR_CC_A
| FPSR_CC_N
);
5496 tcg_gen_or_i32(c
->v1
, c
->v1
, fpsr
);
5497 tcg_gen_xori_i32(c
->v1
, c
->v1
, FPSR_CC_N
);
5498 c
->tcond
= TCG_COND_NE
;
5500 case 11: /* Unordered or Greater or Equal A || Z || !N */
5501 case 27: /* Not Less Than A || Z || !N */
5502 c
->v1
= tcg_temp_new();
5504 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
| FPSR_CC_Z
| FPSR_CC_N
);
5505 tcg_gen_xori_i32(c
->v1
, c
->v1
, FPSR_CC_N
);
5506 c
->tcond
= TCG_COND_NE
;
5508 case 12: /* Unordered or Less Than A || (N && !Z) */
5509 case 28: /* Not Greater than or Equal A || (N && !Z) */
5510 c
->v1
= tcg_temp_new();
5512 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_Z
);
5513 tcg_gen_shli_i32(c
->v1
, c
->v1
, ctz32(FPSR_CC_N
) - ctz32(FPSR_CC_Z
));
5514 tcg_gen_andc_i32(c
->v1
, fpsr
, c
->v1
);
5515 tcg_gen_andi_i32(c
->v1
, c
->v1
, FPSR_CC_A
| FPSR_CC_N
);
5516 c
->tcond
= TCG_COND_NE
;
5518 case 13: /* Unordered or Less or Equal A || Z || N */
5519 case 29: /* Not Greater Than A || Z || N */
5520 c
->v1
= tcg_temp_new();
5522 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
| FPSR_CC_Z
| FPSR_CC_N
);
5523 c
->tcond
= TCG_COND_NE
;
5525 case 14: /* Not Equal !Z */
5526 case 30: /* Signaling Not Equal !Z */
5527 c
->v1
= tcg_temp_new();
5529 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_Z
);
5530 c
->tcond
= TCG_COND_EQ
;
5533 case 31: /* Signaling True */
5535 c
->tcond
= TCG_COND_ALWAYS
;
5538 tcg_temp_free(fpsr
);
5541 static void gen_fjmpcc(DisasContext
*s
, int cond
, TCGLabel
*l1
)
5545 gen_fcc_cond(&c
, s
, cond
);
5547 tcg_gen_brcond_i32(c
.tcond
, c
.v1
, c
.v2
, l1
);
5558 offset
= (int16_t)read_im16(env
, s
);
5559 if (insn
& (1 << 6)) {
5560 offset
= (offset
<< 16) | read_im16(env
, s
);
5563 l1
= gen_new_label();
5565 gen_fjmpcc(s
, insn
& 0x3f, l1
);
5566 gen_jmp_tb(s
, 0, s
->pc
, s
->base
.pc_next
);
5568 gen_jmp_tb(s
, 1, base
+ offset
, s
->base
.pc_next
);
5578 ext
= read_im16(env
, s
);
5580 gen_fcc_cond(&c
, s
, cond
);
5582 tmp
= tcg_temp_new();
5583 tcg_gen_setcond_i32(c
.tcond
, tmp
, c
.v1
, c
.v2
);
5586 tcg_gen_neg_i32(tmp
, tmp
);
5587 DEST_EA(env
, insn
, OS_BYTE
, tmp
, NULL
);
5597 ext
= read_im16(env
, s
);
5600 /* Consume and discard the immediate operand. */
5601 switch (extract32(insn
, 0, 3)) {
5602 case 2: /* ftrapcc.w */
5603 (void)read_im16(env
, s
);
5605 case 3: /* ftrapcc.l */
5606 (void)read_im32(env
, s
);
5608 case 4: /* ftrapcc (no operand) */
5611 /* ftrapcc registered with only valid opmodes */
5612 g_assert_not_reached();
5615 gen_fcc_cond(&c
, s
, cond
);
5619 #if defined(CONFIG_SOFTMMU)
5620 DISAS_INSN(frestore
)
5625 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
5628 if (m68k_feature(s
->env
, M68K_FEATURE_M68040
)) {
5629 SRC_EA(env
, addr
, OS_LONG
, 0, NULL
);
5630 /* FIXME: check the state frame */
5632 disas_undef(env
, s
, insn
);
5639 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
5643 if (m68k_feature(s
->env
, M68K_FEATURE_M68040
)) {
5644 /* always write IDLE */
5645 TCGv idle
= tcg_const_i32(0x41000000);
5646 DEST_EA(env
, insn
, OS_LONG
, idle
, NULL
);
5647 tcg_temp_free(idle
);
5649 disas_undef(env
, s
, insn
);
5654 static inline TCGv
gen_mac_extract_word(DisasContext
*s
, TCGv val
, int upper
)
5656 TCGv tmp
= tcg_temp_new();
5657 if (s
->env
->macsr
& MACSR_FI
) {
5659 tcg_gen_andi_i32(tmp
, val
, 0xffff0000);
5661 tcg_gen_shli_i32(tmp
, val
, 16);
5662 } else if (s
->env
->macsr
& MACSR_SU
) {
5664 tcg_gen_sari_i32(tmp
, val
, 16);
5666 tcg_gen_ext16s_i32(tmp
, val
);
5669 tcg_gen_shri_i32(tmp
, val
, 16);
5671 tcg_gen_ext16u_i32(tmp
, val
);
5676 static void gen_mac_clear_flags(void)
5678 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
,
5679 ~(MACSR_V
| MACSR_Z
| MACSR_N
| MACSR_EV
));
5695 s
->mactmp
= tcg_temp_new_i64();
5699 ext
= read_im16(env
, s
);
5701 acc
= ((insn
>> 7) & 1) | ((ext
>> 3) & 2);
5702 dual
= ((insn
& 0x30) != 0 && (ext
& 3) != 0);
5703 if (dual
&& !m68k_feature(s
->env
, M68K_FEATURE_CF_EMAC_B
)) {
5704 disas_undef(env
, s
, insn
);
5708 /* MAC with load. */
5709 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
5710 addr
= tcg_temp_new();
5711 tcg_gen_and_i32(addr
, tmp
, QREG_MAC_MASK
);
5713 * Load the value now to ensure correct exception behavior.
5714 * Perform writeback after reading the MAC inputs.
5716 loadval
= gen_load(s
, OS_LONG
, addr
, 0, IS_USER(s
));
5719 rx
= (ext
& 0x8000) ? AREG(ext
, 12) : DREG(insn
, 12);
5720 ry
= (ext
& 8) ? AREG(ext
, 0) : DREG(ext
, 0);
5722 loadval
= addr
= NULL_QREG
;
5723 rx
= (insn
& 0x40) ? AREG(insn
, 9) : DREG(insn
, 9);
5724 ry
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5727 gen_mac_clear_flags();
5730 /* Disabled because conditional branches clobber temporary vars. */
5731 if ((s
->env
->macsr
& MACSR_OMC
) != 0 && !dual
) {
5732 /* Skip the multiply if we know we will ignore it. */
5733 l1
= gen_new_label();
5734 tmp
= tcg_temp_new();
5735 tcg_gen_andi_i32(tmp
, QREG_MACSR
, 1 << (acc
+ 8));
5736 gen_op_jmp_nz32(tmp
, l1
);
5740 if ((ext
& 0x0800) == 0) {
5742 rx
= gen_mac_extract_word(s
, rx
, (ext
& 0x80) != 0);
5743 ry
= gen_mac_extract_word(s
, ry
, (ext
& 0x40) != 0);
5745 if (s
->env
->macsr
& MACSR_FI
) {
5746 gen_helper_macmulf(s
->mactmp
, cpu_env
, rx
, ry
);
5748 if (s
->env
->macsr
& MACSR_SU
)
5749 gen_helper_macmuls(s
->mactmp
, cpu_env
, rx
, ry
);
5751 gen_helper_macmulu(s
->mactmp
, cpu_env
, rx
, ry
);
5752 switch ((ext
>> 9) & 3) {
5754 tcg_gen_shli_i64(s
->mactmp
, s
->mactmp
, 1);
5757 tcg_gen_shri_i64(s
->mactmp
, s
->mactmp
, 1);
5763 /* Save the overflow flag from the multiply. */
5764 saved_flags
= tcg_temp_new();
5765 tcg_gen_mov_i32(saved_flags
, QREG_MACSR
);
5767 saved_flags
= NULL_QREG
;
5771 /* Disabled because conditional branches clobber temporary vars. */
5772 if ((s
->env
->macsr
& MACSR_OMC
) != 0 && dual
) {
5773 /* Skip the accumulate if the value is already saturated. */
5774 l1
= gen_new_label();
5775 tmp
= tcg_temp_new();
5776 gen_op_and32(tmp
, QREG_MACSR
, tcg_const_i32(MACSR_PAV0
<< acc
));
5777 gen_op_jmp_nz32(tmp
, l1
);
5782 tcg_gen_sub_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
5784 tcg_gen_add_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
5786 if (s
->env
->macsr
& MACSR_FI
)
5787 gen_helper_macsatf(cpu_env
, tcg_const_i32(acc
));
5788 else if (s
->env
->macsr
& MACSR_SU
)
5789 gen_helper_macsats(cpu_env
, tcg_const_i32(acc
));
5791 gen_helper_macsatu(cpu_env
, tcg_const_i32(acc
));
5794 /* Disabled because conditional branches clobber temporary vars. */
5800 /* Dual accumulate variant. */
5801 acc
= (ext
>> 2) & 3;
5802 /* Restore the overflow flag from the multiplier. */
5803 tcg_gen_mov_i32(QREG_MACSR
, saved_flags
);
5805 /* Disabled because conditional branches clobber temporary vars. */
5806 if ((s
->env
->macsr
& MACSR_OMC
) != 0) {
5807 /* Skip the accumulate if the value is already saturated. */
5808 l1
= gen_new_label();
5809 tmp
= tcg_temp_new();
5810 gen_op_and32(tmp
, QREG_MACSR
, tcg_const_i32(MACSR_PAV0
<< acc
));
5811 gen_op_jmp_nz32(tmp
, l1
);
5815 tcg_gen_sub_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
5817 tcg_gen_add_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
5818 if (s
->env
->macsr
& MACSR_FI
)
5819 gen_helper_macsatf(cpu_env
, tcg_const_i32(acc
));
5820 else if (s
->env
->macsr
& MACSR_SU
)
5821 gen_helper_macsats(cpu_env
, tcg_const_i32(acc
));
5823 gen_helper_macsatu(cpu_env
, tcg_const_i32(acc
));
5825 /* Disabled because conditional branches clobber temporary vars. */
5830 gen_helper_mac_set_flags(cpu_env
, tcg_const_i32(acc
));
5834 rw
= (insn
& 0x40) ? AREG(insn
, 9) : DREG(insn
, 9);
5835 tcg_gen_mov_i32(rw
, loadval
);
5837 * FIXME: Should address writeback happen with the masked or
5840 switch ((insn
>> 3) & 7) {
5841 case 3: /* Post-increment. */
5842 tcg_gen_addi_i32(AREG(insn
, 0), addr
, 4);
5844 case 4: /* Pre-decrement. */
5845 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
5847 tcg_temp_free(loadval
);
5851 DISAS_INSN(from_mac
)
5857 rx
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5858 accnum
= (insn
>> 9) & 3;
5859 acc
= MACREG(accnum
);
5860 if (s
->env
->macsr
& MACSR_FI
) {
5861 gen_helper_get_macf(rx
, cpu_env
, acc
);
5862 } else if ((s
->env
->macsr
& MACSR_OMC
) == 0) {
5863 tcg_gen_extrl_i64_i32(rx
, acc
);
5864 } else if (s
->env
->macsr
& MACSR_SU
) {
5865 gen_helper_get_macs(rx
, acc
);
5867 gen_helper_get_macu(rx
, acc
);
5870 tcg_gen_movi_i64(acc
, 0);
5871 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
, ~(MACSR_PAV0
<< accnum
));
5875 DISAS_INSN(move_mac
)
5877 /* FIXME: This can be done without a helper. */
5881 dest
= tcg_const_i32((insn
>> 9) & 3);
5882 gen_helper_mac_move(cpu_env
, dest
, tcg_const_i32(src
));
5883 gen_mac_clear_flags();
5884 gen_helper_mac_set_flags(cpu_env
, dest
);
5887 DISAS_INSN(from_macsr
)
5891 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5892 tcg_gen_mov_i32(reg
, QREG_MACSR
);
5895 DISAS_INSN(from_mask
)
5898 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5899 tcg_gen_mov_i32(reg
, QREG_MAC_MASK
);
5902 DISAS_INSN(from_mext
)
5906 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5907 acc
= tcg_const_i32((insn
& 0x400) ? 2 : 0);
5908 if (s
->env
->macsr
& MACSR_FI
)
5909 gen_helper_get_mac_extf(reg
, cpu_env
, acc
);
5911 gen_helper_get_mac_exti(reg
, cpu_env
, acc
);
5914 DISAS_INSN(macsr_to_ccr
)
5916 TCGv tmp
= tcg_temp_new();
5918 /* Note that X and C are always cleared. */
5919 tcg_gen_andi_i32(tmp
, QREG_MACSR
, CCF_N
| CCF_Z
| CCF_V
);
5920 gen_helper_set_ccr(cpu_env
, tmp
);
5922 set_cc_op(s
, CC_OP_FLAGS
);
5930 accnum
= (insn
>> 9) & 3;
5931 acc
= MACREG(accnum
);
5932 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
5933 if (s
->env
->macsr
& MACSR_FI
) {
5934 tcg_gen_ext_i32_i64(acc
, val
);
5935 tcg_gen_shli_i64(acc
, acc
, 8);
5936 } else if (s
->env
->macsr
& MACSR_SU
) {
5937 tcg_gen_ext_i32_i64(acc
, val
);
5939 tcg_gen_extu_i32_i64(acc
, val
);
5941 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
, ~(MACSR_PAV0
<< accnum
));
5942 gen_mac_clear_flags();
5943 gen_helper_mac_set_flags(cpu_env
, tcg_const_i32(accnum
));
5946 DISAS_INSN(to_macsr
)
5949 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
5950 gen_helper_set_macsr(cpu_env
, val
);
5957 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
5958 tcg_gen_ori_i32(QREG_MAC_MASK
, val
, 0xffff0000);
5965 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
5966 acc
= tcg_const_i32((insn
& 0x400) ? 2 : 0);
5967 if (s
->env
->macsr
& MACSR_FI
)
5968 gen_helper_set_mac_extf(cpu_env
, val
, acc
);
5969 else if (s
->env
->macsr
& MACSR_SU
)
5970 gen_helper_set_mac_exts(cpu_env
, val
, acc
);
5972 gen_helper_set_mac_extu(cpu_env
, val
, acc
);
5975 static disas_proc opcode_table
[65536];
5978 register_opcode (disas_proc proc
, uint16_t opcode
, uint16_t mask
)
5984 /* Sanity check. All set bits must be included in the mask. */
5985 if (opcode
& ~mask
) {
5987 "qemu internal error: bogus opcode definition %04x/%04x\n",
5992 * This could probably be cleverer. For now just optimize the case where
5993 * the top bits are known.
5995 /* Find the first zero bit in the mask. */
5997 while ((i
& mask
) != 0)
5999 /* Iterate over all combinations of this and lower bits. */
6004 from
= opcode
& ~(i
- 1);
6006 for (i
= from
; i
< to
; i
++) {
6007 if ((i
& mask
) == opcode
)
6008 opcode_table
[i
] = proc
;
6013 * Register m68k opcode handlers. Order is important.
6014 * Later insn override earlier ones.
6016 void register_m68k_insns (CPUM68KState
*env
)
6019 * Build the opcode table only once to avoid
6020 * multithreading issues.
6022 if (opcode_table
[0] != NULL
) {
6027 * use BASE() for instruction available
6028 * for CF_ISA_A and M68000.
6030 #define BASE(name, opcode, mask) \
6031 register_opcode(disas_##name, 0x##opcode, 0x##mask)
6032 #define INSN(name, opcode, mask, feature) do { \
6033 if (m68k_feature(env, M68K_FEATURE_##feature)) \
6034 BASE(name, opcode, mask); \
6036 BASE(undef
, 0000, 0000);
6037 INSN(arith_im
, 0080, fff8
, CF_ISA_A
);
6038 INSN(arith_im
, 0000, ff00
, M68K
);
6039 INSN(chk2
, 00c0
, f9c0
, CHK2
);
6040 INSN(bitrev
, 00c0
, fff8
, CF_ISA_APLUSC
);
6041 BASE(bitop_reg
, 0100, f1c0
);
6042 BASE(bitop_reg
, 0140, f1c0
);
6043 BASE(bitop_reg
, 0180, f1c0
);
6044 BASE(bitop_reg
, 01c0
, f1c0
);
6045 INSN(movep
, 0108, f138
, MOVEP
);
6046 INSN(arith_im
, 0280, fff8
, CF_ISA_A
);
6047 INSN(arith_im
, 0200, ff00
, M68K
);
6048 INSN(undef
, 02c0
, ffc0
, M68K
);
6049 INSN(byterev
, 02c0
, fff8
, CF_ISA_APLUSC
);
6050 INSN(arith_im
, 0480, fff8
, CF_ISA_A
);
6051 INSN(arith_im
, 0400, ff00
, M68K
);
6052 INSN(undef
, 04c0
, ffc0
, M68K
);
6053 INSN(arith_im
, 0600, ff00
, M68K
);
6054 INSN(undef
, 06c0
, ffc0
, M68K
);
6055 INSN(ff1
, 04c0
, fff8
, CF_ISA_APLUSC
);
6056 INSN(arith_im
, 0680, fff8
, CF_ISA_A
);
6057 INSN(arith_im
, 0c00
, ff38
, CF_ISA_A
);
6058 INSN(arith_im
, 0c00
, ff00
, M68K
);
6059 BASE(bitop_im
, 0800, ffc0
);
6060 BASE(bitop_im
, 0840, ffc0
);
6061 BASE(bitop_im
, 0880, ffc0
);
6062 BASE(bitop_im
, 08c0
, ffc0
);
6063 INSN(arith_im
, 0a80
, fff8
, CF_ISA_A
);
6064 INSN(arith_im
, 0a00
, ff00
, M68K
);
6065 #if defined(CONFIG_SOFTMMU)
6066 INSN(moves
, 0e00
, ff00
, M68K
);
6068 INSN(cas
, 0ac0
, ffc0
, CAS
);
6069 INSN(cas
, 0cc0
, ffc0
, CAS
);
6070 INSN(cas
, 0ec0
, ffc0
, CAS
);
6071 INSN(cas2w
, 0cfc
, ffff
, CAS
);
6072 INSN(cas2l
, 0efc
, ffff
, CAS
);
6073 BASE(move
, 1000, f000
);
6074 BASE(move
, 2000, f000
);
6075 BASE(move
, 3000, f000
);
6076 INSN(chk
, 4000, f040
, M68K
);
6077 INSN(strldsr
, 40e7
, ffff
, CF_ISA_APLUSC
);
6078 INSN(negx
, 4080, fff8
, CF_ISA_A
);
6079 INSN(negx
, 4000, ff00
, M68K
);
6080 INSN(undef
, 40c0
, ffc0
, M68K
);
6081 INSN(move_from_sr
, 40c0
, fff8
, CF_ISA_A
);
6082 INSN(move_from_sr
, 40c0
, ffc0
, M68K
);
6083 BASE(lea
, 41c0
, f1c0
);
6084 BASE(clr
, 4200, ff00
);
6085 BASE(undef
, 42c0
, ffc0
);
6086 INSN(move_from_ccr
, 42c0
, fff8
, CF_ISA_A
);
6087 INSN(move_from_ccr
, 42c0
, ffc0
, M68K
);
6088 INSN(neg
, 4480, fff8
, CF_ISA_A
);
6089 INSN(neg
, 4400, ff00
, M68K
);
6090 INSN(undef
, 44c0
, ffc0
, M68K
);
6091 BASE(move_to_ccr
, 44c0
, ffc0
);
6092 INSN(not, 4680, fff8
, CF_ISA_A
);
6093 INSN(not, 4600, ff00
, M68K
);
6094 #if defined(CONFIG_SOFTMMU)
6095 BASE(move_to_sr
, 46c0
, ffc0
);
6097 INSN(nbcd
, 4800, ffc0
, M68K
);
6098 INSN(linkl
, 4808, fff8
, M68K
);
6099 BASE(pea
, 4840, ffc0
);
6100 BASE(swap
, 4840, fff8
);
6101 INSN(bkpt
, 4848, fff8
, BKPT
);
6102 INSN(movem
, 48d0
, fbf8
, CF_ISA_A
);
6103 INSN(movem
, 48e8
, fbf8
, CF_ISA_A
);
6104 INSN(movem
, 4880, fb80
, M68K
);
6105 BASE(ext
, 4880, fff8
);
6106 BASE(ext
, 48c0
, fff8
);
6107 BASE(ext
, 49c0
, fff8
);
6108 BASE(tst
, 4a00
, ff00
);
6109 INSN(tas
, 4ac0
, ffc0
, CF_ISA_B
);
6110 INSN(tas
, 4ac0
, ffc0
, M68K
);
6111 #if defined(CONFIG_SOFTMMU)
6112 INSN(halt
, 4ac8
, ffff
, CF_ISA_A
);
6113 INSN(halt
, 4ac8
, ffff
, M68K
);
6115 INSN(pulse
, 4acc
, ffff
, CF_ISA_A
);
6116 BASE(illegal
, 4afc
, ffff
);
6117 INSN(mull
, 4c00
, ffc0
, CF_ISA_A
);
6118 INSN(mull
, 4c00
, ffc0
, LONG_MULDIV
);
6119 INSN(divl
, 4c40
, ffc0
, CF_ISA_A
);
6120 INSN(divl
, 4c40
, ffc0
, LONG_MULDIV
);
6121 INSN(sats
, 4c80
, fff8
, CF_ISA_B
);
6122 BASE(trap
, 4e40
, fff0
);
6123 BASE(link
, 4e50
, fff8
);
6124 BASE(unlk
, 4e58
, fff8
);
6125 #if defined(CONFIG_SOFTMMU)
6126 INSN(move_to_usp
, 4e60
, fff8
, USP
);
6127 INSN(move_from_usp
, 4e68
, fff8
, USP
);
6128 INSN(reset
, 4e70
, ffff
, M68K
);
6129 BASE(stop
, 4e72
, ffff
);
6130 BASE(rte
, 4e73
, ffff
);
6131 INSN(cf_movec
, 4e7b
, ffff
, CF_ISA_A
);
6132 INSN(m68k_movec
, 4e7a
, fffe
, MOVEC
);
6134 BASE(nop
, 4e71
, ffff
);
6135 INSN(rtd
, 4e74
, ffff
, RTD
);
6136 BASE(rts
, 4e75
, ffff
);
6137 INSN(trapv
, 4e76
, ffff
, M68K
);
6138 INSN(rtr
, 4e77
, ffff
, M68K
);
6139 BASE(jump
, 4e80
, ffc0
);
6140 BASE(jump
, 4ec0
, ffc0
);
6141 INSN(addsubq
, 5000, f080
, M68K
);
6142 BASE(addsubq
, 5080, f0c0
);
6143 INSN(scc
, 50c0
, f0f8
, CF_ISA_A
); /* Scc.B Dx */
6144 INSN(scc
, 50c0
, f0c0
, M68K
); /* Scc.B <EA> */
6145 INSN(dbcc
, 50c8
, f0f8
, M68K
);
6146 INSN(trapcc
, 50fa
, f0fe
, TRAPCC
); /* opmode 010, 011 */
6147 INSN(trapcc
, 50fc
, f0ff
, TRAPCC
); /* opmode 100 */
6148 INSN(trapcc
, 51fa
, fffe
, CF_ISA_A
); /* TPF (trapf) opmode 010, 011 */
6149 INSN(trapcc
, 51fc
, ffff
, CF_ISA_A
); /* TPF (trapf) opmode 100 */
6151 /* Branch instructions. */
6152 BASE(branch
, 6000, f000
);
6153 /* Disable long branch instructions, then add back the ones we want. */
6154 BASE(undef
, 60ff
, f0ff
); /* All long branches. */
6155 INSN(branch
, 60ff
, f0ff
, CF_ISA_B
);
6156 INSN(undef
, 60ff
, ffff
, CF_ISA_B
); /* bra.l */
6157 INSN(branch
, 60ff
, ffff
, BRAL
);
6158 INSN(branch
, 60ff
, f0ff
, BCCL
);
6160 BASE(moveq
, 7000, f100
);
6161 INSN(mvzs
, 7100, f100
, CF_ISA_B
);
6162 BASE(or, 8000, f000
);
6163 BASE(divw
, 80c0
, f0c0
);
6164 INSN(sbcd_reg
, 8100, f1f8
, M68K
);
6165 INSN(sbcd_mem
, 8108, f1f8
, M68K
);
6166 BASE(addsub
, 9000, f000
);
6167 INSN(undef
, 90c0
, f0c0
, CF_ISA_A
);
6168 INSN(subx_reg
, 9180, f1f8
, CF_ISA_A
);
6169 INSN(subx_reg
, 9100, f138
, M68K
);
6170 INSN(subx_mem
, 9108, f138
, M68K
);
6171 INSN(suba
, 91c0
, f1c0
, CF_ISA_A
);
6172 INSN(suba
, 90c0
, f0c0
, M68K
);
6174 BASE(undef_mac
, a000
, f000
);
6175 INSN(mac
, a000
, f100
, CF_EMAC
);
6176 INSN(from_mac
, a180
, f9b0
, CF_EMAC
);
6177 INSN(move_mac
, a110
, f9fc
, CF_EMAC
);
6178 INSN(from_macsr
,a980
, f9f0
, CF_EMAC
);
6179 INSN(from_mask
, ad80
, fff0
, CF_EMAC
);
6180 INSN(from_mext
, ab80
, fbf0
, CF_EMAC
);
6181 INSN(macsr_to_ccr
, a9c0
, ffff
, CF_EMAC
);
6182 INSN(to_mac
, a100
, f9c0
, CF_EMAC
);
6183 INSN(to_macsr
, a900
, ffc0
, CF_EMAC
);
6184 INSN(to_mext
, ab00
, fbc0
, CF_EMAC
);
6185 INSN(to_mask
, ad00
, ffc0
, CF_EMAC
);
6187 INSN(mov3q
, a140
, f1c0
, CF_ISA_B
);
6188 INSN(cmp
, b000
, f1c0
, CF_ISA_B
); /* cmp.b */
6189 INSN(cmp
, b040
, f1c0
, CF_ISA_B
); /* cmp.w */
6190 INSN(cmpa
, b0c0
, f1c0
, CF_ISA_B
); /* cmpa.w */
6191 INSN(cmp
, b080
, f1c0
, CF_ISA_A
);
6192 INSN(cmpa
, b1c0
, f1c0
, CF_ISA_A
);
6193 INSN(cmp
, b000
, f100
, M68K
);
6194 INSN(eor
, b100
, f100
, M68K
);
6195 INSN(cmpm
, b108
, f138
, M68K
);
6196 INSN(cmpa
, b0c0
, f0c0
, M68K
);
6197 INSN(eor
, b180
, f1c0
, CF_ISA_A
);
6198 BASE(and, c000
, f000
);
6199 INSN(exg_dd
, c140
, f1f8
, M68K
);
6200 INSN(exg_aa
, c148
, f1f8
, M68K
);
6201 INSN(exg_da
, c188
, f1f8
, M68K
);
6202 BASE(mulw
, c0c0
, f0c0
);
6203 INSN(abcd_reg
, c100
, f1f8
, M68K
);
6204 INSN(abcd_mem
, c108
, f1f8
, M68K
);
6205 BASE(addsub
, d000
, f000
);
6206 INSN(undef
, d0c0
, f0c0
, CF_ISA_A
);
6207 INSN(addx_reg
, d180
, f1f8
, CF_ISA_A
);
6208 INSN(addx_reg
, d100
, f138
, M68K
);
6209 INSN(addx_mem
, d108
, f138
, M68K
);
6210 INSN(adda
, d1c0
, f1c0
, CF_ISA_A
);
6211 INSN(adda
, d0c0
, f0c0
, M68K
);
6212 INSN(shift_im
, e080
, f0f0
, CF_ISA_A
);
6213 INSN(shift_reg
, e0a0
, f0f0
, CF_ISA_A
);
6214 INSN(shift8_im
, e000
, f0f0
, M68K
);
6215 INSN(shift16_im
, e040
, f0f0
, M68K
);
6216 INSN(shift_im
, e080
, f0f0
, M68K
);
6217 INSN(shift8_reg
, e020
, f0f0
, M68K
);
6218 INSN(shift16_reg
, e060
, f0f0
, M68K
);
6219 INSN(shift_reg
, e0a0
, f0f0
, M68K
);
6220 INSN(shift_mem
, e0c0
, fcc0
, M68K
);
6221 INSN(rotate_im
, e090
, f0f0
, M68K
);
6222 INSN(rotate8_im
, e010
, f0f0
, M68K
);
6223 INSN(rotate16_im
, e050
, f0f0
, M68K
);
6224 INSN(rotate_reg
, e0b0
, f0f0
, M68K
);
6225 INSN(rotate8_reg
, e030
, f0f0
, M68K
);
6226 INSN(rotate16_reg
, e070
, f0f0
, M68K
);
6227 INSN(rotate_mem
, e4c0
, fcc0
, M68K
);
6228 INSN(bfext_mem
, e9c0
, fdc0
, BITFIELD
); /* bfextu & bfexts */
6229 INSN(bfext_reg
, e9c0
, fdf8
, BITFIELD
);
6230 INSN(bfins_mem
, efc0
, ffc0
, BITFIELD
);
6231 INSN(bfins_reg
, efc0
, fff8
, BITFIELD
);
6232 INSN(bfop_mem
, eac0
, ffc0
, BITFIELD
); /* bfchg */
6233 INSN(bfop_reg
, eac0
, fff8
, BITFIELD
); /* bfchg */
6234 INSN(bfop_mem
, ecc0
, ffc0
, BITFIELD
); /* bfclr */
6235 INSN(bfop_reg
, ecc0
, fff8
, BITFIELD
); /* bfclr */
6236 INSN(bfop_mem
, edc0
, ffc0
, BITFIELD
); /* bfffo */
6237 INSN(bfop_reg
, edc0
, fff8
, BITFIELD
); /* bfffo */
6238 INSN(bfop_mem
, eec0
, ffc0
, BITFIELD
); /* bfset */
6239 INSN(bfop_reg
, eec0
, fff8
, BITFIELD
); /* bfset */
6240 INSN(bfop_mem
, e8c0
, ffc0
, BITFIELD
); /* bftst */
6241 INSN(bfop_reg
, e8c0
, fff8
, BITFIELD
); /* bftst */
6242 BASE(undef_fpu
, f000
, f000
);
6243 INSN(fpu
, f200
, ffc0
, CF_FPU
);
6244 INSN(fbcc
, f280
, ffc0
, CF_FPU
);
6245 INSN(fpu
, f200
, ffc0
, FPU
);
6246 INSN(fscc
, f240
, ffc0
, FPU
);
6247 INSN(ftrapcc
, f27a
, fffe
, FPU
); /* opmode 010, 011 */
6248 INSN(ftrapcc
, f27c
, ffff
, FPU
); /* opmode 100 */
6249 INSN(fbcc
, f280
, ff80
, FPU
);
6250 #if defined(CONFIG_SOFTMMU)
6251 INSN(frestore
, f340
, ffc0
, CF_FPU
);
6252 INSN(fsave
, f300
, ffc0
, CF_FPU
);
6253 INSN(frestore
, f340
, ffc0
, FPU
);
6254 INSN(fsave
, f300
, ffc0
, FPU
);
6255 INSN(intouch
, f340
, ffc0
, CF_ISA_A
);
6256 INSN(cpushl
, f428
, ff38
, CF_ISA_A
);
6257 INSN(cpush
, f420
, ff20
, M68040
);
6258 INSN(cinv
, f400
, ff20
, M68040
);
6259 INSN(pflush
, f500
, ffe0
, M68040
);
6260 INSN(ptest
, f548
, ffd8
, M68040
);
6261 INSN(wddata
, fb00
, ff00
, CF_ISA_A
);
6262 INSN(wdebug
, fbc0
, ffc0
, CF_ISA_A
);
6264 INSN(move16_mem
, f600
, ffe0
, M68040
);
6265 INSN(move16_reg
, f620
, fff8
, M68040
);
6269 static void m68k_tr_init_disas_context(DisasContextBase
*dcbase
, CPUState
*cpu
)
6271 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
6272 CPUM68KState
*env
= cpu
->env_ptr
;
6275 dc
->pc
= dc
->base
.pc_first
;
6276 /* This value will always be filled in properly before m68k_tr_tb_stop. */
6277 dc
->pc_prev
= 0xdeadbeef;
6278 dc
->cc_op
= CC_OP_DYNAMIC
;
6279 dc
->cc_op_synced
= 1;
6281 dc
->writeback_mask
= 0;
6282 init_release_array(dc
);
6284 dc
->ss_active
= (M68K_SR_TRACE(env
->sr
) == M68K_SR_TRACE_ANY_INS
);
6285 /* If architectural single step active, limit to 1 */
6286 if (dc
->ss_active
) {
6287 dc
->base
.max_insns
= 1;
6291 static void m68k_tr_tb_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
6295 static void m68k_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
6297 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
6298 tcg_gen_insn_start(dc
->base
.pc_next
, dc
->cc_op
);
6301 static void m68k_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
6303 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
6304 CPUM68KState
*env
= cpu
->env_ptr
;
6305 uint16_t insn
= read_im16(env
, dc
);
6307 opcode_table
[insn
](env
, dc
, insn
);
6311 dc
->pc_prev
= dc
->base
.pc_next
;
6312 dc
->base
.pc_next
= dc
->pc
;
6314 if (dc
->base
.is_jmp
== DISAS_NEXT
) {
6316 * Stop translation when the next insn might touch a new page.
6317 * This ensures that prefetch aborts at the right place.
6319 * We cannot determine the size of the next insn without
6320 * completely decoding it. However, the maximum insn size
6321 * is 32 bytes, so end if we do not have that much remaining.
6322 * This may produce several small TBs at the end of each page,
6323 * but they will all be linked with goto_tb.
6325 * ??? ColdFire maximum is 4 bytes; MC68000's maximum is also
6326 * smaller than MC68020's.
6328 target_ulong start_page_offset
6329 = dc
->pc
- (dc
->base
.pc_first
& TARGET_PAGE_MASK
);
6331 if (start_page_offset
>= TARGET_PAGE_SIZE
- 32) {
6332 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
6337 static void m68k_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
6339 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
6341 switch (dc
->base
.is_jmp
) {
6342 case DISAS_NORETURN
:
6344 case DISAS_TOO_MANY
:
6346 gen_jmp_tb(dc
, 0, dc
->pc
, dc
->pc_prev
);
6349 /* We updated CC_OP and PC in gen_jmp/gen_jmp_im. */
6350 if (dc
->ss_active
) {
6351 gen_raise_exception_format2(dc
, EXCP_TRACE
, dc
->pc_prev
);
6353 tcg_gen_lookup_and_goto_ptr();
6358 * We updated CC_OP and PC in gen_exit_tb, but also modified
6359 * other state that may require returning to the main loop.
6361 if (dc
->ss_active
) {
6362 gen_raise_exception_format2(dc
, EXCP_TRACE
, dc
->pc_prev
);
6364 tcg_gen_exit_tb(NULL
, 0);
6368 g_assert_not_reached();
6372 static void m68k_tr_disas_log(const DisasContextBase
*dcbase
,
6373 CPUState
*cpu
, FILE *logfile
)
6375 fprintf(logfile
, "IN: %s\n", lookup_symbol(dcbase
->pc_first
));
6376 target_disas(logfile
, cpu
, dcbase
->pc_first
, dcbase
->tb
->size
);
6379 static const TranslatorOps m68k_tr_ops
= {
6380 .init_disas_context
= m68k_tr_init_disas_context
,
6381 .tb_start
= m68k_tr_tb_start
,
6382 .insn_start
= m68k_tr_insn_start
,
6383 .translate_insn
= m68k_tr_translate_insn
,
6384 .tb_stop
= m68k_tr_tb_stop
,
6385 .disas_log
= m68k_tr_disas_log
,
6388 void gen_intermediate_code(CPUState
*cpu
, TranslationBlock
*tb
, int max_insns
,
6389 target_ulong pc
, void *host_pc
)
6392 translator_loop(cpu
, tb
, max_insns
, pc
, host_pc
, &m68k_tr_ops
, &dc
.base
);
6395 static double floatx80_to_double(CPUM68KState
*env
, uint16_t high
, uint64_t low
)
6397 floatx80 a
= { .high
= high
, .low
= low
};
6403 u
.f64
= floatx80_to_float64(a
, &env
->fp_status
);
6407 void m68k_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
6409 M68kCPU
*cpu
= M68K_CPU(cs
);
6410 CPUM68KState
*env
= &cpu
->env
;
6413 for (i
= 0; i
< 8; i
++) {
6414 qemu_fprintf(f
, "D%d = %08x A%d = %08x "
6415 "F%d = %04x %016"PRIx64
" (%12g)\n",
6416 i
, env
->dregs
[i
], i
, env
->aregs
[i
],
6417 i
, env
->fregs
[i
].l
.upper
, env
->fregs
[i
].l
.lower
,
6418 floatx80_to_double(env
, env
->fregs
[i
].l
.upper
,
6419 env
->fregs
[i
].l
.lower
));
6421 qemu_fprintf(f
, "PC = %08x ", env
->pc
);
6422 sr
= env
->sr
| cpu_m68k_get_ccr(env
);
6423 qemu_fprintf(f
, "SR = %04x T:%x I:%x %c%c %c%c%c%c%c\n",
6424 sr
, (sr
& SR_T
) >> SR_T_SHIFT
, (sr
& SR_I
) >> SR_I_SHIFT
,
6425 (sr
& SR_S
) ? 'S' : 'U', (sr
& SR_M
) ? '%' : 'I',
6426 (sr
& CCF_X
) ? 'X' : '-', (sr
& CCF_N
) ? 'N' : '-',
6427 (sr
& CCF_Z
) ? 'Z' : '-', (sr
& CCF_V
) ? 'V' : '-',
6428 (sr
& CCF_C
) ? 'C' : '-');
6429 qemu_fprintf(f
, "FPSR = %08x %c%c%c%c ", env
->fpsr
,
6430 (env
->fpsr
& FPSR_CC_A
) ? 'A' : '-',
6431 (env
->fpsr
& FPSR_CC_I
) ? 'I' : '-',
6432 (env
->fpsr
& FPSR_CC_Z
) ? 'Z' : '-',
6433 (env
->fpsr
& FPSR_CC_N
) ? 'N' : '-');
6434 qemu_fprintf(f
, "\n "
6435 "FPCR = %04x ", env
->fpcr
);
6436 switch (env
->fpcr
& FPCR_PREC_MASK
) {
6438 qemu_fprintf(f
, "X ");
6441 qemu_fprintf(f
, "S ");
6444 qemu_fprintf(f
, "D ");
6447 switch (env
->fpcr
& FPCR_RND_MASK
) {
6449 qemu_fprintf(f
, "RN ");
6452 qemu_fprintf(f
, "RZ ");
6455 qemu_fprintf(f
, "RM ");
6458 qemu_fprintf(f
, "RP ");
6461 qemu_fprintf(f
, "\n");
6462 #ifdef CONFIG_SOFTMMU
6463 qemu_fprintf(f
, "%sA7(MSP) = %08x %sA7(USP) = %08x %sA7(ISP) = %08x\n",
6464 env
->current_sp
== M68K_SSP
? "->" : " ", env
->sp
[M68K_SSP
],
6465 env
->current_sp
== M68K_USP
? "->" : " ", env
->sp
[M68K_USP
],
6466 env
->current_sp
== M68K_ISP
? "->" : " ", env
->sp
[M68K_ISP
]);
6467 qemu_fprintf(f
, "VBR = 0x%08x\n", env
->vbr
);
6468 qemu_fprintf(f
, "SFC = %x DFC %x\n", env
->sfc
, env
->dfc
);
6469 qemu_fprintf(f
, "SSW %08x TCR %08x URP %08x SRP %08x\n",
6470 env
->mmu
.ssw
, env
->mmu
.tcr
, env
->mmu
.urp
, env
->mmu
.srp
);
6471 qemu_fprintf(f
, "DTTR0/1: %08x/%08x ITTR0/1: %08x/%08x\n",
6472 env
->mmu
.ttr
[M68K_DTTR0
], env
->mmu
.ttr
[M68K_DTTR1
],
6473 env
->mmu
.ttr
[M68K_ITTR0
], env
->mmu
.ttr
[M68K_ITTR1
]);
6474 qemu_fprintf(f
, "MMUSR %08x, fault at %08x\n",
6475 env
->mmu
.mmusr
, env
->mmu
.ar
);
6479 void restore_state_to_opc(CPUM68KState
*env
, TranslationBlock
*tb
,
6482 int cc_op
= data
[1];
6484 if (cc_op
!= CC_OP_DYNAMIC
) {