target-mips/helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <stdarg.h>
  20 #include <stdlib.h>
  21 #include <stdio.h>
  22 #include <string.h>
  23 #include <inttypes.h>
  24 #include <signal.h>
  25
  26 #include "cpu.h"
  27 #include "sysemu/kvm.h"
  28 #include "exec/cpu_ldst.h"
  29
  30 enum {
  31     TLBRET_XI = -6,
  32     TLBRET_RI = -5,
  33     TLBRET_DIRTY = -4,
  34     TLBRET_INVALID = -3,
  35     TLBRET_NOMATCH = -2,
  36     TLBRET_BADADDR = -1,
  37     TLBRET_MATCH = 0
  38 };
  39
  40 #if !defined(CONFIG_USER_ONLY)
  41
  42 /* no MMU emulation */
  43 int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
  44                         target_ulong address, int rw, int access_type)
  45 {
  46     *physical = address;
  47     *prot = PAGE_READ | PAGE_WRITE;
  48     return TLBRET_MATCH;
  49 }
  50
  51 /* fixed mapping MMU emulation */
  52 int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
  53                            target_ulong address, int rw, int access_type)
  54 {
  55     if (address <= (int32_t)0x7FFFFFFFUL) {
  56         if (!(env->CP0_Status & (1 << CP0St_ERL)))
  57             *physical = address + 0x40000000UL;
  58         else
  59             *physical = address;
  60     } else if (address <= (int32_t)0xBFFFFFFFUL)
  61         *physical = address & 0x1FFFFFFF;
  62     else
  63         *physical = address;
  64
  65     *prot = PAGE_READ | PAGE_WRITE;
  66     return TLBRET_MATCH;
  67 }
  68
  69 /* MIPS32/MIPS64 R4000-style MMU emulation */
  70 int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
  71                      target_ulong address, int rw, int access_type)
  72 {
  73     uint8_t ASID = env->CP0_EntryHi & 0xFF;
  74     int i;
  75
  76     for (i = 0; i < env->tlb->tlb_in_use; i++) {
  77         r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];
  78         /* 1k pages are not supported. */
  79         target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
  80         target_ulong tag = address & ~mask;
  81         target_ulong VPN = tlb->VPN & ~mask;
  82 #if defined(TARGET_MIPS64)
  83         tag &= env->SEGMask;
  84 #endif
  85
  86         /* Check ASID, virtual page number & size */
  87         if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag && !tlb->EHINV) {
  88             /* TLB match */
  89             int n = !!(address & mask & ~(mask >> 1));
  90             /* Check access rights */
  91             if (!(n ? tlb->V1 : tlb->V0)) {
  92                 return TLBRET_INVALID;
  93             }
  94             if (rw == MMU_INST_FETCH && (n ? tlb->XI1 : tlb->XI0)) {
  95                 return TLBRET_XI;
  96             }
  97             if (rw == MMU_DATA_LOAD && (n ? tlb->RI1 : tlb->RI0)) {
  98                 return TLBRET_RI;
  99             }
 100             if (rw != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) {
 101                 *physical = tlb->PFN[n] | (address & (mask >> 1));
 102                 *prot = PAGE_READ;
 103                 if (n ? tlb->D1 : tlb->D0)
 104                     *prot |= PAGE_WRITE;
 105                 return TLBRET_MATCH;
 106             }
 107             return TLBRET_DIRTY;
 108         }
 109     }
 110     return TLBRET_NOMATCH;
 111 }
 112
 113 static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
 114                                 int *prot, target_ulong real_address,
 115                                 int rw, int access_type)
 116 {
 117     /* User mode can only access useg/xuseg */
 118     int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
 119     int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM;
 120     int kernel_mode = !user_mode && !supervisor_mode;
 121 #if defined(TARGET_MIPS64)
 122     int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 123     int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 124     int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 125 #endif
 126     int ret = TLBRET_MATCH;
 127     /* effective address (modified for KVM T&E kernel segments) */
 128     target_ulong address = real_address;
 129
 130 #if 0
 131     qemu_log("user mode %d h %08x\n", user_mode, env->hflags);
 132 #endif
 133
 134 #define USEG_LIMIT      0x7FFFFFFFUL
 135 #define KSEG0_BASE      0x80000000UL
 136 #define KSEG1_BASE      0xA0000000UL
 137 #define KSEG2_BASE      0xC0000000UL
 138 #define KSEG3_BASE      0xE0000000UL
 139
 140 #define KVM_KSEG0_BASE  0x40000000UL
 141 #define KVM_KSEG2_BASE  0x60000000UL
 142
 143     if (kvm_enabled()) {
 144         /* KVM T&E adds guest kernel segments in useg */
 145         if (real_address >= KVM_KSEG0_BASE) {
 146             if (real_address < KVM_KSEG2_BASE) {
 147                 /* kseg0 */
 148                 address += KSEG0_BASE - KVM_KSEG0_BASE;
 149             } else if (real_address <= USEG_LIMIT) {
 150                 /* kseg2/3 */
 151                 address += KSEG2_BASE - KVM_KSEG2_BASE;
 152             }
 153         }
 154     }
 155
 156     if (address <= USEG_LIMIT) {
 157         /* useg */
 158         if (env->CP0_Status & (1 << CP0St_ERL)) {
 159             *physical = address & 0xFFFFFFFF;
 160             *prot = PAGE_READ | PAGE_WRITE;
 161         } else {
 162             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 163         }
 164 #if defined(TARGET_MIPS64)
 165     } else if (address < 0x4000000000000000ULL) {
 166         /* xuseg */
 167         if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
 168             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 169         } else {
 170             ret = TLBRET_BADADDR;
 171         }
 172     } else if (address < 0x8000000000000000ULL) {
 173         /* xsseg */
 174         if ((supervisor_mode || kernel_mode) &&
 175             SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
 176             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 177         } else {
 178             ret = TLBRET_BADADDR;
 179         }
 180     } else if (address < 0xC000000000000000ULL) {
 181         /* xkphys */
 182         if (kernel_mode && KX &&
 183             (address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) {
 184             *physical = address & env->PAMask;
 185             *prot = PAGE_READ | PAGE_WRITE;
 186         } else {
 187             ret = TLBRET_BADADDR;
 188         }
 189     } else if (address < 0xFFFFFFFF80000000ULL) {
 190         /* xkseg */
 191         if (kernel_mode && KX &&
 192             address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
 193             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 194         } else {
 195             ret = TLBRET_BADADDR;
 196         }
 197 #endif
 198     } else if (address < (int32_t)KSEG1_BASE) {
 199         /* kseg0 */
 200         if (kernel_mode) {
 201             *physical = address - (int32_t)KSEG0_BASE;
 202             *prot = PAGE_READ | PAGE_WRITE;
 203         } else {
 204             ret = TLBRET_BADADDR;
 205         }
 206     } else if (address < (int32_t)KSEG2_BASE) {
 207         /* kseg1 */
 208         if (kernel_mode) {
 209             *physical = address - (int32_t)KSEG1_BASE;
 210             *prot = PAGE_READ | PAGE_WRITE;
 211         } else {
 212             ret = TLBRET_BADADDR;
 213         }
 214     } else if (address < (int32_t)KSEG3_BASE) {
 215         /* sseg (kseg2) */
 216         if (supervisor_mode || kernel_mode) {
 217             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 218         } else {
 219             ret = TLBRET_BADADDR;
 220         }
 221     } else {
 222         /* kseg3 */
 223         /* XXX: debug segment is not emulated */
 224         if (kernel_mode) {
 225             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 226         } else {
 227             ret = TLBRET_BADADDR;
 228         }
 229     }
 230 #if 0
 231     qemu_log(TARGET_FMT_lx " %d %d => %" HWADDR_PRIx " %d (%d)\n",
 232             address, rw, access_type, *physical, *prot, ret);
 233 #endif
 234
 235     return ret;
 236 }
 237 #endif
 238
 239 static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
 240                                 int rw, int tlb_error)
 241 {
 242     CPUState *cs = CPU(mips_env_get_cpu(env));
 243     int exception = 0, error_code = 0;
 244
 245     if (rw == MMU_INST_FETCH) {
 246         error_code |= EXCP_INST_NOTAVAIL;
 247     }
 248
 249     switch (tlb_error) {
 250     default:
 251     case TLBRET_BADADDR:
 252         /* Reference to kernel address from user mode or supervisor mode */
 253         /* Reference to supervisor address from user mode */
 254         if (rw == MMU_DATA_STORE) {
 255             exception = EXCP_AdES;
 256         } else {
 257             exception = EXCP_AdEL;
 258         }
 259         break;
 260     case TLBRET_NOMATCH:
 261         /* No TLB match for a mapped address */
 262         if (rw == MMU_DATA_STORE) {
 263             exception = EXCP_TLBS;
 264         } else {
 265             exception = EXCP_TLBL;
 266         }
 267         error_code |= EXCP_TLB_NOMATCH;
 268         break;
 269     case TLBRET_INVALID:
 270         /* TLB match with no valid bit */
 271         if (rw == MMU_DATA_STORE) {
 272             exception = EXCP_TLBS;
 273         } else {
 274             exception = EXCP_TLBL;
 275         }
 276         break;
 277     case TLBRET_DIRTY:
 278         /* TLB match but 'D' bit is cleared */
 279         exception = EXCP_LTLBL;
 280         break;
 281     case TLBRET_XI:
 282         /* Execute-Inhibit Exception */
 283         if (env->CP0_PageGrain & (1 << CP0PG_IEC)) {
 284             exception = EXCP_TLBXI;
 285         } else {
 286             exception = EXCP_TLBL;
 287         }
 288         break;
 289     case TLBRET_RI:
 290         /* Read-Inhibit Exception */
 291         if (env->CP0_PageGrain & (1 << CP0PG_IEC)) {
 292             exception = EXCP_TLBRI;
 293         } else {
 294             exception = EXCP_TLBL;
 295         }
 296         break;
 297     }
 298     /* Raise exception */
 299     env->CP0_BadVAddr = address;
 300     env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
 301                        ((address >> 9) & 0x007ffff0);
 302     env->CP0_EntryHi =
 303         (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));
 304 #if defined(TARGET_MIPS64)
 305     env->CP0_EntryHi &= env->SEGMask;
 306     env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |
 307                         ((address & 0xC00000000000ULL) >> (55 - env->SEGBITS)) |
 308                         ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9);
 309 #endif
 310     cs->exception_index = exception;
 311     env->error_code = error_code;
 312 }
 313
 314 #if !defined(CONFIG_USER_ONLY)
 315 hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 316 {
 317     MIPSCPU *cpu = MIPS_CPU(cs);
 318     hwaddr phys_addr;
 319     int prot;
 320
 321     if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0,
 322                              ACCESS_INT) != 0) {
 323         return -1;
 324     }
 325     return phys_addr;
 326 }
 327 #endif
 328
 329 int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
 330                               int mmu_idx)
 331 {
 332     MIPSCPU *cpu = MIPS_CPU(cs);
 333     CPUMIPSState *env = &cpu->env;
 334 #if !defined(CONFIG_USER_ONLY)
 335     hwaddr physical;
 336     int prot;
 337     int access_type;
 338 #endif
 339     int ret = 0;
 340
 341 #if 0
 342     log_cpu_state(cs, 0);
 343 #endif
 344     qemu_log("%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
 345               __func__, env->active_tc.PC, address, rw, mmu_idx);
 346
 347     /* data access */
 348 #if !defined(CONFIG_USER_ONLY)
 349     /* XXX: put correct access by using cpu_restore_state()
 350        correctly */
 351     access_type = ACCESS_INT;
 352     ret = get_physical_address(env, &physical, &prot,
 353                                address, rw, access_type);
 354     qemu_log("%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx
 355              " prot %d\n",
 356              __func__, address, ret, physical, prot);
 357     if (ret == TLBRET_MATCH) {
 358         tlb_set_page(cs, address & TARGET_PAGE_MASK,
 359                      physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
 360                      mmu_idx, TARGET_PAGE_SIZE);
 361         ret = 0;
 362     } else if (ret < 0)
 363 #endif
 364     {
 365         raise_mmu_exception(env, address, rw, ret);
 366         ret = 1;
 367     }
 368
 369     return ret;
 370 }
 371
 372 #if !defined(CONFIG_USER_ONLY)
 373 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw)
 374 {
 375     hwaddr physical;
 376     int prot;
 377     int access_type;
 378     int ret = 0;
 379
 380     /* data access */
 381     access_type = ACCESS_INT;
 382     ret = get_physical_address(env, &physical, &prot,
 383                                address, rw, access_type);
 384     if (ret != TLBRET_MATCH) {
 385         raise_mmu_exception(env, address, rw, ret);
 386         return -1LL;
 387     } else {
 388         return physical;
 389     }
 390 }
 391 #endif
 392
 393 static const char * const excp_names[EXCP_LAST + 1] = {
 394     [EXCP_RESET] = "reset",
 395     [EXCP_SRESET] = "soft reset",
 396     [EXCP_DSS] = "debug single step",
 397     [EXCP_DINT] = "debug interrupt",
 398     [EXCP_NMI] = "non-maskable interrupt",
 399     [EXCP_MCHECK] = "machine check",
 400     [EXCP_EXT_INTERRUPT] = "interrupt",
 401     [EXCP_DFWATCH] = "deferred watchpoint",
 402     [EXCP_DIB] = "debug instruction breakpoint",
 403     [EXCP_IWATCH] = "instruction fetch watchpoint",
 404     [EXCP_AdEL] = "address error load",
 405     [EXCP_AdES] = "address error store",
 406     [EXCP_TLBF] = "TLB refill",
 407     [EXCP_IBE] = "instruction bus error",
 408     [EXCP_DBp] = "debug breakpoint",
 409     [EXCP_SYSCALL] = "syscall",
 410     [EXCP_BREAK] = "break",
 411     [EXCP_CpU] = "coprocessor unusable",
 412     [EXCP_RI] = "reserved instruction",
 413     [EXCP_OVERFLOW] = "arithmetic overflow",
 414     [EXCP_TRAP] = "trap",
 415     [EXCP_FPE] = "floating point",
 416     [EXCP_DDBS] = "debug data break store",
 417     [EXCP_DWATCH] = "data watchpoint",
 418     [EXCP_LTLBL] = "TLB modify",
 419     [EXCP_TLBL] = "TLB load",
 420     [EXCP_TLBS] = "TLB store",
 421     [EXCP_DBE] = "data bus error",
 422     [EXCP_DDBL] = "debug data break load",
 423     [EXCP_THREAD] = "thread",
 424     [EXCP_MDMX] = "MDMX",
 425     [EXCP_C2E] = "precise coprocessor 2",
 426     [EXCP_CACHE] = "cache error",
 427     [EXCP_TLBXI] = "TLB execute-inhibit",
 428     [EXCP_TLBRI] = "TLB read-inhibit",
 429 };
 430
 431 target_ulong exception_resume_pc (CPUMIPSState *env)
 432 {
 433     target_ulong bad_pc;
 434     target_ulong isa_mode;
 435
 436     isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
 437     bad_pc = env->active_tc.PC | isa_mode;
 438     if (env->hflags & MIPS_HFLAG_BMASK) {
 439         /* If the exception was raised from a delay slot, come back to
 440            the jump.  */
 441         bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
 442     }
 443
 444     return bad_pc;
 445 }
 446
 447 #if !defined(CONFIG_USER_ONLY)
 448 static void set_hflags_for_handler (CPUMIPSState *env)
 449 {
 450     /* Exception handlers are entered in 32-bit mode.  */
 451     env->hflags &= ~(MIPS_HFLAG_M16);
 452     /* ...except that microMIPS lets you choose.  */
 453     if (env->insn_flags & ASE_MICROMIPS) {
 454         env->hflags |= (!!(env->CP0_Config3
 455                            & (1 << CP0C3_ISA_ON_EXC))
 456                         << MIPS_HFLAG_M16_SHIFT);
 457     }
 458 }
 459
 460 static inline void set_badinstr_registers(CPUMIPSState *env)
 461 {
 462     if (env->hflags & MIPS_HFLAG_M16) {
 463         /* TODO: add BadInstr support for microMIPS */
 464         return;
 465     }
 466     if (env->CP0_Config3 & (1 << CP0C3_BI)) {
 467         env->CP0_BadInstr = cpu_ldl_code(env, env->active_tc.PC);
 468     }
 469     if ((env->CP0_Config3 & (1 << CP0C3_BP)) &&
 470         (env->hflags & MIPS_HFLAG_BMASK)) {
 471         env->CP0_BadInstrP = cpu_ldl_code(env, env->active_tc.PC - 4);
 472     }
 473 }
 474 #endif
 475
 476 void mips_cpu_do_interrupt(CPUState *cs)
 477 {
 478 #if !defined(CONFIG_USER_ONLY)
 479     MIPSCPU *cpu = MIPS_CPU(cs);
 480     CPUMIPSState *env = &cpu->env;
 481     bool update_badinstr = 0;
 482     target_ulong offset;
 483     int cause = -1;
 484     const char *name;
 485
 486     if (qemu_log_enabled() && cs->exception_index != EXCP_EXT_INTERRUPT) {
 487         if (cs->exception_index < 0 || cs->exception_index > EXCP_LAST) {
 488             name = "unknown";
 489         } else {
 490             name = excp_names[cs->exception_index];
 491         }
 492
 493         qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n",
 494                  __func__, env->active_tc.PC, env->CP0_EPC, name);
 495     }
 496     if (cs->exception_index == EXCP_EXT_INTERRUPT &&
 497         (env->hflags & MIPS_HFLAG_DM)) {
 498         cs->exception_index = EXCP_DINT;
 499     }
 500     offset = 0x180;
 501     switch (cs->exception_index) {
 502     case EXCP_DSS:
 503         env->CP0_Debug |= 1 << CP0DB_DSS;
 504         /* Debug single step cannot be raised inside a delay slot and
 505            resume will always occur on the next instruction
 506            (but we assume the pc has always been updated during
 507            code translation). */
 508         env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16);
 509         goto enter_debug_mode;
 510     case EXCP_DINT:
 511         env->CP0_Debug |= 1 << CP0DB_DINT;
 512         goto set_DEPC;
 513     case EXCP_DIB:
 514         env->CP0_Debug |= 1 << CP0DB_DIB;
 515         goto set_DEPC;
 516     case EXCP_DBp:
 517         env->CP0_Debug |= 1 << CP0DB_DBp;
 518         goto set_DEPC;
 519     case EXCP_DDBS:
 520         env->CP0_Debug |= 1 << CP0DB_DDBS;
 521         goto set_DEPC;
 522     case EXCP_DDBL:
 523         env->CP0_Debug |= 1 << CP0DB_DDBL;
 524     set_DEPC:
 525         env->CP0_DEPC = exception_resume_pc(env);
 526         env->hflags &= ~MIPS_HFLAG_BMASK;
 527  enter_debug_mode:
 528         env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
 529         env->hflags &= ~(MIPS_HFLAG_KSU);
 530         /* EJTAG probe trap enable is not implemented... */
 531         if (!(env->CP0_Status & (1 << CP0St_EXL)))
 532             env->CP0_Cause &= ~(1U << CP0Ca_BD);
 533         env->active_tc.PC = (int32_t)0xBFC00480;
 534         set_hflags_for_handler(env);
 535         break;
 536     case EXCP_RESET:
 537         cpu_reset(CPU(cpu));
 538         break;
 539     case EXCP_SRESET:
 540         env->CP0_Status |= (1 << CP0St_SR);
 541         memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo));
 542         goto set_error_EPC;
 543     case EXCP_NMI:
 544         env->CP0_Status |= (1 << CP0St_NMI);
 545  set_error_EPC:
 546         env->CP0_ErrorEPC = exception_resume_pc(env);
 547         env->hflags &= ~MIPS_HFLAG_BMASK;
 548         env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
 549         env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
 550         env->hflags &= ~(MIPS_HFLAG_KSU);
 551         if (!(env->CP0_Status & (1 << CP0St_EXL)))
 552             env->CP0_Cause &= ~(1U << CP0Ca_BD);
 553         env->active_tc.PC = (int32_t)0xBFC00000;
 554         set_hflags_for_handler(env);
 555         break;
 556     case EXCP_EXT_INTERRUPT:
 557         cause = 0;
 558         if (env->CP0_Cause & (1 << CP0Ca_IV))
 559             offset = 0x200;
 560
 561         if (env->CP0_Config3 & ((1 << CP0C3_VInt) | (1 << CP0C3_VEIC))) {
 562             /* Vectored Interrupts.  */
 563             unsigned int spacing;
 564             unsigned int vector;
 565             unsigned int pending = (env->CP0_Cause & CP0Ca_IP_mask) >> 8;
 566
 567             pending &= env->CP0_Status >> 8;
 568             /* Compute the Vector Spacing.  */
 569             spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & ((1 << 6) - 1);
 570             spacing <<= 5;
 571
 572             if (env->CP0_Config3 & (1 << CP0C3_VInt)) {
 573                 /* For VInt mode, the MIPS computes the vector internally.  */
 574                 for (vector = 7; vector > 0; vector--) {
 575                     if (pending & (1 << vector)) {
 576                         /* Found it.  */
 577                         break;
 578                     }
 579                 }
 580             } else {
 581                 /* For VEIC mode, the external interrupt controller feeds the
 582                    vector through the CP0Cause IP lines.  */
 583                 vector = pending;
 584             }
 585             offset = 0x200 + vector * spacing;
 586         }
 587         goto set_EPC;
 588     case EXCP_LTLBL:
 589         cause = 1;
 590         update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
 591         goto set_EPC;
 592     case EXCP_TLBL:
 593         cause = 2;
 594         update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
 595         if ((env->error_code & EXCP_TLB_NOMATCH) &&
 596             !(env->CP0_Status & (1 << CP0St_EXL))) {
 597 #if defined(TARGET_MIPS64)
 598             int R = env->CP0_BadVAddr >> 62;
 599             int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 600             int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 601             int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 602
 603             if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) &&
 604                 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F))))
 605                 offset = 0x080;
 606             else
 607 #endif
 608                 offset = 0x000;
 609         }
 610         goto set_EPC;
 611     case EXCP_TLBS:
 612         cause = 3;
 613         update_badinstr = 1;
 614         if ((env->error_code & EXCP_TLB_NOMATCH) &&
 615             !(env->CP0_Status & (1 << CP0St_EXL))) {
 616 #if defined(TARGET_MIPS64)
 617             int R = env->CP0_BadVAddr >> 62;
 618             int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 619             int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 620             int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 621
 622             if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) &&
 623                 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F))))
 624                 offset = 0x080;
 625             else
 626 #endif
 627                 offset = 0x000;
 628         }
 629         goto set_EPC;
 630     case EXCP_AdEL:
 631         cause = 4;
 632         update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
 633         goto set_EPC;
 634     case EXCP_AdES:
 635         cause = 5;
 636         update_badinstr = 1;
 637         goto set_EPC;
 638     case EXCP_IBE:
 639         cause = 6;
 640         goto set_EPC;
 641     case EXCP_DBE:
 642         cause = 7;
 643         goto set_EPC;
 644     case EXCP_SYSCALL:
 645         cause = 8;
 646         update_badinstr = 1;
 647         goto set_EPC;
 648     case EXCP_BREAK:
 649         cause = 9;
 650         update_badinstr = 1;
 651         goto set_EPC;
 652     case EXCP_RI:
 653         cause = 10;
 654         update_badinstr = 1;
 655         goto set_EPC;
 656     case EXCP_CpU:
 657         cause = 11;
 658         update_badinstr = 1;
 659         env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
 660                          (env->error_code << CP0Ca_CE);
 661         goto set_EPC;
 662     case EXCP_OVERFLOW:
 663         cause = 12;
 664         update_badinstr = 1;
 665         goto set_EPC;
 666     case EXCP_TRAP:
 667         cause = 13;
 668         update_badinstr = 1;
 669         goto set_EPC;
 670     case EXCP_FPE:
 671         cause = 15;
 672         update_badinstr = 1;
 673         goto set_EPC;
 674     case EXCP_C2E:
 675         cause = 18;
 676         goto set_EPC;
 677     case EXCP_TLBRI:
 678         cause = 19;
 679         update_badinstr = 1;
 680         goto set_EPC;
 681     case EXCP_TLBXI:
 682         cause = 20;
 683         goto set_EPC;
 684     case EXCP_MDMX:
 685         cause = 22;
 686         goto set_EPC;
 687     case EXCP_DWATCH:
 688         cause = 23;
 689         /* XXX: TODO: manage defered watch exceptions */
 690         goto set_EPC;
 691     case EXCP_MCHECK:
 692         cause = 24;
 693         goto set_EPC;
 694     case EXCP_THREAD:
 695         cause = 25;
 696         goto set_EPC;
 697     case EXCP_DSPDIS:
 698         cause = 26;
 699         goto set_EPC;
 700     case EXCP_CACHE:
 701         cause = 30;
 702         if (env->CP0_Status & (1 << CP0St_BEV)) {
 703             offset = 0x100;
 704         } else {
 705             offset = 0x20000100;
 706         }
 707  set_EPC:
 708         if (!(env->CP0_Status & (1 << CP0St_EXL))) {
 709             env->CP0_EPC = exception_resume_pc(env);
 710             if (update_badinstr) {
 711                 set_badinstr_registers(env);
 712             }
 713             if (env->hflags & MIPS_HFLAG_BMASK) {
 714                 env->CP0_Cause |= (1U << CP0Ca_BD);
 715             } else {
 716                 env->CP0_Cause &= ~(1U << CP0Ca_BD);
 717             }
 718             env->CP0_Status |= (1 << CP0St_EXL);
 719             env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
 720             env->hflags &= ~(MIPS_HFLAG_KSU);
 721         }
 722         env->hflags &= ~MIPS_HFLAG_BMASK;
 723         if (env->CP0_Status & (1 << CP0St_BEV)) {
 724             env->active_tc.PC = (int32_t)0xBFC00200;
 725         } else {
 726             env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff);
 727         }
 728         env->active_tc.PC += offset;
 729         set_hflags_for_handler(env);
 730         env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
 731         break;
 732     default:
 733         qemu_log("Invalid MIPS exception %d. Exiting\n", cs->exception_index);
 734         printf("Invalid MIPS exception %d. Exiting\n", cs->exception_index);
 735         exit(1);
 736     }
 737     if (qemu_log_enabled() && cs->exception_index != EXCP_EXT_INTERRUPT) {
 738         qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"
 739                 "    S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
 740                 __func__, env->active_tc.PC, env->CP0_EPC, cause,
 741                 env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
 742                 env->CP0_DEPC);
 743     }
 744 #endif
 745     cs->exception_index = EXCP_NONE;
 746 }
 747
 748 bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 749 {
 750     if (interrupt_request & CPU_INTERRUPT_HARD) {
 751         MIPSCPU *cpu = MIPS_CPU(cs);
 752         CPUMIPSState *env = &cpu->env;
 753
 754         if (cpu_mips_hw_interrupts_pending(env)) {
 755             /* Raise it */
 756             cs->exception_index = EXCP_EXT_INTERRUPT;
 757             env->error_code = 0;
 758             mips_cpu_do_interrupt(cs);
 759             return true;
 760         }
 761     }
 762     return false;
 763 }
 764
 765 #if !defined(CONFIG_USER_ONLY)
 766 void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
 767 {
 768     MIPSCPU *cpu = mips_env_get_cpu(env);
 769     CPUState *cs;
 770     r4k_tlb_t *tlb;
 771     target_ulong addr;
 772     target_ulong end;
 773     uint8_t ASID = env->CP0_EntryHi & 0xFF;
 774     target_ulong mask;
 775
 776     tlb = &env->tlb->mmu.r4k.tlb[idx];
 777     /* The qemu TLB is flushed when the ASID changes, so no need to
 778        flush these entries again.  */
 779     if (tlb->G == 0 && tlb->ASID != ASID) {
 780         return;
 781     }
 782
 783     if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
 784         /* For tlbwr, we can shadow the discarded entry into
 785            a new (fake) TLB entry, as long as the guest can not
 786            tell that it's there.  */
 787         env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
 788         env->tlb->tlb_in_use++;
 789         return;
 790     }
 791
 792     /* 1k pages are not supported. */
 793     mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
 794     if (tlb->V0) {
 795         cs = CPU(cpu);
 796         addr = tlb->VPN & ~mask;
 797 #if defined(TARGET_MIPS64)
 798         if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
 799             addr |= 0x3FFFFF0000000000ULL;
 800         }
 801 #endif
 802         end = addr | (mask >> 1);
 803         while (addr < end) {
 804             tlb_flush_page(cs, addr);
 805             addr += TARGET_PAGE_SIZE;
 806         }
 807     }
 808     if (tlb->V1) {
 809         cs = CPU(cpu);
 810         addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
 811 #if defined(TARGET_MIPS64)
 812         if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
 813             addr |= 0x3FFFFF0000000000ULL;
 814         }
 815 #endif
 816         end = addr | mask;
 817         while (addr - 1 < end) {
 818             tlb_flush_page(cs, addr);
 819             addr += TARGET_PAGE_SIZE;
 820         }
 821     }
 822 }
 823 #endif