include/hw/pci-host/sabre.h

   1 #ifndef PCI_HOST_APB_H
   2 #define PCI_HOST_APB_H
   3
   4 #include "hw/sparc/sun4u_iommu.h"
   5
   6 #define MAX_IVEC 0x40
   7
   8 /* OBIO IVEC IRQs */
   9 #define OBIO_HDD_IRQ         0x20
  10 #define OBIO_NIC_IRQ         0x21
  11 #define OBIO_LPT_IRQ         0x22
  12 #define OBIO_FDD_IRQ         0x27
  13 #define OBIO_KBD_IRQ         0x29
  14 #define OBIO_MSE_IRQ         0x2a
  15 #define OBIO_SER_IRQ         0x2b
  16
  17 typedef struct SabrePCIState {
  18     PCIDevice parent_obj;
  19 } SabrePCIState;
  20
  21 #define TYPE_SABRE_PCI_DEVICE "sabre-pci"
  22 #define SABRE_PCI_DEVICE(obj) \
  23     OBJECT_CHECK(SabrePCIState, (obj), TYPE_SABRE_PCI_DEVICE)
  24
  25 typedef struct SabreState {
  26     PCIHostState parent_obj;
  27
  28     hwaddr special_base;
  29     hwaddr mem_base;
  30     MemoryRegion sabre_config;
  31     MemoryRegion pci_config;
  32     MemoryRegion pci_mmio;
  33     MemoryRegion pci_ioport;
  34     uint64_t pci_irq_in;
  35     IOMMUState *iommu;
  36     PCIBridge *bridgeA;
  37     PCIBridge *bridgeB;
  38     uint32_t pci_control[16];
  39     uint32_t pci_irq_map[8];
  40     uint32_t pci_err_irq_map[4];
  41     uint32_t obio_irq_map[32];
  42     qemu_irq ivec_irqs[MAX_IVEC];
  43     unsigned int irq_request;
  44     uint32_t reset_control;
  45     unsigned int nr_resets;
  46 } SabreState;
  47
  48 #define TYPE_SABRE "sabre"
  49 #define SABRE_DEVICE(obj) \
  50     OBJECT_CHECK(SabreState, (obj), TYPE_SABRE)
  51
  52 #endif