ppc/pnv: add a PSI bridge class model
[qemu/ar7.git] / include / hw / ppc / pnv_psi.h
blob7087cbcb9ad77212bcdfbc440601ec36f68cc0b9
1 /*
2 * QEMU PowerPC PowerNV Processor Service Interface (PSI) model
4 * Copyright (c) 2015-2017, IBM Corporation.
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #ifndef _PPC_PNV_PSI_H
20 #define _PPC_PNV_PSI_H
22 #include "hw/sysbus.h"
23 #include "hw/ppc/xics.h"
25 #define TYPE_PNV_PSI "pnv-psi"
26 #define PNV_PSI(obj) \
27 OBJECT_CHECK(PnvPsi, (obj), TYPE_PNV_PSI)
29 #define PSIHB_XSCOM_MAX 0x20
31 typedef struct PnvPsi {
32 SysBusDevice parent;
34 MemoryRegion regs_mr;
35 uint64_t bar;
37 /* FSP region not supported */
38 /* MemoryRegion fsp_mr; */
39 uint64_t fsp_bar;
41 /* Interrupt generation */
42 qemu_irq *qirqs;
44 /* Registers */
45 uint64_t regs[PSIHB_XSCOM_MAX];
47 MemoryRegion xscom_regs;
48 } PnvPsi;
50 #define TYPE_PNV8_PSI TYPE_PNV_PSI "-POWER8"
51 #define PNV8_PSI(obj) \
52 OBJECT_CHECK(Pnv8Psi, (obj), TYPE_PNV8_PSI)
54 typedef struct Pnv8Psi {
55 PnvPsi parent;
57 ICSState ics;
58 } Pnv8Psi;
60 #define PNV_PSI_CLASS(klass) \
61 OBJECT_CLASS_CHECK(PnvPsiClass, (klass), TYPE_PNV_PSI)
62 #define PNV_PSI_GET_CLASS(obj) \
63 OBJECT_GET_CLASS(PnvPsiClass, (obj), TYPE_PNV_PSI)
65 typedef struct PnvPsiClass {
66 SysBusDeviceClass parent_class;
68 int chip_type;
69 uint32_t xscom_pcba;
70 uint32_t xscom_size;
71 uint64_t bar_mask;
73 void (*irq_set)(PnvPsi *psi, int, bool state);
74 } PnvPsiClass;
76 /* The PSI and FSP interrupts are muxed on the same IRQ number */
77 typedef enum PnvPsiIrq {
78 PSIHB_IRQ_PSI, /* internal use only */
79 PSIHB_IRQ_FSP, /* internal use only */
80 PSIHB_IRQ_OCC,
81 PSIHB_IRQ_FSI,
82 PSIHB_IRQ_LPC_I2C,
83 PSIHB_IRQ_LOCAL_ERR,
84 PSIHB_IRQ_EXTERNAL,
85 } PnvPsiIrq;
87 #define PSI_NUM_INTERRUPTS 6
89 void pnv_psi_irq_set(PnvPsi *psi, int irq, bool state);
91 #endif /* _PPC_PNV_PSI_H */