2 * s390 PCI BUS definitions
4 * Copyright 2014 IBM Corp.
5 * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com>
6 * Hong Bo Li <lihbbj@cn.ibm.com>
7 * Yi Min Zhao <zyimin@cn.ibm.com>
9 * This work is licensed under the terms of the GNU GPL, version 2 or (at
10 * your option) any later version. See the COPYING file in the top-level
14 #ifndef HW_S390_PCI_BUS_H
15 #define HW_S390_PCI_BUS_H
17 #include "hw/pci/pci.h"
18 #include "hw/pci/pci_host.h"
19 #include "hw/s390x/sclp.h"
20 #include "hw/s390x/s390_flic.h"
21 #include "hw/s390x/css.h"
22 #include "qom/object.h"
24 #define TYPE_S390_PCI_HOST_BRIDGE "s390-pcihost"
25 #define TYPE_S390_PCI_BUS "s390-pcibus"
26 #define TYPE_S390_PCI_DEVICE "zpci"
27 #define TYPE_S390_PCI_IOMMU "s390-pci-iommu"
28 #define TYPE_S390_IOMMU_MEMORY_REGION "s390-iommu-memory-region"
29 #define FH_MASK_ENABLE 0x80000000
30 #define FH_MASK_INSTANCE 0x7f000000
31 #define FH_MASK_SHM 0x00ff0000
32 #define FH_MASK_INDEX 0x0000ffff
33 #define FH_SHM_VFIO 0x00010000
34 #define FH_SHM_EMUL 0x00020000
35 #define ZPCI_MAX_FID 0xffffffff
36 #define ZPCI_MAX_UID 0xffff
37 #define UID_UNDEFINED 0
38 #define UID_CHECKING_ENABLED 0x01
40 typedef struct S390pciState S390pciState
;
41 DECLARE_INSTANCE_CHECKER(S390pciState
, S390_PCI_HOST_BRIDGE
,
42 TYPE_S390_PCI_HOST_BRIDGE
)
43 typedef struct S390PCIBus S390PCIBus
;
44 DECLARE_INSTANCE_CHECKER(S390PCIBus
, S390_PCI_BUS
,
46 typedef struct S390PCIBusDevice S390PCIBusDevice
;
47 DECLARE_INSTANCE_CHECKER(S390PCIBusDevice
, S390_PCI_DEVICE
,
49 typedef struct S390PCIIOMMU S390PCIIOMMU
;
50 DECLARE_INSTANCE_CHECKER(S390PCIIOMMU
, S390_PCI_IOMMU
,
53 #define HP_EVENT_TO_CONFIGURED 0x0301
54 #define HP_EVENT_RESERVED_TO_STANDBY 0x0302
55 #define HP_EVENT_DECONFIGURE_REQUEST 0x0303
56 #define HP_EVENT_CONFIGURED_TO_STBRES 0x0304
57 #define HP_EVENT_STANDBY_TO_RESERVED 0x0308
59 #define ERR_EVENT_INVALAS 0x1
60 #define ERR_EVENT_OORANGE 0x2
61 #define ERR_EVENT_INVALTF 0x3
62 #define ERR_EVENT_TPROTE 0x4
63 #define ERR_EVENT_APROTE 0x5
64 #define ERR_EVENT_KEYE 0x6
65 #define ERR_EVENT_INVALTE 0x7
66 #define ERR_EVENT_INVALTL 0x8
67 #define ERR_EVENT_TT 0x9
68 #define ERR_EVENT_INVALMS 0xa
69 #define ERR_EVENT_SERR 0xb
70 #define ERR_EVENT_NOMSI 0x10
71 #define ERR_EVENT_INVALBV 0x11
72 #define ERR_EVENT_AIBV 0x12
73 #define ERR_EVENT_AIRERR 0x13
74 #define ERR_EVENT_FMBA 0x2a
75 #define ERR_EVENT_FMBUP 0x2b
76 #define ERR_EVENT_FMBPRO 0x2c
77 #define ERR_EVENT_CCONF 0x30
78 #define ERR_EVENT_SERVAC 0x3a
79 #define ERR_EVENT_PERMERR 0x3b
81 #define ERR_EVENT_Q_BIT 0x2
82 #define ERR_EVENT_MVN_OFFSET 16
84 #define ZPCI_MSI_VEC_BITS 11
85 #define ZPCI_MSI_VEC_MASK 0x7ff
87 #define ZPCI_MSI_ADDR 0xfe00000000000000ULL
88 #define ZPCI_SDMA_ADDR 0x100000000ULL
89 #define ZPCI_EDMA_ADDR 0x1ffffffffffffffULL
92 #define PAGE_SIZE (1 << PAGE_SHIFT)
93 #define PAGE_MASK (~(PAGE_SIZE-1))
94 #define PAGE_DEFAULT_ACC 0
95 #define PAGE_DEFAULT_KEY (PAGE_DEFAULT_ACC << 4)
97 /* I/O Translation Anchor (IOTA) */
104 ZPCI_IOTA_IOPFAA
= 5,
108 #define ZPCI_IOTA_IOT_ENABLED 0x800ULL
109 #define ZPCI_IOTA_DT_ST (ZPCI_IOTA_STO << 2)
110 #define ZPCI_IOTA_DT_RT (ZPCI_IOTA_RTTO << 2)
111 #define ZPCI_IOTA_DT_RS (ZPCI_IOTA_RSTO << 2)
112 #define ZPCI_IOTA_DT_RF (ZPCI_IOTA_RFTO << 2)
113 #define ZPCI_IOTA_DT_PF (ZPCI_IOTA_PFAA << 2)
114 #define ZPCI_IOTA_FS_4K 0
115 #define ZPCI_IOTA_FS_1M 1
116 #define ZPCI_IOTA_FS_2G 2
117 #define ZPCI_KEY (PAGE_DEFAULT_KEY << 5)
119 #define ZPCI_IOTA_STO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_ST)
120 #define ZPCI_IOTA_RTTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RT)
121 #define ZPCI_IOTA_RSTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RS)
122 #define ZPCI_IOTA_RFTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RF)
123 #define ZPCI_IOTA_RFAA_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY |\
124 ZPCI_IOTA_DT_PF | ZPCI_IOTA_FS_2G)
126 /* I/O Region and segment tables */
127 #define ZPCI_INDEX_MASK 0x7ffULL
129 #define ZPCI_TABLE_TYPE_MASK 0xc
130 #define ZPCI_TABLE_TYPE_RFX 0xc
131 #define ZPCI_TABLE_TYPE_RSX 0x8
132 #define ZPCI_TABLE_TYPE_RTX 0x4
133 #define ZPCI_TABLE_TYPE_SX 0x0
135 #define ZPCI_TABLE_LEN_RFX 0x3
136 #define ZPCI_TABLE_LEN_RSX 0x3
137 #define ZPCI_TABLE_LEN_RTX 0x3
139 #define ZPCI_TABLE_OFFSET_MASK 0xc0
140 #define ZPCI_TABLE_SIZE 0x4000
141 #define ZPCI_TABLE_ALIGN ZPCI_TABLE_SIZE
142 #define ZPCI_TABLE_ENTRY_SIZE (sizeof(unsigned long))
143 #define ZPCI_TABLE_ENTRIES (ZPCI_TABLE_SIZE / ZPCI_TABLE_ENTRY_SIZE)
145 #define ZPCI_TABLE_BITS 11
146 #define ZPCI_PT_BITS 8
147 #define ZPCI_ST_SHIFT (ZPCI_PT_BITS + PAGE_SHIFT)
148 #define ZPCI_RT_SHIFT (ZPCI_ST_SHIFT + ZPCI_TABLE_BITS)
150 #define ZPCI_RTE_FLAG_MASK 0x3fffULL
151 #define ZPCI_RTE_ADDR_MASK (~ZPCI_RTE_FLAG_MASK)
152 #define ZPCI_STE_FLAG_MASK 0x7ffULL
153 #define ZPCI_STE_ADDR_MASK (~ZPCI_STE_FLAG_MASK)
155 #define ZPCI_SFAA_MASK (~((1ULL << 20) - 1))
157 /* I/O Page tables */
158 #define ZPCI_PTE_VALID_MASK 0x400
159 #define ZPCI_PTE_INVALID 0x400
160 #define ZPCI_PTE_VALID 0x000
161 #define ZPCI_PT_SIZE 0x800
162 #define ZPCI_PT_ALIGN ZPCI_PT_SIZE
163 #define ZPCI_PT_ENTRIES (ZPCI_PT_SIZE / ZPCI_TABLE_ENTRY_SIZE)
164 #define ZPCI_PT_MASK (ZPCI_PT_ENTRIES - 1)
166 #define ZPCI_PTE_FLAG_MASK 0xfffULL
167 #define ZPCI_PTE_ADDR_MASK (~ZPCI_PTE_FLAG_MASK)
170 #define ZPCI_TABLE_VALID 0x00
171 #define ZPCI_TABLE_INVALID 0x20
172 #define ZPCI_TABLE_PROTECTED 0x200
173 #define ZPCI_TABLE_UNPROTECTED 0x000
174 #define ZPCI_TABLE_FC 0x400
176 #define ZPCI_TABLE_VALID_MASK 0x20
177 #define ZPCI_TABLE_PROT_MASK 0x200
179 #define ZPCI_ETT_RT 1
180 #define ZPCI_ETT_ST 0
181 #define ZPCI_ETT_PT -1
183 /* PCI Function States
185 * reserved: default; device has just been plugged or is in progress of being
187 * standby: device is present but not configured; transition from any
188 * configured state/to this state via sclp configure/deconfigure
190 * The following states make up the "configured" meta-state:
191 * disabled: device is configured but not enabled; transition between this
192 * state and enabled via clp enable/disable
193 * enbaled: device is ready for use; transition to disabled via clp disable;
194 * may enter an error state
195 * blocked: ignore all DMA and interrupts; transition back to enabled or from
196 * error state via mpcifc
197 * error: an error occurred; transition back to enabled via mpcifc
198 * permanent error: an unrecoverable error occurred; transition to standby via
208 ZPCI_FS_PERMANENT_ERROR
,
211 typedef struct SeiContainer
{
212 QTAILQ_ENTRY(SeiContainer
) link
;
221 typedef struct PciCcdfErr
{
230 } QEMU_PACKED PciCcdfErr
;
232 typedef struct PciCcdfAvail
{
242 } QEMU_PACKED PciCcdfAvail
;
244 typedef struct ChscSeiNt2Res
{
254 uint32_t reserved5
[13];
256 } QEMU_PACKED ChscSeiNt2Res
;
258 typedef struct S390MsixInfo
{
262 uint32_t table_offset
;
266 typedef struct S390IOTLBEntry
{
268 uint64_t translated_addr
;
273 struct S390PCIIOMMU
{
275 S390PCIBusDevice
*pbdev
;
278 IOMMUMemoryRegion iommu_mr
;
286 typedef struct S390PCIIOMMUTable
{
288 S390PCIIOMMU
*iommu
[PCI_SLOT_MAX
];
291 /* Function Measurement Block */
292 #define DEFAULT_MUI 4000
293 #define UPDATE_U_BIT 0x1ULL
294 #define FMBK_MASK 0xfULL
296 typedef struct ZpciFmbFmt0
{
301 #define ZPCI_FMB_CNT_LD 0
302 #define ZPCI_FMB_CNT_ST 1
303 #define ZPCI_FMB_CNT_STB 2
304 #define ZPCI_FMB_CNT_RPCIT 3
305 #define ZPCI_FMB_CNT_MAX 4
307 #define ZPCI_FMB_FORMAT 0
309 typedef struct ZpciFmb
{
312 uint64_t last_update
;
313 uint64_t counter
[ZPCI_FMB_CNT_MAX
];
316 QEMU_BUILD_BUG_MSG(offsetof(ZpciFmb
, fmt0
) != 48, "padding in ZpciFmb");
318 struct S390PCIBusDevice
{
330 QEMUTimer
*fmb_timer
;
336 AdapterRoutes routes
;
338 MemoryRegion msix_notify_mr
;
339 IndAddr
*summary_ind
;
341 bool pci_unplug_request_processed
;
342 bool unplug_requested
;
343 QTAILQ_ENTRY(S390PCIBusDevice
) link
;
350 struct S390pciState
{
351 PCIHostState parent_obj
;
355 GHashTable
*iommu_table
;
356 GHashTable
*zpci_table
;
357 QTAILQ_HEAD(, SeiContainer
) pending_sei
;
358 QTAILQ_HEAD(, S390PCIBusDevice
) zpci_devs
;
361 S390pciState
*s390_get_phb(void);
362 int pci_chsc_sei_nt2_get_event(void *res
);
363 int pci_chsc_sei_nt2_have_event(void);
364 void s390_pci_sclp_configure(SCCB
*sccb
);
365 void s390_pci_sclp_deconfigure(SCCB
*sccb
);
366 void s390_pci_iommu_enable(S390PCIIOMMU
*iommu
);
367 void s390_pci_iommu_disable(S390PCIIOMMU
*iommu
);
368 void s390_pci_generate_error_event(uint16_t pec
, uint32_t fh
, uint32_t fid
,
369 uint64_t faddr
, uint32_t e
);
370 uint16_t s390_guest_io_table_walk(uint64_t g_iota
, hwaddr addr
,
371 S390IOTLBEntry
*entry
);
372 S390PCIBusDevice
*s390_pci_find_dev_by_idx(S390pciState
*s
, uint32_t idx
);
373 S390PCIBusDevice
*s390_pci_find_dev_by_fh(S390pciState
*s
, uint32_t fh
);
374 S390PCIBusDevice
*s390_pci_find_dev_by_fid(S390pciState
*s
, uint32_t fid
);
375 S390PCIBusDevice
*s390_pci_find_dev_by_target(S390pciState
*s
,
377 S390PCIBusDevice
*s390_pci_find_next_avail_dev(S390pciState
*s
,
378 S390PCIBusDevice
*pbdev
);