hw/misc/puv3_pm.c

   1 /*
   2  * Power Management device simulation in PKUnity SoC
   3  *
   4  * Copyright (C) 2010-2012 Guan Xuetao
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation, or any later version.
   9  * See the COPYING file in the top-level directory.
  10  */
  11
  12 #include "qemu/osdep.h"
  13 #include "hw/sysbus.h"
  14 #include "qom/object.h"
  15
  16 #undef DEBUG_PUV3
  17 #include "hw/unicore32/puv3.h"
  18 #include "qemu/module.h"
  19 #include "qemu/log.h"
  20
  21 #define TYPE_PUV3_PM "puv3_pm"
  22 typedef struct PUV3PMState PUV3PMState;
  23 DECLARE_INSTANCE_CHECKER(PUV3PMState, PUV3_PM,
  24                          TYPE_PUV3_PM)
  25
  26 struct PUV3PMState {
  27     SysBusDevice parent_obj;
  28
  29     MemoryRegion iomem;
  30
  31     uint32_t reg_PMCR;
  32     uint32_t reg_PCGR;
  33     uint32_t reg_PLL_SYS_CFG;
  34     uint32_t reg_PLL_DDR_CFG;
  35     uint32_t reg_PLL_VGA_CFG;
  36     uint32_t reg_DIVCFG;
  37 };
  38
  39 static uint64_t puv3_pm_read(void *opaque, hwaddr offset,
  40         unsigned size)
  41 {
  42     PUV3PMState *s = opaque;
  43     uint32_t ret = 0;
  44
  45     switch (offset) {
  46     case 0x14:
  47         ret = s->reg_PCGR;
  48         break;
  49     case 0x18:
  50         ret = s->reg_PLL_SYS_CFG;
  51         break;
  52     case 0x1c:
  53         ret = s->reg_PLL_DDR_CFG;
  54         break;
  55     case 0x20:
  56         ret = s->reg_PLL_VGA_CFG;
  57         break;
  58     case 0x24:
  59         ret = s->reg_DIVCFG;
  60         break;
  61     case 0x28: /* PLL SYS STATUS */
  62         ret = 0x00002401;
  63         break;
  64     case 0x2c: /* PLL DDR STATUS */
  65         ret = 0x00100c00;
  66         break;
  67     case 0x30: /* PLL VGA STATUS */
  68         ret = 0x00003801;
  69         break;
  70     case 0x34: /* DIV STATUS */
  71         ret = 0x22f52015;
  72         break;
  73     case 0x38: /* SW RESET */
  74         ret = 0x0;
  75         break;
  76     case 0x44: /* PLL DFC DONE */
  77         ret = 0x7;
  78         break;
  79     default:
  80         qemu_log_mask(LOG_GUEST_ERROR,
  81                       "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
  82                       __func__, offset);
  83     }
  84     DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
  85
  86     return ret;
  87 }
  88
  89 static void puv3_pm_write(void *opaque, hwaddr offset,
  90         uint64_t value, unsigned size)
  91 {
  92     PUV3PMState *s = opaque;
  93
  94     switch (offset) {
  95     case 0x0:
  96         s->reg_PMCR = value;
  97         break;
  98     case 0x14:
  99         s->reg_PCGR = value;
 100         break;
 101     case 0x18:
 102         s->reg_PLL_SYS_CFG = value;
 103         break;
 104     case 0x1c:
 105         s->reg_PLL_DDR_CFG = value;
 106         break;
 107     case 0x20:
 108         s->reg_PLL_VGA_CFG = value;
 109         break;
 110     case 0x24:
 111     case 0x38:
 112         break;
 113     default:
 114         qemu_log_mask(LOG_GUEST_ERROR,
 115                       "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
 116                       __func__, offset);
 117     }
 118     DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
 119 }
 120
 121 static const MemoryRegionOps puv3_pm_ops = {
 122     .read = puv3_pm_read,
 123     .write = puv3_pm_write,
 124     .impl = {
 125         .min_access_size = 4,
 126         .max_access_size = 4,
 127     },
 128     .endianness = DEVICE_NATIVE_ENDIAN,
 129 };
 130
 131 static void puv3_pm_realize(DeviceState *dev, Error **errp)
 132 {
 133     PUV3PMState *s = PUV3_PM(dev);
 134
 135     s->reg_PCGR = 0x0;
 136
 137     memory_region_init_io(&s->iomem, OBJECT(s), &puv3_pm_ops, s, "puv3_pm",
 138             PUV3_REGS_OFFSET);
 139     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
 140 }
 141
 142 static void puv3_pm_class_init(ObjectClass *klass, void *data)
 143 {
 144     DeviceClass *dc = DEVICE_CLASS(klass);
 145
 146     dc->realize = puv3_pm_realize;
 147 }
 148
 149 static const TypeInfo puv3_pm_info = {
 150     .name = TYPE_PUV3_PM,
 151     .parent = TYPE_SYS_BUS_DEVICE,
 152     .instance_size = sizeof(PUV3PMState),
 153     .class_init = puv3_pm_class_init,
 154 };
 155
 156 static void puv3_pm_register_type(void)
 157 {
 158     type_register_static(&puv3_pm_info);
 159 }
 160
 161 type_init(puv3_pm_register_type)