2 * ARM V2M MPS2 board emulation.
4 * Copyright (c) 2017 Linaro Limited
5 * Written by Peter Maydell
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or
9 * (at your option) any later version.
12 /* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger
13 * FPGA but is otherwise the same as the 2). Since the CPU itself
14 * and most of the devices are in the FPGA, the details of the board
15 * as seen by the guest depend significantly on the FPGA image.
16 * We model the following FPGA images:
17 * "mps2-an385" -- Cortex-M3 as documented in ARM Application Note AN385
18 * "mps2-an511" -- Cortex-M3 'DesignStart' as documented in AN511
20 * Links to the TRM for the board itself and to the various Application
21 * Notes which document the FPGA images can be found here:
22 * https://developer.arm.com/products/system-design/development-boards/cortex-m-prototyping-system
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "qemu/cutils.h"
28 #include "qapi/error.h"
29 #include "qemu/error-report.h"
30 #include "hw/arm/boot.h"
31 #include "hw/arm/armv7m.h"
32 #include "hw/or-irq.h"
33 #include "hw/boards.h"
34 #include "exec/address-spaces.h"
35 #include "sysemu/sysemu.h"
36 #include "hw/misc/unimp.h"
37 #include "hw/char/cmsdk-apb-uart.h"
38 #include "hw/timer/cmsdk-apb-timer.h"
39 #include "hw/timer/cmsdk-apb-dualtimer.h"
40 #include "hw/misc/mps2-scc.h"
41 #include "hw/misc/mps2-fpgaio.h"
42 #include "hw/ssi/pl022.h"
43 #include "hw/i2c/arm_sbcon_i2c.h"
44 #include "hw/net/lan9118.h"
46 #include "hw/watchdog/cmsdk-apb-watchdog.h"
47 #include "qom/object.h"
49 typedef enum MPS2FPGAType
{
54 struct MPS2MachineClass
{
56 MPS2FPGAType fpga_type
;
59 typedef struct MPS2MachineClass MPS2MachineClass
;
61 struct MPS2MachineState
{
66 MemoryRegion ssram1_m
;
68 MemoryRegion ssram23_m
;
69 MemoryRegion blockram
;
70 MemoryRegion blockram_m1
;
71 MemoryRegion blockram_m2
;
72 MemoryRegion blockram_m3
;
74 /* FPGA APB subsystem */
77 /* CMSDK APB subsystem */
78 CMSDKAPBDualTimer dualtimer
;
79 CMSDKAPBWatchdog watchdog
;
81 typedef struct MPS2MachineState MPS2MachineState
;
83 #define TYPE_MPS2_MACHINE "mps2"
84 #define TYPE_MPS2_AN385_MACHINE MACHINE_TYPE_NAME("mps2-an385")
85 #define TYPE_MPS2_AN511_MACHINE MACHINE_TYPE_NAME("mps2-an511")
87 DECLARE_OBJ_CHECKERS(MPS2MachineState
, MPS2MachineClass
,
88 MPS2_MACHINE
, TYPE_MPS2_MACHINE
)
90 /* Main SYSCLK frequency in Hz */
91 #define SYSCLK_FRQ 25000000
93 /* Initialize the auxiliary RAM region @mr and map it into
94 * the memory map at @base.
96 static void make_ram(MemoryRegion
*mr
, const char *name
,
97 hwaddr base
, hwaddr size
)
99 memory_region_init_ram(mr
, NULL
, name
, size
, &error_fatal
);
100 memory_region_add_subregion(get_system_memory(), base
, mr
);
103 /* Create an alias of an entire original MemoryRegion @orig
104 * located at @base in the memory map.
106 static void make_ram_alias(MemoryRegion
*mr
, const char *name
,
107 MemoryRegion
*orig
, hwaddr base
)
109 memory_region_init_alias(mr
, NULL
, name
, orig
, 0,
110 memory_region_size(orig
));
111 memory_region_add_subregion(get_system_memory(), base
, mr
);
114 static void mps2_common_init(MachineState
*machine
)
116 MPS2MachineState
*mms
= MPS2_MACHINE(machine
);
117 MPS2MachineClass
*mmc
= MPS2_MACHINE_GET_CLASS(machine
);
118 MemoryRegion
*system_memory
= get_system_memory();
119 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
120 DeviceState
*armv7m
, *sccdev
;
123 if (strcmp(machine
->cpu_type
, mc
->default_cpu_type
) != 0) {
124 error_report("This board can only be used with CPU %s",
125 mc
->default_cpu_type
);
129 if (machine
->ram_size
!= mc
->default_ram_size
) {
130 char *sz
= size_to_str(mc
->default_ram_size
);
131 error_report("Invalid RAM size, should be %s", sz
);
136 /* The FPGA images have an odd combination of different RAMs,
137 * because in hardware they are different implementations and
138 * connected to different buses, giving varying performance/size
139 * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily
140 * call the 16MB our "system memory", as it's the largest lump.
142 * Common to both boards:
143 * 0x21000000..0x21ffffff : PSRAM (16MB)
145 * 0x00000000 .. 0x003fffff : ZBT SSRAM1
146 * 0x00400000 .. 0x007fffff : mirror of ZBT SSRAM1
147 * 0x20000000 .. 0x203fffff : ZBT SSRAM 2&3
148 * 0x20400000 .. 0x207fffff : mirror of ZBT SSRAM 2&3
149 * 0x01000000 .. 0x01003fff : block RAM (16K)
150 * 0x01004000 .. 0x01007fff : mirror of above
151 * 0x01008000 .. 0x0100bfff : mirror of above
152 * 0x0100c000 .. 0x0100ffff : mirror of above
154 * 0x00000000 .. 0x0003ffff : FPGA block RAM
155 * 0x00400000 .. 0x007fffff : ZBT SSRAM1
156 * 0x20000000 .. 0x2001ffff : SRAM
157 * 0x20400000 .. 0x207fffff : ZBT SSRAM 2&3
159 * The AN385 has a feature where the lowest 16K can be mapped
160 * either to the bottom of the ZBT SSRAM1 or to the block RAM.
161 * This is of no use for QEMU so we don't implement it (as if
162 * zbt_boot_ctrl is always zero).
164 memory_region_add_subregion(system_memory
, 0x21000000, machine
->ram
);
166 switch (mmc
->fpga_type
) {
168 make_ram(&mms
->ssram1
, "mps.ssram1", 0x0, 0x400000);
169 make_ram_alias(&mms
->ssram1_m
, "mps.ssram1_m", &mms
->ssram1
, 0x400000);
170 make_ram(&mms
->ssram23
, "mps.ssram23", 0x20000000, 0x400000);
171 make_ram_alias(&mms
->ssram23_m
, "mps.ssram23_m",
172 &mms
->ssram23
, 0x20400000);
173 make_ram(&mms
->blockram
, "mps.blockram", 0x01000000, 0x4000);
174 make_ram_alias(&mms
->blockram_m1
, "mps.blockram_m1",
175 &mms
->blockram
, 0x01004000);
176 make_ram_alias(&mms
->blockram_m2
, "mps.blockram_m2",
177 &mms
->blockram
, 0x01008000);
178 make_ram_alias(&mms
->blockram_m3
, "mps.blockram_m3",
179 &mms
->blockram
, 0x0100c000);
182 make_ram(&mms
->blockram
, "mps.blockram", 0x0, 0x40000);
183 make_ram(&mms
->ssram1
, "mps.ssram1", 0x00400000, 0x00800000);
184 make_ram(&mms
->sram
, "mps.sram", 0x20000000, 0x20000);
185 make_ram(&mms
->ssram23
, "mps.ssram23", 0x20400000, 0x400000);
188 g_assert_not_reached();
191 object_initialize_child(OBJECT(mms
), "armv7m", &mms
->armv7m
, TYPE_ARMV7M
);
192 armv7m
= DEVICE(&mms
->armv7m
);
193 switch (mmc
->fpga_type
) {
195 qdev_prop_set_uint32(armv7m
, "num-irq", 32);
198 qdev_prop_set_uint32(armv7m
, "num-irq", 64);
201 g_assert_not_reached();
203 qdev_prop_set_string(armv7m
, "cpu-type", machine
->cpu_type
);
204 qdev_prop_set_bit(armv7m
, "enable-bitband", true);
205 object_property_set_link(OBJECT(&mms
->armv7m
), "memory",
206 OBJECT(system_memory
), &error_abort
);
207 sysbus_realize(SYS_BUS_DEVICE(&mms
->armv7m
), &error_fatal
);
209 create_unimplemented_device("zbtsmram mirror", 0x00400000, 0x00400000);
210 create_unimplemented_device("RESERVED 1", 0x00800000, 0x00800000);
211 create_unimplemented_device("Block RAM", 0x01000000, 0x00010000);
212 create_unimplemented_device("RESERVED 2", 0x01010000, 0x1EFF0000);
213 create_unimplemented_device("RESERVED 3", 0x20800000, 0x00800000);
214 create_unimplemented_device("PSRAM", 0x21000000, 0x01000000);
215 /* These three ranges all cover multiple devices; we may implement
216 * some of them below (in which case the real device takes precedence
217 * over the unimplemented-region mapping).
219 create_unimplemented_device("CMSDK APB peripheral region @0x40000000",
220 0x40000000, 0x00010000);
221 create_unimplemented_device("CMSDK AHB peripheral region @0x40010000",
222 0x40010000, 0x00010000);
223 create_unimplemented_device("Extra peripheral region @0x40020000",
224 0x40020000, 0x00010000);
226 create_unimplemented_device("RESERVED 4", 0x40030000, 0x001D0000);
227 create_unimplemented_device("VGA", 0x41000000, 0x0200000);
229 switch (mmc
->fpga_type
) {
232 /* The overflow IRQs for UARTs 0, 1 and 2 are ORed together.
233 * Overflow for UARTs 4 and 5 doesn't trigger any interrupt.
236 DeviceState
*orgate_dev
;
238 orgate
= object_new(TYPE_OR_IRQ
);
239 object_property_set_int(orgate
, "num-lines", 6, &error_fatal
);
240 qdev_realize(DEVICE(orgate
), NULL
, &error_fatal
);
241 orgate_dev
= DEVICE(orgate
);
242 qdev_connect_gpio_out(orgate_dev
, 0, qdev_get_gpio_in(armv7m
, 12));
244 for (i
= 0; i
< 5; i
++) {
245 static const hwaddr uartbase
[] = {0x40004000, 0x40005000,
246 0x40006000, 0x40007000,
248 /* RX irq number; TX irq is always one greater */
249 static const int uartirq
[] = {0, 2, 4, 18, 20};
250 qemu_irq txovrint
= NULL
, rxovrint
= NULL
;
253 txovrint
= qdev_get_gpio_in(orgate_dev
, i
* 2);
254 rxovrint
= qdev_get_gpio_in(orgate_dev
, i
* 2 + 1);
257 cmsdk_apb_uart_create(uartbase
[i
],
258 qdev_get_gpio_in(armv7m
, uartirq
[i
] + 1),
259 qdev_get_gpio_in(armv7m
, uartirq
[i
]),
262 serial_hd(i
), SYSCLK_FRQ
);
268 /* The overflow IRQs for all UARTs are ORed together.
269 * Tx and Rx IRQs for each UART are ORed together.
272 DeviceState
*orgate_dev
;
274 orgate
= object_new(TYPE_OR_IRQ
);
275 object_property_set_int(orgate
, "num-lines", 10, &error_fatal
);
276 qdev_realize(DEVICE(orgate
), NULL
, &error_fatal
);
277 orgate_dev
= DEVICE(orgate
);
278 qdev_connect_gpio_out(orgate_dev
, 0, qdev_get_gpio_in(armv7m
, 12));
280 for (i
= 0; i
< 5; i
++) {
281 /* system irq numbers for the combined tx/rx for each UART */
282 static const int uart_txrx_irqno
[] = {0, 2, 45, 46, 56};
283 static const hwaddr uartbase
[] = {0x40004000, 0x40005000,
284 0x4002c000, 0x4002d000,
287 DeviceState
*txrx_orgate_dev
;
289 txrx_orgate
= object_new(TYPE_OR_IRQ
);
290 object_property_set_int(txrx_orgate
, "num-lines", 2, &error_fatal
);
291 qdev_realize(DEVICE(txrx_orgate
), NULL
, &error_fatal
);
292 txrx_orgate_dev
= DEVICE(txrx_orgate
);
293 qdev_connect_gpio_out(txrx_orgate_dev
, 0,
294 qdev_get_gpio_in(armv7m
, uart_txrx_irqno
[i
]));
295 cmsdk_apb_uart_create(uartbase
[i
],
296 qdev_get_gpio_in(txrx_orgate_dev
, 0),
297 qdev_get_gpio_in(txrx_orgate_dev
, 1),
298 qdev_get_gpio_in(orgate_dev
, i
* 2),
299 qdev_get_gpio_in(orgate_dev
, i
* 2 + 1),
301 serial_hd(i
), SYSCLK_FRQ
);
306 g_assert_not_reached();
308 for (i
= 0; i
< 4; i
++) {
309 static const hwaddr gpiobase
[] = {0x40010000, 0x40011000,
310 0x40012000, 0x40013000};
311 create_unimplemented_device("cmsdk-ahb-gpio", gpiobase
[i
], 0x1000);
314 /* CMSDK APB subsystem */
315 cmsdk_apb_timer_create(0x40000000, qdev_get_gpio_in(armv7m
, 8), SYSCLK_FRQ
);
316 cmsdk_apb_timer_create(0x40001000, qdev_get_gpio_in(armv7m
, 9), SYSCLK_FRQ
);
317 object_initialize_child(OBJECT(mms
), "dualtimer", &mms
->dualtimer
,
318 TYPE_CMSDK_APB_DUALTIMER
);
319 qdev_prop_set_uint32(DEVICE(&mms
->dualtimer
), "pclk-frq", SYSCLK_FRQ
);
320 sysbus_realize(SYS_BUS_DEVICE(&mms
->dualtimer
), &error_fatal
);
321 sysbus_connect_irq(SYS_BUS_DEVICE(&mms
->dualtimer
), 0,
322 qdev_get_gpio_in(armv7m
, 10));
323 sysbus_mmio_map(SYS_BUS_DEVICE(&mms
->dualtimer
), 0, 0x40002000);
324 object_initialize_child(OBJECT(mms
), "watchdog", &mms
->watchdog
,
325 TYPE_CMSDK_APB_WATCHDOG
);
326 qdev_prop_set_uint32(DEVICE(&mms
->watchdog
), "wdogclk-frq", SYSCLK_FRQ
);
327 sysbus_realize(SYS_BUS_DEVICE(&mms
->watchdog
), &error_fatal
);
328 sysbus_connect_irq(SYS_BUS_DEVICE(&mms
->watchdog
), 0,
329 qdev_get_gpio_in_named(armv7m
, "NMI", 0));
330 sysbus_mmio_map(SYS_BUS_DEVICE(&mms
->watchdog
), 0, 0x40008000);
332 /* FPGA APB subsystem */
333 object_initialize_child(OBJECT(mms
), "scc", &mms
->scc
, TYPE_MPS2_SCC
);
334 sccdev
= DEVICE(&mms
->scc
);
335 qdev_prop_set_uint32(sccdev
, "scc-cfg4", 0x2);
336 qdev_prop_set_uint32(sccdev
, "scc-aid", 0x00200008);
337 qdev_prop_set_uint32(sccdev
, "scc-id", mmc
->scc_id
);
338 sysbus_realize(SYS_BUS_DEVICE(&mms
->scc
), &error_fatal
);
339 sysbus_mmio_map(SYS_BUS_DEVICE(sccdev
), 0, 0x4002f000);
340 object_initialize_child(OBJECT(mms
), "fpgaio",
341 &mms
->fpgaio
, TYPE_MPS2_FPGAIO
);
342 qdev_prop_set_uint32(DEVICE(&mms
->fpgaio
), "prescale-clk", 25000000);
343 sysbus_realize(SYS_BUS_DEVICE(&mms
->fpgaio
), &error_fatal
);
344 sysbus_mmio_map(SYS_BUS_DEVICE(&mms
->fpgaio
), 0, 0x40028000);
345 sysbus_create_simple(TYPE_PL022
, 0x40025000, /* External ADC */
346 qdev_get_gpio_in(armv7m
, 22));
347 for (i
= 0; i
< 2; i
++) {
348 static const int spi_irqno
[] = {11, 24};
349 static const hwaddr spibase
[] = {0x40020000, /* APB */
350 0x40021000, /* LCD */
351 0x40026000, /* Shield0 */
352 0x40027000}; /* Shield1 */
353 DeviceState
*orgate_dev
;
357 orgate
= object_new(TYPE_OR_IRQ
);
358 object_property_set_int(orgate
, "num-lines", 2, &error_fatal
);
359 orgate_dev
= DEVICE(orgate
);
360 qdev_realize(orgate_dev
, NULL
, &error_fatal
);
361 qdev_connect_gpio_out(orgate_dev
, 0,
362 qdev_get_gpio_in(armv7m
, spi_irqno
[i
]));
363 for (j
= 0; j
< 2; j
++) {
364 sysbus_create_simple(TYPE_PL022
, spibase
[2 * i
+ j
],
365 qdev_get_gpio_in(orgate_dev
, j
));
368 for (i
= 0; i
< 4; i
++) {
369 static const hwaddr i2cbase
[] = {0x40022000, /* Touch */
370 0x40023000, /* Audio */
371 0x40029000, /* Shield0 */
372 0x4002a000}; /* Shield1 */
373 sysbus_create_simple(TYPE_ARM_SBCON_I2C
, i2cbase
[i
], NULL
);
375 create_unimplemented_device("i2s", 0x40024000, 0x400);
377 /* In hardware this is a LAN9220; the LAN9118 is software compatible
378 * except that it doesn't support the checksum-offload feature.
380 lan9118_init(&nd_table
[0], 0x40200000,
381 qdev_get_gpio_in(armv7m
,
382 mmc
->fpga_type
== FPGA_AN385
? 13 : 47));
384 system_clock_scale
= NANOSECONDS_PER_SECOND
/ SYSCLK_FRQ
;
386 armv7m_load_kernel(ARM_CPU(first_cpu
), machine
->kernel_filename
,
390 static void mps2_class_init(ObjectClass
*oc
, void *data
)
392 MachineClass
*mc
= MACHINE_CLASS(oc
);
394 mc
->init
= mps2_common_init
;
396 mc
->default_ram_size
= 16 * MiB
;
397 mc
->default_ram_id
= "mps.ram";
400 static void mps2_an385_class_init(ObjectClass
*oc
, void *data
)
402 MachineClass
*mc
= MACHINE_CLASS(oc
);
403 MPS2MachineClass
*mmc
= MPS2_MACHINE_CLASS(oc
);
405 mc
->desc
= "ARM MPS2 with AN385 FPGA image for Cortex-M3";
406 mmc
->fpga_type
= FPGA_AN385
;
407 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-m3");
408 mmc
->scc_id
= 0x41043850;
411 static void mps2_an511_class_init(ObjectClass
*oc
, void *data
)
413 MachineClass
*mc
= MACHINE_CLASS(oc
);
414 MPS2MachineClass
*mmc
= MPS2_MACHINE_CLASS(oc
);
416 mc
->desc
= "ARM MPS2 with AN511 DesignStart FPGA image for Cortex-M3";
417 mmc
->fpga_type
= FPGA_AN511
;
418 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-m3");
419 mmc
->scc_id
= 0x41045110;
422 static const TypeInfo mps2_info
= {
423 .name
= TYPE_MPS2_MACHINE
,
424 .parent
= TYPE_MACHINE
,
426 .instance_size
= sizeof(MPS2MachineState
),
427 .class_size
= sizeof(MPS2MachineClass
),
428 .class_init
= mps2_class_init
,
431 static const TypeInfo mps2_an385_info
= {
432 .name
= TYPE_MPS2_AN385_MACHINE
,
433 .parent
= TYPE_MPS2_MACHINE
,
434 .class_init
= mps2_an385_class_init
,
437 static const TypeInfo mps2_an511_info
= {
438 .name
= TYPE_MPS2_AN511_MACHINE
,
439 .parent
= TYPE_MPS2_MACHINE
,
440 .class_init
= mps2_an511_class_init
,
443 static void mps2_machine_init(void)
445 type_register_static(&mps2_info
);
446 type_register_static(&mps2_an385_info
);
447 type_register_static(&mps2_an511_info
);
450 type_init(mps2_machine_init
);