target/microblaze/cpu.c

   1 /*
   2  * QEMU MicroBlaze CPU
   3  *
   4  * Copyright (c) 2009 Edgar E. Iglesias
   5  * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
   6  * Copyright (c) 2012 SUSE LINUX Products GmbH
   7  * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2.1 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see
  21  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  22  */
  23
  24 #include "qemu/osdep.h"
  25 #include "qapi/error.h"
  26 #include "cpu.h"
  27 #include "qemu/module.h"
  28 #include "hw/qdev-properties.h"
  29 #include "exec/exec-all.h"
  30 #include "fpu/softfloat-helpers.h"
  31
  32 static const struct {
  33     const char *name;
  34     uint8_t version_id;
  35 } mb_cpu_lookup[] = {
  36     /* These key value are as per MBV field in PVR0 */
  37     {"5.00.a", 0x01},
  38     {"5.00.b", 0x02},
  39     {"5.00.c", 0x03},
  40     {"6.00.a", 0x04},
  41     {"6.00.b", 0x06},
  42     {"7.00.a", 0x05},
  43     {"7.00.b", 0x07},
  44     {"7.10.a", 0x08},
  45     {"7.10.b", 0x09},
  46     {"7.10.c", 0x0a},
  47     {"7.10.d", 0x0b},
  48     {"7.20.a", 0x0c},
  49     {"7.20.b", 0x0d},
  50     {"7.20.c", 0x0e},
  51     {"7.20.d", 0x0f},
  52     {"7.30.a", 0x10},
  53     {"7.30.b", 0x11},
  54     {"8.00.a", 0x12},
  55     {"8.00.b", 0x13},
  56     {"8.10.a", 0x14},
  57     {"8.20.a", 0x15},
  58     {"8.20.b", 0x16},
  59     {"8.30.a", 0x17},
  60     {"8.40.a", 0x18},
  61     {"8.40.b", 0x19},
  62     {"8.50.a", 0x1A},
  63     {"9.0", 0x1B},
  64     {"9.1", 0x1D},
  65     {"9.2", 0x1F},
  66     {"9.3", 0x20},
  67     {"9.4", 0x21},
  68     {"9.5", 0x22},
  69     {"9.6", 0x23},
  70     {"10.0", 0x24},
  71     {NULL, 0},
  72 };
  73
  74 /* If no specific version gets selected, default to the following.  */
  75 #define DEFAULT_CPU_VERSION "10.0"
  76
  77 static void mb_cpu_set_pc(CPUState *cs, vaddr value)
  78 {
  79     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
  80
  81     cpu->env.pc = value;
  82     /* Ensure D_FLAG and IMM_FLAG are clear for the new PC */
  83     cpu->env.iflags = 0;
  84 }
  85
  86 static void mb_cpu_synchronize_from_tb(CPUState *cs,
  87                                        const TranslationBlock *tb)
  88 {
  89     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
  90
  91     cpu->env.pc = tb->pc;
  92     cpu->env.iflags = tb->flags & IFLAGS_TB_MASK;
  93 }
  94
  95 static bool mb_cpu_has_work(CPUState *cs)
  96 {
  97     return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
  98 }
  99
 100 #ifndef CONFIG_USER_ONLY
 101 static void mb_cpu_ns_axi_dp(void *opaque, int irq, int level)
 102 {
 103     MicroBlazeCPU *cpu = opaque;
 104     bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_DP_MASK;
 105
 106     cpu->ns_axi_dp = level & en;
 107 }
 108
 109 static void mb_cpu_ns_axi_ip(void *opaque, int irq, int level)
 110 {
 111     MicroBlazeCPU *cpu = opaque;
 112     bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_IP_MASK;
 113
 114     cpu->ns_axi_ip = level & en;
 115 }
 116
 117 static void mb_cpu_ns_axi_dc(void *opaque, int irq, int level)
 118 {
 119     MicroBlazeCPU *cpu = opaque;
 120     bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_DC_MASK;
 121
 122     cpu->ns_axi_dc = level & en;
 123 }
 124
 125 static void mb_cpu_ns_axi_ic(void *opaque, int irq, int level)
 126 {
 127     MicroBlazeCPU *cpu = opaque;
 128     bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_IC_MASK;
 129
 130     cpu->ns_axi_ic = level & en;
 131 }
 132
 133 static void microblaze_cpu_set_irq(void *opaque, int irq, int level)
 134 {
 135     MicroBlazeCPU *cpu = opaque;
 136     CPUState *cs = CPU(cpu);
 137     int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
 138
 139     if (level) {
 140         cpu_interrupt(cs, type);
 141     } else {
 142         cpu_reset_interrupt(cs, type);
 143     }
 144 }
 145 #endif
 146
 147 static void mb_cpu_reset(DeviceState *dev)
 148 {
 149     CPUState *s = CPU(dev);
 150     MicroBlazeCPU *cpu = MICROBLAZE_CPU(s);
 151     MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu);
 152     CPUMBState *env = &cpu->env;
 153
 154     mcc->parent_reset(dev);
 155
 156     memset(env, 0, offsetof(CPUMBState, end_reset_fields));
 157     env->res_addr = RES_ADDR_NONE;
 158
 159     /* Disable stack protector.  */
 160     env->shr = ~0;
 161
 162     env->pc = cpu->cfg.base_vectors;
 163
 164 #if defined(CONFIG_USER_ONLY)
 165     /* start in user mode with interrupts enabled.  */
 166     mb_cpu_write_msr(env, MSR_EE | MSR_IE | MSR_VM | MSR_UM);
 167 #else
 168     mb_cpu_write_msr(env, 0);
 169     mmu_init(&env->mmu);
 170 #endif
 171 }
 172
 173 static void mb_disas_set_info(CPUState *cpu, disassemble_info *info)
 174 {
 175     info->mach = bfd_arch_microblaze;
 176     info->print_insn = print_insn_microblaze;
 177 }
 178
 179 static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
 180 {
 181     CPUState *cs = CPU(dev);
 182     MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
 183     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
 184     uint8_t version_code = 0;
 185     const char *version;
 186     int i = 0;
 187     Error *local_err = NULL;
 188
 189     cpu_exec_realizefn(cs, &local_err);
 190     if (local_err != NULL) {
 191         error_propagate(errp, local_err);
 192         return;
 193     }
 194
 195     if (cpu->cfg.addr_size < 32 || cpu->cfg.addr_size > 64) {
 196         error_setg(errp, "addr-size %d is out of range (32 - 64)",
 197                    cpu->cfg.addr_size);
 198         return;
 199     }
 200
 201     qemu_init_vcpu(cs);
 202
 203     version = cpu->cfg.version ? cpu->cfg.version : DEFAULT_CPU_VERSION;
 204     for (i = 0; mb_cpu_lookup[i].name && version; i++) {
 205         if (strcmp(mb_cpu_lookup[i].name, version) == 0) {
 206             version_code = mb_cpu_lookup[i].version_id;
 207             break;
 208         }
 209     }
 210
 211     if (!version_code) {
 212         qemu_log("Invalid MicroBlaze version number: %s\n", cpu->cfg.version);
 213     }
 214
 215     cpu->cfg.pvr_regs[0] =
 216         (PVR0_USE_EXC_MASK |
 217          PVR0_USE_ICACHE_MASK |
 218          PVR0_USE_DCACHE_MASK |
 219          (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
 220          (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
 221          (cpu->cfg.use_hw_mul ? PVR0_USE_HW_MUL_MASK : 0) |
 222          (cpu->cfg.use_barrel ? PVR0_USE_BARREL_MASK : 0) |
 223          (cpu->cfg.use_div ? PVR0_USE_DIV_MASK : 0) |
 224          (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) |
 225          (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
 226          (version_code << PVR0_VERSION_SHIFT) |
 227          (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0) |
 228          cpu->cfg.pvr_user1);
 229
 230     cpu->cfg.pvr_regs[1] = cpu->cfg.pvr_user2;
 231
 232     cpu->cfg.pvr_regs[2] =
 233         (PVR2_D_OPB_MASK |
 234          PVR2_D_LMB_MASK |
 235          PVR2_I_OPB_MASK |
 236          PVR2_I_LMB_MASK |
 237          PVR2_FPU_EXC_MASK |
 238          (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
 239          (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) |
 240          (cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) |
 241          (cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) |
 242          (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) |
 243          (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) |
 244          (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0) |
 245          (cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0) |
 246          (cpu->cfg.dopb_bus_exception ? PVR2_DOPB_BUS_EXC_MASK : 0) |
 247          (cpu->cfg.iopb_bus_exception ? PVR2_IOPB_BUS_EXC_MASK : 0) |
 248          (cpu->cfg.div_zero_exception ? PVR2_DIV_ZERO_EXC_MASK : 0) |
 249          (cpu->cfg.illegal_opcode_exception ? PVR2_ILL_OPCODE_EXC_MASK : 0) |
 250          (cpu->cfg.unaligned_exceptions ? PVR2_UNALIGNED_EXC_MASK : 0) |
 251          (cpu->cfg.opcode_0_illegal ? PVR2_OPCODE_0x0_ILL_MASK : 0));
 252
 253     cpu->cfg.pvr_regs[5] |=
 254         cpu->cfg.dcache_writeback ? PVR5_DCACHE_WRITEBACK_MASK : 0;
 255
 256     cpu->cfg.pvr_regs[10] =
 257         (0x0c000000 | /* Default to spartan 3a dsp family.  */
 258          (cpu->cfg.addr_size - 32) << PVR10_ASIZE_SHIFT);
 259
 260     cpu->cfg.pvr_regs[11] = ((cpu->cfg.use_mmu ? PVR11_USE_MMU : 0) |
 261                              16 << 17);
 262
 263     cpu->cfg.mmu = 3;
 264     cpu->cfg.mmu_tlb_access = 3;
 265     cpu->cfg.mmu_zones = 16;
 266     cpu->cfg.addr_mask = MAKE_64BIT_MASK(0, cpu->cfg.addr_size);
 267
 268     mcc->parent_realize(dev, errp);
 269 }
 270
 271 static void mb_cpu_initfn(Object *obj)
 272 {
 273     MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj);
 274     CPUMBState *env = &cpu->env;
 275
 276     cpu_set_cpustate_pointers(cpu);
 277
 278     set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
 279
 280 #ifndef CONFIG_USER_ONLY
 281     /* Inbound IRQ and FIR lines */
 282     qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2);
 283     qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dp, "ns_axi_dp", 1);
 284     qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ip, "ns_axi_ip", 1);
 285     qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dc, "ns_axi_dc", 1);
 286     qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ic, "ns_axi_ic", 1);
 287 #endif
 288 }
 289
 290 static Property mb_properties[] = {
 291     DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0),
 292     DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot,
 293                      false),
 294     /*
 295      * This is the C_ADDR_SIZE synth-time configuration option of the
 296      * MicroBlaze cores. Supported values range between 32 and 64.
 297      *
 298      * When set to > 32, 32bit MicroBlaze can emit load/stores
 299      * with extended addressing.
 300      */
 301     DEFINE_PROP_UINT8("addr-size", MicroBlazeCPU, cfg.addr_size, 32),
 302     /* If use-fpu > 0 - FPU is enabled
 303      * If use-fpu = 2 - Floating point conversion and square root instructions
 304      *                  are enabled
 305      */
 306     DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2),
 307     /* If use-hw-mul > 0 - Multiplier is enabled
 308      * If use-hw-mul = 2 - 64-bit multiplier is enabled
 309      */
 310     DEFINE_PROP_UINT8("use-hw-mul", MicroBlazeCPU, cfg.use_hw_mul, 2),
 311     DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true),
 312     DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true),
 313     DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU, cfg.use_msr_instr, true),
 314     DEFINE_PROP_BOOL("use-pcmp-instr", MicroBlazeCPU, cfg.use_pcmp_instr, true),
 315     DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
 316     /*
 317      * use-non-secure enables/disables the use of the non_secure[3:0] signals.
 318      * It is a bitfield where 1 = non-secure for the following bits and their
 319      * corresponding interfaces:
 320      * 0x1 - M_AXI_DP
 321      * 0x2 - M_AXI_IP
 322      * 0x4 - M_AXI_DC
 323      * 0x8 - M_AXI_IC
 324      */
 325     DEFINE_PROP_UINT8("use-non-secure", MicroBlazeCPU, cfg.use_non_secure, 0),
 326     DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
 327                      false),
 328     DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
 329     /* Enables bus exceptions on failed data accesses (load/stores).  */
 330     DEFINE_PROP_BOOL("dopb-bus-exception", MicroBlazeCPU,
 331                      cfg.dopb_bus_exception, false),
 332     /* Enables bus exceptions on failed instruction fetches.  */
 333     DEFINE_PROP_BOOL("iopb-bus-exception", MicroBlazeCPU,
 334                      cfg.iopb_bus_exception, false),
 335     DEFINE_PROP_BOOL("ill-opcode-exception", MicroBlazeCPU,
 336                      cfg.illegal_opcode_exception, false),
 337     DEFINE_PROP_BOOL("div-zero-exception", MicroBlazeCPU,
 338                      cfg.div_zero_exception, false),
 339     DEFINE_PROP_BOOL("unaligned-exceptions", MicroBlazeCPU,
 340                      cfg.unaligned_exceptions, false),
 341     DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU,
 342                      cfg.opcode_0_illegal, false),
 343     DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
 344     DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
 345     DEFINE_PROP_UINT8("pvr-user1", MicroBlazeCPU, cfg.pvr_user1, 0),
 346     DEFINE_PROP_UINT32("pvr-user2", MicroBlazeCPU, cfg.pvr_user2, 0),
 347     DEFINE_PROP_END_OF_LIST(),
 348 };
 349
 350 static ObjectClass *mb_cpu_class_by_name(const char *cpu_model)
 351 {
 352     return object_class_by_name(TYPE_MICROBLAZE_CPU);
 353 }
 354
 355 #include "hw/core/tcg-cpu-ops.h"
 356
 357 static struct TCGCPUOps mb_tcg_ops = {
 358     .initialize = mb_tcg_init,
 359     .synchronize_from_tb = mb_cpu_synchronize_from_tb,
 360     .cpu_exec_interrupt = mb_cpu_exec_interrupt,
 361     .tlb_fill = mb_cpu_tlb_fill,
 362
 363 #ifndef CONFIG_USER_ONLY
 364     .do_interrupt = mb_cpu_do_interrupt,
 365     .do_transaction_failed = mb_cpu_transaction_failed,
 366     .do_unaligned_access = mb_cpu_do_unaligned_access,
 367 #endif /* !CONFIG_USER_ONLY */
 368 };
 369
 370 static void mb_cpu_class_init(ObjectClass *oc, void *data)
 371 {
 372     DeviceClass *dc = DEVICE_CLASS(oc);
 373     CPUClass *cc = CPU_CLASS(oc);
 374     MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc);
 375
 376     device_class_set_parent_realize(dc, mb_cpu_realizefn,
 377                                     &mcc->parent_realize);
 378     device_class_set_parent_reset(dc, mb_cpu_reset, &mcc->parent_reset);
 379
 380     cc->class_by_name = mb_cpu_class_by_name;
 381     cc->has_work = mb_cpu_has_work;
 382
 383     cc->dump_state = mb_cpu_dump_state;
 384     cc->set_pc = mb_cpu_set_pc;
 385     cc->gdb_read_register = mb_cpu_gdb_read_register;
 386     cc->gdb_write_register = mb_cpu_gdb_write_register;
 387
 388 #ifndef CONFIG_USER_ONLY
 389     cc->get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug;
 390     dc->vmsd = &vmstate_mb_cpu;
 391 #endif
 392     device_class_set_props(dc, mb_properties);
 393     cc->gdb_num_core_regs = 32 + 27;
 394
 395     cc->disas_set_info = mb_disas_set_info;
 396     cc->tcg_ops = &mb_tcg_ops;
 397 }
 398
 399 static const TypeInfo mb_cpu_type_info = {
 400     .name = TYPE_MICROBLAZE_CPU,
 401     .parent = TYPE_CPU,
 402     .instance_size = sizeof(MicroBlazeCPU),
 403     .instance_init = mb_cpu_initfn,
 404     .class_size = sizeof(MicroBlazeCPUClass),
 405     .class_init = mb_cpu_class_init,
 406 };
 407
 408 static void mb_cpu_register_types(void)
 409 {
 410     type_register_static(&mb_cpu_type_info);
 411 }
 412
 413 type_init(mb_cpu_register_types)