target/arm/cpu64.c

   1 /*
   2  * QEMU AArch64 CPU
   3  *
   4  * Copyright (c) 2013 Linaro Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qapi/error.h"
  23 #include "cpu.h"
  24 #include "qemu-common.h"
  25 #if !defined(CONFIG_USER_ONLY)
  26 #include "hw/loader.h"
  27 #endif
  28 #include "hw/arm/arm.h"
  29 #include "sysemu/sysemu.h"
  30 #include "sysemu/kvm.h"
  31 #include "kvm_arm.h"
  32 #include "qapi/visitor.h"
  33
  34 static inline void set_feature(CPUARMState *env, int feature)
  35 {
  36     env->features |= 1ULL << feature;
  37 }
  38
  39 static inline void unset_feature(CPUARMState *env, int feature)
  40 {
  41     env->features &= ~(1ULL << feature);
  42 }
  43
  44 #ifndef CONFIG_USER_ONLY
  45 static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
  46 {
  47     ARMCPU *cpu = arm_env_get_cpu(env);
  48
  49     /* Number of cores is in [25:24]; otherwise we RAZ */
  50     return (cpu->core_count - 1) << 24;
  51 }
  52 #endif
  53
  54 static const ARMCPRegInfo cortex_a57_a53_cp_reginfo[] = {
  55 #ifndef CONFIG_USER_ONLY
  56     { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
  57       .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
  58       .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
  59       .writefn = arm_cp_write_ignore },
  60     { .name = "L2CTLR",
  61       .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
  62       .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
  63       .writefn = arm_cp_write_ignore },
  64 #endif
  65     { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
  66       .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
  67       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  68     { .name = "L2ECTLR",
  69       .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
  70       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  71     { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
  72       .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
  73       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  74     { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
  75       .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
  76       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  77     { .name = "CPUACTLR",
  78       .cp = 15, .opc1 = 0, .crm = 15,
  79       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
  80     { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
  81       .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
  82       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  83     { .name = "CPUECTLR",
  84       .cp = 15, .opc1 = 1, .crm = 15,
  85       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
  86     { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
  87       .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
  88       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  89     { .name = "CPUMERRSR",
  90       .cp = 15, .opc1 = 2, .crm = 15,
  91       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
  92     { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
  93       .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
  94       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  95     { .name = "L2MERRSR",
  96       .cp = 15, .opc1 = 3, .crm = 15,
  97       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
  98     REGINFO_SENTINEL
  99 };
 100
 101 static void aarch64_a57_initfn(Object *obj)
 102 {
 103     ARMCPU *cpu = ARM_CPU(obj);
 104
 105     cpu->dtb_compatible = "arm,cortex-a57";
 106     set_feature(&cpu->env, ARM_FEATURE_V8);
 107     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 108     set_feature(&cpu->env, ARM_FEATURE_NEON);
 109     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 110     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 111     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 112     set_feature(&cpu->env, ARM_FEATURE_V8_AES);
 113     set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
 114     set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
 115     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
 116     set_feature(&cpu->env, ARM_FEATURE_CRC);
 117     set_feature(&cpu->env, ARM_FEATURE_EL2);
 118     set_feature(&cpu->env, ARM_FEATURE_EL3);
 119     set_feature(&cpu->env, ARM_FEATURE_PMU);
 120     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
 121     cpu->midr = 0x411fd070;
 122     cpu->revidr = 0x00000000;
 123     cpu->reset_fpsid = 0x41034070;
 124     cpu->mvfr0 = 0x10110222;
 125     cpu->mvfr1 = 0x12111111;
 126     cpu->mvfr2 = 0x00000043;
 127     cpu->ctr = 0x8444c004;
 128     cpu->reset_sctlr = 0x00c50838;
 129     cpu->id_pfr0 = 0x00000131;
 130     cpu->id_pfr1 = 0x00011011;
 131     cpu->id_dfr0 = 0x03010066;
 132     cpu->id_afr0 = 0x00000000;
 133     cpu->id_mmfr0 = 0x10101105;
 134     cpu->id_mmfr1 = 0x40000000;
 135     cpu->id_mmfr2 = 0x01260000;
 136     cpu->id_mmfr3 = 0x02102211;
 137     cpu->id_isar0 = 0x02101110;
 138     cpu->id_isar1 = 0x13112111;
 139     cpu->id_isar2 = 0x21232042;
 140     cpu->id_isar3 = 0x01112131;
 141     cpu->id_isar4 = 0x00011142;
 142     cpu->id_isar5 = 0x00011121;
 143     cpu->id_isar6 = 0;
 144     cpu->id_aa64pfr0 = 0x00002222;
 145     cpu->id_aa64dfr0 = 0x10305106;
 146     cpu->pmceid0 = 0x00000000;
 147     cpu->pmceid1 = 0x00000000;
 148     cpu->id_aa64isar0 = 0x00011120;
 149     cpu->id_aa64mmfr0 = 0x00001124;
 150     cpu->dbgdidr = 0x3516d000;
 151     cpu->clidr = 0x0a200023;
 152     cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
 153     cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
 154     cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
 155     cpu->dcz_blocksize = 4; /* 64 bytes */
 156     cpu->gic_num_lrs = 4;
 157     cpu->gic_vpribits = 5;
 158     cpu->gic_vprebits = 5;
 159     define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
 160 }
 161
 162 static void aarch64_a53_initfn(Object *obj)
 163 {
 164     ARMCPU *cpu = ARM_CPU(obj);
 165
 166     cpu->dtb_compatible = "arm,cortex-a53";
 167     set_feature(&cpu->env, ARM_FEATURE_V8);
 168     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 169     set_feature(&cpu->env, ARM_FEATURE_NEON);
 170     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 171     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 172     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 173     set_feature(&cpu->env, ARM_FEATURE_V8_AES);
 174     set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
 175     set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
 176     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
 177     set_feature(&cpu->env, ARM_FEATURE_CRC);
 178     set_feature(&cpu->env, ARM_FEATURE_EL2);
 179     set_feature(&cpu->env, ARM_FEATURE_EL3);
 180     set_feature(&cpu->env, ARM_FEATURE_PMU);
 181     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
 182     cpu->midr = 0x410fd034;
 183     cpu->revidr = 0x00000000;
 184     cpu->reset_fpsid = 0x41034070;
 185     cpu->mvfr0 = 0x10110222;
 186     cpu->mvfr1 = 0x12111111;
 187     cpu->mvfr2 = 0x00000043;
 188     cpu->ctr = 0x84448004; /* L1Ip = VIPT */
 189     cpu->reset_sctlr = 0x00c50838;
 190     cpu->id_pfr0 = 0x00000131;
 191     cpu->id_pfr1 = 0x00011011;
 192     cpu->id_dfr0 = 0x03010066;
 193     cpu->id_afr0 = 0x00000000;
 194     cpu->id_mmfr0 = 0x10101105;
 195     cpu->id_mmfr1 = 0x40000000;
 196     cpu->id_mmfr2 = 0x01260000;
 197     cpu->id_mmfr3 = 0x02102211;
 198     cpu->id_isar0 = 0x02101110;
 199     cpu->id_isar1 = 0x13112111;
 200     cpu->id_isar2 = 0x21232042;
 201     cpu->id_isar3 = 0x01112131;
 202     cpu->id_isar4 = 0x00011142;
 203     cpu->id_isar5 = 0x00011121;
 204     cpu->id_isar6 = 0;
 205     cpu->id_aa64pfr0 = 0x00002222;
 206     cpu->id_aa64dfr0 = 0x10305106;
 207     cpu->id_aa64isar0 = 0x00011120;
 208     cpu->id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
 209     cpu->dbgdidr = 0x3516d000;
 210     cpu->clidr = 0x0a200023;
 211     cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
 212     cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
 213     cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
 214     cpu->dcz_blocksize = 4; /* 64 bytes */
 215     cpu->gic_num_lrs = 4;
 216     cpu->gic_vpribits = 5;
 217     cpu->gic_vprebits = 5;
 218     define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
 219 }
 220
 221 static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name,
 222                                void *opaque, Error **errp)
 223 {
 224     ARMCPU *cpu = ARM_CPU(obj);
 225     visit_type_uint32(v, name, &cpu->sve_max_vq, errp);
 226 }
 227
 228 static void cpu_max_set_sve_vq(Object *obj, Visitor *v, const char *name,
 229                                void *opaque, Error **errp)
 230 {
 231     ARMCPU *cpu = ARM_CPU(obj);
 232     Error *err = NULL;
 233
 234     visit_type_uint32(v, name, &cpu->sve_max_vq, &err);
 235
 236     if (!err && (cpu->sve_max_vq == 0 || cpu->sve_max_vq > ARM_MAX_VQ)) {
 237         error_setg(&err, "unsupported SVE vector length");
 238         error_append_hint(&err, "Valid sve-max-vq in range [1-%d]\n",
 239                           ARM_MAX_VQ);
 240     }
 241     error_propagate(errp, err);
 242 }
 243
 244 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
 245  * otherwise, a CPU with as many features enabled as our emulation supports.
 246  * The version of '-cpu max' for qemu-system-arm is defined in cpu.c;
 247  * this only needs to handle 64 bits.
 248  */
 249 static void aarch64_max_initfn(Object *obj)
 250 {
 251     ARMCPU *cpu = ARM_CPU(obj);
 252
 253     if (kvm_enabled()) {
 254         kvm_arm_set_cpu_features_from_host(cpu);
 255     } else {
 256         aarch64_a57_initfn(obj);
 257 #ifdef CONFIG_USER_ONLY
 258         /* We don't set these in system emulation mode for the moment,
 259          * since we don't correctly set the ID registers to advertise them,
 260          * and in some cases they're only available in AArch64 and not AArch32,
 261          * whereas the architecture requires them to be present in both if
 262          * present in either.
 263          */
 264         set_feature(&cpu->env, ARM_FEATURE_V8_SHA512);
 265         set_feature(&cpu->env, ARM_FEATURE_V8_SHA3);
 266         set_feature(&cpu->env, ARM_FEATURE_V8_SM3);
 267         set_feature(&cpu->env, ARM_FEATURE_V8_SM4);
 268         set_feature(&cpu->env, ARM_FEATURE_V8_ATOMICS);
 269         set_feature(&cpu->env, ARM_FEATURE_V8_RDM);
 270         set_feature(&cpu->env, ARM_FEATURE_V8_DOTPROD);
 271         set_feature(&cpu->env, ARM_FEATURE_V8_FP16);
 272         set_feature(&cpu->env, ARM_FEATURE_V8_FCMA);
 273         set_feature(&cpu->env, ARM_FEATURE_SVE);
 274         /* For usermode -cpu max we can use a larger and more efficient DCZ
 275          * blocksize since we don't have to follow what the hardware does.
 276          */
 277         cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
 278         cpu->dcz_blocksize = 7; /*  512 bytes */
 279 #endif
 280
 281         cpu->sve_max_vq = ARM_MAX_VQ;
 282         object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_vq,
 283                             cpu_max_set_sve_vq, NULL, NULL, &error_fatal);
 284     }
 285 }
 286
 287 typedef struct ARMCPUInfo {
 288     const char *name;
 289     void (*initfn)(Object *obj);
 290     void (*class_init)(ObjectClass *oc, void *data);
 291 } ARMCPUInfo;
 292
 293 static const ARMCPUInfo aarch64_cpus[] = {
 294     { .name = "cortex-a57",         .initfn = aarch64_a57_initfn },
 295     { .name = "cortex-a53",         .initfn = aarch64_a53_initfn },
 296     { .name = "max",                .initfn = aarch64_max_initfn },
 297     { .name = NULL }
 298 };
 299
 300 static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp)
 301 {
 302     ARMCPU *cpu = ARM_CPU(obj);
 303
 304     return arm_feature(&cpu->env, ARM_FEATURE_AARCH64);
 305 }
 306
 307 static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp)
 308 {
 309     ARMCPU *cpu = ARM_CPU(obj);
 310
 311     /* At this time, this property is only allowed if KVM is enabled.  This
 312      * restriction allows us to avoid fixing up functionality that assumes a
 313      * uniform execution state like do_interrupt.
 314      */
 315     if (!kvm_enabled()) {
 316         error_setg(errp, "'aarch64' feature cannot be disabled "
 317                          "unless KVM is enabled");
 318         return;
 319     }
 320
 321     if (value == false) {
 322         unset_feature(&cpu->env, ARM_FEATURE_AARCH64);
 323     } else {
 324         set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 325     }
 326 }
 327
 328 static void aarch64_cpu_initfn(Object *obj)
 329 {
 330     object_property_add_bool(obj, "aarch64", aarch64_cpu_get_aarch64,
 331                              aarch64_cpu_set_aarch64, NULL);
 332     object_property_set_description(obj, "aarch64",
 333                                     "Set on/off to enable/disable aarch64 "
 334                                     "execution state ",
 335                                     NULL);
 336 }
 337
 338 static void aarch64_cpu_finalizefn(Object *obj)
 339 {
 340 }
 341
 342 static void aarch64_cpu_set_pc(CPUState *cs, vaddr value)
 343 {
 344     ARMCPU *cpu = ARM_CPU(cs);
 345     /* It's OK to look at env for the current mode here, because it's
 346      * never possible for an AArch64 TB to chain to an AArch32 TB.
 347      * (Otherwise we would need to use synchronize_from_tb instead.)
 348      */
 349     if (is_a64(&cpu->env)) {
 350         cpu->env.pc = value;
 351     } else {
 352         cpu->env.regs[15] = value;
 353     }
 354 }
 355
 356 static gchar *aarch64_gdb_arch_name(CPUState *cs)
 357 {
 358     return g_strdup("aarch64");
 359 }
 360
 361 static void aarch64_cpu_class_init(ObjectClass *oc, void *data)
 362 {
 363     CPUClass *cc = CPU_CLASS(oc);
 364
 365     cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
 366     cc->set_pc = aarch64_cpu_set_pc;
 367     cc->gdb_read_register = aarch64_cpu_gdb_read_register;
 368     cc->gdb_write_register = aarch64_cpu_gdb_write_register;
 369     cc->gdb_num_core_regs = 34;
 370     cc->gdb_core_xml_file = "aarch64-core.xml";
 371     cc->gdb_arch_name = aarch64_gdb_arch_name;
 372 }
 373
 374 static void aarch64_cpu_register(const ARMCPUInfo *info)
 375 {
 376     TypeInfo type_info = {
 377         .parent = TYPE_AARCH64_CPU,
 378         .instance_size = sizeof(ARMCPU),
 379         .instance_init = info->initfn,
 380         .class_size = sizeof(ARMCPUClass),
 381         .class_init = info->class_init,
 382     };
 383
 384     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
 385     type_register(&type_info);
 386     g_free((void *)type_info.name);
 387 }
 388
 389 static const TypeInfo aarch64_cpu_type_info = {
 390     .name = TYPE_AARCH64_CPU,
 391     .parent = TYPE_ARM_CPU,
 392     .instance_size = sizeof(ARMCPU),
 393     .instance_init = aarch64_cpu_initfn,
 394     .instance_finalize = aarch64_cpu_finalizefn,
 395     .abstract = true,
 396     .class_size = sizeof(AArch64CPUClass),
 397     .class_init = aarch64_cpu_class_init,
 398 };
 399
 400 static void aarch64_cpu_register_types(void)
 401 {
 402     const ARMCPUInfo *info = aarch64_cpus;
 403
 404     type_register_static(&aarch64_cpu_type_info);
 405
 406     while (info->name) {
 407         aarch64_cpu_register(info);
 408         info++;
 409     }
 410 }
 411
 412 type_init(aarch64_cpu_register_types)
 413
 414 /* The manual says that when SVE is enabled and VQ is widened the
 415  * implementation is allowed to zero the previously inaccessible
 416  * portion of the registers.  The corollary to that is that when
 417  * SVE is enabled and VQ is narrowed we are also allowed to zero
 418  * the now inaccessible portion of the registers.
 419  *
 420  * The intent of this is that no predicate bit beyond VQ is ever set.
 421  * Which means that some operations on predicate registers themselves
 422  * may operate on full uint64_t or even unrolled across the maximum
 423  * uint64_t[4].  Performing 4 bits of host arithmetic unconditionally
 424  * may well be cheaper than conditionals to restrict the operation
 425  * to the relevant portion of a uint16_t[16].
 426  *
 427  * TODO: Need to call this for changes to the real system registers
 428  * and EL state changes.
 429  */
 430 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq)
 431 {
 432     int i, j;
 433     uint64_t pmask;
 434
 435     assert(vq >= 1 && vq <= ARM_MAX_VQ);
 436     assert(vq <= arm_env_get_cpu(env)->sve_max_vq);
 437
 438     /* Zap the high bits of the zregs.  */
 439     for (i = 0; i < 32; i++) {
 440         memset(&env->vfp.zregs[i].d[2 * vq], 0, 16 * (ARM_MAX_VQ - vq));
 441     }
 442
 443     /* Zap the high bits of the pregs and ffr.  */
 444     pmask = 0;
 445     if (vq & 3) {
 446         pmask = ~(-1ULL << (16 * (vq & 3)));
 447     }
 448     for (j = vq / 4; j < ARM_MAX_VQ / 4; j++) {
 449         for (i = 0; i < 17; ++i) {
 450             env->vfp.pregs[i].p[j] &= pmask;
 451         }
 452         pmask = 0;
 453     }
 454 }