4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
21 #include "qemu/osdep.h"
22 #include "target/arm/idau.h"
23 #include "qemu/error-report.h"
24 #include "qapi/error.h"
26 #include "internals.h"
27 #include "qemu-common.h"
28 #include "exec/exec-all.h"
29 #include "hw/qdev-properties.h"
30 #if !defined(CONFIG_USER_ONLY)
31 #include "hw/loader.h"
33 #include "hw/arm/arm.h"
34 #include "sysemu/sysemu.h"
35 #include "sysemu/hw_accel.h"
37 #include "disas/capstone.h"
38 #include "fpu/softfloat.h"
40 static void arm_cpu_set_pc(CPUState
*cs
, vaddr value
)
42 ARMCPU
*cpu
= ARM_CPU(cs
);
44 cpu
->env
.regs
[15] = value
;
47 static bool arm_cpu_has_work(CPUState
*cs
)
49 ARMCPU
*cpu
= ARM_CPU(cs
);
51 return (cpu
->power_state
!= PSCI_OFF
)
52 && cs
->interrupt_request
&
53 (CPU_INTERRUPT_FIQ
| CPU_INTERRUPT_HARD
54 | CPU_INTERRUPT_VFIQ
| CPU_INTERRUPT_VIRQ
55 | CPU_INTERRUPT_EXITTB
);
58 void arm_register_pre_el_change_hook(ARMCPU
*cpu
, ARMELChangeHookFn
*hook
,
61 ARMELChangeHook
*entry
= g_new0(ARMELChangeHook
, 1);
64 entry
->opaque
= opaque
;
66 QLIST_INSERT_HEAD(&cpu
->pre_el_change_hooks
, entry
, node
);
69 void arm_register_el_change_hook(ARMCPU
*cpu
, ARMELChangeHookFn
*hook
,
72 ARMELChangeHook
*entry
= g_new0(ARMELChangeHook
, 1);
75 entry
->opaque
= opaque
;
77 QLIST_INSERT_HEAD(&cpu
->el_change_hooks
, entry
, node
);
80 static void cp_reg_reset(gpointer key
, gpointer value
, gpointer opaque
)
82 /* Reset a single ARMCPRegInfo register */
83 ARMCPRegInfo
*ri
= value
;
86 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
)) {
91 ri
->resetfn(&cpu
->env
, ri
);
95 /* A zero offset is never possible as it would be regs[0]
96 * so we use it to indicate that reset is being handled elsewhere.
97 * This is basically only used for fields in non-core coprocessors
98 * (like the pxa2xx ones).
100 if (!ri
->fieldoffset
) {
104 if (cpreg_field_is_64bit(ri
)) {
105 CPREG_FIELD64(&cpu
->env
, ri
) = ri
->resetvalue
;
107 CPREG_FIELD32(&cpu
->env
, ri
) = ri
->resetvalue
;
111 static void cp_reg_check_reset(gpointer key
, gpointer value
, gpointer opaque
)
113 /* Purely an assertion check: we've already done reset once,
114 * so now check that running the reset for the cpreg doesn't
115 * change its value. This traps bugs where two different cpregs
116 * both try to reset the same state field but to different values.
118 ARMCPRegInfo
*ri
= value
;
119 ARMCPU
*cpu
= opaque
;
120 uint64_t oldvalue
, newvalue
;
122 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
| ARM_CP_NO_RAW
)) {
126 oldvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
127 cp_reg_reset(key
, value
, opaque
);
128 newvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
129 assert(oldvalue
== newvalue
);
132 /* CPUClass::reset() */
133 static void arm_cpu_reset(CPUState
*s
)
135 ARMCPU
*cpu
= ARM_CPU(s
);
136 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(cpu
);
137 CPUARMState
*env
= &cpu
->env
;
139 acc
->parent_reset(s
);
141 memset(env
, 0, offsetof(CPUARMState
, end_reset_fields
));
143 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_reset
, cpu
);
144 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_check_reset
, cpu
);
146 env
->vfp
.xregs
[ARM_VFP_FPSID
] = cpu
->reset_fpsid
;
147 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = cpu
->mvfr0
;
148 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = cpu
->mvfr1
;
149 env
->vfp
.xregs
[ARM_VFP_MVFR2
] = cpu
->mvfr2
;
151 cpu
->power_state
= cpu
->start_powered_off
? PSCI_OFF
: PSCI_ON
;
152 s
->halted
= cpu
->start_powered_off
;
154 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
155 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
158 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
159 /* 64 bit CPUs always start in 64 bit mode */
161 #if defined(CONFIG_USER_ONLY)
162 env
->pstate
= PSTATE_MODE_EL0t
;
163 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
164 env
->cp15
.sctlr_el
[1] |= SCTLR_UCT
| SCTLR_UCI
| SCTLR_DZE
;
165 /* and to the FP/Neon instructions */
166 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 2, 3);
167 /* and to the SVE instructions */
168 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 16, 2, 3);
169 env
->cp15
.cptr_el
[3] |= CPTR_EZ
;
170 /* with maximum vector length */
171 env
->vfp
.zcr_el
[1] = cpu
->sve_max_vq
- 1;
172 env
->vfp
.zcr_el
[2] = env
->vfp
.zcr_el
[1];
173 env
->vfp
.zcr_el
[3] = env
->vfp
.zcr_el
[1];
175 /* Reset into the highest available EL */
176 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
177 env
->pstate
= PSTATE_MODE_EL3h
;
178 } else if (arm_feature(env
, ARM_FEATURE_EL2
)) {
179 env
->pstate
= PSTATE_MODE_EL2h
;
181 env
->pstate
= PSTATE_MODE_EL1h
;
183 env
->pc
= cpu
->rvbar
;
186 #if defined(CONFIG_USER_ONLY)
187 /* Userspace expects access to cp10 and cp11 for FP/Neon */
188 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 4, 0xf);
192 #if defined(CONFIG_USER_ONLY)
193 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
194 /* For user mode we must enable access to coprocessors */
195 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
196 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
197 env
->cp15
.c15_cpar
= 3;
198 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
199 env
->cp15
.c15_cpar
= 1;
202 /* SVC mode with interrupts disabled. */
203 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
;
204 env
->daif
= PSTATE_D
| PSTATE_A
| PSTATE_I
| PSTATE_F
;
206 if (arm_feature(env
, ARM_FEATURE_M
)) {
207 uint32_t initial_msp
; /* Loaded from 0x0 */
208 uint32_t initial_pc
; /* Loaded from 0x4 */
212 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
213 env
->v7m
.secure
= true;
215 /* This bit resets to 0 if security is supported, but 1 if
216 * it is not. The bit is not present in v7M, but we set it
217 * here so we can avoid having to make checks on it conditional
218 * on ARM_FEATURE_V8 (we don't let the guest see the bit).
220 env
->v7m
.aircr
= R_V7M_AIRCR_BFHFNMINS_MASK
;
223 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends
224 * that it resets to 1, so QEMU always does that rather than making
225 * it dependent on CPU model. In v8M it is RES1.
227 env
->v7m
.ccr
[M_REG_NS
] = R_V7M_CCR_STKALIGN_MASK
;
228 env
->v7m
.ccr
[M_REG_S
] = R_V7M_CCR_STKALIGN_MASK
;
229 if (arm_feature(env
, ARM_FEATURE_V8
)) {
230 /* in v8M the NONBASETHRDENA bit [0] is RES1 */
231 env
->v7m
.ccr
[M_REG_NS
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
232 env
->v7m
.ccr
[M_REG_S
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
234 if (!arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
235 env
->v7m
.ccr
[M_REG_NS
] |= R_V7M_CCR_UNALIGN_TRP_MASK
;
236 env
->v7m
.ccr
[M_REG_S
] |= R_V7M_CCR_UNALIGN_TRP_MASK
;
239 /* Unlike A/R profile, M profile defines the reset LR value */
240 env
->regs
[14] = 0xffffffff;
242 env
->v7m
.vecbase
[M_REG_S
] = cpu
->init_svtor
& 0xffffff80;
244 /* Load the initial SP and PC from offset 0 and 4 in the vector table */
245 vecbase
= env
->v7m
.vecbase
[env
->v7m
.secure
];
246 rom
= rom_ptr(vecbase
, 8);
248 /* Address zero is covered by ROM which hasn't yet been
249 * copied into physical memory.
251 initial_msp
= ldl_p(rom
);
252 initial_pc
= ldl_p(rom
+ 4);
254 /* Address zero not covered by a ROM blob, or the ROM blob
255 * is in non-modifiable memory and this is a second reset after
256 * it got copied into memory. In the latter case, rom_ptr
257 * will return a NULL pointer and we should use ldl_phys instead.
259 initial_msp
= ldl_phys(s
->as
, vecbase
);
260 initial_pc
= ldl_phys(s
->as
, vecbase
+ 4);
263 env
->regs
[13] = initial_msp
& 0xFFFFFFFC;
264 env
->regs
[15] = initial_pc
& ~1;
265 env
->thumb
= initial_pc
& 1;
268 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
269 * executing as AArch32 then check if highvecs are enabled and
270 * adjust the PC accordingly.
272 if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
273 env
->regs
[15] = 0xFFFF0000;
276 /* M profile requires that reset clears the exclusive monitor;
277 * A profile does not, but clearing it makes more sense than having it
278 * set with an exclusive access on address zero.
280 arm_clear_exclusive(env
);
282 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
285 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
286 if (cpu
->pmsav7_dregion
> 0) {
287 if (arm_feature(env
, ARM_FEATURE_V8
)) {
288 memset(env
->pmsav8
.rbar
[M_REG_NS
], 0,
289 sizeof(*env
->pmsav8
.rbar
[M_REG_NS
])
290 * cpu
->pmsav7_dregion
);
291 memset(env
->pmsav8
.rlar
[M_REG_NS
], 0,
292 sizeof(*env
->pmsav8
.rlar
[M_REG_NS
])
293 * cpu
->pmsav7_dregion
);
294 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
295 memset(env
->pmsav8
.rbar
[M_REG_S
], 0,
296 sizeof(*env
->pmsav8
.rbar
[M_REG_S
])
297 * cpu
->pmsav7_dregion
);
298 memset(env
->pmsav8
.rlar
[M_REG_S
], 0,
299 sizeof(*env
->pmsav8
.rlar
[M_REG_S
])
300 * cpu
->pmsav7_dregion
);
302 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
303 memset(env
->pmsav7
.drbar
, 0,
304 sizeof(*env
->pmsav7
.drbar
) * cpu
->pmsav7_dregion
);
305 memset(env
->pmsav7
.drsr
, 0,
306 sizeof(*env
->pmsav7
.drsr
) * cpu
->pmsav7_dregion
);
307 memset(env
->pmsav7
.dracr
, 0,
308 sizeof(*env
->pmsav7
.dracr
) * cpu
->pmsav7_dregion
);
311 env
->pmsav7
.rnr
[M_REG_NS
] = 0;
312 env
->pmsav7
.rnr
[M_REG_S
] = 0;
313 env
->pmsav8
.mair0
[M_REG_NS
] = 0;
314 env
->pmsav8
.mair0
[M_REG_S
] = 0;
315 env
->pmsav8
.mair1
[M_REG_NS
] = 0;
316 env
->pmsav8
.mair1
[M_REG_S
] = 0;
319 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
320 if (cpu
->sau_sregion
> 0) {
321 memset(env
->sau
.rbar
, 0, sizeof(*env
->sau
.rbar
) * cpu
->sau_sregion
);
322 memset(env
->sau
.rlar
, 0, sizeof(*env
->sau
.rlar
) * cpu
->sau_sregion
);
325 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what
326 * the Cortex-M33 does.
331 set_flush_to_zero(1, &env
->vfp
.standard_fp_status
);
332 set_flush_inputs_to_zero(1, &env
->vfp
.standard_fp_status
);
333 set_default_nan_mode(1, &env
->vfp
.standard_fp_status
);
334 set_float_detect_tininess(float_tininess_before_rounding
,
335 &env
->vfp
.fp_status
);
336 set_float_detect_tininess(float_tininess_before_rounding
,
337 &env
->vfp
.standard_fp_status
);
338 set_float_detect_tininess(float_tininess_before_rounding
,
339 &env
->vfp
.fp_status_f16
);
340 #ifndef CONFIG_USER_ONLY
342 kvm_arm_reset_vcpu(cpu
);
346 hw_breakpoint_update_all(cpu
);
347 hw_watchpoint_update_all(cpu
);
350 bool arm_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
352 CPUClass
*cc
= CPU_GET_CLASS(cs
);
353 CPUARMState
*env
= cs
->env_ptr
;
354 uint32_t cur_el
= arm_current_el(env
);
355 bool secure
= arm_is_secure(env
);
360 if (interrupt_request
& CPU_INTERRUPT_FIQ
) {
362 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
363 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
364 cs
->exception_index
= excp_idx
;
365 env
->exception
.target_el
= target_el
;
366 cc
->do_interrupt(cs
);
370 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
372 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
373 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
374 cs
->exception_index
= excp_idx
;
375 env
->exception
.target_el
= target_el
;
376 cc
->do_interrupt(cs
);
380 if (interrupt_request
& CPU_INTERRUPT_VIRQ
) {
381 excp_idx
= EXCP_VIRQ
;
383 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
384 cs
->exception_index
= excp_idx
;
385 env
->exception
.target_el
= target_el
;
386 cc
->do_interrupt(cs
);
390 if (interrupt_request
& CPU_INTERRUPT_VFIQ
) {
391 excp_idx
= EXCP_VFIQ
;
393 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
394 cs
->exception_index
= excp_idx
;
395 env
->exception
.target_el
= target_el
;
396 cc
->do_interrupt(cs
);
404 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
405 static bool arm_v7m_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
407 CPUClass
*cc
= CPU_GET_CLASS(cs
);
408 ARMCPU
*cpu
= ARM_CPU(cs
);
409 CPUARMState
*env
= &cpu
->env
;
412 /* ARMv7-M interrupt masking works differently than -A or -R.
413 * There is no FIQ/IRQ distinction. Instead of I and F bits
414 * masking FIQ and IRQ interrupts, an exception is taken only
415 * if it is higher priority than the current execution priority
416 * (which depends on state like BASEPRI, FAULTMASK and the
417 * currently active exception).
419 if (interrupt_request
& CPU_INTERRUPT_HARD
420 && (armv7m_nvic_can_take_pending_exception(env
->nvic
))) {
421 cs
->exception_index
= EXCP_IRQ
;
422 cc
->do_interrupt(cs
);
429 #ifndef CONFIG_USER_ONLY
430 static void arm_cpu_set_irq(void *opaque
, int irq
, int level
)
432 ARMCPU
*cpu
= opaque
;
433 CPUARMState
*env
= &cpu
->env
;
434 CPUState
*cs
= CPU(cpu
);
435 static const int mask
[] = {
436 [ARM_CPU_IRQ
] = CPU_INTERRUPT_HARD
,
437 [ARM_CPU_FIQ
] = CPU_INTERRUPT_FIQ
,
438 [ARM_CPU_VIRQ
] = CPU_INTERRUPT_VIRQ
,
439 [ARM_CPU_VFIQ
] = CPU_INTERRUPT_VFIQ
445 assert(arm_feature(env
, ARM_FEATURE_EL2
));
450 cpu_interrupt(cs
, mask
[irq
]);
452 cpu_reset_interrupt(cs
, mask
[irq
]);
456 g_assert_not_reached();
460 static void arm_cpu_kvm_set_irq(void *opaque
, int irq
, int level
)
463 ARMCPU
*cpu
= opaque
;
464 CPUState
*cs
= CPU(cpu
);
465 int kvm_irq
= KVM_ARM_IRQ_TYPE_CPU
<< KVM_ARM_IRQ_TYPE_SHIFT
;
469 kvm_irq
|= KVM_ARM_IRQ_CPU_IRQ
;
472 kvm_irq
|= KVM_ARM_IRQ_CPU_FIQ
;
475 g_assert_not_reached();
477 kvm_irq
|= cs
->cpu_index
<< KVM_ARM_IRQ_VCPU_SHIFT
;
478 kvm_set_irq(kvm_state
, kvm_irq
, level
? 1 : 0);
482 static bool arm_cpu_virtio_is_big_endian(CPUState
*cs
)
484 ARMCPU
*cpu
= ARM_CPU(cs
);
485 CPUARMState
*env
= &cpu
->env
;
487 cpu_synchronize_state(cs
);
488 return arm_cpu_data_is_big_endian(env
);
493 static inline void set_feature(CPUARMState
*env
, int feature
)
495 env
->features
|= 1ULL << feature
;
498 static inline void unset_feature(CPUARMState
*env
, int feature
)
500 env
->features
&= ~(1ULL << feature
);
504 print_insn_thumb1(bfd_vma pc
, disassemble_info
*info
)
506 return print_insn_arm(pc
| 1, info
);
509 static void arm_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
511 ARMCPU
*ac
= ARM_CPU(cpu
);
512 CPUARMState
*env
= &ac
->env
;
516 /* We might not be compiled with the A64 disassembler
517 * because it needs a C++ compiler. Leave print_insn
518 * unset in this case to use the caller default behaviour.
520 #if defined(CONFIG_ARM_A64_DIS)
521 info
->print_insn
= print_insn_arm_a64
;
523 info
->cap_arch
= CS_ARCH_ARM64
;
524 info
->cap_insn_unit
= 4;
525 info
->cap_insn_split
= 4;
529 info
->print_insn
= print_insn_thumb1
;
530 info
->cap_insn_unit
= 2;
531 info
->cap_insn_split
= 4;
532 cap_mode
= CS_MODE_THUMB
;
534 info
->print_insn
= print_insn_arm
;
535 info
->cap_insn_unit
= 4;
536 info
->cap_insn_split
= 4;
537 cap_mode
= CS_MODE_ARM
;
539 if (arm_feature(env
, ARM_FEATURE_V8
)) {
540 cap_mode
|= CS_MODE_V8
;
542 if (arm_feature(env
, ARM_FEATURE_M
)) {
543 cap_mode
|= CS_MODE_MCLASS
;
545 info
->cap_arch
= CS_ARCH_ARM
;
546 info
->cap_mode
= cap_mode
;
549 sctlr_b
= arm_sctlr_b(env
);
550 if (bswap_code(sctlr_b
)) {
551 #ifdef TARGET_WORDS_BIGENDIAN
552 info
->endian
= BFD_ENDIAN_LITTLE
;
554 info
->endian
= BFD_ENDIAN_BIG
;
557 info
->flags
&= ~INSN_ARM_BE32
;
558 #ifndef CONFIG_USER_ONLY
560 info
->flags
|= INSN_ARM_BE32
;
565 uint64_t arm_cpu_mp_affinity(int idx
, uint8_t clustersz
)
567 uint32_t Aff1
= idx
/ clustersz
;
568 uint32_t Aff0
= idx
% clustersz
;
569 return (Aff1
<< ARM_AFF1_SHIFT
) | Aff0
;
572 static void arm_cpu_initfn(Object
*obj
)
574 CPUState
*cs
= CPU(obj
);
575 ARMCPU
*cpu
= ARM_CPU(obj
);
577 cs
->env_ptr
= &cpu
->env
;
578 cpu
->cp_regs
= g_hash_table_new_full(g_int_hash
, g_int_equal
,
581 QLIST_INIT(&cpu
->pre_el_change_hooks
);
582 QLIST_INIT(&cpu
->el_change_hooks
);
584 #ifndef CONFIG_USER_ONLY
585 /* Our inbound IRQ and FIQ lines */
587 /* VIRQ and VFIQ are unused with KVM but we add them to maintain
588 * the same interface as non-KVM CPUs.
590 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_kvm_set_irq
, 4);
592 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_set_irq
, 4);
595 cpu
->gt_timer
[GTIMER_PHYS
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
596 arm_gt_ptimer_cb
, cpu
);
597 cpu
->gt_timer
[GTIMER_VIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
598 arm_gt_vtimer_cb
, cpu
);
599 cpu
->gt_timer
[GTIMER_HYP
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
600 arm_gt_htimer_cb
, cpu
);
601 cpu
->gt_timer
[GTIMER_SEC
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
602 arm_gt_stimer_cb
, cpu
);
603 qdev_init_gpio_out(DEVICE(cpu
), cpu
->gt_timer_outputs
,
604 ARRAY_SIZE(cpu
->gt_timer_outputs
));
606 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->gicv3_maintenance_interrupt
,
607 "gicv3-maintenance-interrupt", 1);
608 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->pmu_interrupt
,
612 /* DTB consumers generally don't in fact care what the 'compatible'
613 * string is, so always provide some string and trust that a hypothetical
614 * picky DTB consumer will also provide a helpful error message.
616 cpu
->dtb_compatible
= "qemu,unknown";
617 cpu
->psci_version
= 1; /* By default assume PSCI v0.1 */
618 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_NONE
;
621 cpu
->psci_version
= 2; /* TCG implements PSCI 0.2 */
625 static Property arm_cpu_reset_cbar_property
=
626 DEFINE_PROP_UINT64("reset-cbar", ARMCPU
, reset_cbar
, 0);
628 static Property arm_cpu_reset_hivecs_property
=
629 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU
, reset_hivecs
, false);
631 static Property arm_cpu_rvbar_property
=
632 DEFINE_PROP_UINT64("rvbar", ARMCPU
, rvbar
, 0);
634 static Property arm_cpu_has_el2_property
=
635 DEFINE_PROP_BOOL("has_el2", ARMCPU
, has_el2
, true);
637 static Property arm_cpu_has_el3_property
=
638 DEFINE_PROP_BOOL("has_el3", ARMCPU
, has_el3
, true);
640 static Property arm_cpu_cfgend_property
=
641 DEFINE_PROP_BOOL("cfgend", ARMCPU
, cfgend
, false);
643 /* use property name "pmu" to match other archs and virt tools */
644 static Property arm_cpu_has_pmu_property
=
645 DEFINE_PROP_BOOL("pmu", ARMCPU
, has_pmu
, true);
647 static Property arm_cpu_has_mpu_property
=
648 DEFINE_PROP_BOOL("has-mpu", ARMCPU
, has_mpu
, true);
650 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value,
651 * because the CPU initfn will have already set cpu->pmsav7_dregion to
652 * the right value for that particular CPU type, and we don't want
653 * to override that with an incorrect constant value.
655 static Property arm_cpu_pmsav7_dregion_property
=
656 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU
,
658 qdev_prop_uint32
, uint32_t);
660 /* M profile: initial value of the Secure VTOR */
661 static Property arm_cpu_initsvtor_property
=
662 DEFINE_PROP_UINT32("init-svtor", ARMCPU
, init_svtor
, 0);
664 static void arm_cpu_post_init(Object
*obj
)
666 ARMCPU
*cpu
= ARM_CPU(obj
);
668 /* M profile implies PMSA. We have to do this here rather than
669 * in realize with the other feature-implication checks because
670 * we look at the PMSA bit to see if we should add some properties.
672 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
673 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
676 if (arm_feature(&cpu
->env
, ARM_FEATURE_CBAR
) ||
677 arm_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
)) {
678 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_cbar_property
,
682 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
683 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_hivecs_property
,
687 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
688 qdev_property_add_static(DEVICE(obj
), &arm_cpu_rvbar_property
,
692 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL3
)) {
693 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
694 * prevent "has_el3" from existing on CPUs which cannot support EL3.
696 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el3_property
,
699 #ifndef CONFIG_USER_ONLY
700 object_property_add_link(obj
, "secure-memory",
702 (Object
**)&cpu
->secure_memory
,
703 qdev_prop_allow_set_link_before_realize
,
704 OBJ_PROP_LINK_STRONG
,
709 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL2
)) {
710 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el2_property
,
714 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMU
)) {
715 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_pmu_property
,
719 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMSA
)) {
720 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_mpu_property
,
722 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
723 qdev_property_add_static(DEVICE(obj
),
724 &arm_cpu_pmsav7_dregion_property
,
729 if (arm_feature(&cpu
->env
, ARM_FEATURE_M_SECURITY
)) {
730 object_property_add_link(obj
, "idau", TYPE_IDAU_INTERFACE
, &cpu
->idau
,
731 qdev_prop_allow_set_link_before_realize
,
732 OBJ_PROP_LINK_STRONG
,
734 qdev_property_add_static(DEVICE(obj
), &arm_cpu_initsvtor_property
,
738 qdev_property_add_static(DEVICE(obj
), &arm_cpu_cfgend_property
,
742 static void arm_cpu_finalizefn(Object
*obj
)
744 ARMCPU
*cpu
= ARM_CPU(obj
);
745 ARMELChangeHook
*hook
, *next
;
747 g_hash_table_destroy(cpu
->cp_regs
);
749 QLIST_FOREACH_SAFE(hook
, &cpu
->pre_el_change_hooks
, node
, next
) {
750 QLIST_REMOVE(hook
, node
);
753 QLIST_FOREACH_SAFE(hook
, &cpu
->el_change_hooks
, node
, next
) {
754 QLIST_REMOVE(hook
, node
);
759 static void arm_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
761 CPUState
*cs
= CPU(dev
);
762 ARMCPU
*cpu
= ARM_CPU(dev
);
763 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(dev
);
764 CPUARMState
*env
= &cpu
->env
;
766 Error
*local_err
= NULL
;
768 /* If we needed to query the host kernel for the CPU features
769 * then it's possible that might have failed in the initfn, but
770 * this is the first point where we can report it.
772 if (cpu
->host_cpu_probe_failed
) {
773 if (!kvm_enabled()) {
774 error_setg(errp
, "The 'host' CPU type can only be used with KVM");
776 error_setg(errp
, "Failed to retrieve host CPU features");
781 #ifndef CONFIG_USER_ONLY
782 /* The NVIC and M-profile CPU are two halves of a single piece of
783 * hardware; trying to use one without the other is a command line
784 * error and will result in segfaults if not caught here.
786 if (arm_feature(env
, ARM_FEATURE_M
)) {
788 error_setg(errp
, "This board cannot be used with Cortex-M CPUs");
793 error_setg(errp
, "This board can only be used with Cortex-M CPUs");
799 cpu_exec_realizefn(cs
, &local_err
);
800 if (local_err
!= NULL
) {
801 error_propagate(errp
, local_err
);
805 /* Some features automatically imply others: */
806 if (arm_feature(env
, ARM_FEATURE_V8
)) {
807 set_feature(env
, ARM_FEATURE_V7VE
);
809 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
810 /* v7 Virtualization Extensions. In real hardware this implies
811 * EL2 and also the presence of the Security Extensions.
812 * For QEMU, for backwards-compatibility we implement some
813 * CPUs or CPU configs which have no actual EL2 or EL3 but do
814 * include the various other features that V7VE implies.
815 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
816 * Security Extensions is ARM_FEATURE_EL3.
818 set_feature(env
, ARM_FEATURE_ARM_DIV
);
819 set_feature(env
, ARM_FEATURE_LPAE
);
820 set_feature(env
, ARM_FEATURE_V7
);
822 if (arm_feature(env
, ARM_FEATURE_V7
)) {
823 set_feature(env
, ARM_FEATURE_VAPA
);
824 set_feature(env
, ARM_FEATURE_THUMB2
);
825 set_feature(env
, ARM_FEATURE_MPIDR
);
826 if (!arm_feature(env
, ARM_FEATURE_M
)) {
827 set_feature(env
, ARM_FEATURE_V6K
);
829 set_feature(env
, ARM_FEATURE_V6
);
832 /* Always define VBAR for V7 CPUs even if it doesn't exist in
833 * non-EL3 configs. This is needed by some legacy boards.
835 set_feature(env
, ARM_FEATURE_VBAR
);
837 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
838 set_feature(env
, ARM_FEATURE_V6
);
839 set_feature(env
, ARM_FEATURE_MVFR
);
841 if (arm_feature(env
, ARM_FEATURE_V6
)) {
842 set_feature(env
, ARM_FEATURE_V5
);
843 set_feature(env
, ARM_FEATURE_JAZELLE
);
844 if (!arm_feature(env
, ARM_FEATURE_M
)) {
845 set_feature(env
, ARM_FEATURE_AUXCR
);
848 if (arm_feature(env
, ARM_FEATURE_V5
)) {
849 set_feature(env
, ARM_FEATURE_V4T
);
851 if (arm_feature(env
, ARM_FEATURE_M
)) {
852 set_feature(env
, ARM_FEATURE_THUMB_DIV
);
854 if (arm_feature(env
, ARM_FEATURE_ARM_DIV
)) {
855 set_feature(env
, ARM_FEATURE_THUMB_DIV
);
857 if (arm_feature(env
, ARM_FEATURE_VFP4
)) {
858 set_feature(env
, ARM_FEATURE_VFP3
);
859 set_feature(env
, ARM_FEATURE_VFP_FP16
);
861 if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
862 set_feature(env
, ARM_FEATURE_VFP
);
864 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
865 set_feature(env
, ARM_FEATURE_V7MP
);
866 set_feature(env
, ARM_FEATURE_PXN
);
868 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
869 set_feature(env
, ARM_FEATURE_CBAR
);
871 if (arm_feature(env
, ARM_FEATURE_THUMB2
) &&
872 !arm_feature(env
, ARM_FEATURE_M
)) {
873 set_feature(env
, ARM_FEATURE_THUMB_DSP
);
876 if (arm_feature(env
, ARM_FEATURE_V7
) &&
877 !arm_feature(env
, ARM_FEATURE_M
) &&
878 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
879 /* v7VMSA drops support for the old ARMv5 tiny pages, so we
884 /* For CPUs which might have tiny 1K pages, or which have an
885 * MPU and might have small region sizes, stick with 1K pages.
889 if (!set_preferred_target_page_bits(pagebits
)) {
890 /* This can only ever happen for hotplugging a CPU, or if
891 * the board code incorrectly creates a CPU which it has
892 * promised via minimum_page_size that it will not.
894 error_setg(errp
, "This CPU requires a smaller page size than the "
899 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
900 * We don't support setting cluster ID ([16..23]) (known as Aff2
901 * in later ARM ARM versions), or any of the higher affinity level fields,
902 * so these bits always RAZ.
904 if (cpu
->mp_affinity
== ARM64_AFFINITY_INVALID
) {
905 cpu
->mp_affinity
= arm_cpu_mp_affinity(cs
->cpu_index
,
906 ARM_DEFAULT_CPUS_PER_CLUSTER
);
909 if (cpu
->reset_hivecs
) {
910 cpu
->reset_sctlr
|= (1 << 13);
914 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
915 cpu
->reset_sctlr
|= SCTLR_EE
;
917 cpu
->reset_sctlr
|= SCTLR_B
;
922 /* If the has_el3 CPU property is disabled then we need to disable the
925 unset_feature(env
, ARM_FEATURE_EL3
);
927 /* Disable the security extension feature bits in the processor feature
928 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
930 cpu
->id_pfr1
&= ~0xf0;
931 cpu
->id_aa64pfr0
&= ~0xf000;
935 unset_feature(env
, ARM_FEATURE_EL2
);
939 unset_feature(env
, ARM_FEATURE_PMU
);
940 cpu
->id_aa64dfr0
&= ~0xf00;
943 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
944 /* Disable the hypervisor feature bits in the processor feature
945 * registers if we don't have EL2. These are id_pfr1[15:12] and
946 * id_aa64pfr0_el1[11:8].
948 cpu
->id_aa64pfr0
&= ~0xf00;
949 cpu
->id_pfr1
&= ~0xf000;
952 /* MPU can be configured out of a PMSA CPU either by setting has-mpu
953 * to false or by setting pmsav7-dregion to 0.
956 cpu
->pmsav7_dregion
= 0;
958 if (cpu
->pmsav7_dregion
== 0) {
959 cpu
->has_mpu
= false;
962 if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
963 arm_feature(env
, ARM_FEATURE_V7
)) {
964 uint32_t nr
= cpu
->pmsav7_dregion
;
967 error_setg(errp
, "PMSAv7 MPU #regions invalid %" PRIu32
, nr
);
972 if (arm_feature(env
, ARM_FEATURE_V8
)) {
974 env
->pmsav8
.rbar
[M_REG_NS
] = g_new0(uint32_t, nr
);
975 env
->pmsav8
.rlar
[M_REG_NS
] = g_new0(uint32_t, nr
);
976 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
977 env
->pmsav8
.rbar
[M_REG_S
] = g_new0(uint32_t, nr
);
978 env
->pmsav8
.rlar
[M_REG_S
] = g_new0(uint32_t, nr
);
981 env
->pmsav7
.drbar
= g_new0(uint32_t, nr
);
982 env
->pmsav7
.drsr
= g_new0(uint32_t, nr
);
983 env
->pmsav7
.dracr
= g_new0(uint32_t, nr
);
988 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
989 uint32_t nr
= cpu
->sau_sregion
;
992 error_setg(errp
, "v8M SAU #regions invalid %" PRIu32
, nr
);
997 env
->sau
.rbar
= g_new0(uint32_t, nr
);
998 env
->sau
.rlar
= g_new0(uint32_t, nr
);
1002 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
1003 set_feature(env
, ARM_FEATURE_VBAR
);
1006 register_cp_regs_for_features(cpu
);
1007 arm_cpu_register_gdb_regs_for_features(cpu
);
1009 init_cpreg_list(cpu
);
1011 #ifndef CONFIG_USER_ONLY
1012 if (cpu
->has_el3
|| arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1015 if (!cpu
->secure_memory
) {
1016 cpu
->secure_memory
= cs
->memory
;
1018 cpu_address_space_init(cs
, ARMASIdx_S
, "cpu-secure-memory",
1019 cpu
->secure_memory
);
1023 cpu_address_space_init(cs
, ARMASIdx_NS
, "cpu-memory", cs
->memory
);
1025 /* No core_count specified, default to smp_cpus. */
1026 if (cpu
->core_count
== -1) {
1027 cpu
->core_count
= smp_cpus
;
1034 acc
->parent_realize(dev
, errp
);
1037 static ObjectClass
*arm_cpu_class_by_name(const char *cpu_model
)
1042 const char *cpunamestr
;
1044 cpuname
= g_strsplit(cpu_model
, ",", 1);
1045 cpunamestr
= cpuname
[0];
1046 #ifdef CONFIG_USER_ONLY
1047 /* For backwards compatibility usermode emulation allows "-cpu any",
1048 * which has the same semantics as "-cpu max".
1050 if (!strcmp(cpunamestr
, "any")) {
1054 typename
= g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr
);
1055 oc
= object_class_by_name(typename
);
1056 g_strfreev(cpuname
);
1058 if (!oc
|| !object_class_dynamic_cast(oc
, TYPE_ARM_CPU
) ||
1059 object_class_is_abstract(oc
)) {
1065 /* CPU models. These are not needed for the AArch64 linux-user build. */
1066 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1068 static void arm926_initfn(Object
*obj
)
1070 ARMCPU
*cpu
= ARM_CPU(obj
);
1072 cpu
->dtb_compatible
= "arm,arm926";
1073 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1074 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1075 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1076 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
1077 set_feature(&cpu
->env
, ARM_FEATURE_JAZELLE
);
1078 cpu
->midr
= 0x41069265;
1079 cpu
->reset_fpsid
= 0x41011090;
1080 cpu
->ctr
= 0x1dd20d2;
1081 cpu
->reset_sctlr
= 0x00090078;
1084 static void arm946_initfn(Object
*obj
)
1086 ARMCPU
*cpu
= ARM_CPU(obj
);
1088 cpu
->dtb_compatible
= "arm,arm946";
1089 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1090 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
1091 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1092 cpu
->midr
= 0x41059461;
1093 cpu
->ctr
= 0x0f004006;
1094 cpu
->reset_sctlr
= 0x00000078;
1097 static void arm1026_initfn(Object
*obj
)
1099 ARMCPU
*cpu
= ARM_CPU(obj
);
1101 cpu
->dtb_compatible
= "arm,arm1026";
1102 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1103 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1104 set_feature(&cpu
->env
, ARM_FEATURE_AUXCR
);
1105 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1106 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
1107 set_feature(&cpu
->env
, ARM_FEATURE_JAZELLE
);
1108 cpu
->midr
= 0x4106a262;
1109 cpu
->reset_fpsid
= 0x410110a0;
1110 cpu
->ctr
= 0x1dd20d2;
1111 cpu
->reset_sctlr
= 0x00090078;
1112 cpu
->reset_auxcr
= 1;
1114 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
1115 ARMCPRegInfo ifar
= {
1116 .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
1118 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifar_ns
),
1121 define_one_arm_cp_reg(cpu
, &ifar
);
1125 static void arm1136_r2_initfn(Object
*obj
)
1127 ARMCPU
*cpu
= ARM_CPU(obj
);
1128 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
1129 * older core than plain "arm1136". In particular this does not
1130 * have the v6K features.
1131 * These ID register values are correct for 1136 but may be wrong
1132 * for 1136_r2 (in particular r0p2 does not actually implement most
1133 * of the ID registers).
1136 cpu
->dtb_compatible
= "arm,arm1136";
1137 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
1138 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1139 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1140 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
1141 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
1142 cpu
->midr
= 0x4107b362;
1143 cpu
->reset_fpsid
= 0x410120b4;
1144 cpu
->mvfr0
= 0x11111111;
1145 cpu
->mvfr1
= 0x00000000;
1146 cpu
->ctr
= 0x1dd20d2;
1147 cpu
->reset_sctlr
= 0x00050078;
1148 cpu
->id_pfr0
= 0x111;
1152 cpu
->id_mmfr0
= 0x01130003;
1153 cpu
->id_mmfr1
= 0x10030302;
1154 cpu
->id_mmfr2
= 0x01222110;
1155 cpu
->id_isar0
= 0x00140011;
1156 cpu
->id_isar1
= 0x12002111;
1157 cpu
->id_isar2
= 0x11231111;
1158 cpu
->id_isar3
= 0x01102131;
1159 cpu
->id_isar4
= 0x141;
1160 cpu
->reset_auxcr
= 7;
1163 static void arm1136_initfn(Object
*obj
)
1165 ARMCPU
*cpu
= ARM_CPU(obj
);
1167 cpu
->dtb_compatible
= "arm,arm1136";
1168 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
1169 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
1170 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1171 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1172 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
1173 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
1174 cpu
->midr
= 0x4117b363;
1175 cpu
->reset_fpsid
= 0x410120b4;
1176 cpu
->mvfr0
= 0x11111111;
1177 cpu
->mvfr1
= 0x00000000;
1178 cpu
->ctr
= 0x1dd20d2;
1179 cpu
->reset_sctlr
= 0x00050078;
1180 cpu
->id_pfr0
= 0x111;
1184 cpu
->id_mmfr0
= 0x01130003;
1185 cpu
->id_mmfr1
= 0x10030302;
1186 cpu
->id_mmfr2
= 0x01222110;
1187 cpu
->id_isar0
= 0x00140011;
1188 cpu
->id_isar1
= 0x12002111;
1189 cpu
->id_isar2
= 0x11231111;
1190 cpu
->id_isar3
= 0x01102131;
1191 cpu
->id_isar4
= 0x141;
1192 cpu
->reset_auxcr
= 7;
1195 static void arm1176_initfn(Object
*obj
)
1197 ARMCPU
*cpu
= ARM_CPU(obj
);
1199 cpu
->dtb_compatible
= "arm,arm1176";
1200 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
1201 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1202 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
1203 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1204 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
1205 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
1206 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1207 cpu
->midr
= 0x410fb767;
1208 cpu
->reset_fpsid
= 0x410120b5;
1209 cpu
->mvfr0
= 0x11111111;
1210 cpu
->mvfr1
= 0x00000000;
1211 cpu
->ctr
= 0x1dd20d2;
1212 cpu
->reset_sctlr
= 0x00050078;
1213 cpu
->id_pfr0
= 0x111;
1214 cpu
->id_pfr1
= 0x11;
1215 cpu
->id_dfr0
= 0x33;
1217 cpu
->id_mmfr0
= 0x01130003;
1218 cpu
->id_mmfr1
= 0x10030302;
1219 cpu
->id_mmfr2
= 0x01222100;
1220 cpu
->id_isar0
= 0x0140011;
1221 cpu
->id_isar1
= 0x12002111;
1222 cpu
->id_isar2
= 0x11231121;
1223 cpu
->id_isar3
= 0x01102131;
1224 cpu
->id_isar4
= 0x01141;
1225 cpu
->reset_auxcr
= 7;
1228 static void arm11mpcore_initfn(Object
*obj
)
1230 ARMCPU
*cpu
= ARM_CPU(obj
);
1232 cpu
->dtb_compatible
= "arm,arm11mpcore";
1233 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
1234 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1235 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
1236 set_feature(&cpu
->env
, ARM_FEATURE_MPIDR
);
1237 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1238 cpu
->midr
= 0x410fb022;
1239 cpu
->reset_fpsid
= 0x410120b4;
1240 cpu
->mvfr0
= 0x11111111;
1241 cpu
->mvfr1
= 0x00000000;
1242 cpu
->ctr
= 0x1d192992; /* 32K icache 32K dcache */
1243 cpu
->id_pfr0
= 0x111;
1247 cpu
->id_mmfr0
= 0x01100103;
1248 cpu
->id_mmfr1
= 0x10020302;
1249 cpu
->id_mmfr2
= 0x01222000;
1250 cpu
->id_isar0
= 0x00100011;
1251 cpu
->id_isar1
= 0x12002111;
1252 cpu
->id_isar2
= 0x11221011;
1253 cpu
->id_isar3
= 0x01102131;
1254 cpu
->id_isar4
= 0x141;
1255 cpu
->reset_auxcr
= 1;
1258 static void cortex_m3_initfn(Object
*obj
)
1260 ARMCPU
*cpu
= ARM_CPU(obj
);
1261 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1262 set_feature(&cpu
->env
, ARM_FEATURE_M
);
1263 set_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
);
1264 cpu
->midr
= 0x410fc231;
1265 cpu
->pmsav7_dregion
= 8;
1266 cpu
->id_pfr0
= 0x00000030;
1267 cpu
->id_pfr1
= 0x00000200;
1268 cpu
->id_dfr0
= 0x00100000;
1269 cpu
->id_afr0
= 0x00000000;
1270 cpu
->id_mmfr0
= 0x00000030;
1271 cpu
->id_mmfr1
= 0x00000000;
1272 cpu
->id_mmfr2
= 0x00000000;
1273 cpu
->id_mmfr3
= 0x00000000;
1274 cpu
->id_isar0
= 0x01141110;
1275 cpu
->id_isar1
= 0x02111000;
1276 cpu
->id_isar2
= 0x21112231;
1277 cpu
->id_isar3
= 0x01111110;
1278 cpu
->id_isar4
= 0x01310102;
1279 cpu
->id_isar5
= 0x00000000;
1280 cpu
->id_isar6
= 0x00000000;
1283 static void cortex_m4_initfn(Object
*obj
)
1285 ARMCPU
*cpu
= ARM_CPU(obj
);
1287 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1288 set_feature(&cpu
->env
, ARM_FEATURE_M
);
1289 set_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
);
1290 set_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
);
1291 cpu
->midr
= 0x410fc240; /* r0p0 */
1292 cpu
->pmsav7_dregion
= 8;
1293 cpu
->id_pfr0
= 0x00000030;
1294 cpu
->id_pfr1
= 0x00000200;
1295 cpu
->id_dfr0
= 0x00100000;
1296 cpu
->id_afr0
= 0x00000000;
1297 cpu
->id_mmfr0
= 0x00000030;
1298 cpu
->id_mmfr1
= 0x00000000;
1299 cpu
->id_mmfr2
= 0x00000000;
1300 cpu
->id_mmfr3
= 0x00000000;
1301 cpu
->id_isar0
= 0x01141110;
1302 cpu
->id_isar1
= 0x02111000;
1303 cpu
->id_isar2
= 0x21112231;
1304 cpu
->id_isar3
= 0x01111110;
1305 cpu
->id_isar4
= 0x01310102;
1306 cpu
->id_isar5
= 0x00000000;
1307 cpu
->id_isar6
= 0x00000000;
1310 static void cortex_m33_initfn(Object
*obj
)
1312 ARMCPU
*cpu
= ARM_CPU(obj
);
1314 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
1315 set_feature(&cpu
->env
, ARM_FEATURE_M
);
1316 set_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
);
1317 set_feature(&cpu
->env
, ARM_FEATURE_M_SECURITY
);
1318 set_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
);
1319 cpu
->midr
= 0x410fd213; /* r0p3 */
1320 cpu
->pmsav7_dregion
= 16;
1321 cpu
->sau_sregion
= 8;
1322 cpu
->id_pfr0
= 0x00000030;
1323 cpu
->id_pfr1
= 0x00000210;
1324 cpu
->id_dfr0
= 0x00200000;
1325 cpu
->id_afr0
= 0x00000000;
1326 cpu
->id_mmfr0
= 0x00101F40;
1327 cpu
->id_mmfr1
= 0x00000000;
1328 cpu
->id_mmfr2
= 0x01000000;
1329 cpu
->id_mmfr3
= 0x00000000;
1330 cpu
->id_isar0
= 0x01101110;
1331 cpu
->id_isar1
= 0x02212000;
1332 cpu
->id_isar2
= 0x20232232;
1333 cpu
->id_isar3
= 0x01111131;
1334 cpu
->id_isar4
= 0x01310132;
1335 cpu
->id_isar5
= 0x00000000;
1336 cpu
->id_isar6
= 0x00000000;
1337 cpu
->clidr
= 0x00000000;
1338 cpu
->ctr
= 0x8000c000;
1341 static void arm_v7m_class_init(ObjectClass
*oc
, void *data
)
1343 CPUClass
*cc
= CPU_CLASS(oc
);
1345 #ifndef CONFIG_USER_ONLY
1346 cc
->do_interrupt
= arm_v7m_cpu_do_interrupt
;
1349 cc
->cpu_exec_interrupt
= arm_v7m_cpu_exec_interrupt
;
1352 static const ARMCPRegInfo cortexr5_cp_reginfo
[] = {
1353 /* Dummy the TCM region regs for the moment */
1354 { .name
= "ATCM", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
1355 .access
= PL1_RW
, .type
= ARM_CP_CONST
},
1356 { .name
= "BTCM", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
1357 .access
= PL1_RW
, .type
= ARM_CP_CONST
},
1358 { .name
= "DCACHE_INVAL", .cp
= 15, .opc1
= 0, .crn
= 15, .crm
= 5,
1359 .opc2
= 0, .access
= PL1_W
, .type
= ARM_CP_NOP
},
1363 static void cortex_r5_initfn(Object
*obj
)
1365 ARMCPU
*cpu
= ARM_CPU(obj
);
1367 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1368 set_feature(&cpu
->env
, ARM_FEATURE_THUMB_DIV
);
1369 set_feature(&cpu
->env
, ARM_FEATURE_ARM_DIV
);
1370 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
1371 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
1372 cpu
->midr
= 0x411fc153; /* r1p3 */
1373 cpu
->id_pfr0
= 0x0131;
1374 cpu
->id_pfr1
= 0x001;
1375 cpu
->id_dfr0
= 0x010400;
1377 cpu
->id_mmfr0
= 0x0210030;
1378 cpu
->id_mmfr1
= 0x00000000;
1379 cpu
->id_mmfr2
= 0x01200000;
1380 cpu
->id_mmfr3
= 0x0211;
1381 cpu
->id_isar0
= 0x2101111;
1382 cpu
->id_isar1
= 0x13112111;
1383 cpu
->id_isar2
= 0x21232141;
1384 cpu
->id_isar3
= 0x01112131;
1385 cpu
->id_isar4
= 0x0010142;
1386 cpu
->id_isar5
= 0x0;
1387 cpu
->id_isar6
= 0x0;
1388 cpu
->mp_is_up
= true;
1389 cpu
->pmsav7_dregion
= 16;
1390 define_arm_cp_regs(cpu
, cortexr5_cp_reginfo
);
1393 static void cortex_r5f_initfn(Object
*obj
)
1395 ARMCPU
*cpu
= ARM_CPU(obj
);
1397 cortex_r5_initfn(obj
);
1398 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
1401 static const ARMCPRegInfo cortexa8_cp_reginfo
[] = {
1402 { .name
= "L2LOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 0,
1403 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1404 { .name
= "L2AUXCR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
1405 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1409 static void cortex_a8_initfn(Object
*obj
)
1411 ARMCPU
*cpu
= ARM_CPU(obj
);
1413 cpu
->dtb_compatible
= "arm,cortex-a8";
1414 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1415 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
1416 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1417 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1418 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1419 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1420 cpu
->midr
= 0x410fc080;
1421 cpu
->reset_fpsid
= 0x410330c0;
1422 cpu
->mvfr0
= 0x11110222;
1423 cpu
->mvfr1
= 0x00011111;
1424 cpu
->ctr
= 0x82048004;
1425 cpu
->reset_sctlr
= 0x00c50078;
1426 cpu
->id_pfr0
= 0x1031;
1427 cpu
->id_pfr1
= 0x11;
1428 cpu
->id_dfr0
= 0x400;
1430 cpu
->id_mmfr0
= 0x31100003;
1431 cpu
->id_mmfr1
= 0x20000000;
1432 cpu
->id_mmfr2
= 0x01202000;
1433 cpu
->id_mmfr3
= 0x11;
1434 cpu
->id_isar0
= 0x00101111;
1435 cpu
->id_isar1
= 0x12112111;
1436 cpu
->id_isar2
= 0x21232031;
1437 cpu
->id_isar3
= 0x11112131;
1438 cpu
->id_isar4
= 0x00111142;
1439 cpu
->dbgdidr
= 0x15141000;
1440 cpu
->clidr
= (1 << 27) | (2 << 24) | 3;
1441 cpu
->ccsidr
[0] = 0xe007e01a; /* 16k L1 dcache. */
1442 cpu
->ccsidr
[1] = 0x2007e01a; /* 16k L1 icache. */
1443 cpu
->ccsidr
[2] = 0xf0000000; /* No L2 icache. */
1444 cpu
->reset_auxcr
= 2;
1445 define_arm_cp_regs(cpu
, cortexa8_cp_reginfo
);
1448 static const ARMCPRegInfo cortexa9_cp_reginfo
[] = {
1449 /* power_control should be set to maximum latency. Again,
1450 * default to 0 and set by private hook
1452 { .name
= "A9_PWRCTL", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
1453 .access
= PL1_RW
, .resetvalue
= 0,
1454 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_control
) },
1455 { .name
= "A9_DIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 1,
1456 .access
= PL1_RW
, .resetvalue
= 0,
1457 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_diagnostic
) },
1458 { .name
= "A9_PWRDIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 2,
1459 .access
= PL1_RW
, .resetvalue
= 0,
1460 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_diagnostic
) },
1461 { .name
= "NEONBUSY", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
1462 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1463 /* TLB lockdown control */
1464 { .name
= "TLB_LOCKR", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 2,
1465 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
1466 { .name
= "TLB_LOCKW", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 4,
1467 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
1468 { .name
= "TLB_VA", .cp
= 15, .crn
= 15, .crm
= 5, .opc1
= 5, .opc2
= 2,
1469 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1470 { .name
= "TLB_PA", .cp
= 15, .crn
= 15, .crm
= 6, .opc1
= 5, .opc2
= 2,
1471 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1472 { .name
= "TLB_ATTR", .cp
= 15, .crn
= 15, .crm
= 7, .opc1
= 5, .opc2
= 2,
1473 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1477 static void cortex_a9_initfn(Object
*obj
)
1479 ARMCPU
*cpu
= ARM_CPU(obj
);
1481 cpu
->dtb_compatible
= "arm,cortex-a9";
1482 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1483 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
1484 set_feature(&cpu
->env
, ARM_FEATURE_VFP_FP16
);
1485 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1486 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1487 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1488 /* Note that A9 supports the MP extensions even for
1489 * A9UP and single-core A9MP (which are both different
1490 * and valid configurations; we don't model A9UP).
1492 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
1493 set_feature(&cpu
->env
, ARM_FEATURE_CBAR
);
1494 cpu
->midr
= 0x410fc090;
1495 cpu
->reset_fpsid
= 0x41033090;
1496 cpu
->mvfr0
= 0x11110222;
1497 cpu
->mvfr1
= 0x01111111;
1498 cpu
->ctr
= 0x80038003;
1499 cpu
->reset_sctlr
= 0x00c50078;
1500 cpu
->id_pfr0
= 0x1031;
1501 cpu
->id_pfr1
= 0x11;
1502 cpu
->id_dfr0
= 0x000;
1504 cpu
->id_mmfr0
= 0x00100103;
1505 cpu
->id_mmfr1
= 0x20000000;
1506 cpu
->id_mmfr2
= 0x01230000;
1507 cpu
->id_mmfr3
= 0x00002111;
1508 cpu
->id_isar0
= 0x00101111;
1509 cpu
->id_isar1
= 0x13112111;
1510 cpu
->id_isar2
= 0x21232041;
1511 cpu
->id_isar3
= 0x11112131;
1512 cpu
->id_isar4
= 0x00111142;
1513 cpu
->dbgdidr
= 0x35141000;
1514 cpu
->clidr
= (1 << 27) | (1 << 24) | 3;
1515 cpu
->ccsidr
[0] = 0xe00fe019; /* 16k L1 dcache. */
1516 cpu
->ccsidr
[1] = 0x200fe019; /* 16k L1 icache. */
1517 define_arm_cp_regs(cpu
, cortexa9_cp_reginfo
);
1520 #ifndef CONFIG_USER_ONLY
1521 static uint64_t a15_l2ctlr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1523 /* Linux wants the number of processors from here.
1524 * Might as well set the interrupt-controller bit too.
1526 return ((smp_cpus
- 1) << 24) | (1 << 23);
1530 static const ARMCPRegInfo cortexa15_cp_reginfo
[] = {
1531 #ifndef CONFIG_USER_ONLY
1532 { .name
= "L2CTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
1533 .access
= PL1_RW
, .resetvalue
= 0, .readfn
= a15_l2ctlr_read
,
1534 .writefn
= arm_cp_write_ignore
, },
1536 { .name
= "L2ECTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 3,
1537 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1541 static void cortex_a7_initfn(Object
*obj
)
1543 ARMCPU
*cpu
= ARM_CPU(obj
);
1545 cpu
->dtb_compatible
= "arm,cortex-a7";
1546 set_feature(&cpu
->env
, ARM_FEATURE_V7VE
);
1547 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
1548 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1549 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1550 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
1551 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1552 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
1553 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1554 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_CORTEX_A7
;
1555 cpu
->midr
= 0x410fc075;
1556 cpu
->reset_fpsid
= 0x41023075;
1557 cpu
->mvfr0
= 0x10110222;
1558 cpu
->mvfr1
= 0x11111111;
1559 cpu
->ctr
= 0x84448003;
1560 cpu
->reset_sctlr
= 0x00c50078;
1561 cpu
->id_pfr0
= 0x00001131;
1562 cpu
->id_pfr1
= 0x00011011;
1563 cpu
->id_dfr0
= 0x02010555;
1564 cpu
->pmceid0
= 0x00000000;
1565 cpu
->pmceid1
= 0x00000000;
1566 cpu
->id_afr0
= 0x00000000;
1567 cpu
->id_mmfr0
= 0x10101105;
1568 cpu
->id_mmfr1
= 0x40000000;
1569 cpu
->id_mmfr2
= 0x01240000;
1570 cpu
->id_mmfr3
= 0x02102211;
1571 cpu
->id_isar0
= 0x01101110;
1572 cpu
->id_isar1
= 0x13112111;
1573 cpu
->id_isar2
= 0x21232041;
1574 cpu
->id_isar3
= 0x11112131;
1575 cpu
->id_isar4
= 0x10011142;
1576 cpu
->dbgdidr
= 0x3515f005;
1577 cpu
->clidr
= 0x0a200023;
1578 cpu
->ccsidr
[0] = 0x701fe00a; /* 32K L1 dcache */
1579 cpu
->ccsidr
[1] = 0x201fe00a; /* 32K L1 icache */
1580 cpu
->ccsidr
[2] = 0x711fe07a; /* 4096K L2 unified cache */
1581 define_arm_cp_regs(cpu
, cortexa15_cp_reginfo
); /* Same as A15 */
1584 static void cortex_a15_initfn(Object
*obj
)
1586 ARMCPU
*cpu
= ARM_CPU(obj
);
1588 cpu
->dtb_compatible
= "arm,cortex-a15";
1589 set_feature(&cpu
->env
, ARM_FEATURE_V7VE
);
1590 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
1591 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1592 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1593 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
1594 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1595 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
1596 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1597 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_CORTEX_A15
;
1598 cpu
->midr
= 0x412fc0f1;
1599 cpu
->reset_fpsid
= 0x410430f0;
1600 cpu
->mvfr0
= 0x10110222;
1601 cpu
->mvfr1
= 0x11111111;
1602 cpu
->ctr
= 0x8444c004;
1603 cpu
->reset_sctlr
= 0x00c50078;
1604 cpu
->id_pfr0
= 0x00001131;
1605 cpu
->id_pfr1
= 0x00011011;
1606 cpu
->id_dfr0
= 0x02010555;
1607 cpu
->pmceid0
= 0x0000000;
1608 cpu
->pmceid1
= 0x00000000;
1609 cpu
->id_afr0
= 0x00000000;
1610 cpu
->id_mmfr0
= 0x10201105;
1611 cpu
->id_mmfr1
= 0x20000000;
1612 cpu
->id_mmfr2
= 0x01240000;
1613 cpu
->id_mmfr3
= 0x02102211;
1614 cpu
->id_isar0
= 0x02101110;
1615 cpu
->id_isar1
= 0x13112111;
1616 cpu
->id_isar2
= 0x21232041;
1617 cpu
->id_isar3
= 0x11112131;
1618 cpu
->id_isar4
= 0x10011142;
1619 cpu
->dbgdidr
= 0x3515f021;
1620 cpu
->clidr
= 0x0a200023;
1621 cpu
->ccsidr
[0] = 0x701fe00a; /* 32K L1 dcache */
1622 cpu
->ccsidr
[1] = 0x201fe00a; /* 32K L1 icache */
1623 cpu
->ccsidr
[2] = 0x711fe07a; /* 4096K L2 unified cache */
1624 define_arm_cp_regs(cpu
, cortexa15_cp_reginfo
);
1627 static void ti925t_initfn(Object
*obj
)
1629 ARMCPU
*cpu
= ARM_CPU(obj
);
1630 set_feature(&cpu
->env
, ARM_FEATURE_V4T
);
1631 set_feature(&cpu
->env
, ARM_FEATURE_OMAPCP
);
1632 cpu
->midr
= ARM_CPUID_TI925T
;
1633 cpu
->ctr
= 0x5109149;
1634 cpu
->reset_sctlr
= 0x00000070;
1637 static void sa1100_initfn(Object
*obj
)
1639 ARMCPU
*cpu
= ARM_CPU(obj
);
1641 cpu
->dtb_compatible
= "intel,sa1100";
1642 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
1643 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1644 cpu
->midr
= 0x4401A11B;
1645 cpu
->reset_sctlr
= 0x00000070;
1648 static void sa1110_initfn(Object
*obj
)
1650 ARMCPU
*cpu
= ARM_CPU(obj
);
1651 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
1652 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1653 cpu
->midr
= 0x6901B119;
1654 cpu
->reset_sctlr
= 0x00000070;
1657 static void pxa250_initfn(Object
*obj
)
1659 ARMCPU
*cpu
= ARM_CPU(obj
);
1661 cpu
->dtb_compatible
= "marvell,xscale";
1662 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1663 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1664 cpu
->midr
= 0x69052100;
1665 cpu
->ctr
= 0xd172172;
1666 cpu
->reset_sctlr
= 0x00000078;
1669 static void pxa255_initfn(Object
*obj
)
1671 ARMCPU
*cpu
= ARM_CPU(obj
);
1673 cpu
->dtb_compatible
= "marvell,xscale";
1674 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1675 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1676 cpu
->midr
= 0x69052d00;
1677 cpu
->ctr
= 0xd172172;
1678 cpu
->reset_sctlr
= 0x00000078;
1681 static void pxa260_initfn(Object
*obj
)
1683 ARMCPU
*cpu
= ARM_CPU(obj
);
1685 cpu
->dtb_compatible
= "marvell,xscale";
1686 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1687 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1688 cpu
->midr
= 0x69052903;
1689 cpu
->ctr
= 0xd172172;
1690 cpu
->reset_sctlr
= 0x00000078;
1693 static void pxa261_initfn(Object
*obj
)
1695 ARMCPU
*cpu
= ARM_CPU(obj
);
1697 cpu
->dtb_compatible
= "marvell,xscale";
1698 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1699 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1700 cpu
->midr
= 0x69052d05;
1701 cpu
->ctr
= 0xd172172;
1702 cpu
->reset_sctlr
= 0x00000078;
1705 static void pxa262_initfn(Object
*obj
)
1707 ARMCPU
*cpu
= ARM_CPU(obj
);
1709 cpu
->dtb_compatible
= "marvell,xscale";
1710 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1711 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1712 cpu
->midr
= 0x69052d06;
1713 cpu
->ctr
= 0xd172172;
1714 cpu
->reset_sctlr
= 0x00000078;
1717 static void pxa270a0_initfn(Object
*obj
)
1719 ARMCPU
*cpu
= ARM_CPU(obj
);
1721 cpu
->dtb_compatible
= "marvell,xscale";
1722 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1723 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1724 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1725 cpu
->midr
= 0x69054110;
1726 cpu
->ctr
= 0xd172172;
1727 cpu
->reset_sctlr
= 0x00000078;
1730 static void pxa270a1_initfn(Object
*obj
)
1732 ARMCPU
*cpu
= ARM_CPU(obj
);
1734 cpu
->dtb_compatible
= "marvell,xscale";
1735 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1736 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1737 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1738 cpu
->midr
= 0x69054111;
1739 cpu
->ctr
= 0xd172172;
1740 cpu
->reset_sctlr
= 0x00000078;
1743 static void pxa270b0_initfn(Object
*obj
)
1745 ARMCPU
*cpu
= ARM_CPU(obj
);
1747 cpu
->dtb_compatible
= "marvell,xscale";
1748 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1749 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1750 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1751 cpu
->midr
= 0x69054112;
1752 cpu
->ctr
= 0xd172172;
1753 cpu
->reset_sctlr
= 0x00000078;
1756 static void pxa270b1_initfn(Object
*obj
)
1758 ARMCPU
*cpu
= ARM_CPU(obj
);
1760 cpu
->dtb_compatible
= "marvell,xscale";
1761 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1762 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1763 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1764 cpu
->midr
= 0x69054113;
1765 cpu
->ctr
= 0xd172172;
1766 cpu
->reset_sctlr
= 0x00000078;
1769 static void pxa270c0_initfn(Object
*obj
)
1771 ARMCPU
*cpu
= ARM_CPU(obj
);
1773 cpu
->dtb_compatible
= "marvell,xscale";
1774 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1775 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1776 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1777 cpu
->midr
= 0x69054114;
1778 cpu
->ctr
= 0xd172172;
1779 cpu
->reset_sctlr
= 0x00000078;
1782 static void pxa270c5_initfn(Object
*obj
)
1784 ARMCPU
*cpu
= ARM_CPU(obj
);
1786 cpu
->dtb_compatible
= "marvell,xscale";
1787 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1788 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1789 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1790 cpu
->midr
= 0x69054117;
1791 cpu
->ctr
= 0xd172172;
1792 cpu
->reset_sctlr
= 0x00000078;
1795 #ifndef TARGET_AARCH64
1796 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
1797 * otherwise, a CPU with as many features enabled as our emulation supports.
1798 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
1799 * this only needs to handle 32 bits.
1801 static void arm_max_initfn(Object
*obj
)
1803 ARMCPU
*cpu
= ARM_CPU(obj
);
1805 if (kvm_enabled()) {
1806 kvm_arm_set_cpu_features_from_host(cpu
);
1808 cortex_a15_initfn(obj
);
1809 #ifdef CONFIG_USER_ONLY
1810 /* We don't set these in system emulation mode for the moment,
1811 * since we don't correctly set the ID registers to advertise them,
1813 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
1814 set_feature(&cpu
->env
, ARM_FEATURE_V8_AES
);
1815 set_feature(&cpu
->env
, ARM_FEATURE_V8_SHA1
);
1816 set_feature(&cpu
->env
, ARM_FEATURE_V8_SHA256
);
1817 set_feature(&cpu
->env
, ARM_FEATURE_V8_PMULL
);
1818 set_feature(&cpu
->env
, ARM_FEATURE_CRC
);
1819 set_feature(&cpu
->env
, ARM_FEATURE_V8_RDM
);
1820 set_feature(&cpu
->env
, ARM_FEATURE_V8_DOTPROD
);
1821 set_feature(&cpu
->env
, ARM_FEATURE_V8_FCMA
);
1827 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
1829 typedef struct ARMCPUInfo
{
1831 void (*initfn
)(Object
*obj
);
1832 void (*class_init
)(ObjectClass
*oc
, void *data
);
1835 static const ARMCPUInfo arm_cpus
[] = {
1836 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1837 { .name
= "arm926", .initfn
= arm926_initfn
},
1838 { .name
= "arm946", .initfn
= arm946_initfn
},
1839 { .name
= "arm1026", .initfn
= arm1026_initfn
},
1840 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1841 * older core than plain "arm1136". In particular this does not
1842 * have the v6K features.
1844 { .name
= "arm1136-r2", .initfn
= arm1136_r2_initfn
},
1845 { .name
= "arm1136", .initfn
= arm1136_initfn
},
1846 { .name
= "arm1176", .initfn
= arm1176_initfn
},
1847 { .name
= "arm11mpcore", .initfn
= arm11mpcore_initfn
},
1848 { .name
= "cortex-m3", .initfn
= cortex_m3_initfn
,
1849 .class_init
= arm_v7m_class_init
},
1850 { .name
= "cortex-m4", .initfn
= cortex_m4_initfn
,
1851 .class_init
= arm_v7m_class_init
},
1852 { .name
= "cortex-m33", .initfn
= cortex_m33_initfn
,
1853 .class_init
= arm_v7m_class_init
},
1854 { .name
= "cortex-r5", .initfn
= cortex_r5_initfn
},
1855 { .name
= "cortex-r5f", .initfn
= cortex_r5f_initfn
},
1856 { .name
= "cortex-a7", .initfn
= cortex_a7_initfn
},
1857 { .name
= "cortex-a8", .initfn
= cortex_a8_initfn
},
1858 { .name
= "cortex-a9", .initfn
= cortex_a9_initfn
},
1859 { .name
= "cortex-a15", .initfn
= cortex_a15_initfn
},
1860 { .name
= "ti925t", .initfn
= ti925t_initfn
},
1861 { .name
= "sa1100", .initfn
= sa1100_initfn
},
1862 { .name
= "sa1110", .initfn
= sa1110_initfn
},
1863 { .name
= "pxa250", .initfn
= pxa250_initfn
},
1864 { .name
= "pxa255", .initfn
= pxa255_initfn
},
1865 { .name
= "pxa260", .initfn
= pxa260_initfn
},
1866 { .name
= "pxa261", .initfn
= pxa261_initfn
},
1867 { .name
= "pxa262", .initfn
= pxa262_initfn
},
1868 /* "pxa270" is an alias for "pxa270-a0" */
1869 { .name
= "pxa270", .initfn
= pxa270a0_initfn
},
1870 { .name
= "pxa270-a0", .initfn
= pxa270a0_initfn
},
1871 { .name
= "pxa270-a1", .initfn
= pxa270a1_initfn
},
1872 { .name
= "pxa270-b0", .initfn
= pxa270b0_initfn
},
1873 { .name
= "pxa270-b1", .initfn
= pxa270b1_initfn
},
1874 { .name
= "pxa270-c0", .initfn
= pxa270c0_initfn
},
1875 { .name
= "pxa270-c5", .initfn
= pxa270c5_initfn
},
1876 #ifndef TARGET_AARCH64
1877 { .name
= "max", .initfn
= arm_max_initfn
},
1879 #ifdef CONFIG_USER_ONLY
1880 { .name
= "any", .initfn
= arm_max_initfn
},
1886 static Property arm_cpu_properties
[] = {
1887 DEFINE_PROP_BOOL("start-powered-off", ARMCPU
, start_powered_off
, false),
1888 DEFINE_PROP_UINT32("psci-conduit", ARMCPU
, psci_conduit
, 0),
1889 DEFINE_PROP_UINT32("midr", ARMCPU
, midr
, 0),
1890 DEFINE_PROP_UINT64("mp-affinity", ARMCPU
,
1891 mp_affinity
, ARM64_AFFINITY_INVALID
),
1892 DEFINE_PROP_INT32("node-id", ARMCPU
, node_id
, CPU_UNSET_NUMA_NODE_ID
),
1893 DEFINE_PROP_INT32("core-count", ARMCPU
, core_count
, -1),
1894 DEFINE_PROP_END_OF_LIST()
1897 #ifdef CONFIG_USER_ONLY
1898 static int arm_cpu_handle_mmu_fault(CPUState
*cs
, vaddr address
, int size
,
1899 int rw
, int mmu_idx
)
1901 ARMCPU
*cpu
= ARM_CPU(cs
);
1902 CPUARMState
*env
= &cpu
->env
;
1904 env
->exception
.vaddress
= address
;
1906 cs
->exception_index
= EXCP_PREFETCH_ABORT
;
1908 cs
->exception_index
= EXCP_DATA_ABORT
;
1914 static gchar
*arm_gdb_arch_name(CPUState
*cs
)
1916 ARMCPU
*cpu
= ARM_CPU(cs
);
1917 CPUARMState
*env
= &cpu
->env
;
1919 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
1920 return g_strdup("iwmmxt");
1922 return g_strdup("arm");
1925 static void arm_cpu_class_init(ObjectClass
*oc
, void *data
)
1927 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
1928 CPUClass
*cc
= CPU_CLASS(acc
);
1929 DeviceClass
*dc
= DEVICE_CLASS(oc
);
1931 device_class_set_parent_realize(dc
, arm_cpu_realizefn
,
1932 &acc
->parent_realize
);
1933 dc
->props
= arm_cpu_properties
;
1935 acc
->parent_reset
= cc
->reset
;
1936 cc
->reset
= arm_cpu_reset
;
1938 cc
->class_by_name
= arm_cpu_class_by_name
;
1939 cc
->has_work
= arm_cpu_has_work
;
1940 cc
->cpu_exec_interrupt
= arm_cpu_exec_interrupt
;
1941 cc
->dump_state
= arm_cpu_dump_state
;
1942 cc
->set_pc
= arm_cpu_set_pc
;
1943 cc
->gdb_read_register
= arm_cpu_gdb_read_register
;
1944 cc
->gdb_write_register
= arm_cpu_gdb_write_register
;
1945 #ifdef CONFIG_USER_ONLY
1946 cc
->handle_mmu_fault
= arm_cpu_handle_mmu_fault
;
1948 cc
->do_interrupt
= arm_cpu_do_interrupt
;
1949 cc
->do_unaligned_access
= arm_cpu_do_unaligned_access
;
1950 cc
->do_transaction_failed
= arm_cpu_do_transaction_failed
;
1951 cc
->get_phys_page_attrs_debug
= arm_cpu_get_phys_page_attrs_debug
;
1952 cc
->asidx_from_attrs
= arm_asidx_from_attrs
;
1953 cc
->vmsd
= &vmstate_arm_cpu
;
1954 cc
->virtio_is_big_endian
= arm_cpu_virtio_is_big_endian
;
1955 cc
->write_elf64_note
= arm_cpu_write_elf64_note
;
1956 cc
->write_elf32_note
= arm_cpu_write_elf32_note
;
1958 cc
->gdb_num_core_regs
= 26;
1959 cc
->gdb_core_xml_file
= "arm-core.xml";
1960 cc
->gdb_arch_name
= arm_gdb_arch_name
;
1961 cc
->gdb_get_dynamic_xml
= arm_gdb_get_dynamic_xml
;
1962 cc
->gdb_stop_before_watchpoint
= true;
1963 cc
->debug_excp_handler
= arm_debug_excp_handler
;
1964 cc
->debug_check_watchpoint
= arm_debug_check_watchpoint
;
1965 #if !defined(CONFIG_USER_ONLY)
1966 cc
->adjust_watchpoint_address
= arm_adjust_watchpoint_address
;
1969 cc
->disas_set_info
= arm_disas_set_info
;
1971 cc
->tcg_initialize
= arm_translate_init
;
1976 static void arm_host_initfn(Object
*obj
)
1978 ARMCPU
*cpu
= ARM_CPU(obj
);
1980 kvm_arm_set_cpu_features_from_host(cpu
);
1983 static const TypeInfo host_arm_cpu_type_info
= {
1984 .name
= TYPE_ARM_HOST_CPU
,
1985 #ifdef TARGET_AARCH64
1986 .parent
= TYPE_AARCH64_CPU
,
1988 .parent
= TYPE_ARM_CPU
,
1990 .instance_init
= arm_host_initfn
,
1995 static void cpu_register(const ARMCPUInfo
*info
)
1997 TypeInfo type_info
= {
1998 .parent
= TYPE_ARM_CPU
,
1999 .instance_size
= sizeof(ARMCPU
),
2000 .instance_init
= info
->initfn
,
2001 .class_size
= sizeof(ARMCPUClass
),
2002 .class_init
= info
->class_init
,
2005 type_info
.name
= g_strdup_printf("%s-" TYPE_ARM_CPU
, info
->name
);
2006 type_register(&type_info
);
2007 g_free((void *)type_info
.name
);
2010 static const TypeInfo arm_cpu_type_info
= {
2011 .name
= TYPE_ARM_CPU
,
2013 .instance_size
= sizeof(ARMCPU
),
2014 .instance_init
= arm_cpu_initfn
,
2015 .instance_post_init
= arm_cpu_post_init
,
2016 .instance_finalize
= arm_cpu_finalizefn
,
2018 .class_size
= sizeof(ARMCPUClass
),
2019 .class_init
= arm_cpu_class_init
,
2022 static const TypeInfo idau_interface_type_info
= {
2023 .name
= TYPE_IDAU_INTERFACE
,
2024 .parent
= TYPE_INTERFACE
,
2025 .class_size
= sizeof(IDAUInterfaceClass
),
2028 static void arm_cpu_register_types(void)
2030 const ARMCPUInfo
*info
= arm_cpus
;
2032 type_register_static(&arm_cpu_type_info
);
2033 type_register_static(&idau_interface_type_info
);
2035 while (info
->name
) {
2041 type_register_static(&host_arm_cpu_type_info
);
2045 type_init(arm_cpu_register_types
)