hw/arm/highbank.c

   1 /*
   2  * Calxeda Highbank SoC emulation
   3  *
   4  * Copyright (c) 2010-2012 Calxeda
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2 or later, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qapi/error.h"
  22 #include "hw/sysbus.h"
  23 #include "hw/arm/arm.h"
  24 #include "hw/devices.h"
  25 #include "hw/loader.h"
  26 #include "net/net.h"
  27 #include "sysemu/kvm.h"
  28 #include "sysemu/sysemu.h"
  29 #include "hw/boards.h"
  30 #include "sysemu/block-backend.h"
  31 #include "exec/address-spaces.h"
  32 #include "qemu/error-report.h"
  33 #include "hw/char/pl011.h"
  34 #include "hw/ide/ahci.h"
  35 #include "hw/cpu/a9mpcore.h"
  36 #include "hw/cpu/a15mpcore.h"
  37
  38 #define SMP_BOOT_ADDR           0x100
  39 #define SMP_BOOT_REG            0x40
  40 #define MPCORE_PERIPHBASE       0xfff10000
  41
  42 #define MVBAR_ADDR              0x200
  43 #define BOARD_SETUP_ADDR        (MVBAR_ADDR + 8 * sizeof(uint32_t))
  44
  45 #define NIRQ_GIC                160
  46
  47 /* Board init.  */
  48
  49 static void hb_write_board_setup(ARMCPU *cpu,
  50                                  const struct arm_boot_info *info)
  51 {
  52     arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR);
  53 }
  54
  55 static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
  56 {
  57     int n;
  58     uint32_t smpboot[] = {
  59         0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 - read current core id */
  60         0xe210000f, /* ands r0, r0, #0x0f */
  61         0xe3a03040, /* mov r3, #0x40 - jump address is 0x40 + 0x10 * core id */
  62         0xe0830200, /* add r0, r3, r0, lsl #4 */
  63         0xe59f2024, /* ldr r2, privbase */
  64         0xe3a01001, /* mov r1, #1 */
  65         0xe5821100, /* str r1, [r2, #256] - set GICC_CTLR.Enable */
  66         0xe3a010ff, /* mov r1, #0xff */
  67         0xe5821104, /* str r1, [r2, #260] - set GICC_PMR.Priority to 0xff */
  68         0xf57ff04f, /* dsb */
  69         0xe320f003, /* wfi */
  70         0xe5901000, /* ldr     r1, [r0] */
  71         0xe1110001, /* tst     r1, r1 */
  72         0x0afffffb, /* beq     <wfi> */
  73         0xe12fff11, /* bx      r1 */
  74         MPCORE_PERIPHBASE   /* privbase: MPCore peripheral base address.  */
  75     };
  76     for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
  77         smpboot[n] = tswap32(smpboot[n]);
  78     }
  79     rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR);
  80 }
  81
  82 static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
  83 {
  84     CPUARMState *env = &cpu->env;
  85
  86     switch (info->nb_cpus) {
  87     case 4:
  88         address_space_stl_notdirty(&address_space_memory,
  89                                    SMP_BOOT_REG + 0x30, 0,
  90                                    MEMTXATTRS_UNSPECIFIED, NULL);
  91     case 3:
  92         address_space_stl_notdirty(&address_space_memory,
  93                                    SMP_BOOT_REG + 0x20, 0,
  94                                    MEMTXATTRS_UNSPECIFIED, NULL);
  95     case 2:
  96         address_space_stl_notdirty(&address_space_memory,
  97                                    SMP_BOOT_REG + 0x10, 0,
  98                                    MEMTXATTRS_UNSPECIFIED, NULL);
  99         env->regs[15] = SMP_BOOT_ADDR;
 100         break;
 101     default:
 102         break;
 103     }
 104 }
 105
 106 #define NUM_REGS      0x200
 107 static void hb_regs_write(void *opaque, hwaddr offset,
 108                           uint64_t value, unsigned size)
 109 {
 110     uint32_t *regs = opaque;
 111
 112     if (offset == 0xf00) {
 113         if (value == 1 || value == 2) {
 114             qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 115         } else if (value == 3) {
 116             qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
 117         }
 118     }
 119
 120     regs[offset/4] = value;
 121 }
 122
 123 static uint64_t hb_regs_read(void *opaque, hwaddr offset,
 124                              unsigned size)
 125 {
 126     uint32_t *regs = opaque;
 127     uint32_t value = regs[offset/4];
 128
 129     if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) {
 130         value |= 0x30000000;
 131     }
 132
 133     return value;
 134 }
 135
 136 static const MemoryRegionOps hb_mem_ops = {
 137     .read = hb_regs_read,
 138     .write = hb_regs_write,
 139     .endianness = DEVICE_NATIVE_ENDIAN,
 140 };
 141
 142 #define TYPE_HIGHBANK_REGISTERS "highbank-regs"
 143 #define HIGHBANK_REGISTERS(obj) \
 144     OBJECT_CHECK(HighbankRegsState, (obj), TYPE_HIGHBANK_REGISTERS)
 145
 146 typedef struct {
 147     /*< private >*/
 148     SysBusDevice parent_obj;
 149     /*< public >*/
 150
 151     MemoryRegion iomem;
 152     uint32_t regs[NUM_REGS];
 153 } HighbankRegsState;
 154
 155 static VMStateDescription vmstate_highbank_regs = {
 156     .name = "highbank-regs",
 157     .version_id = 0,
 158     .minimum_version_id = 0,
 159     .fields = (VMStateField[]) {
 160         VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS),
 161         VMSTATE_END_OF_LIST(),
 162     },
 163 };
 164
 165 static void highbank_regs_reset(DeviceState *dev)
 166 {
 167     HighbankRegsState *s = HIGHBANK_REGISTERS(dev);
 168
 169     s->regs[0x40] = 0x05F20121;
 170     s->regs[0x41] = 0x2;
 171     s->regs[0x42] = 0x05F30121;
 172     s->regs[0x43] = 0x05F40121;
 173 }
 174
 175 static void highbank_regs_init(Object *obj)
 176 {
 177     HighbankRegsState *s = HIGHBANK_REGISTERS(obj);
 178     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 179
 180     memory_region_init_io(&s->iomem, obj, &hb_mem_ops, s->regs,
 181                           "highbank_regs", 0x1000);
 182     sysbus_init_mmio(dev, &s->iomem);
 183 }
 184
 185 static void highbank_regs_class_init(ObjectClass *klass, void *data)
 186 {
 187     DeviceClass *dc = DEVICE_CLASS(klass);
 188
 189     dc->desc = "Calxeda Highbank registers";
 190     dc->vmsd = &vmstate_highbank_regs;
 191     dc->reset = highbank_regs_reset;
 192 }
 193
 194 static const TypeInfo highbank_regs_info = {
 195     .name          = TYPE_HIGHBANK_REGISTERS,
 196     .parent        = TYPE_SYS_BUS_DEVICE,
 197     .instance_size = sizeof(HighbankRegsState),
 198     .instance_init = highbank_regs_init,
 199     .class_init    = highbank_regs_class_init,
 200 };
 201
 202 static void highbank_regs_register_types(void)
 203 {
 204     type_register_static(&highbank_regs_info);
 205 }
 206
 207 type_init(highbank_regs_register_types)
 208
 209 static struct arm_boot_info highbank_binfo;
 210
 211 enum cxmachines {
 212     CALXEDA_HIGHBANK,
 213     CALXEDA_MIDWAY,
 214 };
 215
 216 /* ram_size must be set to match the upper bound of memory in the
 217  * device tree (linux/arch/arm/boot/dts/highbank.dts), which is
 218  * normally 0xff900000 or -m 4089. When running this board on a
 219  * 32-bit host, set the reg value of memory to 0xf7ff00000 in the
 220  * device tree and pass -m 2047 to QEMU.
 221  */
 222 static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
 223 {
 224     ram_addr_t ram_size = machine->ram_size;
 225     const char *kernel_filename = machine->kernel_filename;
 226     const char *kernel_cmdline = machine->kernel_cmdline;
 227     const char *initrd_filename = machine->initrd_filename;
 228     DeviceState *dev = NULL;
 229     SysBusDevice *busdev;
 230     qemu_irq pic[128];
 231     int n;
 232     qemu_irq cpu_irq[4];
 233     qemu_irq cpu_fiq[4];
 234     MemoryRegion *sysram;
 235     MemoryRegion *dram;
 236     MemoryRegion *sysmem;
 237     char *sysboot_filename;
 238
 239     switch (machine_id) {
 240     case CALXEDA_HIGHBANK:
 241         machine->cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
 242         break;
 243     case CALXEDA_MIDWAY:
 244         machine->cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
 245         break;
 246     default:
 247         assert(0);
 248     }
 249
 250     for (n = 0; n < smp_cpus; n++) {
 251         Object *cpuobj;
 252         ARMCPU *cpu;
 253
 254         cpuobj = object_new(machine->cpu_type);
 255         cpu = ARM_CPU(cpuobj);
 256
 257         object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_SMC,
 258                                 "psci-conduit", &error_abort);
 259
 260         if (n) {
 261             /* Secondary CPUs start in PSCI powered-down state */
 262             object_property_set_bool(cpuobj, true,
 263                                      "start-powered-off", &error_abort);
 264         }
 265
 266         if (object_property_find(cpuobj, "reset-cbar", NULL)) {
 267             object_property_set_int(cpuobj, MPCORE_PERIPHBASE,
 268                                     "reset-cbar", &error_abort);
 269         }
 270         object_property_set_bool(cpuobj, true, "realized", &error_fatal);
 271         cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ);
 272         cpu_fiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ);
 273     }
 274
 275     sysmem = get_system_memory();
 276     dram = g_new(MemoryRegion, 1);
 277     memory_region_allocate_system_memory(dram, NULL, "highbank.dram", ram_size);
 278     /* SDRAM at address zero.  */
 279     memory_region_add_subregion(sysmem, 0, dram);
 280
 281     sysram = g_new(MemoryRegion, 1);
 282     memory_region_init_ram_nomigrate(sysram, NULL, "highbank.sysram", 0x8000,
 283                            &error_fatal);
 284     memory_region_add_subregion(sysmem, 0xfff88000, sysram);
 285     if (bios_name != NULL) {
 286         sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 287         if (sysboot_filename != NULL) {
 288             if (load_image_targphys(sysboot_filename, 0xfff88000, 0x8000) < 0) {
 289                 error_report("Unable to load %s", bios_name);
 290                 exit(1);
 291             }
 292             g_free(sysboot_filename);
 293         } else {
 294             error_report("Unable to find %s", bios_name);
 295             exit(1);
 296         }
 297     }
 298
 299     switch (machine_id) {
 300     case CALXEDA_HIGHBANK:
 301         dev = qdev_create(NULL, "l2x0");
 302         qdev_init_nofail(dev);
 303         busdev = SYS_BUS_DEVICE(dev);
 304         sysbus_mmio_map(busdev, 0, 0xfff12000);
 305
 306         dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV);
 307         break;
 308     case CALXEDA_MIDWAY:
 309         dev = qdev_create(NULL, TYPE_A15MPCORE_PRIV);
 310         break;
 311     }
 312     qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
 313     qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
 314     qdev_init_nofail(dev);
 315     busdev = SYS_BUS_DEVICE(dev);
 316     sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
 317     for (n = 0; n < smp_cpus; n++) {
 318         sysbus_connect_irq(busdev, n, cpu_irq[n]);
 319         sysbus_connect_irq(busdev, n + smp_cpus, cpu_fiq[n]);
 320     }
 321
 322     for (n = 0; n < 128; n++) {
 323         pic[n] = qdev_get_gpio_in(dev, n);
 324     }
 325
 326     dev = qdev_create(NULL, "sp804");
 327     qdev_prop_set_uint32(dev, "freq0", 150000000);
 328     qdev_prop_set_uint32(dev, "freq1", 150000000);
 329     qdev_init_nofail(dev);
 330     busdev = SYS_BUS_DEVICE(dev);
 331     sysbus_mmio_map(busdev, 0, 0xfff34000);
 332     sysbus_connect_irq(busdev, 0, pic[18]);
 333     pl011_create(0xfff36000, pic[20], serial_hds[0]);
 334
 335     dev = qdev_create(NULL, TYPE_HIGHBANK_REGISTERS);
 336     qdev_init_nofail(dev);
 337     busdev = SYS_BUS_DEVICE(dev);
 338     sysbus_mmio_map(busdev, 0, 0xfff3c000);
 339
 340     sysbus_create_simple("pl061", 0xfff30000, pic[14]);
 341     sysbus_create_simple("pl061", 0xfff31000, pic[15]);
 342     sysbus_create_simple("pl061", 0xfff32000, pic[16]);
 343     sysbus_create_simple("pl061", 0xfff33000, pic[17]);
 344     sysbus_create_simple("pl031", 0xfff35000, pic[19]);
 345     sysbus_create_simple("pl022", 0xfff39000, pic[23]);
 346
 347     sysbus_create_simple(TYPE_SYSBUS_AHCI, 0xffe08000, pic[83]);
 348
 349     if (nd_table[0].used) {
 350         qemu_check_nic_model(&nd_table[0], "xgmac");
 351         dev = qdev_create(NULL, "xgmac");
 352         qdev_set_nic_properties(dev, &nd_table[0]);
 353         qdev_init_nofail(dev);
 354         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff50000);
 355         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[77]);
 356         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[78]);
 357         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[79]);
 358
 359         qemu_check_nic_model(&nd_table[1], "xgmac");
 360         dev = qdev_create(NULL, "xgmac");
 361         qdev_set_nic_properties(dev, &nd_table[1]);
 362         qdev_init_nofail(dev);
 363         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff51000);
 364         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[80]);
 365         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[81]);
 366         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[82]);
 367     }
 368
 369     /* TODO create and connect IDE devices for ide_drive_get() */
 370
 371     highbank_binfo.ram_size = ram_size;
 372     highbank_binfo.kernel_filename = kernel_filename;
 373     highbank_binfo.kernel_cmdline = kernel_cmdline;
 374     highbank_binfo.initrd_filename = initrd_filename;
 375     /* highbank requires a dtb in order to boot, and the dtb will override
 376      * the board ID. The following value is ignored, so set it to -1 to be
 377      * clear that the value is meaningless.
 378      */
 379     highbank_binfo.board_id = -1;
 380     highbank_binfo.nb_cpus = smp_cpus;
 381     highbank_binfo.loader_start = 0;
 382     highbank_binfo.write_secondary_boot = hb_write_secondary;
 383     highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary;
 384     if (!kvm_enabled()) {
 385         highbank_binfo.board_setup_addr = BOARD_SETUP_ADDR;
 386         highbank_binfo.write_board_setup = hb_write_board_setup;
 387         highbank_binfo.secure_board_setup = true;
 388     } else {
 389         warn_report("cannot load built-in Monitor support "
 390                     "if KVM is enabled. Some guests (such as Linux) "
 391                     "may not boot.");
 392     }
 393
 394     arm_load_kernel(ARM_CPU(first_cpu), &highbank_binfo);
 395 }
 396
 397 static void highbank_init(MachineState *machine)
 398 {
 399     calxeda_init(machine, CALXEDA_HIGHBANK);
 400 }
 401
 402 static void midway_init(MachineState *machine)
 403 {
 404     calxeda_init(machine, CALXEDA_MIDWAY);
 405 }
 406
 407 static void highbank_class_init(ObjectClass *oc, void *data)
 408 {
 409     MachineClass *mc = MACHINE_CLASS(oc);
 410
 411     mc->desc = "Calxeda Highbank (ECX-1000)";
 412     mc->init = highbank_init;
 413     mc->block_default_type = IF_IDE;
 414     mc->units_per_default_bus = 1;
 415     mc->max_cpus = 4;
 416     mc->ignore_memory_transaction_failures = true;
 417 }
 418
 419 static const TypeInfo highbank_type = {
 420     .name = MACHINE_TYPE_NAME("highbank"),
 421     .parent = TYPE_MACHINE,
 422     .class_init = highbank_class_init,
 423 };
 424
 425 static void midway_class_init(ObjectClass *oc, void *data)
 426 {
 427     MachineClass *mc = MACHINE_CLASS(oc);
 428
 429     mc->desc = "Calxeda Midway (ECX-2000)";
 430     mc->init = midway_init;
 431     mc->block_default_type = IF_IDE;
 432     mc->units_per_default_bus = 1;
 433     mc->max_cpus = 4;
 434     mc->ignore_memory_transaction_failures = true;
 435 }
 436
 437 static const TypeInfo midway_type = {
 438     .name = MACHINE_TYPE_NAME("midway"),
 439     .parent = TYPE_MACHINE,
 440     .class_init = midway_class_init,
 441 };
 442
 443 static void calxeda_machines_init(void)
 444 {
 445     type_register_static(&highbank_type);
 446     type_register_static(&midway_type);
 447 }
 448
 449 type_init(calxeda_machines_init)