?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
pc: acpi: drop cpu->found_cpus bitmap
[qemu/ar7.git] / hw / i386 / acpi-build.c
blob8736917f0b9a2bc2bb2b10ac6481a2e221792ff3
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "qemu/osdep.h"
24 #include "acpi-build.h"
25 #include <glib.h>
26 #include "qemu-common.h"
27 #include "qemu/bitmap.h"
28 #include "qemu/error-report.h"
29 #include "hw/pci/pci.h"
30 #include "qom/cpu.h"
31 #include "hw/i386/pc.h"
32 #include "target-i386/cpu.h"
33 #include "hw/timer/hpet.h"
34 #include "hw/acpi/acpi-defs.h"
35 #include "hw/acpi/acpi.h"
36 #include "hw/nvram/fw_cfg.h"
37 #include "hw/acpi/bios-linker-loader.h"
38 #include "hw/loader.h"
39 #include "hw/isa/isa.h"
40 #include "hw/block/fdc.h"
41 #include "hw/acpi/memory_hotplug.h"
42 #include "sysemu/tpm.h"
43 #include "hw/acpi/tpm.h"
44 #include "sysemu/tpm_backend.h"
45 #include "hw/timer/mc146818rtc_regs.h"
46
47 /* Supported chipsets: */
48 #include "hw/acpi/piix4.h"
49 #include "hw/acpi/pcihp.h"
50 #include "hw/i386/ich9.h"
51 #include "hw/pci/pci_bus.h"
52 #include "hw/pci-host/q35.h"
53 #include "hw/i386/intel_iommu.h"
54 #include "hw/timer/hpet.h"
55
56 #include "hw/acpi/aml-build.h"
57
58 #include "qapi/qmp/qint.h"
59 #include "qom/qom-qobject.h"
60
61 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
62 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
63 * a little bit, there should be plenty of free space since the DSDT
64 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
65 */
66 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
67 #define ACPI_BUILD_ALIGN_SIZE 0x1000
68
69 #define ACPI_BUILD_TABLE_SIZE 0x20000
70
71 /* #define DEBUG_ACPI_BUILD */
72 #ifdef DEBUG_ACPI_BUILD
73 #define ACPI_BUILD_DPRINTF(fmt, ...) \
74 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
75 #else
76 #define ACPI_BUILD_DPRINTF(fmt, ...)
77 #endif
78
79 typedef struct AcpiMcfgInfo {
80 uint64_t mcfg_base;
81 uint32_t mcfg_size;
82 } AcpiMcfgInfo;
83
84 typedef struct AcpiPmInfo {
85 bool s3_disabled;
86 bool s4_disabled;
87 bool pcihp_bridge_en;
88 uint8_t s4_val;
89 uint16_t sci_int;
90 uint8_t acpi_enable_cmd;
91 uint8_t acpi_disable_cmd;
92 uint32_t gpe0_blk;
93 uint32_t gpe0_blk_len;
94 uint32_t io_base;
95 uint16_t cpu_hp_io_base;
96 uint16_t cpu_hp_io_len;
97 uint16_t mem_hp_io_base;
98 uint16_t mem_hp_io_len;
99 uint16_t pcihp_io_base;
100 uint16_t pcihp_io_len;
101 } AcpiPmInfo;
102
103 typedef struct AcpiMiscInfo {
104 bool is_piix4;
105 bool has_hpet;
106 TPMVersion tpm_version;
107 const unsigned char *dsdt_code;
108 unsigned dsdt_size;
109 uint16_t pvpanic_port;
110 uint16_t applesmc_io_base;
111 } AcpiMiscInfo;
112
113 typedef struct AcpiBuildPciBusHotplugState {
114 GArray *device_table;
115 GArray *notify_table;
116 struct AcpiBuildPciBusHotplugState *parent;
117 bool pcihp_bridge_en;
118 } AcpiBuildPciBusHotplugState;
119
120 static void acpi_get_pm_info(AcpiPmInfo *pm)
121 {
122 Object *piix = piix4_pm_find();
123 Object *lpc = ich9_lpc_find();
124 Object *obj = NULL;
125 QObject *o;
126
127 pm->cpu_hp_io_base = 0;
128 pm->pcihp_io_base = 0;
129 pm->pcihp_io_len = 0;
130 if (piix) {
131 obj = piix;
132 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
133 pm->pcihp_io_base =
134 object_property_get_int(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
135 pm->pcihp_io_len =
136 object_property_get_int(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
137 }
138 if (lpc) {
139 obj = lpc;
140 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
141 }
142 assert(obj);
143
144 pm->cpu_hp_io_len = ACPI_GPE_PROC_LEN;
145 pm->mem_hp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
146 pm->mem_hp_io_len = ACPI_MEMORY_HOTPLUG_IO_LEN;
147
148 /* Fill in optional s3/s4 related properties */
149 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
150 if (o) {
151 pm->s3_disabled = qint_get_int(qobject_to_qint(o));
152 } else {
153 pm->s3_disabled = false;
154 }
155 qobject_decref(o);
156 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
157 if (o) {
158 pm->s4_disabled = qint_get_int(qobject_to_qint(o));
159 } else {
160 pm->s4_disabled = false;
161 }
162 qobject_decref(o);
163 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
164 if (o) {
165 pm->s4_val = qint_get_int(qobject_to_qint(o));
166 } else {
167 pm->s4_val = false;
168 }
169 qobject_decref(o);
170
171 /* Fill in mandatory properties */
172 pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL);
173
174 pm->acpi_enable_cmd = object_property_get_int(obj,
175 ACPI_PM_PROP_ACPI_ENABLE_CMD,
176 NULL);
177 pm->acpi_disable_cmd = object_property_get_int(obj,
178 ACPI_PM_PROP_ACPI_DISABLE_CMD,
179 NULL);
180 pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE,
181 NULL);
182 pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK,
183 NULL);
184 pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
185 NULL);
186 pm->pcihp_bridge_en =
187 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
188 NULL);
189 }
190
191 static void acpi_get_misc_info(AcpiMiscInfo *info)
192 {
193 Object *piix = piix4_pm_find();
194 Object *lpc = ich9_lpc_find();
195 assert(!!piix != !!lpc);
196
197 if (piix) {
198 info->is_piix4 = true;
199 }
200 if (lpc) {
201 info->is_piix4 = false;
202 }
203
204 info->has_hpet = hpet_find();
205 info->tpm_version = tpm_get_version();
206 info->pvpanic_port = pvpanic_port();
207 info->applesmc_io_base = applesmc_port();
208 }
209
210 /*
211 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
212 * On i386 arch we only have two pci hosts, so we can look only for them.
213 */
214 static Object *acpi_get_i386_pci_host(void)
215 {
216 PCIHostState *host;
217
218 host = OBJECT_CHECK(PCIHostState,
219 object_resolve_path("/machine/i440fx", NULL),
220 TYPE_PCI_HOST_BRIDGE);
221 if (!host) {
222 host = OBJECT_CHECK(PCIHostState,
223 object_resolve_path("/machine/q35", NULL),
224 TYPE_PCI_HOST_BRIDGE);
225 }
226
227 return OBJECT(host);
228 }
229
230 static void acpi_get_pci_info(PcPciInfo *info)
231 {
232 Object *pci_host;
233
234
235 pci_host = acpi_get_i386_pci_host();
236 g_assert(pci_host);
237
238 info->w32.begin = object_property_get_int(pci_host,
239 PCI_HOST_PROP_PCI_HOLE_START,
240 NULL);
241 info->w32.end = object_property_get_int(pci_host,
242 PCI_HOST_PROP_PCI_HOLE_END,
243 NULL);
244 info->w64.begin = object_property_get_int(pci_host,
245 PCI_HOST_PROP_PCI_HOLE64_START,
246 NULL);
247 info->w64.end = object_property_get_int(pci_host,
248 PCI_HOST_PROP_PCI_HOLE64_END,
249 NULL);
250 }
251
252 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
253
254 static void acpi_align_size(GArray *blob, unsigned align)
255 {
256 /* Align size to multiple of given size. This reduces the chance
257 * we need to change size in the future (breaking cross version migration).
258 */
259 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
260 }
261
262 /* FACS */
263 static void
264 build_facs(GArray *table_data, GArray *linker)
265 {
266 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
267 memcpy(&facs->signature, "FACS", 4);
268 facs->length = cpu_to_le32(sizeof(*facs));
269 }
270
271 /* Load chipset information in FADT */
272 static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm)
273 {
274 fadt->model = 1;
275 fadt->reserved1 = 0;
276 fadt->sci_int = cpu_to_le16(pm->sci_int);
277 fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD);
278 fadt->acpi_enable = pm->acpi_enable_cmd;
279 fadt->acpi_disable = pm->acpi_disable_cmd;
280 /* EVT, CNT, TMR offset matches hw/acpi/core.c */
281 fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base);
282 fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04);
283 fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08);
284 fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk);
285 /* EVT, CNT, TMR length matches hw/acpi/core.c */
286 fadt->pm1_evt_len = 4;
287 fadt->pm1_cnt_len = 2;
288 fadt->pm_tmr_len = 4;
289 fadt->gpe0_blk_len = pm->gpe0_blk_len;
290 fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */
291 fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */
292 fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) |
293 (1 << ACPI_FADT_F_PROC_C1) |
294 (1 << ACPI_FADT_F_SLP_BUTTON) |
295 (1 << ACPI_FADT_F_RTC_S4));
296 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK);
297 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs
298 * For more than 8 CPUs, "Clustered Logical" mode has to be used
299 */
300 if (max_cpus > 8) {
301 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL);
302 }
303 fadt->century = RTC_CENTURY;
304 }
305
306
307 /* FADT */
308 static void
309 build_fadt(GArray *table_data, GArray *linker, AcpiPmInfo *pm,
310 unsigned facs, unsigned dsdt,
311 const char *oem_id, const char *oem_table_id)
312 {
313 AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt));
314
315 fadt->firmware_ctrl = cpu_to_le32(facs);
316 /* FACS address to be filled by Guest linker */
317 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
318 ACPI_BUILD_TABLE_FILE,
319 table_data, &fadt->firmware_ctrl,
320 sizeof fadt->firmware_ctrl);
321
322 fadt->dsdt = cpu_to_le32(dsdt);
323 /* DSDT address to be filled by Guest linker */
324 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
325 ACPI_BUILD_TABLE_FILE,
326 table_data, &fadt->dsdt,
327 sizeof fadt->dsdt);
328
329 fadt_setup(fadt, pm);
330
331 build_header(linker, table_data,
332 (void *)fadt, "FACP", sizeof(*fadt), 1, oem_id, oem_table_id);
333 }
334
335 static void
336 build_madt(GArray *table_data, GArray *linker, PCMachineState *pcms)
337 {
338 MachineClass *mc = MACHINE_GET_CLASS(pcms);
339 CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(MACHINE(pcms));
340 int madt_start = table_data->len;
341
342 AcpiMultipleApicTable *madt;
343 AcpiMadtIoApic *io_apic;
344 AcpiMadtIntsrcovr *intsrcovr;
345 AcpiMadtLocalNmi *local_nmi;
346 int i;
347
348 madt = acpi_data_push(table_data, sizeof *madt);
349 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
350 madt->flags = cpu_to_le32(1);
351
352 for (i = 0; i < apic_ids->len; i++) {
353 AcpiMadtProcessorApic *apic = acpi_data_push(table_data, sizeof *apic);
354 int apic_id = apic_ids->cpus[i].arch_id;
355
356 apic->type = ACPI_APIC_PROCESSOR;
357 apic->length = sizeof(*apic);
358 apic->processor_id = apic_id;
359 apic->local_apic_id = apic_id;
360 if (apic_ids->cpus[i].cpu != NULL) {
361 apic->flags = cpu_to_le32(1);
362 } else {
363 apic->flags = cpu_to_le32(0);
364 }
365 }
366 g_free(apic_ids);
367
368 io_apic = acpi_data_push(table_data, sizeof *io_apic);
369 io_apic->type = ACPI_APIC_IO;
370 io_apic->length = sizeof(*io_apic);
371 #define ACPI_BUILD_IOAPIC_ID 0x0
372 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
373 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
374 io_apic->interrupt = cpu_to_le32(0);
375
376 if (pcms->apic_xrupt_override) {
377 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
378 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
379 intsrcovr->length = sizeof(*intsrcovr);
380 intsrcovr->source = 0;
381 intsrcovr->gsi = cpu_to_le32(2);
382 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */
383 }
384 for (i = 1; i < 16; i++) {
385 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
386 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
387 /* No need for a INT source override structure. */
388 continue;
389 }
390 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
391 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
392 intsrcovr->length = sizeof(*intsrcovr);
393 intsrcovr->source = i;
394 intsrcovr->gsi = cpu_to_le32(i);
395 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */
396 }
397
398 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
399 local_nmi->type = ACPI_APIC_LOCAL_NMI;
400 local_nmi->length = sizeof(*local_nmi);
401 local_nmi->processor_id = 0xff; /* all processors */
402 local_nmi->flags = cpu_to_le16(0);
403 local_nmi->lint = 1; /* ACPI_LINT1 */
404
405 build_header(linker, table_data,
406 (void *)(table_data->data + madt_start), "APIC",
407 table_data->len - madt_start, 1, NULL, NULL);
408 }
409
410 /* Assign BSEL property to all buses. In the future, this can be changed
411 * to only assign to buses that support hotplug.
412 */
413 static void *acpi_set_bsel(PCIBus *bus, void *opaque)
414 {
415 unsigned *bsel_alloc = opaque;
416 unsigned *bus_bsel;
417
418 if (qbus_is_hotpluggable(BUS(bus))) {
419 bus_bsel = g_malloc(sizeof *bus_bsel);
420
421 *bus_bsel = (*bsel_alloc)++;
422 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL,
423 bus_bsel, NULL);
424 }
425
426 return bsel_alloc;
427 }
428
429 static void acpi_set_pci_info(void)
430 {
431 PCIBus *bus = find_i440fx(); /* TODO: Q35 support */
432 unsigned bsel_alloc = 0;
433
434 if (bus) {
435 /* Scan all PCI buses. Set property to enable acpi based hotplug. */
436 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc);
437 }
438 }
439
440 static void build_append_pcihp_notify_entry(Aml *method, int slot)
441 {
442 Aml *if_ctx;
443 int32_t devfn = PCI_DEVFN(slot, 0);
444
445 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
446 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
447 aml_append(method, if_ctx);
448 }
449
450 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
451 bool pcihp_bridge_en)
452 {
453 Aml *dev, *notify_method, *method;
454 QObject *bsel;
455 PCIBus *sec;
456 int i;
457
458 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
459 if (bsel) {
460 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
461
462 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
463 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
464 }
465
466 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
467 DeviceClass *dc;
468 PCIDeviceClass *pc;
469 PCIDevice *pdev = bus->devices[i];
470 int slot = PCI_SLOT(i);
471 bool hotplug_enabled_dev;
472 bool bridge_in_acpi;
473
474 if (!pdev) {
475 if (bsel) { /* add hotplug slots for non present devices */
476 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
477 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
478 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
479 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
480 aml_append(method,
481 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
482 );
483 aml_append(dev, method);
484 aml_append(parent_scope, dev);
485
486 build_append_pcihp_notify_entry(notify_method, slot);
487 }
488 continue;
489 }
490
491 pc = PCI_DEVICE_GET_CLASS(pdev);
492 dc = DEVICE_GET_CLASS(pdev);
493
494 /* When hotplug for bridges is enabled, bridges are
495 * described in ACPI separately (see build_pci_bus_end).
496 * In this case they aren't themselves hot-pluggable.
497 * Hotplugged bridges *are* hot-pluggable.
498 */
499 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en &&
500 !DEVICE(pdev)->hotplugged;
501
502 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi;
503
504 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
505 continue;
506 }
507
508 /* start to compose PCI slot descriptor */
509 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
510 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
511
512 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
513 /* add VGA specific AML methods */
514 int s3d;
515
516 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
517 s3d = 3;
518 } else {
519 s3d = 0;
520 }
521
522 method = aml_method("_S1D", 0, AML_NOTSERIALIZED);
523 aml_append(method, aml_return(aml_int(0)));
524 aml_append(dev, method);
525
526 method = aml_method("_S2D", 0, AML_NOTSERIALIZED);
527 aml_append(method, aml_return(aml_int(0)));
528 aml_append(dev, method);
529
530 method = aml_method("_S3D", 0, AML_NOTSERIALIZED);
531 aml_append(method, aml_return(aml_int(s3d)));
532 aml_append(dev, method);
533 } else if (hotplug_enabled_dev) {
534 /* add _SUN/_EJ0 to make slot hotpluggable */
535 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
536
537 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
538 aml_append(method,
539 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
540 );
541 aml_append(dev, method);
542
543 if (bsel) {
544 build_append_pcihp_notify_entry(notify_method, slot);
545 }
546 } else if (bridge_in_acpi) {
547 /*
548 * device is coldplugged bridge,
549 * add child device descriptions into its scope
550 */
551 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
552
553 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
554 }
555 /* slot descriptor has been composed, add it into parent context */
556 aml_append(parent_scope, dev);
557 }
558
559 if (bsel) {
560 aml_append(parent_scope, notify_method);
561 }
562
563 /* Append PCNT method to notify about events on local and child buses.
564 * Add unconditionally for root since DSDT expects it.
565 */
566 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
567
568 /* If bus supports hotplug select it and notify about local events */
569 if (bsel) {
570 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
571 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
572 aml_append(method,
573 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
574 );
575 aml_append(method,
576 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
577 );
578 }
579
580 /* Notify about child bus events in any case */
581 if (pcihp_bridge_en) {
582 QLIST_FOREACH(sec, &bus->child, sibling) {
583 int32_t devfn = sec->parent_dev->devfn;
584
585 aml_append(method, aml_name("^S%.02X.PCNT", devfn));
586 }
587 }
588 aml_append(parent_scope, method);
589 qobject_decref(bsel);
590 }
591
592 /**
593 * build_prt_entry:
594 * @link_name: link name for PCI route entry
595 *
596 * build AML package containing a PCI route entry for @link_name
597 */
598 static Aml *build_prt_entry(const char *link_name)
599 {
600 Aml *a_zero = aml_int(0);
601 Aml *pkg = aml_package(4);
602 aml_append(pkg, a_zero);
603 aml_append(pkg, a_zero);
604 aml_append(pkg, aml_name("%s", link_name));
605 aml_append(pkg, a_zero);
606 return pkg;
607 }
608
609 /*
610 * initialize_route - Initialize the interrupt routing rule
611 * through a specific LINK:
612 * if (lnk_idx == idx)
613 * route using link 'link_name'
614 */
615 static Aml *initialize_route(Aml *route, const char *link_name,
616 Aml *lnk_idx, int idx)
617 {
618 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
619 Aml *pkg = build_prt_entry(link_name);
620
621 aml_append(if_ctx, aml_store(pkg, route));
622
623 return if_ctx;
624 }
625
626 /*
627 * build_prt - Define interrupt rounting rules
628 *
629 * Returns an array of 128 routes, one for each device,
630 * based on device location.
631 * The main goal is to equaly distribute the interrupts
632 * over the 4 existing ACPI links (works only for i440fx).
633 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
634 *
635 */
636 static Aml *build_prt(bool is_pci0_prt)
637 {
638 Aml *method, *while_ctx, *pin, *res;
639
640 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
641 res = aml_local(0);
642 pin = aml_local(1);
643 aml_append(method, aml_store(aml_package(128), res));
644 aml_append(method, aml_store(aml_int(0), pin));
645
646 /* while (pin < 128) */
647 while_ctx = aml_while(aml_lless(pin, aml_int(128)));
648 {
649 Aml *slot = aml_local(2);
650 Aml *lnk_idx = aml_local(3);
651 Aml *route = aml_local(4);
652
653 /* slot = pin >> 2 */
654 aml_append(while_ctx,
655 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
656 /* lnk_idx = (slot + pin) & 3 */
657 aml_append(while_ctx,
658 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL),
659 lnk_idx));
660
661 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
662 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
663 if (is_pci0_prt) {
664 Aml *if_device_1, *if_pin_4, *else_pin_4;
665
666 /* device 1 is the power-management device, needs SCI */
667 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1)));
668 {
669 if_pin_4 = aml_if(aml_equal(pin, aml_int(4)));
670 {
671 aml_append(if_pin_4,
672 aml_store(build_prt_entry("LNKS"), route));
673 }
674 aml_append(if_device_1, if_pin_4);
675 else_pin_4 = aml_else();
676 {
677 aml_append(else_pin_4,
678 aml_store(build_prt_entry("LNKA"), route));
679 }
680 aml_append(if_device_1, else_pin_4);
681 }
682 aml_append(while_ctx, if_device_1);
683 } else {
684 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
685 }
686 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
687 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
688
689 /* route[0] = 0x[slot]FFFF */
690 aml_append(while_ctx,
691 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF),
692 NULL),
693 aml_index(route, aml_int(0))));
694 /* route[1] = pin & 3 */
695 aml_append(while_ctx,
696 aml_store(aml_and(pin, aml_int(3), NULL),
697 aml_index(route, aml_int(1))));
698 /* res[pin] = route */
699 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
700 /* pin++ */
701 aml_append(while_ctx, aml_increment(pin));
702 }
703 aml_append(method, while_ctx);
704 /* return res*/
705 aml_append(method, aml_return(res));
706
707 return method;
708 }
709
710 typedef struct CrsRangeEntry {
711 uint64_t base;
712 uint64_t limit;
713 } CrsRangeEntry;
714
715 static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit)
716 {
717 CrsRangeEntry *entry;
718
719 entry = g_malloc(sizeof(*entry));
720 entry->base = base;
721 entry->limit = limit;
722
723 g_ptr_array_add(ranges, entry);
724 }
725
726 static void crs_range_free(gpointer data)
727 {
728 CrsRangeEntry *entry = (CrsRangeEntry *)data;
729 g_free(entry);
730 }
731
732 static gint crs_range_compare(gconstpointer a, gconstpointer b)
733 {
734 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a;
735 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b;
736
737 return (int64_t)entry_a->base - (int64_t)entry_b->base;
738 }
739
740 /*
741 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
742 * interval, computes the 'free' ranges from the same interval.
743 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
744 * will return { [base - a1], [a2 - b1], [b2 - limit] }.
745 */
746 static void crs_replace_with_free_ranges(GPtrArray *ranges,
747 uint64_t start, uint64_t end)
748 {
749 GPtrArray *free_ranges = g_ptr_array_new_with_free_func(crs_range_free);
750 uint64_t free_base = start;
751 int i;
752
753 g_ptr_array_sort(ranges, crs_range_compare);
754 for (i = 0; i < ranges->len; i++) {
755 CrsRangeEntry *used = g_ptr_array_index(ranges, i);
756
757 if (free_base < used->base) {
758 crs_range_insert(free_ranges, free_base, used->base - 1);
759 }
760
761 free_base = used->limit + 1;
762 }
763
764 if (free_base < end) {
765 crs_range_insert(free_ranges, free_base, end);
766 }
767
768 g_ptr_array_set_size(ranges, 0);
769 for (i = 0; i < free_ranges->len; i++) {
770 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i));
771 }
772
773 g_ptr_array_free(free_ranges, false);
774 }
775
776 /*
777 * crs_range_merge - merges adjacent ranges in the given array.
778 * Array elements are deleted and replaced with the merged ranges.
779 */
780 static void crs_range_merge(GPtrArray *range)
781 {
782 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free);
783 CrsRangeEntry *entry;
784 uint64_t range_base, range_limit;
785 int i;
786
787 if (!range->len) {
788 return;
789 }
790
791 g_ptr_array_sort(range, crs_range_compare);
792
793 entry = g_ptr_array_index(range, 0);
794 range_base = entry->base;
795 range_limit = entry->limit;
796 for (i = 1; i < range->len; i++) {
797 entry = g_ptr_array_index(range, i);
798 if (entry->base - 1 == range_limit) {
799 range_limit = entry->limit;
800 } else {
801 crs_range_insert(tmp, range_base, range_limit);
802 range_base = entry->base;
803 range_limit = entry->limit;
804 }
805 }
806 crs_range_insert(tmp, range_base, range_limit);
807
808 g_ptr_array_set_size(range, 0);
809 for (i = 0; i < tmp->len; i++) {
810 entry = g_ptr_array_index(tmp, i);
811 crs_range_insert(range, entry->base, entry->limit);
812 }
813 g_ptr_array_free(tmp, true);
814 }
815
816 static Aml *build_crs(PCIHostState *host,
817 GPtrArray *io_ranges, GPtrArray *mem_ranges)
818 {
819 Aml *crs = aml_resource_template();
820 GPtrArray *host_io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
821 GPtrArray *host_mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
822 CrsRangeEntry *entry;
823 uint8_t max_bus = pci_bus_num(host->bus);
824 uint8_t type;
825 int devfn;
826 int i;
827
828 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
829 uint64_t range_base, range_limit;
830 PCIDevice *dev = host->bus->devices[devfn];
831
832 if (!dev) {
833 continue;
834 }
835
836 for (i = 0; i < PCI_NUM_REGIONS; i++) {
837 PCIIORegion *r = &dev->io_regions[i];
838
839 range_base = r->addr;
840 range_limit = r->addr + r->size - 1;
841
842 /*
843 * Work-around for old bioses
844 * that do not support multiple root buses
845 */
846 if (!range_base || range_base > range_limit) {
847 continue;
848 }
849
850 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
851 crs_range_insert(host_io_ranges, range_base, range_limit);
852 } else { /* "memory" */
853 crs_range_insert(host_mem_ranges, range_base, range_limit);
854 }
855 }
856
857 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
858 if (type == PCI_HEADER_TYPE_BRIDGE) {
859 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS];
860 if (subordinate > max_bus) {
861 max_bus = subordinate;
862 }
863
864 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
865 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
866
867 /*
868 * Work-around for old bioses
869 * that do not support multiple root buses
870 */
871 if (range_base && range_base <= range_limit) {
872 crs_range_insert(host_io_ranges, range_base, range_limit);
873 }
874
875 range_base =
876 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
877 range_limit =
878 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
879
880 /*
881 * Work-around for old bioses
882 * that do not support multiple root buses
883 */
884 if (range_base && range_base <= range_limit) {
885 crs_range_insert(host_mem_ranges, range_base, range_limit);
886 }
887
888 range_base =
889 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
890 range_limit =
891 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
892
893 /*
894 * Work-around for old bioses
895 * that do not support multiple root buses
896 */
897 if (range_base && range_base <= range_limit) {
898 crs_range_insert(host_mem_ranges, range_base, range_limit);
899 }
900 }
901 }
902
903 crs_range_merge(host_io_ranges);
904 for (i = 0; i < host_io_ranges->len; i++) {
905 entry = g_ptr_array_index(host_io_ranges, i);
906 aml_append(crs,
907 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
908 AML_POS_DECODE, AML_ENTIRE_RANGE,
909 0, entry->base, entry->limit, 0,
910 entry->limit - entry->base + 1));
911 crs_range_insert(io_ranges, entry->base, entry->limit);
912 }
913 g_ptr_array_free(host_io_ranges, true);
914
915 crs_range_merge(host_mem_ranges);
916 for (i = 0; i < host_mem_ranges->len; i++) {
917 entry = g_ptr_array_index(host_mem_ranges, i);
918 aml_append(crs,
919 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
920 AML_MAX_FIXED, AML_NON_CACHEABLE,
921 AML_READ_WRITE,
922 0, entry->base, entry->limit, 0,
923 entry->limit - entry->base + 1));
924 crs_range_insert(mem_ranges, entry->base, entry->limit);
925 }
926 g_ptr_array_free(host_mem_ranges, true);
927
928 aml_append(crs,
929 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
930 0,
931 pci_bus_num(host->bus),
932 max_bus,
933 0,
934 max_bus - pci_bus_num(host->bus) + 1));
935
936 return crs;
937 }
938
939 static void build_processor_devices(Aml *sb_scope, MachineState *machine,
940 AcpiPmInfo *pm)
941 {
942 int i, apic_idx;
943 Aml *dev;
944 Aml *crs;
945 Aml *pkg;
946 Aml *field;
947 Aml *ifctx;
948 Aml *method;
949 MachineClass *mc = MACHINE_GET_CLASS(machine);
950 CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
951 PCMachineState *pcms = PC_MACHINE(machine);
952
953 /* The current AML generator can cover the APIC ID range [0..255],
954 * inclusive, for VCPU hotplug. */
955 QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT > 256);
956 g_assert(pcms->apic_id_limit <= ACPI_CPU_HOTPLUG_ID_LIMIT);
957
958 /* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */
959 dev = aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE));
960 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
961 aml_append(dev,
962 aml_name_decl("_UID", aml_string("CPU Hotplug resources"))
963 );
964 /* device present, functioning, decoding, not shown in UI */
965 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
966 crs = aml_resource_template();
967 aml_append(crs,
968 aml_io(AML_DECODE16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1,
969 pm->cpu_hp_io_len)
970 );
971 aml_append(dev, aml_name_decl("_CRS", crs));
972 aml_append(sb_scope, dev);
973 /* declare CPU hotplug MMIO region and PRS field to access it */
974 aml_append(sb_scope, aml_operation_region(
975 "PRST", AML_SYSTEM_IO, aml_int(pm->cpu_hp_io_base), pm->cpu_hp_io_len));
976 field = aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
977 aml_append(field, aml_named_field("PRS", 256));
978 aml_append(sb_scope, field);
979
980 /* build Processor object for each processor */
981 for (i = 0; i < apic_ids->len; i++) {
982 int apic_id = apic_ids->cpus[i].arch_id;
983
984 assert(apic_id < ACPI_CPU_HOTPLUG_ID_LIMIT);
985
986 dev = aml_processor(apic_id, 0, 0, "CP%.02X", apic_id);
987
988 method = aml_method("_MAT", 0, AML_NOTSERIALIZED);
989 aml_append(method,
990 aml_return(aml_call1(CPU_MAT_METHOD, aml_int(apic_id))));
991 aml_append(dev, method);
992
993 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
994 aml_append(method,
995 aml_return(aml_call1(CPU_STATUS_METHOD, aml_int(apic_id))));
996 aml_append(dev, method);
997
998 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
999 aml_append(method,
1000 aml_return(aml_call2(CPU_EJECT_METHOD, aml_int(apic_id),
1001 aml_arg(0)))
1002 );
1003 aml_append(dev, method);
1004
1005 aml_append(sb_scope, dev);
1006 }
1007
1008 /* build this code:
1009 * Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...}
1010 */
1011 /* Arg0 = Processor ID = APIC ID */
1012 method = aml_method(AML_NOTIFY_METHOD, 2, AML_NOTSERIALIZED);
1013 for (i = 0; i < apic_ids->len; i++) {
1014 int apic_id = apic_ids->cpus[i].arch_id;
1015
1016 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(apic_id)));
1017 aml_append(ifctx,
1018 aml_notify(aml_name("CP%.02X", apic_id), aml_arg(1))
1019 );
1020 aml_append(method, ifctx);
1021 }
1022 aml_append(sb_scope, method);
1023
1024 /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })"
1025 *
1026 * Note: The ability to create variable-sized packages was first
1027 * introduced in ACPI 2.0. ACPI 1.0 only allowed fixed-size packages
1028 * ith up to 255 elements. Windows guests up to win2k8 fail when
1029 * VarPackageOp is used.
1030 */
1031 pkg = pcms->apic_id_limit <= 255 ? aml_package(pcms->apic_id_limit) :
1032 aml_varpackage(pcms->apic_id_limit);
1033
1034 for (i = 0, apic_idx = 0; i < apic_ids->len; i++) {
1035 int apic_id = apic_ids->cpus[i].arch_id;
1036
1037 for (; apic_idx < apic_id; apic_idx++) {
1038 aml_append(pkg, aml_int(0));
1039 }
1040 aml_append(pkg, aml_int(apic_ids->cpus[i].cpu ? 1 : 0));
1041 apic_idx = apic_id + 1;
1042 }
1043 aml_append(sb_scope, aml_name_decl(CPU_ON_BITMAP, pkg));
1044 g_free(apic_ids);
1045 }
1046
1047 static void build_memory_devices(Aml *sb_scope, int nr_mem,
1048 uint16_t io_base, uint16_t io_len)
1049 {
1050 int i;
1051 Aml *scope;
1052 Aml *crs;
1053 Aml *field;
1054 Aml *dev;
1055 Aml *method;
1056 Aml *ifctx;
1057
1058 /* build memory devices */
1059 assert(nr_mem <= ACPI_MAX_RAM_SLOTS);
1060 scope = aml_scope("\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE);
1061 aml_append(scope,
1062 aml_name_decl(MEMORY_SLOTS_NUMBER, aml_int(nr_mem))
1063 );
1064
1065 crs = aml_resource_template();
1066 aml_append(crs,
1067 aml_io(AML_DECODE16, io_base, io_base, 0, io_len)
1068 );
1069 aml_append(scope, aml_name_decl("_CRS", crs));
1070
1071 aml_append(scope, aml_operation_region(
1072 MEMORY_HOTPLUG_IO_REGION, AML_SYSTEM_IO,
1073 aml_int(io_base), io_len)
1074 );
1075
1076 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC,
1077 AML_NOLOCK, AML_PRESERVE);
1078 aml_append(field, /* read only */
1079 aml_named_field(MEMORY_SLOT_ADDR_LOW, 32));
1080 aml_append(field, /* read only */
1081 aml_named_field(MEMORY_SLOT_ADDR_HIGH, 32));
1082 aml_append(field, /* read only */
1083 aml_named_field(MEMORY_SLOT_SIZE_LOW, 32));
1084 aml_append(field, /* read only */
1085 aml_named_field(MEMORY_SLOT_SIZE_HIGH, 32));
1086 aml_append(field, /* read only */
1087 aml_named_field(MEMORY_SLOT_PROXIMITY, 32));
1088 aml_append(scope, field);
1089
1090 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_BYTE_ACC,
1091 AML_NOLOCK, AML_WRITE_AS_ZEROS);
1092 aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */));
1093 aml_append(field, /* 1 if enabled, read only */
1094 aml_named_field(MEMORY_SLOT_ENABLED, 1));
1095 aml_append(field,
1096 /*(read) 1 if has a insert event. (write) 1 to clear event */
1097 aml_named_field(MEMORY_SLOT_INSERT_EVENT, 1));
1098 aml_append(field,
1099 /* (read) 1 if has a remove event. (write) 1 to clear event */
1100 aml_named_field(MEMORY_SLOT_REMOVE_EVENT, 1));
1101 aml_append(field,
1102 /* initiates device eject, write only */
1103 aml_named_field(MEMORY_SLOT_EJECT, 1));
1104 aml_append(scope, field);
1105
1106 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC,
1107 AML_NOLOCK, AML_PRESERVE);
1108 aml_append(field, /* DIMM selector, write only */
1109 aml_named_field(MEMORY_SLOT_SLECTOR, 32));
1110 aml_append(field, /* _OST event code, write only */
1111 aml_named_field(MEMORY_SLOT_OST_EVENT, 32));
1112 aml_append(field, /* _OST status code, write only */
1113 aml_named_field(MEMORY_SLOT_OST_STATUS, 32));
1114 aml_append(scope, field);
1115 aml_append(sb_scope, scope);
1116
1117 for (i = 0; i < nr_mem; i++) {
1118 #define BASEPATH "\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE "."
1119 const char *s;
1120
1121 dev = aml_device("MP%02X", i);
1122 aml_append(dev, aml_name_decl("_UID", aml_string("0x%02X", i)));
1123 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C80")));
1124
1125 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1126 s = BASEPATH MEMORY_SLOT_CRS_METHOD;
1127 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1128 aml_append(dev, method);
1129
1130 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1131 s = BASEPATH MEMORY_SLOT_STATUS_METHOD;
1132 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1133 aml_append(dev, method);
1134
1135 method = aml_method("_PXM", 0, AML_NOTSERIALIZED);
1136 s = BASEPATH MEMORY_SLOT_PROXIMITY_METHOD;
1137 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1138 aml_append(dev, method);
1139
1140 method = aml_method("_OST", 3, AML_NOTSERIALIZED);
1141 s = BASEPATH MEMORY_SLOT_OST_METHOD;
1142
1143 aml_append(method, aml_return(aml_call4(
1144 s, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2)
1145 )));
1146 aml_append(dev, method);
1147
1148 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
1149 s = BASEPATH MEMORY_SLOT_EJECT_METHOD;
1150 aml_append(method, aml_return(aml_call2(
1151 s, aml_name("_UID"), aml_arg(0))));
1152 aml_append(dev, method);
1153
1154 aml_append(sb_scope, dev);
1155 }
1156
1157 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) {
1158 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... }
1159 */
1160 method = aml_method(MEMORY_SLOT_NOTIFY_METHOD, 2, AML_NOTSERIALIZED);
1161 for (i = 0; i < nr_mem; i++) {
1162 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
1163 aml_append(ifctx,
1164 aml_notify(aml_name("MP%.02X", i), aml_arg(1))
1165 );
1166 aml_append(method, ifctx);
1167 }
1168 aml_append(sb_scope, method);
1169 }
1170
1171 static void build_hpet_aml(Aml *table)
1172 {
1173 Aml *crs;
1174 Aml *field;
1175 Aml *method;
1176 Aml *if_ctx;
1177 Aml *scope = aml_scope("_SB");
1178 Aml *dev = aml_device("HPET");
1179 Aml *zero = aml_int(0);
1180 Aml *id = aml_local(0);
1181 Aml *period = aml_local(1);
1182
1183 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
1184 aml_append(dev, aml_name_decl("_UID", zero));
1185
1186 aml_append(dev,
1187 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE),
1188 HPET_LEN));
1189 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
1190 aml_append(field, aml_named_field("VEND", 32));
1191 aml_append(field, aml_named_field("PRD", 32));
1192 aml_append(dev, field);
1193
1194 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1195 aml_append(method, aml_store(aml_name("VEND"), id));
1196 aml_append(method, aml_store(aml_name("PRD"), period));
1197 aml_append(method, aml_shiftright(id, aml_int(16), id));
1198 if_ctx = aml_if(aml_lor(aml_equal(id, zero),
1199 aml_equal(id, aml_int(0xffff))));
1200 {
1201 aml_append(if_ctx, aml_return(zero));
1202 }
1203 aml_append(method, if_ctx);
1204
1205 if_ctx = aml_if(aml_lor(aml_equal(period, zero),
1206 aml_lgreater(period, aml_int(100000000))));
1207 {
1208 aml_append(if_ctx, aml_return(zero));
1209 }
1210 aml_append(method, if_ctx);
1211
1212 aml_append(method, aml_return(aml_int(0x0F)));
1213 aml_append(dev, method);
1214
1215 crs = aml_resource_template();
1216 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
1217 aml_append(dev, aml_name_decl("_CRS", crs));
1218
1219 aml_append(scope, dev);
1220 aml_append(table, scope);
1221 }
1222
1223 static Aml *build_fdinfo_aml(int idx, FloppyDriveType type)
1224 {
1225 Aml *dev, *fdi;
1226 uint8_t maxc, maxh, maxs;
1227
1228 isa_fdc_get_drive_max_chs(type, &maxc, &maxh, &maxs);
1229
1230 dev = aml_device("FLP%c", 'A' + idx);
1231
1232 aml_append(dev, aml_name_decl("_ADR", aml_int(idx)));
1233
1234 fdi = aml_package(16);
1235 aml_append(fdi, aml_int(idx)); /* Drive Number */
1236 aml_append(fdi,
1237 aml_int(cmos_get_fd_drive_type(type))); /* Device Type */
1238 /*
1239 * the values below are the limits of the drive, and are thus independent
1240 * of the inserted media
1241 */
1242 aml_append(fdi, aml_int(maxc)); /* Maximum Cylinder Number */
1243 aml_append(fdi, aml_int(maxs)); /* Maximum Sector Number */
1244 aml_append(fdi, aml_int(maxh)); /* Maximum Head Number */
1245 /*
1246 * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of
1247 * the drive type, so shall we
1248 */
1249 aml_append(fdi, aml_int(0xAF)); /* disk_specify_1 */
1250 aml_append(fdi, aml_int(0x02)); /* disk_specify_2 */
1251 aml_append(fdi, aml_int(0x25)); /* disk_motor_wait */
1252 aml_append(fdi, aml_int(0x02)); /* disk_sector_siz */
1253 aml_append(fdi, aml_int(0x12)); /* disk_eot */
1254 aml_append(fdi, aml_int(0x1B)); /* disk_rw_gap */
1255 aml_append(fdi, aml_int(0xFF)); /* disk_dtl */
1256 aml_append(fdi, aml_int(0x6C)); /* disk_formt_gap */
1257 aml_append(fdi, aml_int(0xF6)); /* disk_fill */
1258 aml_append(fdi, aml_int(0x0F)); /* disk_head_sttl */
1259 aml_append(fdi, aml_int(0x08)); /* disk_motor_strt */
1260
1261 aml_append(dev, aml_name_decl("_FDI", fdi));
1262 return dev;
1263 }
1264
1265 static Aml *build_fdc_device_aml(ISADevice *fdc)
1266 {
1267 int i;
1268 Aml *dev;
1269 Aml *crs;
1270
1271 #define ACPI_FDE_MAX_FD 4
1272 uint32_t fde_buf[5] = {
1273 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */
1274 cpu_to_le32(2) /* tape presence (2 == never present) */
1275 };
1276
1277 dev = aml_device("FDC0");
1278 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700")));
1279
1280 crs = aml_resource_template();
1281 aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04));
1282 aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01));
1283 aml_append(crs, aml_irq_no_flags(6));
1284 aml_append(crs,
1285 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2));
1286 aml_append(dev, aml_name_decl("_CRS", crs));
1287
1288 for (i = 0; i < MIN(MAX_FD, ACPI_FDE_MAX_FD); i++) {
1289 FloppyDriveType type = isa_fdc_get_drive_type(fdc, i);
1290
1291 if (type < FLOPPY_DRIVE_TYPE_NONE) {
1292 fde_buf[i] = cpu_to_le32(1); /* drive present */
1293 aml_append(dev, build_fdinfo_aml(i, type));
1294 }
1295 }
1296 aml_append(dev, aml_name_decl("_FDE",
1297 aml_buffer(sizeof(fde_buf), (uint8_t *)fde_buf)));
1298
1299 return dev;
1300 }
1301
1302 static Aml *build_rtc_device_aml(void)
1303 {
1304 Aml *dev;
1305 Aml *crs;
1306
1307 dev = aml_device("RTC");
1308 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
1309 crs = aml_resource_template();
1310 aml_append(crs, aml_io(AML_DECODE16, 0x0070, 0x0070, 0x10, 0x02));
1311 aml_append(crs, aml_irq_no_flags(8));
1312 aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06));
1313 aml_append(dev, aml_name_decl("_CRS", crs));
1314
1315 return dev;
1316 }
1317
1318 static Aml *build_kbd_device_aml(void)
1319 {
1320 Aml *dev;
1321 Aml *crs;
1322 Aml *method;
1323
1324 dev = aml_device("KBD");
1325 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0303")));
1326
1327 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1328 aml_append(method, aml_return(aml_int(0x0f)));
1329 aml_append(dev, method);
1330
1331 crs = aml_resource_template();
1332 aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01));
1333 aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01));
1334 aml_append(crs, aml_irq_no_flags(1));
1335 aml_append(dev, aml_name_decl("_CRS", crs));
1336
1337 return dev;
1338 }
1339
1340 static Aml *build_mouse_device_aml(void)
1341 {
1342 Aml *dev;
1343 Aml *crs;
1344 Aml *method;
1345
1346 dev = aml_device("MOU");
1347 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
1348
1349 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1350 aml_append(method, aml_return(aml_int(0x0f)));
1351 aml_append(dev, method);
1352
1353 crs = aml_resource_template();
1354 aml_append(crs, aml_irq_no_flags(12));
1355 aml_append(dev, aml_name_decl("_CRS", crs));
1356
1357 return dev;
1358 }
1359
1360 static Aml *build_lpt_device_aml(void)
1361 {
1362 Aml *dev;
1363 Aml *crs;
1364 Aml *method;
1365 Aml *if_ctx;
1366 Aml *else_ctx;
1367 Aml *zero = aml_int(0);
1368 Aml *is_present = aml_local(0);
1369
1370 dev = aml_device("LPT");
1371 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400")));
1372
1373 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1374 aml_append(method, aml_store(aml_name("LPEN"), is_present));
1375 if_ctx = aml_if(aml_equal(is_present, zero));
1376 {
1377 aml_append(if_ctx, aml_return(aml_int(0x00)));
1378 }
1379 aml_append(method, if_ctx);
1380 else_ctx = aml_else();
1381 {
1382 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1383 }
1384 aml_append(method, else_ctx);
1385 aml_append(dev, method);
1386
1387 crs = aml_resource_template();
1388 aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08));
1389 aml_append(crs, aml_irq_no_flags(7));
1390 aml_append(dev, aml_name_decl("_CRS", crs));
1391
1392 return dev;
1393 }
1394
1395 static Aml *build_com_device_aml(uint8_t uid)
1396 {
1397 Aml *dev;
1398 Aml *crs;
1399 Aml *method;
1400 Aml *if_ctx;
1401 Aml *else_ctx;
1402 Aml *zero = aml_int(0);
1403 Aml *is_present = aml_local(0);
1404 const char *enabled_field = "CAEN";
1405 uint8_t irq = 4;
1406 uint16_t io_port = 0x03F8;
1407
1408 assert(uid == 1 || uid == 2);
1409 if (uid == 2) {
1410 enabled_field = "CBEN";
1411 irq = 3;
1412 io_port = 0x02F8;
1413 }
1414
1415 dev = aml_device("COM%d", uid);
1416 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501")));
1417 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1418
1419 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1420 aml_append(method, aml_store(aml_name("%s", enabled_field), is_present));
1421 if_ctx = aml_if(aml_equal(is_present, zero));
1422 {
1423 aml_append(if_ctx, aml_return(aml_int(0x00)));
1424 }
1425 aml_append(method, if_ctx);
1426 else_ctx = aml_else();
1427 {
1428 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1429 }
1430 aml_append(method, else_ctx);
1431 aml_append(dev, method);
1432
1433 crs = aml_resource_template();
1434 aml_append(crs, aml_io(AML_DECODE16, io_port, io_port, 0x00, 0x08));
1435 aml_append(crs, aml_irq_no_flags(irq));
1436 aml_append(dev, aml_name_decl("_CRS", crs));
1437
1438 return dev;
1439 }
1440
1441 static void build_isa_devices_aml(Aml *table)
1442 {
1443 ISADevice *fdc = pc_find_fdc0();
1444
1445 Aml *scope = aml_scope("_SB.PCI0.ISA");
1446
1447 aml_append(scope, build_rtc_device_aml());
1448 aml_append(scope, build_kbd_device_aml());
1449 aml_append(scope, build_mouse_device_aml());
1450 if (fdc) {
1451 aml_append(scope, build_fdc_device_aml(fdc));
1452 }
1453 aml_append(scope, build_lpt_device_aml());
1454 aml_append(scope, build_com_device_aml(1));
1455 aml_append(scope, build_com_device_aml(2));
1456
1457 aml_append(table, scope);
1458 }
1459
1460 static void build_dbg_aml(Aml *table)
1461 {
1462 Aml *field;
1463 Aml *method;
1464 Aml *while_ctx;
1465 Aml *scope = aml_scope("\\");
1466 Aml *buf = aml_local(0);
1467 Aml *len = aml_local(1);
1468 Aml *idx = aml_local(2);
1469
1470 aml_append(scope,
1471 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
1472 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1473 aml_append(field, aml_named_field("DBGB", 8));
1474 aml_append(scope, field);
1475
1476 method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
1477
1478 aml_append(method, aml_to_hexstring(aml_arg(0), buf));
1479 aml_append(method, aml_to_buffer(buf, buf));
1480 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
1481 aml_append(method, aml_store(aml_int(0), idx));
1482
1483 while_ctx = aml_while(aml_lless(idx, len));
1484 aml_append(while_ctx,
1485 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
1486 aml_append(while_ctx, aml_increment(idx));
1487 aml_append(method, while_ctx);
1488
1489 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
1490 aml_append(scope, method);
1491
1492 aml_append(table, scope);
1493 }
1494
1495 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
1496 {
1497 Aml *dev;
1498 Aml *crs;
1499 Aml *method;
1500 uint32_t irqs[] = {5, 10, 11};
1501
1502 dev = aml_device("%s", name);
1503 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1504 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1505
1506 crs = aml_resource_template();
1507 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1508 AML_SHARED, irqs, ARRAY_SIZE(irqs)));
1509 aml_append(dev, aml_name_decl("_PRS", crs));
1510
1511 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1512 aml_append(method, aml_return(aml_call1("IQST", reg)));
1513 aml_append(dev, method);
1514
1515 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1516 aml_append(method, aml_or(reg, aml_int(0x80), reg));
1517 aml_append(dev, method);
1518
1519 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1520 aml_append(method, aml_return(aml_call1("IQCR", reg)));
1521 aml_append(dev, method);
1522
1523 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1524 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
1525 aml_append(method, aml_store(aml_name("PRRI"), reg));
1526 aml_append(dev, method);
1527
1528 return dev;
1529 }
1530
1531 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
1532 {
1533 Aml *dev;
1534 Aml *crs;
1535 Aml *method;
1536 uint32_t irqs;
1537
1538 dev = aml_device("%s", name);
1539 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1540 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1541
1542 crs = aml_resource_template();
1543 irqs = gsi;
1544 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1545 AML_SHARED, &irqs, 1));
1546 aml_append(dev, aml_name_decl("_PRS", crs));
1547
1548 aml_append(dev, aml_name_decl("_CRS", crs));
1549
1550 /*
1551 * _DIS can be no-op because the interrupt cannot be disabled.
1552 */
1553 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1554 aml_append(dev, method);
1555
1556 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1557 aml_append(dev, method);
1558
1559 return dev;
1560 }
1561
1562 /* _CRS method - get current settings */
1563 static Aml *build_iqcr_method(bool is_piix4)
1564 {
1565 Aml *if_ctx;
1566 uint32_t irqs;
1567 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
1568 Aml *crs = aml_resource_template();
1569
1570 irqs = 0;
1571 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1572 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
1573 aml_append(method, aml_name_decl("PRR0", crs));
1574
1575 aml_append(method,
1576 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
1577
1578 if (is_piix4) {
1579 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
1580 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
1581 aml_append(method, if_ctx);
1582 } else {
1583 aml_append(method,
1584 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
1585 aml_name("PRRI")));
1586 }
1587
1588 aml_append(method, aml_return(aml_name("PRR0")));
1589 return method;
1590 }
1591
1592 /* _STA method - get status */
1593 static Aml *build_irq_status_method(void)
1594 {
1595 Aml *if_ctx;
1596 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
1597
1598 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
1599 aml_append(if_ctx, aml_return(aml_int(0x09)));
1600 aml_append(method, if_ctx);
1601 aml_append(method, aml_return(aml_int(0x0B)));
1602 return method;
1603 }
1604
1605 static void build_piix4_pci0_int(Aml *table)
1606 {
1607 Aml *dev;
1608 Aml *crs;
1609 Aml *field;
1610 Aml *method;
1611 uint32_t irqs;
1612 Aml *sb_scope = aml_scope("_SB");
1613 Aml *pci0_scope = aml_scope("PCI0");
1614
1615 aml_append(pci0_scope, build_prt(true));
1616 aml_append(sb_scope, pci0_scope);
1617
1618 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1619 aml_append(field, aml_named_field("PRQ0", 8));
1620 aml_append(field, aml_named_field("PRQ1", 8));
1621 aml_append(field, aml_named_field("PRQ2", 8));
1622 aml_append(field, aml_named_field("PRQ3", 8));
1623 aml_append(sb_scope, field);
1624
1625 aml_append(sb_scope, build_irq_status_method());
1626 aml_append(sb_scope, build_iqcr_method(true));
1627
1628 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1629 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1630 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1631 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1632
1633 dev = aml_device("LNKS");
1634 {
1635 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1636 aml_append(dev, aml_name_decl("_UID", aml_int(4)));
1637
1638 crs = aml_resource_template();
1639 irqs = 9;
1640 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1641 AML_ACTIVE_HIGH, AML_SHARED,
1642 &irqs, 1));
1643 aml_append(dev, aml_name_decl("_PRS", crs));
1644
1645 /* The SCI cannot be disabled and is always attached to GSI 9,
1646 * so these are no-ops. We only need this link to override the
1647 * polarity to active high and match the content of the MADT.
1648 */
1649 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1650 aml_append(method, aml_return(aml_int(0x0b)));
1651 aml_append(dev, method);
1652
1653 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1654 aml_append(dev, method);
1655
1656 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1657 aml_append(method, aml_return(aml_name("_PRS")));
1658 aml_append(dev, method);
1659
1660 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1661 aml_append(dev, method);
1662 }
1663 aml_append(sb_scope, dev);
1664
1665 aml_append(table, sb_scope);
1666 }
1667
1668 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
1669 {
1670 int i;
1671 int head;
1672 Aml *pkg;
1673 char base = name[3] < 'E' ? 'A' : 'E';
1674 char *s = g_strdup(name);
1675 Aml *a_nr = aml_int((nr << 16) | 0xffff);
1676
1677 assert(strlen(s) == 4);
1678
1679 head = name[3] - base;
1680 for (i = 0; i < 4; i++) {
1681 if (head + i > 3) {
1682 head = i * -1;
1683 }
1684 s[3] = base + head + i;
1685 pkg = aml_package(4);
1686 aml_append(pkg, a_nr);
1687 aml_append(pkg, aml_int(i));
1688 aml_append(pkg, aml_name("%s", s));
1689 aml_append(pkg, aml_int(0));
1690 aml_append(ctx, pkg);
1691 }
1692 g_free(s);
1693 }
1694
1695 static Aml *build_q35_routing_table(const char *str)
1696 {
1697 int i;
1698 Aml *pkg;
1699 char *name = g_strdup_printf("%s ", str);
1700
1701 pkg = aml_package(128);
1702 for (i = 0; i < 0x18; i++) {
1703 name[3] = 'E' + (i & 0x3);
1704 append_q35_prt_entry(pkg, i, name);
1705 }
1706
1707 name[3] = 'E';
1708 append_q35_prt_entry(pkg, 0x18, name);
1709
1710 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1711 for (i = 0x0019; i < 0x1e; i++) {
1712 name[3] = 'A';
1713 append_q35_prt_entry(pkg, i, name);
1714 }
1715
1716 /* PCIe->PCI bridge. use PIRQ[E-H] */
1717 name[3] = 'E';
1718 append_q35_prt_entry(pkg, 0x1e, name);
1719 name[3] = 'A';
1720 append_q35_prt_entry(pkg, 0x1f, name);
1721
1722 g_free(name);
1723 return pkg;
1724 }
1725
1726 static void build_q35_pci0_int(Aml *table)
1727 {
1728 Aml *field;
1729 Aml *method;
1730 Aml *sb_scope = aml_scope("_SB");
1731 Aml *pci0_scope = aml_scope("PCI0");
1732
1733 /* Zero => PIC mode, One => APIC Mode */
1734 aml_append(table, aml_name_decl("PICF", aml_int(0)));
1735 method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
1736 {
1737 aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
1738 }
1739 aml_append(table, method);
1740
1741 aml_append(pci0_scope,
1742 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1743 aml_append(pci0_scope,
1744 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1745
1746 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
1747 {
1748 Aml *if_ctx;
1749 Aml *else_ctx;
1750
1751 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1752 section 6.2.8.1 */
1753 /* Note: we provide the same info as the PCI routing
1754 table of the Bochs BIOS */
1755 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1756 aml_append(if_ctx, aml_return(aml_name("PRTP")));
1757 aml_append(method, if_ctx);
1758 else_ctx = aml_else();
1759 aml_append(else_ctx, aml_return(aml_name("PRTA")));
1760 aml_append(method, else_ctx);
1761 }
1762 aml_append(pci0_scope, method);
1763 aml_append(sb_scope, pci0_scope);
1764
1765 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1766 aml_append(field, aml_named_field("PRQA", 8));
1767 aml_append(field, aml_named_field("PRQB", 8));
1768 aml_append(field, aml_named_field("PRQC", 8));
1769 aml_append(field, aml_named_field("PRQD", 8));
1770 aml_append(field, aml_reserved_field(0x20));
1771 aml_append(field, aml_named_field("PRQE", 8));
1772 aml_append(field, aml_named_field("PRQF", 8));
1773 aml_append(field, aml_named_field("PRQG", 8));
1774 aml_append(field, aml_named_field("PRQH", 8));
1775 aml_append(sb_scope, field);
1776
1777 aml_append(sb_scope, build_irq_status_method());
1778 aml_append(sb_scope, build_iqcr_method(false));
1779
1780 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
1781 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
1782 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
1783 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
1784 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
1785 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
1786 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
1787 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
1788
1789 /*
1790 * TODO: UID probably shouldn't be the same for GSIx devices
1791 * but that's how it was in original ASL so keep it for now
1792 */
1793 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0, 0x10));
1794 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0, 0x11));
1795 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0, 0x12));
1796 aml_append(sb_scope, build_gsi_link_dev("GSID", 0, 0x13));
1797 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0, 0x14));
1798 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0, 0x15));
1799 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0, 0x16));
1800 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0, 0x17));
1801
1802 aml_append(table, sb_scope);
1803 }
1804
1805 static void build_q35_isa_bridge(Aml *table)
1806 {
1807 Aml *dev;
1808 Aml *scope;
1809 Aml *field;
1810
1811 scope = aml_scope("_SB.PCI0");
1812 dev = aml_device("ISA");
1813 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000)));
1814
1815 /* ICH9 PCI to ISA irq remapping */
1816 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG,
1817 aml_int(0x60), 0x0C));
1818
1819 aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG,
1820 aml_int(0x80), 0x02));
1821 field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1822 aml_append(field, aml_named_field("COMA", 3));
1823 aml_append(field, aml_reserved_field(1));
1824 aml_append(field, aml_named_field("COMB", 3));
1825 aml_append(field, aml_reserved_field(1));
1826 aml_append(field, aml_named_field("LPTD", 2));
1827 aml_append(dev, field);
1828
1829 aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG,
1830 aml_int(0x82), 0x02));
1831 /* enable bits */
1832 field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1833 aml_append(field, aml_named_field("CAEN", 1));
1834 aml_append(field, aml_named_field("CBEN", 1));
1835 aml_append(field, aml_named_field("LPEN", 1));
1836 aml_append(dev, field);
1837
1838 aml_append(scope, dev);
1839 aml_append(table, scope);
1840 }
1841
1842 static void build_piix4_pm(Aml *table)
1843 {
1844 Aml *dev;
1845 Aml *scope;
1846
1847 scope = aml_scope("_SB.PCI0");
1848 dev = aml_device("PX13");
1849 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010003)));
1850
1851 aml_append(dev, aml_operation_region("P13C", AML_PCI_CONFIG,
1852 aml_int(0x00), 0xff));
1853 aml_append(scope, dev);
1854 aml_append(table, scope);
1855 }
1856
1857 static void build_piix4_isa_bridge(Aml *table)
1858 {
1859 Aml *dev;
1860 Aml *scope;
1861 Aml *field;
1862
1863 scope = aml_scope("_SB.PCI0");
1864 dev = aml_device("ISA");
1865 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000)));
1866
1867 /* PIIX PCI to ISA irq remapping */
1868 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG,
1869 aml_int(0x60), 0x04));
1870 /* enable bits */
1871 field = aml_field("^PX13.P13C", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1872 /* Offset(0x5f),, 7, */
1873 aml_append(field, aml_reserved_field(0x2f8));
1874 aml_append(field, aml_reserved_field(7));
1875 aml_append(field, aml_named_field("LPEN", 1));
1876 /* Offset(0x67),, 3, */
1877 aml_append(field, aml_reserved_field(0x38));
1878 aml_append(field, aml_reserved_field(3));
1879 aml_append(field, aml_named_field("CAEN", 1));
1880 aml_append(field, aml_reserved_field(3));
1881 aml_append(field, aml_named_field("CBEN", 1));
1882 aml_append(dev, field);
1883
1884 aml_append(scope, dev);
1885 aml_append(table, scope);
1886 }
1887
1888 static void build_piix4_pci_hotplug(Aml *table)
1889 {
1890 Aml *scope;
1891 Aml *field;
1892 Aml *method;
1893
1894 scope = aml_scope("_SB.PCI0");
1895
1896 aml_append(scope,
1897 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08));
1898 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1899 aml_append(field, aml_named_field("PCIU", 32));
1900 aml_append(field, aml_named_field("PCID", 32));
1901 aml_append(scope, field);
1902
1903 aml_append(scope,
1904 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04));
1905 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1906 aml_append(field, aml_named_field("B0EJ", 32));
1907 aml_append(scope, field);
1908
1909 aml_append(scope,
1910 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04));
1911 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1912 aml_append(field, aml_named_field("BNUM", 32));
1913 aml_append(scope, field);
1914
1915 aml_append(scope, aml_mutex("BLCK", 0));
1916
1917 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
1918 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1919 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1920 aml_append(method,
1921 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1922 aml_append(method, aml_release(aml_name("BLCK")));
1923 aml_append(method, aml_return(aml_int(0)));
1924 aml_append(scope, method);
1925
1926 aml_append(table, scope);
1927 }
1928
1929 static Aml *build_q35_osc_method(void)
1930 {
1931 Aml *if_ctx;
1932 Aml *if_ctx2;
1933 Aml *else_ctx;
1934 Aml *method;
1935 Aml *a_cwd1 = aml_name("CDW1");
1936 Aml *a_ctrl = aml_name("CTRL");
1937
1938 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
1939 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1940
1941 if_ctx = aml_if(aml_equal(
1942 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1943 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1944 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1945
1946 aml_append(if_ctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
1947 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
1948
1949 /*
1950 * Always allow native PME, AER (no dependencies)
1951 * Never allow SHPC (no SHPC controller in this system)
1952 */
1953 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1D), a_ctrl));
1954
1955 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1956 /* Unknown revision */
1957 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
1958 aml_append(if_ctx, if_ctx2);
1959
1960 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
1961 /* Capabilities bits were masked */
1962 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
1963 aml_append(if_ctx, if_ctx2);
1964
1965 /* Update DWORD3 in the buffer */
1966 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
1967 aml_append(method, if_ctx);
1968
1969 else_ctx = aml_else();
1970 /* Unrecognized UUID */
1971 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
1972 aml_append(method, else_ctx);
1973
1974 aml_append(method, aml_return(aml_arg(3)));
1975 return method;
1976 }
1977
1978 static void
1979 build_dsdt(GArray *table_data, GArray *linker,
1980 AcpiPmInfo *pm, AcpiMiscInfo *misc,
1981 PcPciInfo *pci, MachineState *machine)
1982 {
1983 CrsRangeEntry *entry;
1984 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
1985 GPtrArray *mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
1986 GPtrArray *io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
1987 PCMachineState *pcms = PC_MACHINE(machine);
1988 uint32_t nr_mem = machine->ram_slots;
1989 int root_bus_limit = 0xFF;
1990 PCIBus *bus = NULL;
1991 int i;
1992
1993 dsdt = init_aml_allocator();
1994
1995 /* Reserve space for header */
1996 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
1997
1998 build_dbg_aml(dsdt);
1999 if (misc->is_piix4) {
2000 sb_scope = aml_scope("_SB");
2001 dev = aml_device("PCI0");
2002 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
2003 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
2004 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
2005 aml_append(sb_scope, dev);
2006 aml_append(dsdt, sb_scope);
2007
2008 build_hpet_aml(dsdt);
2009 build_piix4_pm(dsdt);
2010 build_piix4_isa_bridge(dsdt);
2011 build_isa_devices_aml(dsdt);
2012 build_piix4_pci_hotplug(dsdt);
2013 build_piix4_pci0_int(dsdt);
2014 } else {
2015 sb_scope = aml_scope("_SB");
2016 aml_append(sb_scope,
2017 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x0c));
2018 aml_append(sb_scope,
2019 aml_operation_region("PCSB", AML_SYSTEM_IO, aml_int(0xae0c), 0x01));
2020 field = aml_field("PCSB", AML_ANY_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
2021 aml_append(field, aml_named_field("PCIB", 8));
2022 aml_append(sb_scope, field);
2023 aml_append(dsdt, sb_scope);
2024
2025 sb_scope = aml_scope("_SB");
2026 dev = aml_device("PCI0");
2027 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
2028 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
2029 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
2030 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
2031 aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
2032 aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
2033 aml_append(dev, build_q35_osc_method());
2034 aml_append(sb_scope, dev);
2035 aml_append(dsdt, sb_scope);
2036
2037 build_hpet_aml(dsdt);
2038 build_q35_isa_bridge(dsdt);
2039 build_isa_devices_aml(dsdt);
2040 build_q35_pci0_int(dsdt);
2041 }
2042
2043 build_cpu_hotplug_aml(dsdt);
2044 build_memory_hotplug_aml(dsdt, nr_mem, pm->mem_hp_io_base,
2045 pm->mem_hp_io_len);
2046
2047 scope = aml_scope("_GPE");
2048 {
2049 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
2050
2051 aml_append(scope, aml_method("_L00", 0, AML_NOTSERIALIZED));
2052
2053 if (misc->is_piix4) {
2054 method = aml_method("_E01", 0, AML_NOTSERIALIZED);
2055 aml_append(method,
2056 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
2057 aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
2058 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
2059 aml_append(scope, method);
2060 } else {
2061 aml_append(scope, aml_method("_L01", 0, AML_NOTSERIALIZED));
2062 }
2063
2064 method = aml_method("_E02", 0, AML_NOTSERIALIZED);
2065 aml_append(method, aml_call0("\\_SB." CPU_SCAN_METHOD));
2066 aml_append(scope, method);
2067
2068 method = aml_method("_E03", 0, AML_NOTSERIALIZED);
2069 aml_append(method, aml_call0(MEMORY_HOTPLUG_HANDLER_PATH));
2070 aml_append(scope, method);
2071
2072 aml_append(scope, aml_method("_L04", 0, AML_NOTSERIALIZED));
2073 aml_append(scope, aml_method("_L05", 0, AML_NOTSERIALIZED));
2074 aml_append(scope, aml_method("_L06", 0, AML_NOTSERIALIZED));
2075 aml_append(scope, aml_method("_L07", 0, AML_NOTSERIALIZED));
2076 aml_append(scope, aml_method("_L08", 0, AML_NOTSERIALIZED));
2077 aml_append(scope, aml_method("_L09", 0, AML_NOTSERIALIZED));
2078 aml_append(scope, aml_method("_L0A", 0, AML_NOTSERIALIZED));
2079 aml_append(scope, aml_method("_L0B", 0, AML_NOTSERIALIZED));
2080 aml_append(scope, aml_method("_L0C", 0, AML_NOTSERIALIZED));
2081 aml_append(scope, aml_method("_L0D", 0, AML_NOTSERIALIZED));
2082 aml_append(scope, aml_method("_L0E", 0, AML_NOTSERIALIZED));
2083 aml_append(scope, aml_method("_L0F", 0, AML_NOTSERIALIZED));
2084 }
2085 aml_append(dsdt, scope);
2086
2087 bus = PC_MACHINE(machine)->bus;
2088 if (bus) {
2089 QLIST_FOREACH(bus, &bus->child, sibling) {
2090 uint8_t bus_num = pci_bus_num(bus);
2091 uint8_t numa_node = pci_bus_numa_node(bus);
2092
2093 /* look only for expander root buses */
2094 if (!pci_bus_is_root(bus)) {
2095 continue;
2096 }
2097
2098 if (bus_num < root_bus_limit) {
2099 root_bus_limit = bus_num - 1;
2100 }
2101
2102 scope = aml_scope("\\_SB");
2103 dev = aml_device("PC%.02X", bus_num);
2104 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
2105 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
2106 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
2107
2108 if (numa_node != NUMA_NODE_UNASSIGNED) {
2109 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
2110 }
2111
2112 aml_append(dev, build_prt(false));
2113 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent),
2114 io_ranges, mem_ranges);
2115 aml_append(dev, aml_name_decl("_CRS", crs));
2116 aml_append(scope, dev);
2117 aml_append(dsdt, scope);
2118 }
2119 }
2120
2121 scope = aml_scope("\\_SB.PCI0");
2122 /* build PCI0._CRS */
2123 crs = aml_resource_template();
2124 aml_append(crs,
2125 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
2126 0x0000, 0x0, root_bus_limit,
2127 0x0000, root_bus_limit + 1));
2128 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
2129
2130 aml_append(crs,
2131 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
2132 AML_POS_DECODE, AML_ENTIRE_RANGE,
2133 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
2134
2135 crs_replace_with_free_ranges(io_ranges, 0x0D00, 0xFFFF);
2136 for (i = 0; i < io_ranges->len; i++) {
2137 entry = g_ptr_array_index(io_ranges, i);
2138 aml_append(crs,
2139 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
2140 AML_POS_DECODE, AML_ENTIRE_RANGE,
2141 0x0000, entry->base, entry->limit,
2142 0x0000, entry->limit - entry->base + 1));
2143 }
2144
2145 aml_append(crs,
2146 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2147 AML_CACHEABLE, AML_READ_WRITE,
2148 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
2149
2150 crs_replace_with_free_ranges(mem_ranges, pci->w32.begin, pci->w32.end - 1);
2151 for (i = 0; i < mem_ranges->len; i++) {
2152 entry = g_ptr_array_index(mem_ranges, i);
2153 aml_append(crs,
2154 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2155 AML_NON_CACHEABLE, AML_READ_WRITE,
2156 0, entry->base, entry->limit,
2157 0, entry->limit - entry->base + 1));
2158 }
2159
2160 if (pci->w64.begin) {
2161 aml_append(crs,
2162 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2163 AML_CACHEABLE, AML_READ_WRITE,
2164 0, pci->w64.begin, pci->w64.end - 1, 0,
2165 pci->w64.end - pci->w64.begin));
2166 }
2167 aml_append(scope, aml_name_decl("_CRS", crs));
2168
2169 /* reserve GPE0 block resources */
2170 dev = aml_device("GPE0");
2171 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2172 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
2173 /* device present, functioning, decoding, not shown in UI */
2174 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2175 crs = aml_resource_template();
2176 aml_append(crs,
2177 aml_io(AML_DECODE16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len)
2178 );
2179 aml_append(dev, aml_name_decl("_CRS", crs));
2180 aml_append(scope, dev);
2181
2182 g_ptr_array_free(io_ranges, true);
2183 g_ptr_array_free(mem_ranges, true);
2184
2185 /* reserve PCIHP resources */
2186 if (pm->pcihp_io_len) {
2187 dev = aml_device("PHPR");
2188 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2189 aml_append(dev,
2190 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
2191 /* device present, functioning, decoding, not shown in UI */
2192 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2193 crs = aml_resource_template();
2194 aml_append(crs,
2195 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
2196 pm->pcihp_io_len)
2197 );
2198 aml_append(dev, aml_name_decl("_CRS", crs));
2199 aml_append(scope, dev);
2200 }
2201 aml_append(dsdt, scope);
2202
2203 /* create S3_ / S4_ / S5_ packages if necessary */
2204 scope = aml_scope("\\");
2205 if (!pm->s3_disabled) {
2206 pkg = aml_package(4);
2207 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
2208 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2209 aml_append(pkg, aml_int(0)); /* reserved */
2210 aml_append(pkg, aml_int(0)); /* reserved */
2211 aml_append(scope, aml_name_decl("_S3", pkg));
2212 }
2213
2214 if (!pm->s4_disabled) {
2215 pkg = aml_package(4);
2216 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
2217 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2218 aml_append(pkg, aml_int(pm->s4_val));
2219 aml_append(pkg, aml_int(0)); /* reserved */
2220 aml_append(pkg, aml_int(0)); /* reserved */
2221 aml_append(scope, aml_name_decl("_S4", pkg));
2222 }
2223
2224 pkg = aml_package(4);
2225 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
2226 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
2227 aml_append(pkg, aml_int(0)); /* reserved */
2228 aml_append(pkg, aml_int(0)); /* reserved */
2229 aml_append(scope, aml_name_decl("_S5", pkg));
2230 aml_append(dsdt, scope);
2231
2232 /* create fw_cfg node, unconditionally */
2233 {
2234 /* when using port i/o, the 8-bit data register *always* overlaps
2235 * with half of the 16-bit control register. Hence, the total size
2236 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the
2237 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */
2238 uint8_t io_size = object_property_get_bool(OBJECT(pcms->fw_cfg),
2239 "dma_enabled", NULL) ?
2240 ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) :
2241 FW_CFG_CTL_SIZE;
2242
2243 scope = aml_scope("\\_SB.PCI0");
2244 dev = aml_device("FWCF");
2245
2246 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
2247
2248 /* device present, functioning, decoding, not shown in UI */
2249 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2250
2251 crs = aml_resource_template();
2252 aml_append(crs,
2253 aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size)
2254 );
2255 aml_append(dev, aml_name_decl("_CRS", crs));
2256
2257 aml_append(scope, dev);
2258 aml_append(dsdt, scope);
2259 }
2260
2261 if (misc->applesmc_io_base) {
2262 scope = aml_scope("\\_SB.PCI0.ISA");
2263 dev = aml_device("SMC");
2264
2265 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
2266 /* device present, functioning, decoding, not shown in UI */
2267 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2268
2269 crs = aml_resource_template();
2270 aml_append(crs,
2271 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
2272 0x01, APPLESMC_MAX_DATA_LENGTH)
2273 );
2274 aml_append(crs, aml_irq_no_flags(6));
2275 aml_append(dev, aml_name_decl("_CRS", crs));
2276
2277 aml_append(scope, dev);
2278 aml_append(dsdt, scope);
2279 }
2280
2281 if (misc->pvpanic_port) {
2282 scope = aml_scope("\\_SB.PCI0.ISA");
2283
2284 dev = aml_device("PEVT");
2285 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
2286
2287 crs = aml_resource_template();
2288 aml_append(crs,
2289 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
2290 );
2291 aml_append(dev, aml_name_decl("_CRS", crs));
2292
2293 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
2294 aml_int(misc->pvpanic_port), 1));
2295 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
2296 aml_append(field, aml_named_field("PEPT", 8));
2297 aml_append(dev, field);
2298
2299 /* device present, functioning, decoding, shown in UI */
2300 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2301
2302 method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
2303 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
2304 aml_append(method, aml_return(aml_local(0)));
2305 aml_append(dev, method);
2306
2307 method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
2308 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
2309 aml_append(dev, method);
2310
2311 aml_append(scope, dev);
2312 aml_append(dsdt, scope);
2313 }
2314
2315 sb_scope = aml_scope("\\_SB");
2316 {
2317 build_processor_devices(sb_scope, machine, pm);
2318
2319 build_memory_devices(sb_scope, nr_mem, pm->mem_hp_io_base,
2320 pm->mem_hp_io_len);
2321
2322 {
2323 Object *pci_host;
2324 PCIBus *bus = NULL;
2325
2326 pci_host = acpi_get_i386_pci_host();
2327 if (pci_host) {
2328 bus = PCI_HOST_BRIDGE(pci_host)->bus;
2329 }
2330
2331 if (bus) {
2332 Aml *scope = aml_scope("PCI0");
2333 /* Scan all PCI buses. Generate tables to support hotplug. */
2334 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
2335
2336 if (misc->tpm_version != TPM_VERSION_UNSPEC) {
2337 dev = aml_device("ISA.TPM");
2338 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31")));
2339 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2340 crs = aml_resource_template();
2341 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
2342 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
2343 aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ));
2344 aml_append(dev, aml_name_decl("_CRS", crs));
2345 aml_append(scope, dev);
2346 }
2347
2348 aml_append(sb_scope, scope);
2349 }
2350 }
2351 aml_append(dsdt, sb_scope);
2352 }
2353
2354 /* copy AML table into ACPI tables blob and patch header there */
2355 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
2356 build_header(linker, table_data,
2357 (void *)(table_data->data + table_data->len - dsdt->buf->len),
2358 "DSDT", dsdt->buf->len, 1, NULL, NULL);
2359 free_aml_allocator();
2360 }
2361
2362 static void
2363 build_hpet(GArray *table_data, GArray *linker)
2364 {
2365 Acpi20Hpet *hpet;
2366
2367 hpet = acpi_data_push(table_data, sizeof(*hpet));
2368 /* Note timer_block_id value must be kept in sync with value advertised by
2369 * emulated hpet
2370 */
2371 hpet->timer_block_id = cpu_to_le32(0x8086a201);
2372 hpet->addr.address = cpu_to_le64(HPET_BASE);
2373 build_header(linker, table_data,
2374 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL);
2375 }
2376
2377 static void
2378 build_tpm_tcpa(GArray *table_data, GArray *linker, GArray *tcpalog)
2379 {
2380 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
2381 uint64_t log_area_start_address = acpi_data_len(tcpalog);
2382
2383 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
2384 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
2385 tcpa->log_area_start_address = cpu_to_le64(log_area_start_address);
2386
2387 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, 1,
2388 false /* high memory */);
2389
2390 /* log area start address to be filled by Guest linker */
2391 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
2392 ACPI_BUILD_TPMLOG_FILE,
2393 table_data, &tcpa->log_area_start_address,
2394 sizeof(tcpa->log_area_start_address));
2395
2396 build_header(linker, table_data,
2397 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL);
2398
2399 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE);
2400 }
2401
2402 static void
2403 build_tpm2(GArray *table_data, GArray *linker)
2404 {
2405 Acpi20TPM2 *tpm2_ptr;
2406
2407 tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr);
2408
2409 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT);
2410 tpm2_ptr->control_area_address = cpu_to_le64(0);
2411 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO);
2412
2413 build_header(linker, table_data,
2414 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL);
2415 }
2416
2417 typedef enum {
2418 MEM_AFFINITY_NOFLAGS = 0,
2419 MEM_AFFINITY_ENABLED = (1 << 0),
2420 MEM_AFFINITY_HOTPLUGGABLE = (1 << 1),
2421 MEM_AFFINITY_NON_VOLATILE = (1 << 2),
2422 } MemoryAffinityFlags;
2423
2424 static void
2425 acpi_build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base,
2426 uint64_t len, int node, MemoryAffinityFlags flags)
2427 {
2428 numamem->type = ACPI_SRAT_MEMORY;
2429 numamem->length = sizeof(*numamem);
2430 memset(numamem->proximity, 0, 4);
2431 numamem->proximity[0] = node;
2432 numamem->flags = cpu_to_le32(flags);
2433 numamem->base_addr = cpu_to_le64(base);
2434 numamem->range_length = cpu_to_le64(len);
2435 }
2436
2437 static void
2438 build_srat(GArray *table_data, GArray *linker, MachineState *machine)
2439 {
2440 AcpiSystemResourceAffinityTable *srat;
2441 AcpiSratProcessorAffinity *core;
2442 AcpiSratMemoryAffinity *numamem;
2443
2444 int i;
2445 uint64_t curnode;
2446 int srat_start, numa_start, slots;
2447 uint64_t mem_len, mem_base, next_base;
2448 MachineClass *mc = MACHINE_GET_CLASS(machine);
2449 CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
2450 PCMachineState *pcms = PC_MACHINE(machine);
2451 ram_addr_t hotplugabble_address_space_size =
2452 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE,
2453 NULL);
2454
2455 srat_start = table_data->len;
2456
2457 srat = acpi_data_push(table_data, sizeof *srat);
2458 srat->reserved1 = cpu_to_le32(1);
2459
2460 for (i = 0; i < apic_ids->len; i++) {
2461 int apic_id = apic_ids->cpus[i].arch_id;
2462
2463 core = acpi_data_push(table_data, sizeof *core);
2464 core->type = ACPI_SRAT_PROCESSOR;
2465 core->length = sizeof(*core);
2466 core->local_apic_id = apic_id;
2467 curnode = pcms->node_cpu[apic_id];
2468 core->proximity_lo = curnode;
2469 memset(core->proximity_hi, 0, 3);
2470 core->local_sapic_eid = 0;
2471 core->flags = cpu_to_le32(1);
2472 }
2473
2474
2475 /* the memory map is a bit tricky, it contains at least one hole
2476 * from 640k-1M and possibly another one from 3.5G-4G.
2477 */
2478 next_base = 0;
2479 numa_start = table_data->len;
2480
2481 numamem = acpi_data_push(table_data, sizeof *numamem);
2482 acpi_build_srat_memory(numamem, 0, 640*1024, 0, MEM_AFFINITY_ENABLED);
2483 next_base = 1024 * 1024;
2484 for (i = 1; i < pcms->numa_nodes + 1; ++i) {
2485 mem_base = next_base;
2486 mem_len = pcms->node_mem[i - 1];
2487 if (i == 1) {
2488 mem_len -= 1024 * 1024;
2489 }
2490 next_base = mem_base + mem_len;
2491
2492 /* Cut out the ACPI_PCI hole */
2493 if (mem_base <= pcms->below_4g_mem_size &&
2494 next_base > pcms->below_4g_mem_size) {
2495 mem_len -= next_base - pcms->below_4g_mem_size;
2496 if (mem_len > 0) {
2497 numamem = acpi_data_push(table_data, sizeof *numamem);
2498 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1,
2499 MEM_AFFINITY_ENABLED);
2500 }
2501 mem_base = 1ULL << 32;
2502 mem_len = next_base - pcms->below_4g_mem_size;
2503 next_base += (1ULL << 32) - pcms->below_4g_mem_size;
2504 }
2505 numamem = acpi_data_push(table_data, sizeof *numamem);
2506 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1,
2507 MEM_AFFINITY_ENABLED);
2508 }
2509 slots = (table_data->len - numa_start) / sizeof *numamem;
2510 for (; slots < pcms->numa_nodes + 2; slots++) {
2511 numamem = acpi_data_push(table_data, sizeof *numamem);
2512 acpi_build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
2513 }
2514
2515 /*
2516 * Entry is required for Windows to enable memory hotplug in OS.
2517 * Memory devices may override proximity set by this entry,
2518 * providing _PXM method if necessary.
2519 */
2520 if (hotplugabble_address_space_size) {
2521 numamem = acpi_data_push(table_data, sizeof *numamem);
2522 acpi_build_srat_memory(numamem, pcms->hotplug_memory.base,
2523 hotplugabble_address_space_size, 0,
2524 MEM_AFFINITY_HOTPLUGGABLE |
2525 MEM_AFFINITY_ENABLED);
2526 }
2527
2528 build_header(linker, table_data,
2529 (void *)(table_data->data + srat_start),
2530 "SRAT",
2531 table_data->len - srat_start, 1, NULL, NULL);
2532 g_free(apic_ids);
2533 }
2534
2535 static void
2536 build_mcfg_q35(GArray *table_data, GArray *linker, AcpiMcfgInfo *info)
2537 {
2538 AcpiTableMcfg *mcfg;
2539 const char *sig;
2540 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
2541
2542 mcfg = acpi_data_push(table_data, len);
2543 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base);
2544 /* Only a single allocation so no need to play with segments */
2545 mcfg->allocation[0].pci_segment = cpu_to_le16(0);
2546 mcfg->allocation[0].start_bus_number = 0;
2547 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1);
2548
2549 /* MCFG is used for ECAM which can be enabled or disabled by guest.
2550 * To avoid table size changes (which create migration issues),
2551 * always create the table even if there are no allocations,
2552 * but set the signature to a reserved value in this case.
2553 * ACPI spec requires OSPMs to ignore such tables.
2554 */
2555 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) {
2556 /* Reserved signature: ignored by OSPM */
2557 sig = "QEMU";
2558 } else {
2559 sig = "MCFG";
2560 }
2561 build_header(linker, table_data, (void *)mcfg, sig, len, 1, NULL, NULL);
2562 }
2563
2564 static void
2565 build_dmar_q35(GArray *table_data, GArray *linker)
2566 {
2567 int dmar_start = table_data->len;
2568
2569 AcpiTableDmar *dmar;
2570 AcpiDmarHardwareUnit *drhd;
2571
2572 dmar = acpi_data_push(table_data, sizeof(*dmar));
2573 dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1;
2574 dmar->flags = 0; /* No intr_remap for now */
2575
2576 /* DMAR Remapping Hardware Unit Definition structure */
2577 drhd = acpi_data_push(table_data, sizeof(*drhd));
2578 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
2579 drhd->length = cpu_to_le16(sizeof(*drhd)); /* No device scope now */
2580 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
2581 drhd->pci_segment = cpu_to_le16(0);
2582 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
2583
2584 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
2585 "DMAR", table_data->len - dmar_start, 1, NULL, NULL);
2586 }
2587
2588 static GArray *
2589 build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
2590 {
2591 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
2592
2593 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16,
2594 true /* fseg memory */);
2595
2596 memcpy(&rsdp->signature, "RSD PTR ", 8);
2597 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6);
2598 rsdp->rsdt_physical_address = cpu_to_le32(rsdt);
2599 /* Address to be filled by Guest linker */
2600 bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE,
2601 ACPI_BUILD_TABLE_FILE,
2602 rsdp_table, &rsdp->rsdt_physical_address,
2603 sizeof rsdp->rsdt_physical_address);
2604 rsdp->checksum = 0;
2605 /* Checksum to be filled by Guest linker */
2606 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
2607 rsdp_table, rsdp, sizeof *rsdp,
2608 &rsdp->checksum);
2609
2610 return rsdp_table;
2611 }
2612
2613 typedef
2614 struct AcpiBuildState {
2615 /* Copy of table in RAM (for patching). */
2616 MemoryRegion *table_mr;
2617 /* Is table patched? */
2618 uint8_t patched;
2619 void *rsdp;
2620 MemoryRegion *rsdp_mr;
2621 MemoryRegion *linker_mr;
2622 } AcpiBuildState;
2623
2624 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
2625 {
2626 Object *pci_host;
2627 QObject *o;
2628
2629 pci_host = acpi_get_i386_pci_host();
2630 g_assert(pci_host);
2631
2632 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2633 if (!o) {
2634 return false;
2635 }
2636 mcfg->mcfg_base = qint_get_int(qobject_to_qint(o));
2637 qobject_decref(o);
2638
2639 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2640 assert(o);
2641 mcfg->mcfg_size = qint_get_int(qobject_to_qint(o));
2642 qobject_decref(o);
2643 return true;
2644 }
2645
2646 static bool acpi_has_iommu(void)
2647 {
2648 bool ambiguous;
2649 Object *intel_iommu;
2650
2651 intel_iommu = object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE,
2652 &ambiguous);
2653 return intel_iommu && !ambiguous;
2654 }
2655
2656 static
2657 void acpi_build(AcpiBuildTables *tables, MachineState *machine)
2658 {
2659 PCMachineState *pcms = PC_MACHINE(machine);
2660 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2661 GArray *table_offsets;
2662 unsigned facs, dsdt, rsdt, fadt;
2663 AcpiPmInfo pm;
2664 AcpiMiscInfo misc;
2665 AcpiMcfgInfo mcfg;
2666 PcPciInfo pci;
2667 uint8_t *u;
2668 size_t aml_len = 0;
2669 GArray *tables_blob = tables->table_data;
2670 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
2671
2672 acpi_get_pm_info(&pm);
2673 acpi_get_misc_info(&misc);
2674 acpi_get_pci_info(&pci);
2675 acpi_get_slic_oem(&slic_oem);
2676
2677 table_offsets = g_array_new(false, true /* clear */,
2678 sizeof(uint32_t));
2679 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2680
2681 bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE,
2682 64 /* Ensure FACS is aligned */,
2683 false /* high memory */);
2684
2685 /*
2686 * FACS is pointed to by FADT.
2687 * We place it first since it's the only table that has alignment
2688 * requirements.
2689 */
2690 facs = tables_blob->len;
2691 build_facs(tables_blob, tables->linker);
2692
2693 /* DSDT is pointed to by FADT */
2694 dsdt = tables_blob->len;
2695 build_dsdt(tables_blob, tables->linker, &pm, &misc, &pci, machine);
2696
2697 /* Count the size of the DSDT and SSDT, we will need it for legacy
2698 * sizing of ACPI tables.
2699 */
2700 aml_len += tables_blob->len - dsdt;
2701
2702 /* ACPI tables pointed to by RSDT */
2703 fadt = tables_blob->len;
2704 acpi_add_table(table_offsets, tables_blob);
2705 build_fadt(tables_blob, tables->linker, &pm, facs, dsdt,
2706 slic_oem.id, slic_oem.table_id);
2707 aml_len += tables_blob->len - fadt;
2708
2709 acpi_add_table(table_offsets, tables_blob);
2710 build_madt(tables_blob, tables->linker, pcms);
2711
2712 if (misc.has_hpet) {
2713 acpi_add_table(table_offsets, tables_blob);
2714 build_hpet(tables_blob, tables->linker);
2715 }
2716 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
2717 acpi_add_table(table_offsets, tables_blob);
2718 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
2719
2720 if (misc.tpm_version == TPM_VERSION_2_0) {
2721 acpi_add_table(table_offsets, tables_blob);
2722 build_tpm2(tables_blob, tables->linker);
2723 }
2724 }
2725 if (pcms->numa_nodes) {
2726 acpi_add_table(table_offsets, tables_blob);
2727 build_srat(tables_blob, tables->linker, machine);
2728 }
2729 if (acpi_get_mcfg(&mcfg)) {
2730 acpi_add_table(table_offsets, tables_blob);
2731 build_mcfg_q35(tables_blob, tables->linker, &mcfg);
2732 }
2733 if (acpi_has_iommu()) {
2734 acpi_add_table(table_offsets, tables_blob);
2735 build_dmar_q35(tables_blob, tables->linker);
2736 }
2737 if (pcms->acpi_nvdimm_state.is_enabled) {
2738 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker);
2739 }
2740
2741 /* Add tables supplied by user (if any) */
2742 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2743 unsigned len = acpi_table_len(u);
2744
2745 acpi_add_table(table_offsets, tables_blob);
2746 g_array_append_vals(tables_blob, u, len);
2747 }
2748
2749 /* RSDT is pointed to by RSDP */
2750 rsdt = tables_blob->len;
2751 build_rsdt(tables_blob, tables->linker, table_offsets,
2752 slic_oem.id, slic_oem.table_id);
2753
2754 /* RSDP is in FSEG memory, so allocate it separately */
2755 build_rsdp(tables->rsdp, tables->linker, rsdt);
2756
2757 /* We'll expose it all to Guest so we want to reduce
2758 * chance of size changes.
2759 *
2760 * We used to align the tables to 4k, but of course this would
2761 * too simple to be enough. 4k turned out to be too small an
2762 * alignment very soon, and in fact it is almost impossible to
2763 * keep the table size stable for all (max_cpus, max_memory_slots)
2764 * combinations. So the table size is always 64k for pc-i440fx-2.1
2765 * and we give an error if the table grows beyond that limit.
2766 *
2767 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2768 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2769 * than 2.0 and we can always pad the smaller tables with zeros. We can
2770 * then use the exact size of the 2.0 tables.
2771 *
2772 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2773 */
2774 if (pcmc->legacy_acpi_table_size) {
2775 /* Subtracting aml_len gives the size of fixed tables. Then add the
2776 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2777 */
2778 int legacy_aml_len =
2779 pcmc->legacy_acpi_table_size +
2780 ACPI_BUILD_LEGACY_CPU_AML_SIZE * max_cpus;
2781 int legacy_table_size =
2782 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
2783 ACPI_BUILD_ALIGN_SIZE);
2784 if (tables_blob->len > legacy_table_size) {
2785 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
2786 error_report("Warning: migration may not work.");
2787 }
2788 g_array_set_size(tables_blob, legacy_table_size);
2789 } else {
2790 /* Make sure we have a buffer in case we need to resize the tables. */
2791 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
2792 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
2793 error_report("Warning: ACPI tables are larger than 64k.");
2794 error_report("Warning: migration may not work.");
2795 error_report("Warning: please remove CPUs, NUMA nodes, "
2796 "memory slots or PCI bridges.");
2797 }
2798 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
2799 }
2800
2801 acpi_align_size(tables->linker, ACPI_BUILD_ALIGN_SIZE);
2802
2803 /* Cleanup memory that's no longer used. */
2804 g_array_free(table_offsets, true);
2805 }
2806
2807 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
2808 {
2809 uint32_t size = acpi_data_len(data);
2810
2811 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2812 memory_region_ram_resize(mr, size, &error_abort);
2813
2814 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2815 memory_region_set_dirty(mr, 0, size);
2816 }
2817
2818 static void acpi_build_update(void *build_opaque)
2819 {
2820 AcpiBuildState *build_state = build_opaque;
2821 AcpiBuildTables tables;
2822
2823 /* No state to update or already patched? Nothing to do. */
2824 if (!build_state || build_state->patched) {
2825 return;
2826 }
2827 build_state->patched = 1;
2828
2829 acpi_build_tables_init(&tables);
2830
2831 acpi_build(&tables, MACHINE(qdev_get_machine()));
2832
2833 acpi_ram_update(build_state->table_mr, tables.table_data);
2834
2835 if (build_state->rsdp) {
2836 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
2837 } else {
2838 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
2839 }
2840
2841 acpi_ram_update(build_state->linker_mr, tables.linker);
2842 acpi_build_tables_cleanup(&tables, true);
2843 }
2844
2845 static void acpi_build_reset(void *build_opaque)
2846 {
2847 AcpiBuildState *build_state = build_opaque;
2848 build_state->patched = 0;
2849 }
2850
2851 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state,
2852 GArray *blob, const char *name,
2853 uint64_t max_size)
2854 {
2855 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
2856 name, acpi_build_update, build_state);
2857 }
2858
2859 static const VMStateDescription vmstate_acpi_build = {
2860 .name = "acpi_build",
2861 .version_id = 1,
2862 .minimum_version_id = 1,
2863 .fields = (VMStateField[]) {
2864 VMSTATE_UINT8(patched, AcpiBuildState),
2865 VMSTATE_END_OF_LIST()
2866 },
2867 };
2868
2869 void acpi_setup(void)
2870 {
2871 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2872 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2873 AcpiBuildTables tables;
2874 AcpiBuildState *build_state;
2875
2876 if (!pcms->fw_cfg) {
2877 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2878 return;
2879 }
2880
2881 if (!pcmc->has_acpi_build) {
2882 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2883 return;
2884 }
2885
2886 if (!acpi_enabled) {
2887 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2888 return;
2889 }
2890
2891 build_state = g_malloc0(sizeof *build_state);
2892
2893 acpi_set_pci_info();
2894
2895 acpi_build_tables_init(&tables);
2896 acpi_build(&tables, MACHINE(pcms));
2897
2898 /* Now expose it all to Guest */
2899 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data,
2900 ACPI_BUILD_TABLE_FILE,
2901 ACPI_BUILD_TABLE_MAX_SIZE);
2902 assert(build_state->table_mr != NULL);
2903
2904 build_state->linker_mr =
2905 acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0);
2906
2907 fw_cfg_add_file(pcms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
2908 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2909
2910 if (!pcmc->rsdp_in_ram) {
2911 /*
2912 * Keep for compatibility with old machine types.
2913 * Though RSDP is small, its contents isn't immutable, so
2914 * we'll update it along with the rest of tables on guest access.
2915 */
2916 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
2917
2918 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
2919 fw_cfg_add_file_callback(pcms->fw_cfg, ACPI_BUILD_RSDP_FILE,
2920 acpi_build_update, build_state,
2921 build_state->rsdp, rsdp_size);
2922 build_state->rsdp_mr = NULL;
2923 } else {
2924 build_state->rsdp = NULL;
2925 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
2926 ACPI_BUILD_RSDP_FILE, 0);
2927 }
2928
2929 qemu_register_reset(acpi_build_reset, build_state);
2930 acpi_build_reset(build_state);
2931 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
2932
2933 /* Cleanup tables but don't free the memory: we track it
2934 * in build_state.
2935 */
2936 acpi_build_tables_cleanup(&tables, false);
2937 }
AR7 emulation for QEMU