hw/s390x/s390-pci-inst.h

   1 /*
   2  * s390 PCI instruction definitions
   3  *
   4  * Copyright 2014 IBM Corp.
   5  * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com>
   6  *            Hong Bo Li <lihbbj@cn.ibm.com>
   7  *            Yi Min Zhao <zyimin@cn.ibm.com>
   8  *
   9  * This work is licensed under the terms of the GNU GPL, version 2 or (at
  10  * your option) any later version. See the COPYING file in the top-level
  11  * directory.
  12  */
  13
  14 #ifndef HW_S390_PCI_INST_H
  15 #define HW_S390_PCI_INST_H
  16
  17 #include <sysemu/dma.h>
  18
  19 /* CLP common request & response block size */
  20 #define CLP_BLK_SIZE 4096
  21 #define PCI_BAR_COUNT 6
  22 #define PCI_MAX_FUNCTIONS 4096
  23
  24 typedef struct ClpReqHdr {
  25     uint16_t len;
  26     uint16_t cmd;
  27 } QEMU_PACKED ClpReqHdr;
  28
  29 typedef struct ClpRspHdr {
  30     uint16_t len;
  31     uint16_t rsp;
  32 } QEMU_PACKED ClpRspHdr;
  33
  34 /* CLP Response Codes */
  35 #define CLP_RC_OK         0x0010  /* Command request successfully */
  36 #define CLP_RC_CMD        0x0020  /* Command code not recognized */
  37 #define CLP_RC_PERM       0x0030  /* Command not authorized */
  38 #define CLP_RC_FMT        0x0040  /* Invalid command request format */
  39 #define CLP_RC_LEN        0x0050  /* Invalid command request length */
  40 #define CLP_RC_8K         0x0060  /* Command requires 8K LPCB */
  41 #define CLP_RC_RESNOT0    0x0070  /* Reserved field not zero */
  42 #define CLP_RC_NODATA     0x0080  /* No data available */
  43 #define CLP_RC_FC_UNKNOWN 0x0100  /* Function code not recognized */
  44
  45 /*
  46  * Call Logical Processor - Command Codes
  47  */
  48 #define CLP_LIST_PCI            0x0002
  49 #define CLP_QUERY_PCI_FN        0x0003
  50 #define CLP_QUERY_PCI_FNGRP     0x0004
  51 #define CLP_SET_PCI_FN          0x0005
  52
  53 /* PCI function handle list entry */
  54 typedef struct ClpFhListEntry {
  55     uint16_t device_id;
  56     uint16_t vendor_id;
  57 #define CLP_FHLIST_MASK_CONFIG 0x80000000
  58     uint32_t config;
  59     uint32_t fid;
  60     uint32_t fh;
  61 } QEMU_PACKED ClpFhListEntry;
  62
  63 #define CLP_RC_SETPCIFN_FH      0x0101 /* Invalid PCI fn handle */
  64 #define CLP_RC_SETPCIFN_FHOP    0x0102 /* Fn handle not valid for op */
  65 #define CLP_RC_SETPCIFN_DMAAS   0x0103 /* Invalid DMA addr space */
  66 #define CLP_RC_SETPCIFN_RES     0x0104 /* Insufficient resources */
  67 #define CLP_RC_SETPCIFN_ALRDY   0x0105 /* Fn already in requested state */
  68 #define CLP_RC_SETPCIFN_ERR     0x0106 /* Fn in permanent error state */
  69 #define CLP_RC_SETPCIFN_RECPND  0x0107 /* Error recovery pending */
  70 #define CLP_RC_SETPCIFN_BUSY    0x0108 /* Fn busy */
  71 #define CLP_RC_LISTPCI_BADRT    0x010a /* Resume token not recognized */
  72 #define CLP_RC_QUERYPCIFG_PFGID 0x010b /* Unrecognized PFGID */
  73
  74 /* request or response block header length */
  75 #define LIST_PCI_HDR_LEN 32
  76
  77 /* Number of function handles fitting in response block */
  78 #define CLP_FH_LIST_NR_ENTRIES \
  79     ((CLP_BLK_SIZE - 2 * LIST_PCI_HDR_LEN) \
  80         / sizeof(ClpFhListEntry))
  81
  82 #define CLP_SET_ENABLE_PCI_FN  0 /* Yes, 0 enables it */
  83 #define CLP_SET_DISABLE_PCI_FN 1 /* Yes, 1 disables it */
  84
  85 #define CLP_UTIL_STR_LEN 64
  86
  87 #define CLP_MASK_FMT 0xf0000000
  88
  89 /* List PCI functions request */
  90 typedef struct ClpReqListPci {
  91     ClpReqHdr hdr;
  92     uint32_t fmt;
  93     uint64_t reserved1;
  94     uint64_t resume_token;
  95     uint64_t reserved2;
  96 } QEMU_PACKED ClpReqListPci;
  97
  98 /* List PCI functions response */
  99 typedef struct ClpRspListPci {
 100     ClpRspHdr hdr;
 101     uint32_t fmt;
 102     uint64_t reserved1;
 103     uint64_t resume_token;
 104     uint32_t mdd;
 105     uint16_t max_fn;
 106     uint8_t reserved2;
 107     uint8_t entry_size;
 108     ClpFhListEntry fh_list[CLP_FH_LIST_NR_ENTRIES];
 109 } QEMU_PACKED ClpRspListPci;
 110
 111 /* Query PCI function request */
 112 typedef struct ClpReqQueryPci {
 113     ClpReqHdr hdr;
 114     uint32_t fmt;
 115     uint64_t reserved1;
 116     uint32_t fh; /* function handle */
 117     uint32_t reserved2;
 118     uint64_t reserved3;
 119 } QEMU_PACKED ClpReqQueryPci;
 120
 121 /* Query PCI function response */
 122 typedef struct ClpRspQueryPci {
 123     ClpRspHdr hdr;
 124     uint32_t fmt;
 125     uint64_t reserved1;
 126     uint16_t vfn; /* virtual fn number */
 127 #define CLP_RSP_QPCI_MASK_UTIL  0x100
 128 #define CLP_RSP_QPCI_MASK_PFGID 0xff
 129     uint16_t ug;
 130     uint32_t fid; /* pci function id */
 131     uint8_t bar_size[PCI_BAR_COUNT];
 132     uint16_t pchid;
 133     uint32_t bar[PCI_BAR_COUNT];
 134     uint64_t reserved2;
 135     uint64_t sdma; /* start dma as */
 136     uint64_t edma; /* end dma as */
 137     uint32_t reserved3[11];
 138     uint32_t uid;
 139     uint8_t util_str[CLP_UTIL_STR_LEN]; /* utility string */
 140 } QEMU_PACKED ClpRspQueryPci;
 141
 142 /* Query PCI function group request */
 143 typedef struct ClpReqQueryPciGrp {
 144     ClpReqHdr hdr;
 145     uint32_t fmt;
 146     uint64_t reserved1;
 147 #define CLP_REQ_QPCIG_MASK_PFGID 0xff
 148     uint32_t g;
 149     uint32_t reserved2;
 150     uint64_t reserved3;
 151 } QEMU_PACKED ClpReqQueryPciGrp;
 152
 153 /* Query PCI function group response */
 154 typedef struct ClpRspQueryPciGrp {
 155     ClpRspHdr hdr;
 156     uint32_t fmt;
 157     uint64_t reserved1;
 158 #define CLP_RSP_QPCIG_MASK_NOI 0xfff
 159     uint16_t i;
 160     uint8_t version;
 161 #define CLP_RSP_QPCIG_MASK_FRAME   0x2
 162 #define CLP_RSP_QPCIG_MASK_REFRESH 0x1
 163     uint8_t fr;
 164     uint16_t reserved2;
 165     uint16_t mui;
 166     uint64_t reserved3;
 167     uint64_t dasm; /* dma address space mask */
 168     uint64_t msia; /* MSI address */
 169     uint64_t reserved4;
 170     uint64_t reserved5;
 171 } QEMU_PACKED ClpRspQueryPciGrp;
 172
 173 /* Set PCI function request */
 174 typedef struct ClpReqSetPci {
 175     ClpReqHdr hdr;
 176     uint32_t fmt;
 177     uint64_t reserved1;
 178     uint32_t fh; /* function handle */
 179     uint16_t reserved2;
 180     uint8_t oc; /* operation controls */
 181     uint8_t ndas; /* number of dma spaces */
 182     uint64_t reserved3;
 183 } QEMU_PACKED ClpReqSetPci;
 184
 185 /* Set PCI function response */
 186 typedef struct ClpRspSetPci {
 187     ClpRspHdr hdr;
 188     uint32_t fmt;
 189     uint64_t reserved1;
 190     uint32_t fh; /* function handle */
 191     uint32_t reserved3;
 192     uint64_t reserved4;
 193 } QEMU_PACKED ClpRspSetPci;
 194
 195 typedef struct ClpReqRspListPci {
 196     ClpReqListPci request;
 197     ClpRspListPci response;
 198 } QEMU_PACKED ClpReqRspListPci;
 199
 200 typedef struct ClpReqRspSetPci {
 201     ClpReqSetPci request;
 202     ClpRspSetPci response;
 203 } QEMU_PACKED ClpReqRspSetPci;
 204
 205 typedef struct ClpReqRspQueryPci {
 206     ClpReqQueryPci request;
 207     ClpRspQueryPci response;
 208 } QEMU_PACKED ClpReqRspQueryPci;
 209
 210 typedef struct ClpReqRspQueryPciGrp {
 211     ClpReqQueryPciGrp request;
 212     ClpRspQueryPciGrp response;
 213 } QEMU_PACKED ClpReqRspQueryPciGrp;
 214
 215 /* Load/Store status codes */
 216 #define ZPCI_PCI_ST_FUNC_NOT_ENABLED        4
 217 #define ZPCI_PCI_ST_FUNC_IN_ERR             8
 218 #define ZPCI_PCI_ST_BLOCKED                 12
 219 #define ZPCI_PCI_ST_INSUF_RES               16
 220 #define ZPCI_PCI_ST_INVAL_AS                20
 221 #define ZPCI_PCI_ST_FUNC_ALREADY_ENABLED    24
 222 #define ZPCI_PCI_ST_DMA_AS_NOT_ENABLED      28
 223 #define ZPCI_PCI_ST_2ND_OP_IN_INV_AS        36
 224 #define ZPCI_PCI_ST_FUNC_NOT_AVAIL          40
 225 #define ZPCI_PCI_ST_ALREADY_IN_RQ_STATE     44
 226
 227 /* Load/Store return codes */
 228 #define ZPCI_PCI_LS_OK              0
 229 #define ZPCI_PCI_LS_ERR             1
 230 #define ZPCI_PCI_LS_BUSY            2
 231 #define ZPCI_PCI_LS_INVAL_HANDLE    3
 232
 233 /* Modify PCI Function Controls */
 234 #define ZPCI_MOD_FC_REG_INT     2
 235 #define ZPCI_MOD_FC_DEREG_INT   3
 236 #define ZPCI_MOD_FC_REG_IOAT    4
 237 #define ZPCI_MOD_FC_DEREG_IOAT  5
 238 #define ZPCI_MOD_FC_REREG_IOAT  6
 239 #define ZPCI_MOD_FC_RESET_ERROR 7
 240 #define ZPCI_MOD_FC_RESET_BLOCK 9
 241 #define ZPCI_MOD_FC_SET_MEASURE 10
 242
 243 /* FIB function controls */
 244 #define ZPCI_FIB_FC_ENABLED     0x80
 245 #define ZPCI_FIB_FC_ERROR       0x40
 246 #define ZPCI_FIB_FC_LS_BLOCKED  0x20
 247 #define ZPCI_FIB_FC_DMAAS_REG   0x10
 248
 249 /* FIB function controls */
 250 #define ZPCI_FIB_FC_ENABLED     0x80
 251 #define ZPCI_FIB_FC_ERROR       0x40
 252 #define ZPCI_FIB_FC_LS_BLOCKED  0x20
 253 #define ZPCI_FIB_FC_DMAAS_REG   0x10
 254
 255 /* Function Information Block */
 256 typedef struct ZpciFib {
 257     uint8_t fmt;   /* format */
 258     uint8_t reserved1[7];
 259     uint8_t fc;                  /* function controls */
 260     uint8_t reserved2;
 261     uint16_t reserved3;
 262     uint32_t reserved4;
 263     uint64_t pba;                /* PCI base address */
 264     uint64_t pal;                /* PCI address limit */
 265     uint64_t iota;               /* I/O Translation Anchor */
 266 #define FIB_DATA_ISC(x)    (((x) >> 28) & 0x7)
 267 #define FIB_DATA_NOI(x)    (((x) >> 16) & 0xfff)
 268 #define FIB_DATA_AIBVO(x) (((x) >> 8) & 0x3f)
 269 #define FIB_DATA_SUM(x)    (((x) >> 7) & 0x1)
 270 #define FIB_DATA_AISBO(x)  ((x) & 0x3f)
 271     uint32_t data;
 272     uint32_t reserved5;
 273     uint64_t aibv;               /* Adapter int bit vector address */
 274     uint64_t aisb;               /* Adapter int summary bit address */
 275     uint64_t fmb_addr;           /* Function measurement address and key */
 276     uint32_t reserved6;
 277     uint32_t gd;
 278 } QEMU_PACKED ZpciFib;
 279
 280 int clp_service_call(S390CPU *cpu, uint8_t r2);
 281 int pcilg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2);
 282 int pcistg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2);
 283 int rpcit_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2);
 284 int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr,
 285                         uint8_t ar);
 286 int mpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar);
 287 int stpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar);
 288
 289 #endif