hw/arm/xlnx-zcu102.c

   1 /*
   2  * Xilinx ZynqMP ZCU102 board
   3  *
   4  * Copyright (C) 2015 Xilinx Inc
   5  * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  15  * for more details.
  16  */
  17
  18 #include "qemu/osdep.h"
  19 #include "qapi/error.h"
  20 #include "cpu.h"
  21 #include "hw/arm/xlnx-zynqmp.h"
  22 #include "hw/boards.h"
  23 #include "qemu/error-report.h"
  24 #include "qemu/log.h"
  25 #include "sysemu/qtest.h"
  26 #include "sysemu/device_tree.h"
  27 #include "qom/object.h"
  28
  29 struct XlnxZCU102 {
  30     MachineState parent_obj;
  31
  32     XlnxZynqMPState soc;
  33
  34     bool secure;
  35     bool virt;
  36
  37     struct arm_boot_info binfo;
  38 };
  39
  40 #define TYPE_ZCU102_MACHINE   MACHINE_TYPE_NAME("xlnx-zcu102")
  41 OBJECT_DECLARE_SIMPLE_TYPE(XlnxZCU102, ZCU102_MACHINE)
  42
  43
  44 static bool zcu102_get_secure(Object *obj, Error **errp)
  45 {
  46     XlnxZCU102 *s = ZCU102_MACHINE(obj);
  47
  48     return s->secure;
  49 }
  50
  51 static void zcu102_set_secure(Object *obj, bool value, Error **errp)
  52 {
  53     XlnxZCU102 *s = ZCU102_MACHINE(obj);
  54
  55     s->secure = value;
  56 }
  57
  58 static bool zcu102_get_virt(Object *obj, Error **errp)
  59 {
  60     XlnxZCU102 *s = ZCU102_MACHINE(obj);
  61
  62     return s->virt;
  63 }
  64
  65 static void zcu102_set_virt(Object *obj, bool value, Error **errp)
  66 {
  67     XlnxZCU102 *s = ZCU102_MACHINE(obj);
  68
  69     s->virt = value;
  70 }
  71
  72 static void zcu102_modify_dtb(const struct arm_boot_info *binfo, void *fdt)
  73 {
  74     XlnxZCU102 *s = container_of(binfo, XlnxZCU102, binfo);
  75     bool method_is_hvc;
  76     char **node_path;
  77     const char *r;
  78     int prop_len;
  79     int i;
  80
  81     /* If EL3 is enabled, we keep all firmware nodes active.  */
  82     if (!s->secure) {
  83         node_path = qemu_fdt_node_path(fdt, NULL, "xlnx,zynqmp-firmware",
  84                                        &error_fatal);
  85
  86         for (i = 0; node_path && node_path[i]; i++) {
  87             r = qemu_fdt_getprop(fdt, node_path[i], "method", &prop_len, NULL);
  88             method_is_hvc = r && !strcmp("hvc", r);
  89
  90             /* Allow HVC based firmware if EL2 is enabled.  */
  91             if (method_is_hvc && s->virt) {
  92                 continue;
  93             }
  94             qemu_fdt_setprop_string(fdt, node_path[i], "status", "disabled");
  95         }
  96         g_strfreev(node_path);
  97     }
  98 }
  99
 100 static void xlnx_zcu102_init(MachineState *machine)
 101 {
 102     XlnxZCU102 *s = ZCU102_MACHINE(machine);
 103     int i;
 104     uint64_t ram_size = machine->ram_size;
 105
 106     /* Create the memory region to pass to the SoC */
 107     if (ram_size > XLNX_ZYNQMP_MAX_RAM_SIZE) {
 108         error_report("ERROR: RAM size 0x%" PRIx64 " above max supported of "
 109                      "0x%llx", ram_size,
 110                      XLNX_ZYNQMP_MAX_RAM_SIZE);
 111         exit(1);
 112     }
 113
 114     if (ram_size < 0x08000000) {
 115         qemu_log("WARNING: RAM size 0x%" PRIx64 " is small for ZCU102",
 116                  ram_size);
 117     }
 118
 119     object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_XLNX_ZYNQMP);
 120
 121     object_property_set_link(OBJECT(&s->soc), "ddr-ram", OBJECT(machine->ram),
 122                              &error_abort);
 123     object_property_set_bool(OBJECT(&s->soc), "secure", s->secure,
 124                              &error_fatal);
 125     object_property_set_bool(OBJECT(&s->soc), "virtualization", s->virt,
 126                              &error_fatal);
 127
 128     qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
 129
 130     /* Create and plug in the SD cards */
 131     for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
 132         BusState *bus;
 133         DriveInfo *di = drive_get_next(IF_SD);
 134         BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL;
 135         DeviceState *carddev;
 136         char *bus_name;
 137
 138         bus_name = g_strdup_printf("sd-bus%d", i);
 139         bus = qdev_get_child_bus(DEVICE(&s->soc), bus_name);
 140         g_free(bus_name);
 141         if (!bus) {
 142             error_report("No SD bus found for SD card %d", i);
 143             exit(1);
 144         }
 145         carddev = qdev_new(TYPE_SD_CARD);
 146         qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal);
 147         qdev_realize_and_unref(carddev, bus, &error_fatal);
 148     }
 149
 150     for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
 151         BusState *spi_bus;
 152         DeviceState *flash_dev;
 153         qemu_irq cs_line;
 154         DriveInfo *dinfo = drive_get_next(IF_MTD);
 155         gchar *bus_name = g_strdup_printf("spi%d", i);
 156
 157         spi_bus = qdev_get_child_bus(DEVICE(&s->soc), bus_name);
 158         g_free(bus_name);
 159
 160         flash_dev = qdev_new("sst25wf080");
 161         if (dinfo) {
 162             qdev_prop_set_drive_err(flash_dev, "drive",
 163                                     blk_by_legacy_dinfo(dinfo), &error_fatal);
 164         }
 165         qdev_realize_and_unref(flash_dev, spi_bus, &error_fatal);
 166
 167         cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
 168
 169         sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi[i]), 1, cs_line);
 170     }
 171
 172     for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_FLASH; i++) {
 173         BusState *spi_bus;
 174         DeviceState *flash_dev;
 175         qemu_irq cs_line;
 176         DriveInfo *dinfo = drive_get_next(IF_MTD);
 177         int bus = i / XLNX_ZYNQMP_NUM_QSPI_BUS_CS;
 178         gchar *bus_name = g_strdup_printf("qspi%d", bus);
 179
 180         spi_bus = qdev_get_child_bus(DEVICE(&s->soc), bus_name);
 181         g_free(bus_name);
 182
 183         flash_dev = qdev_new("n25q512a11");
 184         if (dinfo) {
 185             qdev_prop_set_drive_err(flash_dev, "drive",
 186                                     blk_by_legacy_dinfo(dinfo), &error_fatal);
 187         }
 188         qdev_realize_and_unref(flash_dev, spi_bus, &error_fatal);
 189
 190         cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
 191
 192         sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.qspi), i + 1, cs_line);
 193     }
 194
 195     /* TODO create and connect IDE devices for ide_drive_get() */
 196
 197     s->binfo.ram_size = ram_size;
 198     s->binfo.loader_start = 0;
 199     s->binfo.modify_dtb = zcu102_modify_dtb;
 200     arm_load_kernel(s->soc.boot_cpu_ptr, machine, &s->binfo);
 201 }
 202
 203 static void xlnx_zcu102_machine_instance_init(Object *obj)
 204 {
 205     XlnxZCU102 *s = ZCU102_MACHINE(obj);
 206
 207     /* Default to secure mode being disabled */
 208     s->secure = false;
 209     /* Default to virt (EL2) being disabled */
 210     s->virt = false;
 211 }
 212
 213 static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data)
 214 {
 215     MachineClass *mc = MACHINE_CLASS(oc);
 216
 217     mc->desc = "Xilinx ZynqMP ZCU102 board with 4xA53s and 2xR5Fs based on " \
 218                "the value of smp";
 219     mc->init = xlnx_zcu102_init;
 220     mc->block_default_type = IF_IDE;
 221     mc->units_per_default_bus = 1;
 222     mc->ignore_memory_transaction_failures = true;
 223     mc->max_cpus = XLNX_ZYNQMP_NUM_APU_CPUS + XLNX_ZYNQMP_NUM_RPU_CPUS;
 224     mc->default_cpus = XLNX_ZYNQMP_NUM_APU_CPUS;
 225     mc->default_ram_id = "ddr-ram";
 226
 227     object_class_property_add_bool(oc, "secure", zcu102_get_secure,
 228                                    zcu102_set_secure);
 229     object_class_property_set_description(oc, "secure",
 230                                           "Set on/off to enable/disable the ARM "
 231                                           "Security Extensions (TrustZone)");
 232
 233     object_class_property_add_bool(oc, "virtualization", zcu102_get_virt,
 234                                    zcu102_set_virt);
 235     object_class_property_set_description(oc, "virtualization",
 236                                           "Set on/off to enable/disable emulating a "
 237                                           "guest CPU which implements the ARM "
 238                                           "Virtualization Extensions");
 239 }
 240
 241 static const TypeInfo xlnx_zcu102_machine_init_typeinfo = {
 242     .name       = TYPE_ZCU102_MACHINE,
 243     .parent     = TYPE_MACHINE,
 244     .class_init = xlnx_zcu102_machine_class_init,
 245     .instance_init = xlnx_zcu102_machine_instance_init,
 246     .instance_size = sizeof(XlnxZCU102),
 247 };
 248
 249 static void xlnx_zcu102_machine_init_register_types(void)
 250 {
 251     type_register_static(&xlnx_zcu102_machine_init_typeinfo);
 252 }
 253
 254 type_init(xlnx_zcu102_machine_init_register_types)