hw/ppc/prep.c

   1 /*
   2  * QEMU PPC PREP hardware System Emulator
   3  *
   4  * Copyright (c) 2003-2007 Jocelyn Mayer
   5  * Copyright (c) 2017 Hervé Poussineau
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "qemu/osdep.h"
  26 #include "cpu.h"
  27 #include "hw/hw.h"
  28 #include "hw/timer/m48t59.h"
  29 #include "hw/char/serial.h"
  30 #include "hw/block/fdc.h"
  31 #include "net/net.h"
  32 #include "sysemu/sysemu.h"
  33 #include "hw/isa/isa.h"
  34 #include "hw/pci/pci.h"
  35 #include "hw/pci/pci_host.h"
  36 #include "hw/ppc/ppc.h"
  37 #include "hw/boards.h"
  38 #include "qemu/error-report.h"
  39 #include "qemu/log.h"
  40 #include "hw/ide.h"
  41 #include "hw/loader.h"
  42 #include "hw/timer/mc146818rtc.h"
  43 #include "hw/input/i8042.h"
  44 #include "hw/isa/pc87312.h"
  45 #include "hw/net/ne2000-isa.h"
  46 #include "sysemu/arch_init.h"
  47 #include "sysemu/kvm.h"
  48 #include "sysemu/qtest.h"
  49 #include "exec/address-spaces.h"
  50 #include "trace.h"
  51 #include "elf.h"
  52 #include "qemu/units.h"
  53 #include "kvm_ppc.h"
  54
  55 /* SMP is not enabled, for now */
  56 #define MAX_CPUS 1
  57
  58 #define MAX_IDE_BUS 2
  59
  60 #define CFG_ADDR 0xf0000510
  61
  62 #define BIOS_SIZE (1 * MiB)
  63 #define BIOS_FILENAME "ppc_rom.bin"
  64 #define KERNEL_LOAD_ADDR 0x01000000
  65 #define INITRD_LOAD_ADDR 0x01800000
  66
  67 /* Constants for devices init */
  68 static const int ide_iobase[2] = { 0x1f0, 0x170 };
  69 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
  70 static const int ide_irq[2] = { 13, 13 };
  71
  72 #define NE2000_NB_MAX 6
  73
  74 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
  75 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
  76
  77 /* ISA IO ports bridge */
  78 #define PPC_IO_BASE 0x80000000
  79
  80 /* Fake super-io ports for PREP platform (Intel 82378ZB) */
  81 typedef struct sysctrl_t {
  82     qemu_irq reset_irq;
  83     Nvram *nvram;
  84     uint8_t state;
  85     uint8_t syscontrol;
  86     int contiguous_map;
  87     qemu_irq contiguous_map_irq;
  88     int endian;
  89 } sysctrl_t;
  90
  91 enum {
  92     STATE_HARDFILE = 0x01,
  93 };
  94
  95 static sysctrl_t *sysctrl;
  96
  97 static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
  98 {
  99     sysctrl_t *sysctrl = opaque;
 100
 101     trace_prep_io_800_writeb(addr - PPC_IO_BASE, val);
 102     switch (addr) {
 103     case 0x0092:
 104         /* Special port 92 */
 105         /* Check soft reset asked */
 106         if (val & 0x01) {
 107             qemu_irq_raise(sysctrl->reset_irq);
 108         } else {
 109             qemu_irq_lower(sysctrl->reset_irq);
 110         }
 111         /* Check LE mode */
 112         if (val & 0x02) {
 113             sysctrl->endian = 1;
 114         } else {
 115             sysctrl->endian = 0;
 116         }
 117         break;
 118     case 0x0800:
 119         /* Motorola CPU configuration register : read-only */
 120         break;
 121     case 0x0802:
 122         /* Motorola base module feature register : read-only */
 123         break;
 124     case 0x0803:
 125         /* Motorola base module status register : read-only */
 126         break;
 127     case 0x0808:
 128         /* Hardfile light register */
 129         if (val & 1)
 130             sysctrl->state |= STATE_HARDFILE;
 131         else
 132             sysctrl->state &= ~STATE_HARDFILE;
 133         break;
 134     case 0x0810:
 135         /* Password protect 1 register */
 136         if (sysctrl->nvram != NULL) {
 137             NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
 138             (k->toggle_lock)(sysctrl->nvram, 1);
 139         }
 140         break;
 141     case 0x0812:
 142         /* Password protect 2 register */
 143         if (sysctrl->nvram != NULL) {
 144             NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
 145             (k->toggle_lock)(sysctrl->nvram, 2);
 146         }
 147         break;
 148     case 0x0814:
 149         /* L2 invalidate register */
 150         //        tlb_flush(first_cpu, 1);
 151         break;
 152     case 0x081C:
 153         /* system control register */
 154         sysctrl->syscontrol = val & 0x0F;
 155         break;
 156     case 0x0850:
 157         /* I/O map type register */
 158         sysctrl->contiguous_map = val & 0x01;
 159         qemu_set_irq(sysctrl->contiguous_map_irq, sysctrl->contiguous_map);
 160         break;
 161     default:
 162         printf("ERROR: unaffected IO port write: %04" PRIx32
 163                " => %02" PRIx32"\n", addr, val);
 164         break;
 165     }
 166 }
 167
 168 static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
 169 {
 170     sysctrl_t *sysctrl = opaque;
 171     uint32_t retval = 0xFF;
 172
 173     switch (addr) {
 174     case 0x0092:
 175         /* Special port 92 */
 176         retval = sysctrl->endian << 1;
 177         break;
 178     case 0x0800:
 179         /* Motorola CPU configuration register */
 180         retval = 0xEF; /* MPC750 */
 181         break;
 182     case 0x0802:
 183         /* Motorola Base module feature register */
 184         retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
 185         break;
 186     case 0x0803:
 187         /* Motorola base module status register */
 188         retval = 0xE0; /* Standard MPC750 */
 189         break;
 190     case 0x080C:
 191         /* Equipment present register:
 192          *  no L2 cache
 193          *  no upgrade processor
 194          *  no cards in PCI slots
 195          *  SCSI fuse is bad
 196          */
 197         retval = 0x3C;
 198         break;
 199     case 0x0810:
 200         /* Motorola base module extended feature register */
 201         retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
 202         break;
 203     case 0x0814:
 204         /* L2 invalidate: don't care */
 205         break;
 206     case 0x0818:
 207         /* Keylock */
 208         retval = 0x00;
 209         break;
 210     case 0x081C:
 211         /* system control register
 212          * 7 - 6 / 1 - 0: L2 cache enable
 213          */
 214         retval = sysctrl->syscontrol;
 215         break;
 216     case 0x0823:
 217         /* */
 218         retval = 0x03; /* no L2 cache */
 219         break;
 220     case 0x0850:
 221         /* I/O map type register */
 222         retval = sysctrl->contiguous_map;
 223         break;
 224     default:
 225         printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr);
 226         break;
 227     }
 228     trace_prep_io_800_readb(addr - PPC_IO_BASE, retval);
 229
 230     return retval;
 231 }
 232
 233
 234 #define NVRAM_SIZE        0x2000
 235
 236 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
 237                             Error **errp)
 238 {
 239     fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
 240 }
 241
 242 static void ppc_prep_reset(void *opaque)
 243 {
 244     PowerPCCPU *cpu = opaque;
 245
 246     cpu_reset(CPU(cpu));
 247 }
 248
 249 static const MemoryRegionPortio prep_portio_list[] = {
 250     /* System control ports */
 251     { 0x0092, 1, 1, .read = PREP_io_800_readb, .write = PREP_io_800_writeb, },
 252     { 0x0800, 0x52, 1,
 253       .read = PREP_io_800_readb, .write = PREP_io_800_writeb, },
 254     /* Special port to get debug messages from Open-Firmware */
 255     { 0x0F00, 4, 1, .write = PPC_debug_write, },
 256     PORTIO_END_OF_LIST(),
 257 };
 258
 259 static PortioList prep_port_list;
 260
 261 /*****************************************************************************/
 262 /* NVRAM helpers */
 263 static inline uint32_t nvram_read(Nvram *nvram, uint32_t addr)
 264 {
 265     NvramClass *k = NVRAM_GET_CLASS(nvram);
 266     return (k->read)(nvram, addr);
 267 }
 268
 269 static inline void nvram_write(Nvram *nvram, uint32_t addr, uint32_t val)
 270 {
 271     NvramClass *k = NVRAM_GET_CLASS(nvram);
 272     (k->write)(nvram, addr, val);
 273 }
 274
 275 static void NVRAM_set_byte(Nvram *nvram, uint32_t addr, uint8_t value)
 276 {
 277     nvram_write(nvram, addr, value);
 278 }
 279
 280 static uint8_t NVRAM_get_byte(Nvram *nvram, uint32_t addr)
 281 {
 282     return nvram_read(nvram, addr);
 283 }
 284
 285 static void NVRAM_set_word(Nvram *nvram, uint32_t addr, uint16_t value)
 286 {
 287     nvram_write(nvram, addr, value >> 8);
 288     nvram_write(nvram, addr + 1, value & 0xFF);
 289 }
 290
 291 static uint16_t NVRAM_get_word(Nvram *nvram, uint32_t addr)
 292 {
 293     uint16_t tmp;
 294
 295     tmp = nvram_read(nvram, addr) << 8;
 296     tmp |= nvram_read(nvram, addr + 1);
 297
 298     return tmp;
 299 }
 300
 301 static void NVRAM_set_lword(Nvram *nvram, uint32_t addr, uint32_t value)
 302 {
 303     nvram_write(nvram, addr, value >> 24);
 304     nvram_write(nvram, addr + 1, (value >> 16) & 0xFF);
 305     nvram_write(nvram, addr + 2, (value >> 8) & 0xFF);
 306     nvram_write(nvram, addr + 3, value & 0xFF);
 307 }
 308
 309 static void NVRAM_set_string(Nvram *nvram, uint32_t addr, const char *str,
 310                              uint32_t max)
 311 {
 312     int i;
 313
 314     for (i = 0; i < max && str[i] != '\0'; i++) {
 315         nvram_write(nvram, addr + i, str[i]);
 316     }
 317     nvram_write(nvram, addr + i, str[i]);
 318     nvram_write(nvram, addr + max - 1, '\0');
 319 }
 320
 321 static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
 322 {
 323     uint16_t tmp;
 324     uint16_t pd, pd1, pd2;
 325
 326     tmp = prev >> 8;
 327     pd = prev ^ value;
 328     pd1 = pd & 0x000F;
 329     pd2 = ((pd >> 4) & 0x000F) ^ pd1;
 330     tmp ^= (pd1 << 3) | (pd1 << 8);
 331     tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
 332
 333     return tmp;
 334 }
 335
 336 static uint16_t NVRAM_compute_crc (Nvram *nvram, uint32_t start, uint32_t count)
 337 {
 338     uint32_t i;
 339     uint16_t crc = 0xFFFF;
 340     int odd;
 341
 342     odd = count & 1;
 343     count &= ~1;
 344     for (i = 0; i != count; i++) {
 345         crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
 346     }
 347     if (odd) {
 348         crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
 349     }
 350
 351     return crc;
 352 }
 353
 354 #define CMDLINE_ADDR 0x017ff000
 355
 356 static int PPC_NVRAM_set_params (Nvram *nvram, uint16_t NVRAM_size,
 357                           const char *arch,
 358                           uint32_t RAM_size, int boot_device,
 359                           uint32_t kernel_image, uint32_t kernel_size,
 360                           const char *cmdline,
 361                           uint32_t initrd_image, uint32_t initrd_size,
 362                           uint32_t NVRAM_image,
 363                           int width, int height, int depth)
 364 {
 365     uint16_t crc;
 366
 367     /* Set parameters for Open Hack'Ware BIOS */
 368     NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
 369     NVRAM_set_lword(nvram,  0x10, 0x00000002); /* structure v2 */
 370     NVRAM_set_word(nvram,   0x14, NVRAM_size);
 371     NVRAM_set_string(nvram, 0x20, arch, 16);
 372     NVRAM_set_lword(nvram,  0x30, RAM_size);
 373     NVRAM_set_byte(nvram,   0x34, boot_device);
 374     NVRAM_set_lword(nvram,  0x38, kernel_image);
 375     NVRAM_set_lword(nvram,  0x3C, kernel_size);
 376     if (cmdline) {
 377         /* XXX: put the cmdline in NVRAM too ? */
 378         pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR,
 379                          cmdline);
 380         NVRAM_set_lword(nvram,  0x40, CMDLINE_ADDR);
 381         NVRAM_set_lword(nvram,  0x44, strlen(cmdline));
 382     } else {
 383         NVRAM_set_lword(nvram,  0x40, 0);
 384         NVRAM_set_lword(nvram,  0x44, 0);
 385     }
 386     NVRAM_set_lword(nvram,  0x48, initrd_image);
 387     NVRAM_set_lword(nvram,  0x4C, initrd_size);
 388     NVRAM_set_lword(nvram,  0x50, NVRAM_image);
 389
 390     NVRAM_set_word(nvram,   0x54, width);
 391     NVRAM_set_word(nvram,   0x56, height);
 392     NVRAM_set_word(nvram,   0x58, depth);
 393     crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
 394     NVRAM_set_word(nvram,   0xFC, crc);
 395
 396     return 0;
 397 }
 398
 399 /* PowerPC PREP hardware initialisation */
 400 static void ppc_prep_init(MachineState *machine)
 401 {
 402     ram_addr_t ram_size = machine->ram_size;
 403     const char *kernel_filename = machine->kernel_filename;
 404     const char *kernel_cmdline = machine->kernel_cmdline;
 405     const char *initrd_filename = machine->initrd_filename;
 406     const char *boot_device = machine->boot_order;
 407     MemoryRegion *sysmem = get_system_memory();
 408     PowerPCCPU *cpu = NULL;
 409     CPUPPCState *env = NULL;
 410     Nvram *m48t59;
 411 #if 0
 412     MemoryRegion *xcsr = g_new(MemoryRegion, 1);
 413 #endif
 414     int linux_boot, i, nb_nics1;
 415     MemoryRegion *ram = g_new(MemoryRegion, 1);
 416     uint32_t kernel_base, initrd_base;
 417     long kernel_size, initrd_size;
 418     DeviceState *dev;
 419     PCIHostState *pcihost;
 420     PCIBus *pci_bus;
 421     PCIDevice *pci;
 422     ISABus *isa_bus;
 423     ISADevice *isa;
 424     int ppc_boot_device;
 425     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 426
 427     sysctrl = g_malloc0(sizeof(sysctrl_t));
 428
 429     linux_boot = (kernel_filename != NULL);
 430
 431     /* init CPUs */
 432     for (i = 0; i < smp_cpus; i++) {
 433         cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
 434         env = &cpu->env;
 435
 436         if (env->flags & POWERPC_FLAG_RTC_CLK) {
 437             /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
 438             cpu_ppc_tb_init(env, 7812500UL);
 439         } else {
 440             /* Set time-base frequency to 100 Mhz */
 441             cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
 442         }
 443         qemu_register_reset(ppc_prep_reset, cpu);
 444     }
 445
 446     /* allocate RAM */
 447     memory_region_allocate_system_memory(ram, NULL, "ppc_prep.ram", ram_size);
 448     memory_region_add_subregion(sysmem, 0, ram);
 449
 450     if (linux_boot) {
 451         kernel_base = KERNEL_LOAD_ADDR;
 452         /* now we can load the kernel */
 453         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 454                                           ram_size - kernel_base);
 455         if (kernel_size < 0) {
 456             error_report("could not load kernel '%s'", kernel_filename);
 457             exit(1);
 458         }
 459         /* load initrd */
 460         if (initrd_filename) {
 461             initrd_base = INITRD_LOAD_ADDR;
 462             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 463                                               ram_size - initrd_base);
 464             if (initrd_size < 0) {
 465                 error_report("could not load initial ram disk '%s'",
 466                              initrd_filename);
 467                 exit(1);
 468             }
 469         } else {
 470             initrd_base = 0;
 471             initrd_size = 0;
 472         }
 473         ppc_boot_device = 'm';
 474     } else {
 475         kernel_base = 0;
 476         kernel_size = 0;
 477         initrd_base = 0;
 478         initrd_size = 0;
 479         ppc_boot_device = '\0';
 480         /* For now, OHW cannot boot from the network. */
 481         for (i = 0; boot_device[i] != '\0'; i++) {
 482             if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
 483                 ppc_boot_device = boot_device[i];
 484                 break;
 485             }
 486         }
 487         if (ppc_boot_device == '\0') {
 488             error_report("No valid boot device for Mac99 machine");
 489             exit(1);
 490         }
 491     }
 492
 493     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 494         error_report("Only 6xx bus is supported on PREP machine");
 495         exit(1);
 496     }
 497
 498     dev = qdev_create(NULL, "raven-pcihost");
 499     if (bios_name == NULL) {
 500         bios_name = BIOS_FILENAME;
 501     }
 502     qdev_prop_set_string(dev, "bios-name", bios_name);
 503     qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE);
 504     qdev_prop_set_bit(dev, "is-legacy-prep", true);
 505     pcihost = PCI_HOST_BRIDGE(dev);
 506     object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL);
 507     qdev_init_nofail(dev);
 508     pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
 509     if (pci_bus == NULL) {
 510         error_report("Couldn't create PCI host controller");
 511         exit(1);
 512     }
 513     sysctrl->contiguous_map_irq = qdev_get_gpio_in(dev, 0);
 514
 515     /* PCI -> ISA bridge */
 516     pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378");
 517     cpu = POWERPC_CPU(first_cpu);
 518     qdev_connect_gpio_out(&pci->qdev, 0,
 519                           cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
 520     sysbus_connect_irq(&pcihost->busdev, 0, qdev_get_gpio_in(&pci->qdev, 9));
 521     sysbus_connect_irq(&pcihost->busdev, 1, qdev_get_gpio_in(&pci->qdev, 11));
 522     sysbus_connect_irq(&pcihost->busdev, 2, qdev_get_gpio_in(&pci->qdev, 9));
 523     sysbus_connect_irq(&pcihost->busdev, 3, qdev_get_gpio_in(&pci->qdev, 11));
 524     isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci), "isa.0"));
 525
 526     /* Super I/O (parallel + serial ports) */
 527     isa = isa_create(isa_bus, TYPE_PC87312_SUPERIO);
 528     dev = DEVICE(isa);
 529     qdev_prop_set_uint8(dev, "config", 13); /* fdc, ser0, ser1, par0 */
 530     qdev_init_nofail(dev);
 531
 532     /* init basic PC hardware */
 533     pci_vga_init(pci_bus);
 534
 535     nb_nics1 = nb_nics;
 536     if (nb_nics1 > NE2000_NB_MAX)
 537         nb_nics1 = NE2000_NB_MAX;
 538     for(i = 0; i < nb_nics1; i++) {
 539         if (nd_table[i].model == NULL) {
 540             nd_table[i].model = g_strdup("ne2k_isa");
 541         }
 542         if (strcmp(nd_table[i].model, "ne2k_isa") == 0) {
 543             isa_ne2000_init(isa_bus, ne2000_io[i], ne2000_irq[i],
 544                             &nd_table[i]);
 545         } else {
 546             pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
 547         }
 548     }
 549
 550     ide_drive_get(hd, ARRAY_SIZE(hd));
 551     for(i = 0; i < MAX_IDE_BUS; i++) {
 552         isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i],
 553                      hd[2 * i],
 554                      hd[2 * i + 1]);
 555     }
 556
 557     cpu = POWERPC_CPU(first_cpu);
 558     sysctrl->reset_irq = cpu->env.irq_inputs[PPC6xx_INPUT_HRESET];
 559
 560     portio_list_init(&prep_port_list, NULL, prep_portio_list, sysctrl, "prep");
 561     portio_list_add(&prep_port_list, isa_address_space_io(isa), 0x0);
 562
 563     /*
 564      * PowerPC control and status register group: unimplemented,
 565      * would be at address 0xFEFF0000.
 566      */
 567
 568     if (machine_usb(machine)) {
 569         pci_create_simple(pci_bus, -1, "pci-ohci");
 570     }
 571
 572     m48t59 = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 2000, 59);
 573     if (m48t59 == NULL)
 574         return;
 575     sysctrl->nvram = m48t59;
 576
 577     /* Initialise NVRAM */
 578     PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", ram_size,
 579                          ppc_boot_device,
 580                          kernel_base, kernel_size,
 581                          kernel_cmdline,
 582                          initrd_base, initrd_size,
 583                          /* XXX: need an option to load a NVRAM image */
 584                          0,
 585                          graphic_width, graphic_height, graphic_depth);
 586 }
 587
 588 static void prep_machine_init(MachineClass *mc)
 589 {
 590     mc->deprecation_reason = "use 40p machine type instead";
 591     mc->desc = "PowerPC PREP platform";
 592     mc->init = ppc_prep_init;
 593     mc->block_default_type = IF_IDE;
 594     mc->max_cpus = MAX_CPUS;
 595     mc->default_boot_order = "cad";
 596     mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("602");
 597     mc->default_display = "std";
 598 }
 599
 600 static int prep_set_cmos_checksum(DeviceState *dev, void *opaque)
 601 {
 602     uint16_t checksum = *(uint16_t *)opaque;
 603     ISADevice *rtc;
 604
 605     if (object_dynamic_cast(OBJECT(dev), "mc146818rtc")) {
 606         rtc = ISA_DEVICE(dev);
 607         rtc_set_memory(rtc, 0x2e, checksum & 0xff);
 608         rtc_set_memory(rtc, 0x3e, checksum & 0xff);
 609         rtc_set_memory(rtc, 0x2f, checksum >> 8);
 610         rtc_set_memory(rtc, 0x3f, checksum >> 8);
 611
 612         object_property_add_alias(qdev_get_machine(), "rtc-time", OBJECT(rtc),
 613                                   "date", NULL);
 614     }
 615     return 0;
 616 }
 617
 618 static void ibm_40p_init(MachineState *machine)
 619 {
 620     CPUPPCState *env = NULL;
 621     uint16_t cmos_checksum;
 622     PowerPCCPU *cpu;
 623     DeviceState *dev, *i82378_dev;
 624     SysBusDevice *pcihost, *s;
 625     Nvram *m48t59 = NULL;
 626     PCIBus *pci_bus;
 627     ISABus *isa_bus;
 628     void *fw_cfg;
 629     int i;
 630     uint32_t kernel_base = 0, initrd_base = 0;
 631     long kernel_size = 0, initrd_size = 0;
 632     char boot_device;
 633
 634     /* init CPU */
 635     cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
 636     env = &cpu->env;
 637     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 638         error_report("only 6xx bus is supported on this machine");
 639         exit(1);
 640     }
 641
 642     if (env->flags & POWERPC_FLAG_RTC_CLK) {
 643         /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
 644         cpu_ppc_tb_init(env, 7812500UL);
 645     } else {
 646         /* Set time-base frequency to 100 Mhz */
 647         cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
 648     }
 649     qemu_register_reset(ppc_prep_reset, cpu);
 650
 651     /* PCI host */
 652     dev = qdev_create(NULL, "raven-pcihost");
 653     if (!bios_name) {
 654         bios_name = "openbios-ppc";
 655     }
 656     qdev_prop_set_string(dev, "bios-name", bios_name);
 657     qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE);
 658     pcihost = SYS_BUS_DEVICE(dev);
 659     object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL);
 660     qdev_init_nofail(dev);
 661     pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0"));
 662     if (!pci_bus) {
 663         error_report("could not create PCI host controller");
 664         exit(1);
 665     }
 666
 667     /* PCI -> ISA bridge */
 668     i82378_dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(11, 0), "i82378"));
 669     qdev_connect_gpio_out(i82378_dev, 0,
 670                           cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
 671     sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(i82378_dev, 15));
 672     isa_bus = ISA_BUS(qdev_get_child_bus(i82378_dev, "isa.0"));
 673
 674     /* Memory controller */
 675     dev = DEVICE(isa_create(isa_bus, "rs6000-mc"));
 676     qdev_prop_set_uint32(dev, "ram-size", machine->ram_size);
 677     qdev_init_nofail(dev);
 678
 679     /* initialize CMOS checksums */
 680     cmos_checksum = 0x6aa9;
 681     qbus_walk_children(BUS(isa_bus), prep_set_cmos_checksum, NULL, NULL, NULL,
 682                        &cmos_checksum);
 683
 684     /* add some more devices */
 685     if (defaults_enabled()) {
 686         m48t59 = NVRAM(isa_create_simple(isa_bus, "isa-m48t59"));
 687
 688         dev = DEVICE(isa_create(isa_bus, "cs4231a"));
 689         qdev_prop_set_uint32(dev, "iobase", 0x830);
 690         qdev_prop_set_uint32(dev, "irq", 10);
 691         qdev_init_nofail(dev);
 692
 693         dev = DEVICE(isa_create(isa_bus, "pc87312"));
 694         qdev_prop_set_uint32(dev, "config", 12);
 695         qdev_init_nofail(dev);
 696
 697         dev = DEVICE(isa_create(isa_bus, "prep-systemio"));
 698         qdev_prop_set_uint32(dev, "ibm-planar-id", 0xfc);
 699         qdev_prop_set_uint32(dev, "equipment", 0xc0);
 700         qdev_init_nofail(dev);
 701
 702         dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(1, 0),
 703                                        "lsi53c810"));
 704         lsi53c8xx_handle_legacy_cmdline(dev);
 705         qdev_connect_gpio_out(dev, 0, qdev_get_gpio_in(i82378_dev, 13));
 706
 707         /* XXX: s3-trio at PCI_DEVFN(2, 0) */
 708         pci_vga_init(pci_bus);
 709
 710         for (i = 0; i < nb_nics; i++) {
 711             pci_nic_init_nofail(&nd_table[i], pci_bus, "pcnet",
 712                                 i == 0 ? "3" : NULL);
 713         }
 714     }
 715
 716     /* Prepare firmware configuration for OpenBIOS */
 717     dev = qdev_create(NULL, TYPE_FW_CFG_MEM);
 718     fw_cfg = FW_CFG(dev);
 719     qdev_prop_set_uint32(dev, "data_width", 1);
 720     qdev_prop_set_bit(dev, "dma_enabled", false);
 721     object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
 722                               OBJECT(fw_cfg), NULL);
 723     qdev_init_nofail(dev);
 724     s = SYS_BUS_DEVICE(dev);
 725     sysbus_mmio_map(s, 0, CFG_ADDR);
 726     sysbus_mmio_map(s, 1, CFG_ADDR + 2);
 727
 728     if (machine->kernel_filename) {
 729         /* load kernel */
 730         kernel_base = KERNEL_LOAD_ADDR;
 731         kernel_size = load_image_targphys(machine->kernel_filename,
 732                                           kernel_base,
 733                                           machine->ram_size - kernel_base);
 734         if (kernel_size < 0) {
 735             error_report("could not load kernel '%s'",
 736                          machine->kernel_filename);
 737             exit(1);
 738         }
 739         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
 740         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 741         /* load initrd */
 742         if (machine->initrd_filename) {
 743             initrd_base = INITRD_LOAD_ADDR;
 744             initrd_size = load_image_targphys(machine->initrd_filename,
 745                                               initrd_base,
 746                                               machine->ram_size - initrd_base);
 747             if (initrd_size < 0) {
 748                 error_report("could not load initial ram disk '%s'",
 749                              machine->initrd_filename);
 750                 exit(1);
 751             }
 752             fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
 753             fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 754         }
 755         if (machine->kernel_cmdline && *machine->kernel_cmdline) {
 756             fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
 757             pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
 758                              machine->kernel_cmdline);
 759             fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA,
 760                               machine->kernel_cmdline);
 761             fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
 762                            strlen(machine->kernel_cmdline) + 1);
 763         }
 764         boot_device = 'm';
 765     } else {
 766         boot_device = machine->boot_order[0];
 767     }
 768
 769     fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
 770     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
 771     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_PREP);
 772
 773     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
 774     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
 775     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
 776
 777     fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
 778     if (kvm_enabled()) {
 779 #ifdef CONFIG_KVM
 780         uint8_t *hypercall;
 781
 782         fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq());
 783         hypercall = g_malloc(16);
 784         kvmppc_get_hypercall(env, hypercall, 16);
 785         fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
 786         fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
 787 #endif
 788     } else {
 789         fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, NANOSECONDS_PER_SECOND);
 790     }
 791     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device);
 792     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 793
 794     /* Prepare firmware configuration for Open Hack'Ware */
 795     if (m48t59) {
 796         PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", ram_size,
 797                              boot_device,
 798                              kernel_base, kernel_size,
 799                              machine->kernel_cmdline,
 800                              initrd_base, initrd_size,
 801                              /* XXX: need an option to load a NVRAM image */
 802                              0,
 803                              graphic_width, graphic_height, graphic_depth);
 804     }
 805 }
 806
 807 static void ibm_40p_machine_init(MachineClass *mc)
 808 {
 809     mc->desc = "IBM RS/6000 7020 (40p)",
 810     mc->init = ibm_40p_init;
 811     mc->max_cpus = 1;
 812     mc->default_ram_size = 128 * MiB;
 813     mc->block_default_type = IF_SCSI;
 814     mc->default_boot_order = "c";
 815     mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("604");
 816     mc->default_display = "std";
 817 }
 818
 819 DEFINE_MACHINE("40p", ibm_40p_machine_init)
 820 DEFINE_MACHINE("prep", prep_machine_init)