3 #include "qemu/cutils.h"
5 typedef struct NvmeBar
{
27 CAP_MPSMIN_SHIFT
= 48,
28 CAP_MPSMAX_SHIFT
= 52,
32 CAP_MQES_MASK
= 0xffff,
39 CAP_MPSMIN_MASK
= 0xf,
40 CAP_MPSMAX_MASK
= 0xf,
43 #define NVME_CAP_MQES(cap) (((cap) >> CAP_MQES_SHIFT) & CAP_MQES_MASK)
44 #define NVME_CAP_CQR(cap) (((cap) >> CAP_CQR_SHIFT) & CAP_CQR_MASK)
45 #define NVME_CAP_AMS(cap) (((cap) >> CAP_AMS_SHIFT) & CAP_AMS_MASK)
46 #define NVME_CAP_TO(cap) (((cap) >> CAP_TO_SHIFT) & CAP_TO_MASK)
47 #define NVME_CAP_DSTRD(cap) (((cap) >> CAP_DSTRD_SHIFT) & CAP_DSTRD_MASK)
48 #define NVME_CAP_NSSRS(cap) (((cap) >> CAP_NSSRS_SHIFT) & CAP_NSSRS_MASK)
49 #define NVME_CAP_CSS(cap) (((cap) >> CAP_CSS_SHIFT) & CAP_CSS_MASK)
50 #define NVME_CAP_MPSMIN(cap)(((cap) >> CAP_MPSMIN_SHIFT) & CAP_MPSMIN_MASK)
51 #define NVME_CAP_MPSMAX(cap)(((cap) >> CAP_MPSMAX_SHIFT) & CAP_MPSMAX_MASK)
53 #define NVME_CAP_SET_MQES(cap, val) (cap |= (uint64_t)(val & CAP_MQES_MASK) \
55 #define NVME_CAP_SET_CQR(cap, val) (cap |= (uint64_t)(val & CAP_CQR_MASK) \
57 #define NVME_CAP_SET_AMS(cap, val) (cap |= (uint64_t)(val & CAP_AMS_MASK) \
59 #define NVME_CAP_SET_TO(cap, val) (cap |= (uint64_t)(val & CAP_TO_MASK) \
61 #define NVME_CAP_SET_DSTRD(cap, val) (cap |= (uint64_t)(val & CAP_DSTRD_MASK) \
63 #define NVME_CAP_SET_NSSRS(cap, val) (cap |= (uint64_t)(val & CAP_NSSRS_MASK) \
65 #define NVME_CAP_SET_CSS(cap, val) (cap |= (uint64_t)(val & CAP_CSS_MASK) \
67 #define NVME_CAP_SET_MPSMIN(cap, val) (cap |= (uint64_t)(val & CAP_MPSMIN_MASK)\
69 #define NVME_CAP_SET_MPSMAX(cap, val) (cap |= (uint64_t)(val & CAP_MPSMAX_MASK)\
92 #define NVME_CC_EN(cc) ((cc >> CC_EN_SHIFT) & CC_EN_MASK)
93 #define NVME_CC_CSS(cc) ((cc >> CC_CSS_SHIFT) & CC_CSS_MASK)
94 #define NVME_CC_MPS(cc) ((cc >> CC_MPS_SHIFT) & CC_MPS_MASK)
95 #define NVME_CC_AMS(cc) ((cc >> CC_AMS_SHIFT) & CC_AMS_MASK)
96 #define NVME_CC_SHN(cc) ((cc >> CC_SHN_SHIFT) & CC_SHN_MASK)
97 #define NVME_CC_IOSQES(cc) ((cc >> CC_IOSQES_SHIFT) & CC_IOSQES_MASK)
98 #define NVME_CC_IOCQES(cc) ((cc >> CC_IOCQES_SHIFT) & CC_IOCQES_MASK)
104 CSTS_NSSRO_SHIFT
= 4,
110 CSTS_SHST_MASK
= 0x3,
111 CSTS_NSSRO_MASK
= 0x1,
115 NVME_CSTS_READY
= 1 << CSTS_RDY_SHIFT
,
116 NVME_CSTS_FAILED
= 1 << CSTS_CFS_SHIFT
,
117 NVME_CSTS_SHST_NORMAL
= 0 << CSTS_SHST_SHIFT
,
118 NVME_CSTS_SHST_PROGRESS
= 1 << CSTS_SHST_SHIFT
,
119 NVME_CSTS_SHST_COMPLETE
= 2 << CSTS_SHST_SHIFT
,
120 NVME_CSTS_NSSRO
= 1 << CSTS_NSSRO_SHIFT
,
123 #define NVME_CSTS_RDY(csts) ((csts >> CSTS_RDY_SHIFT) & CSTS_RDY_MASK)
124 #define NVME_CSTS_CFS(csts) ((csts >> CSTS_CFS_SHIFT) & CSTS_CFS_MASK)
125 #define NVME_CSTS_SHST(csts) ((csts >> CSTS_SHST_SHIFT) & CSTS_SHST_MASK)
126 #define NVME_CSTS_NSSRO(csts) ((csts >> CSTS_NSSRO_SHIFT) & CSTS_NSSRO_MASK)
134 AQA_ASQS_MASK
= 0xfff,
135 AQA_ACQS_MASK
= 0xfff,
138 #define NVME_AQA_ASQS(aqa) ((aqa >> AQA_ASQS_SHIFT) & AQA_ASQS_MASK)
139 #define NVME_AQA_ACQS(aqa) ((aqa >> AQA_ACQS_SHIFT) & AQA_ACQS_MASK)
141 typedef struct NvmeCmd
{
158 enum NvmeAdminCommands
{
159 NVME_ADM_CMD_DELETE_SQ
= 0x00,
160 NVME_ADM_CMD_CREATE_SQ
= 0x01,
161 NVME_ADM_CMD_GET_LOG_PAGE
= 0x02,
162 NVME_ADM_CMD_DELETE_CQ
= 0x04,
163 NVME_ADM_CMD_CREATE_CQ
= 0x05,
164 NVME_ADM_CMD_IDENTIFY
= 0x06,
165 NVME_ADM_CMD_ABORT
= 0x08,
166 NVME_ADM_CMD_SET_FEATURES
= 0x09,
167 NVME_ADM_CMD_GET_FEATURES
= 0x0a,
168 NVME_ADM_CMD_ASYNC_EV_REQ
= 0x0c,
169 NVME_ADM_CMD_ACTIVATE_FW
= 0x10,
170 NVME_ADM_CMD_DOWNLOAD_FW
= 0x11,
171 NVME_ADM_CMD_FORMAT_NVM
= 0x80,
172 NVME_ADM_CMD_SECURITY_SEND
= 0x81,
173 NVME_ADM_CMD_SECURITY_RECV
= 0x82,
176 enum NvmeIoCommands
{
177 NVME_CMD_FLUSH
= 0x00,
178 NVME_CMD_WRITE
= 0x01,
179 NVME_CMD_READ
= 0x02,
180 NVME_CMD_WRITE_UNCOR
= 0x04,
181 NVME_CMD_COMPARE
= 0x05,
182 NVME_CMD_WRITE_ZEROS
= 0x08,
186 typedef struct NvmeDeleteQ
{
196 typedef struct NvmeCreateCq
{
210 #define NVME_CQ_FLAGS_PC(cq_flags) (cq_flags & 0x1)
211 #define NVME_CQ_FLAGS_IEN(cq_flags) ((cq_flags >> 1) & 0x1)
213 typedef struct NvmeCreateSq
{
227 #define NVME_SQ_FLAGS_PC(sq_flags) (sq_flags & 0x1)
228 #define NVME_SQ_FLAGS_QPRIO(sq_flags) ((sq_flags >> 1) & 0x3)
230 enum NvmeQueueFlags
{
232 NVME_Q_PRIO_URGENT
= 0,
233 NVME_Q_PRIO_HIGH
= 1,
234 NVME_Q_PRIO_NORMAL
= 2,
238 typedef struct NvmeIdentify
{
250 typedef struct NvmeRwCmd
{
269 NVME_RW_LR
= 1 << 15,
270 NVME_RW_FUA
= 1 << 14,
271 NVME_RW_DSM_FREQ_UNSPEC
= 0,
272 NVME_RW_DSM_FREQ_TYPICAL
= 1,
273 NVME_RW_DSM_FREQ_RARE
= 2,
274 NVME_RW_DSM_FREQ_READS
= 3,
275 NVME_RW_DSM_FREQ_WRITES
= 4,
276 NVME_RW_DSM_FREQ_RW
= 5,
277 NVME_RW_DSM_FREQ_ONCE
= 6,
278 NVME_RW_DSM_FREQ_PREFETCH
= 7,
279 NVME_RW_DSM_FREQ_TEMP
= 8,
280 NVME_RW_DSM_LATENCY_NONE
= 0 << 4,
281 NVME_RW_DSM_LATENCY_IDLE
= 1 << 4,
282 NVME_RW_DSM_LATENCY_NORM
= 2 << 4,
283 NVME_RW_DSM_LATENCY_LOW
= 3 << 4,
284 NVME_RW_DSM_SEQ_REQ
= 1 << 6,
285 NVME_RW_DSM_COMPRESSED
= 1 << 7,
286 NVME_RW_PRINFO_PRACT
= 1 << 13,
287 NVME_RW_PRINFO_PRCHK_GUARD
= 1 << 12,
288 NVME_RW_PRINFO_PRCHK_APP
= 1 << 11,
289 NVME_RW_PRINFO_PRCHK_REF
= 1 << 10,
292 typedef struct NvmeDsmCmd
{
306 NVME_DSMGMT_IDR
= 1 << 0,
307 NVME_DSMGMT_IDW
= 1 << 1,
308 NVME_DSMGMT_AD
= 1 << 2,
311 typedef struct NvmeDsmRange
{
317 enum NvmeAsyncEventRequest
{
318 NVME_AER_TYPE_ERROR
= 0,
319 NVME_AER_TYPE_SMART
= 1,
320 NVME_AER_TYPE_IO_SPECIFIC
= 6,
321 NVME_AER_TYPE_VENDOR_SPECIFIC
= 7,
322 NVME_AER_INFO_ERR_INVALID_SQ
= 0,
323 NVME_AER_INFO_ERR_INVALID_DB
= 1,
324 NVME_AER_INFO_ERR_DIAG_FAIL
= 2,
325 NVME_AER_INFO_ERR_PERS_INTERNAL_ERR
= 3,
326 NVME_AER_INFO_ERR_TRANS_INTERNAL_ERR
= 4,
327 NVME_AER_INFO_ERR_FW_IMG_LOAD_ERR
= 5,
328 NVME_AER_INFO_SMART_RELIABILITY
= 0,
329 NVME_AER_INFO_SMART_TEMP_THRESH
= 1,
330 NVME_AER_INFO_SMART_SPARE_THRESH
= 2,
333 typedef struct NvmeAerResult
{
340 typedef struct NvmeCqe
{
349 enum NvmeStatusCodes
{
350 NVME_SUCCESS
= 0x0000,
351 NVME_INVALID_OPCODE
= 0x0001,
352 NVME_INVALID_FIELD
= 0x0002,
353 NVME_CID_CONFLICT
= 0x0003,
354 NVME_DATA_TRAS_ERROR
= 0x0004,
355 NVME_POWER_LOSS_ABORT
= 0x0005,
356 NVME_INTERNAL_DEV_ERROR
= 0x0006,
357 NVME_CMD_ABORT_REQ
= 0x0007,
358 NVME_CMD_ABORT_SQ_DEL
= 0x0008,
359 NVME_CMD_ABORT_FAILED_FUSE
= 0x0009,
360 NVME_CMD_ABORT_MISSING_FUSE
= 0x000a,
361 NVME_INVALID_NSID
= 0x000b,
362 NVME_CMD_SEQ_ERROR
= 0x000c,
363 NVME_LBA_RANGE
= 0x0080,
364 NVME_CAP_EXCEEDED
= 0x0081,
365 NVME_NS_NOT_READY
= 0x0082,
366 NVME_NS_RESV_CONFLICT
= 0x0083,
367 NVME_INVALID_CQID
= 0x0100,
368 NVME_INVALID_QID
= 0x0101,
369 NVME_MAX_QSIZE_EXCEEDED
= 0x0102,
370 NVME_ACL_EXCEEDED
= 0x0103,
371 NVME_RESERVED
= 0x0104,
372 NVME_AER_LIMIT_EXCEEDED
= 0x0105,
373 NVME_INVALID_FW_SLOT
= 0x0106,
374 NVME_INVALID_FW_IMAGE
= 0x0107,
375 NVME_INVALID_IRQ_VECTOR
= 0x0108,
376 NVME_INVALID_LOG_ID
= 0x0109,
377 NVME_INVALID_FORMAT
= 0x010a,
378 NVME_FW_REQ_RESET
= 0x010b,
379 NVME_INVALID_QUEUE_DEL
= 0x010c,
380 NVME_FID_NOT_SAVEABLE
= 0x010d,
381 NVME_FID_NOT_NSID_SPEC
= 0x010f,
382 NVME_FW_REQ_SUSYSTEM_RESET
= 0x0110,
383 NVME_CONFLICTING_ATTRS
= 0x0180,
384 NVME_INVALID_PROT_INFO
= 0x0181,
385 NVME_WRITE_TO_RO
= 0x0182,
386 NVME_WRITE_FAULT
= 0x0280,
387 NVME_UNRECOVERED_READ
= 0x0281,
388 NVME_E2E_GUARD_ERROR
= 0x0282,
389 NVME_E2E_APP_ERROR
= 0x0283,
390 NVME_E2E_REF_ERROR
= 0x0284,
391 NVME_CMP_FAILURE
= 0x0285,
392 NVME_ACCESS_DENIED
= 0x0286,
395 NVME_NO_COMPLETE
= 0xffff,
398 typedef struct NvmeFwSlotInfoLog
{
400 uint8_t reserved1
[7];
408 uint8_t reserved2
[448];
411 typedef struct NvmeErrorLog
{
412 uint64_t error_count
;
415 uint16_t status_field
;
416 uint16_t param_error_location
;
423 typedef struct NvmeSmartLog
{
424 uint8_t critical_warning
;
425 uint8_t temperature
[2];
426 uint8_t available_spare
;
427 uint8_t available_spare_threshold
;
428 uint8_t percentage_used
;
429 uint8_t reserved1
[26];
430 uint64_t data_units_read
[2];
431 uint64_t data_units_written
[2];
432 uint64_t host_read_commands
[2];
433 uint64_t host_write_commands
[2];
434 uint64_t controller_busy_time
[2];
435 uint64_t power_cycles
[2];
436 uint64_t power_on_hours
[2];
437 uint64_t unsafe_shutdowns
[2];
438 uint64_t media_errors
[2];
439 uint64_t number_of_error_log_entries
[2];
440 uint8_t reserved2
[320];
444 NVME_SMART_SPARE
= 1 << 0,
445 NVME_SMART_TEMPERATURE
= 1 << 1,
446 NVME_SMART_RELIABILITY
= 1 << 2,
447 NVME_SMART_MEDIA_READ_ONLY
= 1 << 3,
448 NVME_SMART_FAILED_VOLATILE_MEDIA
= 1 << 4,
452 NVME_LOG_ERROR_INFO
= 0x01,
453 NVME_LOG_SMART_INFO
= 0x02,
454 NVME_LOG_FW_SLOT_INFO
= 0x03,
457 typedef struct NvmePSD
{
469 typedef struct NvmeIdCtrl
{
479 uint8_t rsvd255
[178];
487 uint8_t rsvd511
[248];
498 uint8_t rsvd703
[174];
499 uint8_t rsvd2047
[1344];
504 enum NvmeIdCtrlOacs
{
505 NVME_OACS_SECURITY
= 1 << 0,
506 NVME_OACS_FORMAT
= 1 << 1,
507 NVME_OACS_FW
= 1 << 2,
510 enum NvmeIdCtrlOncs
{
511 NVME_ONCS_COMPARE
= 1 << 0,
512 NVME_ONCS_WRITE_UNCORR
= 1 << 1,
513 NVME_ONCS_DSM
= 1 << 2,
514 NVME_ONCS_WRITE_ZEROS
= 1 << 3,
515 NVME_ONCS_FEATURES
= 1 << 4,
516 NVME_ONCS_RESRVATIONS
= 1 << 5,
519 #define NVME_CTRL_SQES_MIN(sqes) ((sqes) & 0xf)
520 #define NVME_CTRL_SQES_MAX(sqes) (((sqes) >> 4) & 0xf)
521 #define NVME_CTRL_CQES_MIN(cqes) ((cqes) & 0xf)
522 #define NVME_CTRL_CQES_MAX(cqes) (((cqes) >> 4) & 0xf)
524 typedef struct NvmeFeatureVal
{
525 uint32_t arbitration
;
527 uint32_t temp_thresh
;
529 uint32_t volatile_wc
;
531 uint32_t int_coalescing
;
532 uint32_t *int_vector_config
;
533 uint32_t write_atomicity
;
534 uint32_t async_config
;
535 uint32_t sw_prog_marker
;
538 #define NVME_ARB_AB(arb) (arb & 0x7)
539 #define NVME_ARB_LPW(arb) ((arb >> 8) & 0xff)
540 #define NVME_ARB_MPW(arb) ((arb >> 16) & 0xff)
541 #define NVME_ARB_HPW(arb) ((arb >> 24) & 0xff)
543 #define NVME_INTC_THR(intc) (intc & 0xff)
544 #define NVME_INTC_TIME(intc) ((intc >> 8) & 0xff)
546 enum NvmeFeatureIds
{
547 NVME_ARBITRATION
= 0x1,
548 NVME_POWER_MANAGEMENT
= 0x2,
549 NVME_LBA_RANGE_TYPE
= 0x3,
550 NVME_TEMPERATURE_THRESHOLD
= 0x4,
551 NVME_ERROR_RECOVERY
= 0x5,
552 NVME_VOLATILE_WRITE_CACHE
= 0x6,
553 NVME_NUMBER_OF_QUEUES
= 0x7,
554 NVME_INTERRUPT_COALESCING
= 0x8,
555 NVME_INTERRUPT_VECTOR_CONF
= 0x9,
556 NVME_WRITE_ATOMICITY
= 0xa,
557 NVME_ASYNCHRONOUS_EVENT_CONF
= 0xb,
558 NVME_SOFTWARE_PROGRESS_MARKER
= 0x80
561 typedef struct NvmeRangeType
{
571 typedef struct NvmeLBAF
{
577 typedef struct NvmeIdNs
{
593 #define NVME_ID_NS_NSFEAT_THIN(nsfeat) ((nsfeat & 0x1))
594 #define NVME_ID_NS_FLBAS_EXTENDED(flbas) ((flbas >> 4) & 0x1)
595 #define NVME_ID_NS_FLBAS_INDEX(flbas) ((flbas & 0xf))
596 #define NVME_ID_NS_MC_SEPARATE(mc) ((mc >> 1) & 0x1)
597 #define NVME_ID_NS_MC_EXTENDED(mc) ((mc & 0x1))
598 #define NVME_ID_NS_DPC_LAST_EIGHT(dpc) ((dpc >> 4) & 0x1)
599 #define NVME_ID_NS_DPC_FIRST_EIGHT(dpc) ((dpc >> 3) & 0x1)
600 #define NVME_ID_NS_DPC_TYPE_3(dpc) ((dpc >> 2) & 0x1)
601 #define NVME_ID_NS_DPC_TYPE_2(dpc) ((dpc >> 1) & 0x1)
602 #define NVME_ID_NS_DPC_TYPE_1(dpc) ((dpc & 0x1))
603 #define NVME_ID_NS_DPC_TYPE_MASK 0x7
614 static inline void _nvme_check_size(void)
616 QEMU_BUILD_BUG_ON(sizeof(NvmeAerResult
) != 4);
617 QEMU_BUILD_BUG_ON(sizeof(NvmeCqe
) != 16);
618 QEMU_BUILD_BUG_ON(sizeof(NvmeDsmRange
) != 16);
619 QEMU_BUILD_BUG_ON(sizeof(NvmeCmd
) != 64);
620 QEMU_BUILD_BUG_ON(sizeof(NvmeDeleteQ
) != 64);
621 QEMU_BUILD_BUG_ON(sizeof(NvmeCreateCq
) != 64);
622 QEMU_BUILD_BUG_ON(sizeof(NvmeCreateSq
) != 64);
623 QEMU_BUILD_BUG_ON(sizeof(NvmeIdentify
) != 64);
624 QEMU_BUILD_BUG_ON(sizeof(NvmeRwCmd
) != 64);
625 QEMU_BUILD_BUG_ON(sizeof(NvmeDsmCmd
) != 64);
626 QEMU_BUILD_BUG_ON(sizeof(NvmeRangeType
) != 64);
627 QEMU_BUILD_BUG_ON(sizeof(NvmeErrorLog
) != 64);
628 QEMU_BUILD_BUG_ON(sizeof(NvmeFwSlotInfoLog
) != 512);
629 QEMU_BUILD_BUG_ON(sizeof(NvmeSmartLog
) != 512);
630 QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrl
) != 4096);
631 QEMU_BUILD_BUG_ON(sizeof(NvmeIdNs
) != 4096);
634 typedef struct NvmeAsyncEvent
{
635 QSIMPLEQ_ENTRY(NvmeAsyncEvent
) entry
;
636 NvmeAerResult result
;
639 typedef struct NvmeRequest
{
640 struct NvmeSQueue
*sq
;
645 BlockAcctCookie acct
;
647 QTAILQ_ENTRY(NvmeRequest
)entry
;
650 typedef struct NvmeSQueue
{
651 struct NvmeCtrl
*ctrl
;
660 QTAILQ_HEAD(sq_req_list
, NvmeRequest
) req_list
;
661 QTAILQ_HEAD(out_req_list
, NvmeRequest
) out_req_list
;
662 QTAILQ_ENTRY(NvmeSQueue
) entry
;
665 typedef struct NvmeCQueue
{
666 struct NvmeCtrl
*ctrl
;
669 uint16_t irq_enabled
;
676 QTAILQ_HEAD(sq_list
, NvmeSQueue
) sq_list
;
677 QTAILQ_HEAD(cq_req_list
, NvmeRequest
) req_list
;
680 typedef struct NvmeNamespace
{
684 #define TYPE_NVME "nvme"
686 OBJECT_CHECK(NvmeCtrl, (obj), TYPE_NVME)
688 typedef struct NvmeCtrl
{
689 PCIDevice parent_obj
;
696 uint16_t max_prp_ents
;
700 uint32_t num_namespaces
;
706 NvmeNamespace
*namespaces
;
714 #endif /* HW_NVME_H */