dma.h

   1 /*
   2  * DMA helper functions
   3  *
   4  * Copyright (c) 2009 Red Hat
   5  *
   6  * This work is licensed under the terms of the GNU General Public License
   7  * (GNU GPL), version 2 or later.
   8  */
   9
  10 #ifndef DMA_H
  11 #define DMA_H
  12
  13 #include <stdio.h>
  14 #include "hw/hw.h"
  15 #include "block.h"
  16
  17 typedef struct DMAContext DMAContext;
  18 typedef struct ScatterGatherEntry ScatterGatherEntry;
  19
  20 typedef enum {
  21     DMA_DIRECTION_TO_DEVICE = 0,
  22     DMA_DIRECTION_FROM_DEVICE = 1,
  23 } DMADirection;
  24
  25 struct QEMUSGList {
  26     ScatterGatherEntry *sg;
  27     int nsg;
  28     int nalloc;
  29     size_t size;
  30     DMAContext *dma;
  31 };
  32
  33 #if defined(TARGET_PHYS_ADDR_BITS)
  34
  35 /*
  36  * When an IOMMU is present, bus addresses become distinct from
  37  * CPU/memory physical addresses and may be a different size.  Because
  38  * the IOVA size depends more on the bus than on the platform, we more
  39  * or less have to treat these as 64-bit always to cover all (or at
  40  * least most) cases.
  41  */
  42 typedef uint64_t dma_addr_t;
  43
  44 #define DMA_ADDR_BITS 64
  45 #define DMA_ADDR_FMT "%" PRIx64
  46
  47 typedef int DMATranslateFunc(DMAContext *dma,
  48                              dma_addr_t addr,
  49                              target_phys_addr_t *paddr,
  50                              target_phys_addr_t *len,
  51                              DMADirection dir);
  52 typedef void* DMAMapFunc(DMAContext *dma,
  53                          dma_addr_t addr,
  54                          dma_addr_t *len,
  55                          DMADirection dir);
  56 typedef void DMAUnmapFunc(DMAContext *dma,
  57                           void *buffer,
  58                           dma_addr_t len,
  59                           DMADirection dir,
  60                           dma_addr_t access_len);
  61
  62 struct DMAContext {
  63     DMATranslateFunc *translate;
  64     DMAMapFunc *map;
  65     DMAUnmapFunc *unmap;
  66 };
  67
  68 static inline bool dma_has_iommu(DMAContext *dma)
  69 {
  70     return !!dma;
  71 }
  72
  73 /* Checks that the given range of addresses is valid for DMA.  This is
  74  * useful for certain cases, but usually you should just use
  75  * dma_memory_{read,write}() and check for errors */
  76 bool iommu_dma_memory_valid(DMAContext *dma, dma_addr_t addr, dma_addr_t len,
  77                             DMADirection dir);
  78 static inline bool dma_memory_valid(DMAContext *dma,
  79                                     dma_addr_t addr, dma_addr_t len,
  80                                     DMADirection dir)
  81 {
  82     if (!dma_has_iommu(dma)) {
  83         return true;
  84     } else {
  85         return iommu_dma_memory_valid(dma, addr, len, dir);
  86     }
  87 }
  88
  89 int iommu_dma_memory_rw(DMAContext *dma, dma_addr_t addr,
  90                         void *buf, dma_addr_t len, DMADirection dir);
  91 static inline int dma_memory_rw(DMAContext *dma, dma_addr_t addr,
  92                                 void *buf, dma_addr_t len, DMADirection dir)
  93 {
  94     if (!dma_has_iommu(dma)) {
  95         /* Fast-path for no IOMMU */
  96         cpu_physical_memory_rw(addr, buf, len,
  97                                dir == DMA_DIRECTION_FROM_DEVICE);
  98         return 0;
  99     } else {
 100         return iommu_dma_memory_rw(dma, addr, buf, len, dir);
 101     }
 102 }
 103
 104 static inline int dma_memory_read(DMAContext *dma, dma_addr_t addr,
 105                                   void *buf, dma_addr_t len)
 106 {
 107     return dma_memory_rw(dma, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
 108 }
 109
 110 static inline int dma_memory_write(DMAContext *dma, dma_addr_t addr,
 111                                    const void *buf, dma_addr_t len)
 112 {
 113     return dma_memory_rw(dma, addr, (void *)buf, len,
 114                          DMA_DIRECTION_FROM_DEVICE);
 115 }
 116
 117 int iommu_dma_memory_set(DMAContext *dma, dma_addr_t addr, uint8_t c,
 118                          dma_addr_t len);
 119
 120 int dma_memory_set(DMAContext *dma, dma_addr_t addr, uint8_t c, dma_addr_t len);
 121
 122 void *iommu_dma_memory_map(DMAContext *dma,
 123                            dma_addr_t addr, dma_addr_t *len,
 124                            DMADirection dir);
 125 static inline void *dma_memory_map(DMAContext *dma,
 126                                    dma_addr_t addr, dma_addr_t *len,
 127                                    DMADirection dir)
 128 {
 129     if (!dma_has_iommu(dma)) {
 130         target_phys_addr_t xlen = *len;
 131         void *p;
 132
 133         p = cpu_physical_memory_map(addr, &xlen,
 134                                     dir == DMA_DIRECTION_FROM_DEVICE);
 135         *len = xlen;
 136         return p;
 137     } else {
 138         return iommu_dma_memory_map(dma, addr, len, dir);
 139     }
 140 }
 141
 142 void iommu_dma_memory_unmap(DMAContext *dma,
 143                             void *buffer, dma_addr_t len,
 144                             DMADirection dir, dma_addr_t access_len);
 145 static inline void dma_memory_unmap(DMAContext *dma,
 146                                     void *buffer, dma_addr_t len,
 147                                     DMADirection dir, dma_addr_t access_len)
 148 {
 149     if (!dma_has_iommu(dma)) {
 150         return cpu_physical_memory_unmap(buffer, (target_phys_addr_t)len,
 151                                          dir == DMA_DIRECTION_FROM_DEVICE,
 152                                          access_len);
 153     } else {
 154         iommu_dma_memory_unmap(dma, buffer, len, dir, access_len);
 155     }
 156 }
 157
 158 #define DEFINE_LDST_DMA(_lname, _sname, _bits, _end) \
 159     static inline uint##_bits##_t ld##_lname##_##_end##_dma(DMAContext *dma, \
 160                                                             dma_addr_t addr) \
 161     {                                                                   \
 162         uint##_bits##_t val;                                            \
 163         dma_memory_read(dma, addr, &val, (_bits) / 8);                  \
 164         return _end##_bits##_to_cpu(val);                               \
 165     }                                                                   \
 166     static inline void st##_sname##_##_end##_dma(DMAContext *dma,       \
 167                                                  dma_addr_t addr,       \
 168                                                  uint##_bits##_t val)   \
 169     {                                                                   \
 170         val = cpu_to_##_end##_bits(val);                                \
 171         dma_memory_write(dma, addr, &val, (_bits) / 8);                 \
 172     }
 173
 174 static inline uint8_t ldub_dma(DMAContext *dma, dma_addr_t addr)
 175 {
 176     uint8_t val;
 177
 178     dma_memory_read(dma, addr, &val, 1);
 179     return val;
 180 }
 181
 182 static inline void stb_dma(DMAContext *dma, dma_addr_t addr, uint8_t val)
 183 {
 184     dma_memory_write(dma, addr, &val, 1);
 185 }
 186
 187 DEFINE_LDST_DMA(uw, w, 16, le);
 188 DEFINE_LDST_DMA(l, l, 32, le);
 189 DEFINE_LDST_DMA(q, q, 64, le);
 190 DEFINE_LDST_DMA(uw, w, 16, be);
 191 DEFINE_LDST_DMA(l, l, 32, be);
 192 DEFINE_LDST_DMA(q, q, 64, be);
 193
 194 #undef DEFINE_LDST_DMA
 195
 196 void dma_context_init(DMAContext *dma, DMATranslateFunc translate,
 197                       DMAMapFunc map, DMAUnmapFunc unmap);
 198
 199 struct ScatterGatherEntry {
 200     dma_addr_t base;
 201     dma_addr_t len;
 202 };
 203
 204 void qemu_sglist_init(QEMUSGList *qsg, int alloc_hint, DMAContext *dma);
 205 void qemu_sglist_add(QEMUSGList *qsg, dma_addr_t base, dma_addr_t len);
 206 void qemu_sglist_destroy(QEMUSGList *qsg);
 207 #endif
 208
 209 typedef BlockDriverAIOCB *DMAIOFunc(BlockDriverState *bs, int64_t sector_num,
 210                                  QEMUIOVector *iov, int nb_sectors,
 211                                  BlockDriverCompletionFunc *cb, void *opaque);
 212
 213 BlockDriverAIOCB *dma_bdrv_io(BlockDriverState *bs,
 214                               QEMUSGList *sg, uint64_t sector_num,
 215                               DMAIOFunc *io_func, BlockDriverCompletionFunc *cb,
 216                               void *opaque, DMADirection dir);
 217 BlockDriverAIOCB *dma_bdrv_read(BlockDriverState *bs,
 218                                 QEMUSGList *sg, uint64_t sector,
 219                                 BlockDriverCompletionFunc *cb, void *opaque);
 220 BlockDriverAIOCB *dma_bdrv_write(BlockDriverState *bs,
 221                                  QEMUSGList *sg, uint64_t sector,
 222                                  BlockDriverCompletionFunc *cb, void *opaque);
 223 uint64_t dma_buf_read(uint8_t *ptr, int32_t len, QEMUSGList *sg);
 224 uint64_t dma_buf_write(uint8_t *ptr, int32_t len, QEMUSGList *sg);
 225
 226 void dma_acct_start(BlockDriverState *bs, BlockAcctCookie *cookie,
 227                     QEMUSGList *sg, enum BlockAcctType type);
 228
 229 #endif