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Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2019-12-17' into...
[qemu/ar7.git] / hw / arm / virt-acpi-build.c
blobbd5f771e9be3a6ed955dc1cba1ee4a579d88f222
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * ARM virt ACPI generation
4 *
5 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
6 * Copyright (C) 2006 Fabrice Bellard
7 * Copyright (C) 2013 Red Hat Inc
8 *
9 * Author: Michael S. Tsirkin <mst@redhat.com>
10 *
11 * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD.
12 *
13 * Author: Shannon Zhao <zhaoshenglong@huawei.com>
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, see <http://www.gnu.org/licenses/>.
27 */
28
29 #include "qemu/osdep.h"
30 #include "qapi/error.h"
31 #include "qemu/bitmap.h"
32 #include "trace.h"
33 #include "hw/core/cpu.h"
34 #include "target/arm/cpu.h"
35 #include "hw/acpi/acpi-defs.h"
36 #include "hw/acpi/acpi.h"
37 #include "hw/nvram/fw_cfg.h"
38 #include "hw/acpi/bios-linker-loader.h"
39 #include "hw/acpi/aml-build.h"
40 #include "hw/acpi/utils.h"
41 #include "hw/acpi/pci.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "hw/acpi/generic_event_device.h"
44 #include "hw/pci/pcie_host.h"
45 #include "hw/pci/pci.h"
46 #include "hw/arm/virt.h"
47 #include "sysemu/numa.h"
48 #include "sysemu/reset.h"
49 #include "kvm_arm.h"
50 #include "migration/vmstate.h"
51
52 #define ARM_SPI_BASE 32
53
54 static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus)
55 {
56 uint16_t i;
57
58 for (i = 0; i < smp_cpus; i++) {
59 Aml *dev = aml_device("C%.03X", i);
60 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007")));
61 aml_append(dev, aml_name_decl("_UID", aml_int(i)));
62 aml_append(scope, dev);
63 }
64 }
65
66 static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
67 uint32_t uart_irq)
68 {
69 Aml *dev = aml_device("COM0");
70 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011")));
71 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
72
73 Aml *crs = aml_resource_template();
74 aml_append(crs, aml_memory32_fixed(uart_memmap->base,
75 uart_memmap->size, AML_READ_WRITE));
76 aml_append(crs,
77 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
78 AML_EXCLUSIVE, &uart_irq, 1));
79 aml_append(dev, aml_name_decl("_CRS", crs));
80
81 /* The _ADR entry is used to link this device to the UART described
82 * in the SPCR table, i.e. SPCR.base_address.address == _ADR.
83 */
84 aml_append(dev, aml_name_decl("_ADR", aml_int(uart_memmap->base)));
85
86 aml_append(scope, dev);
87 }
88
89 static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap)
90 {
91 Aml *dev = aml_device("FWCF");
92 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
93 /* device present, functioning, decoding, not shown in UI */
94 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
95 aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
96
97 Aml *crs = aml_resource_template();
98 aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base,
99 fw_cfg_memmap->size, AML_READ_WRITE));
100 aml_append(dev, aml_name_decl("_CRS", crs));
101 aml_append(scope, dev);
102 }
103
104 static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap)
105 {
106 Aml *dev, *crs;
107 hwaddr base = flash_memmap->base;
108 hwaddr size = flash_memmap->size / 2;
109
110 dev = aml_device("FLS0");
111 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
112 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
113
114 crs = aml_resource_template();
115 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
116 aml_append(dev, aml_name_decl("_CRS", crs));
117 aml_append(scope, dev);
118
119 dev = aml_device("FLS1");
120 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
121 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
122 crs = aml_resource_template();
123 aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE));
124 aml_append(dev, aml_name_decl("_CRS", crs));
125 aml_append(scope, dev);
126 }
127
128 static void acpi_dsdt_add_virtio(Aml *scope,
129 const MemMapEntry *virtio_mmio_memmap,
130 uint32_t mmio_irq, int num)
131 {
132 hwaddr base = virtio_mmio_memmap->base;
133 hwaddr size = virtio_mmio_memmap->size;
134 int i;
135
136 for (i = 0; i < num; i++) {
137 uint32_t irq = mmio_irq + i;
138 Aml *dev = aml_device("VR%02u", i);
139 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
140 aml_append(dev, aml_name_decl("_UID", aml_int(i)));
141 aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
142
143 Aml *crs = aml_resource_template();
144 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
145 aml_append(crs,
146 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
147 AML_EXCLUSIVE, &irq, 1));
148 aml_append(dev, aml_name_decl("_CRS", crs));
149 aml_append(scope, dev);
150 base += size;
151 }
152 }
153
154 static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
155 uint32_t irq, bool use_highmem, bool highmem_ecam)
156 {
157 int ecam_id = VIRT_ECAM_ID(highmem_ecam);
158 Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf;
159 int i, bus_no;
160 hwaddr base_mmio = memmap[VIRT_PCIE_MMIO].base;
161 hwaddr size_mmio = memmap[VIRT_PCIE_MMIO].size;
162 hwaddr base_pio = memmap[VIRT_PCIE_PIO].base;
163 hwaddr size_pio = memmap[VIRT_PCIE_PIO].size;
164 hwaddr base_ecam = memmap[ecam_id].base;
165 hwaddr size_ecam = memmap[ecam_id].size;
166 int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
167
168 Aml *dev = aml_device("%s", "PCI0");
169 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
170 aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
171 aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
172 aml_append(dev, aml_name_decl("_BBN", aml_int(0)));
173 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
174 aml_append(dev, aml_name_decl("_UID", aml_string("PCI0")));
175 aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device")));
176 aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
177
178 /* Declare the PCI Routing Table. */
179 Aml *rt_pkg = aml_varpackage(nr_pcie_buses * PCI_NUM_PINS);
180 for (bus_no = 0; bus_no < nr_pcie_buses; bus_no++) {
181 for (i = 0; i < PCI_NUM_PINS; i++) {
182 int gsi = (i + bus_no) % PCI_NUM_PINS;
183 Aml *pkg = aml_package(4);
184 aml_append(pkg, aml_int((bus_no << 16) | 0xFFFF));
185 aml_append(pkg, aml_int(i));
186 aml_append(pkg, aml_name("GSI%d", gsi));
187 aml_append(pkg, aml_int(0));
188 aml_append(rt_pkg, pkg);
189 }
190 }
191 aml_append(dev, aml_name_decl("_PRT", rt_pkg));
192
193 /* Create GSI link device */
194 for (i = 0; i < PCI_NUM_PINS; i++) {
195 uint32_t irqs = irq + i;
196 Aml *dev_gsi = aml_device("GSI%d", i);
197 aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F")));
198 aml_append(dev_gsi, aml_name_decl("_UID", aml_int(0)));
199 crs = aml_resource_template();
200 aml_append(crs,
201 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
202 AML_EXCLUSIVE, &irqs, 1));
203 aml_append(dev_gsi, aml_name_decl("_PRS", crs));
204 crs = aml_resource_template();
205 aml_append(crs,
206 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
207 AML_EXCLUSIVE, &irqs, 1));
208 aml_append(dev_gsi, aml_name_decl("_CRS", crs));
209 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
210 aml_append(dev_gsi, method);
211 aml_append(dev, dev_gsi);
212 }
213
214 method = aml_method("_CBA", 0, AML_NOTSERIALIZED);
215 aml_append(method, aml_return(aml_int(base_ecam)));
216 aml_append(dev, method);
217
218 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
219 Aml *rbuf = aml_resource_template();
220 aml_append(rbuf,
221 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
222 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000,
223 nr_pcie_buses));
224 aml_append(rbuf,
225 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
226 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_mmio,
227 base_mmio + size_mmio - 1, 0x0000, size_mmio));
228 aml_append(rbuf,
229 aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
230 AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_pio,
231 size_pio));
232
233 if (use_highmem) {
234 hwaddr base_mmio_high = memmap[VIRT_HIGH_PCIE_MMIO].base;
235 hwaddr size_mmio_high = memmap[VIRT_HIGH_PCIE_MMIO].size;
236
237 aml_append(rbuf,
238 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
239 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
240 base_mmio_high,
241 base_mmio_high + size_mmio_high - 1, 0x0000,
242 size_mmio_high));
243 }
244
245 aml_append(method, aml_name_decl("RBUF", rbuf));
246 aml_append(method, aml_return(rbuf));
247 aml_append(dev, method);
248
249 /* Declare an _OSC (OS Control Handoff) method */
250 aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
251 aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
252 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
253 aml_append(method,
254 aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
255
256 /* PCI Firmware Specification 3.0
257 * 4.5.1. _OSC Interface for PCI Host Bridge Devices
258 * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is
259 * identified by the Universal Unique IDentifier (UUID)
260 * 33DB4D5B-1FF7-401C-9657-7441C03DD766
261 */
262 UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766");
263 ifctx = aml_if(aml_equal(aml_arg(0), UUID));
264 aml_append(ifctx,
265 aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
266 aml_append(ifctx,
267 aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
268 aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
269 aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL")));
270
271 /*
272 * Allow OS control for all 5 features:
273 * PCIeHotplug SHPCHotplug PME AER PCIeCapability.
274 */
275 aml_append(ifctx, aml_and(aml_name("CTRL"), aml_int(0x1F),
276 aml_name("CTRL")));
277
278 ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1))));
279 aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x08),
280 aml_name("CDW1")));
281 aml_append(ifctx, ifctx1);
282
283 ifctx1 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL"))));
284 aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x10),
285 aml_name("CDW1")));
286 aml_append(ifctx, ifctx1);
287
288 aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3")));
289 aml_append(ifctx, aml_return(aml_arg(3)));
290 aml_append(method, ifctx);
291
292 elsectx = aml_else();
293 aml_append(elsectx, aml_or(aml_name("CDW1"), aml_int(4),
294 aml_name("CDW1")));
295 aml_append(elsectx, aml_return(aml_arg(3)));
296 aml_append(method, elsectx);
297 aml_append(dev, method);
298
299 method = aml_method("_DSM", 4, AML_NOTSERIALIZED);
300
301 /* PCI Firmware Specification 3.0
302 * 4.6.1. _DSM for PCI Express Slot Information
303 * The UUID in _DSM in this context is
304 * {E5C937D0-3553-4D7A-9117-EA4D19C3434D}
305 */
306 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
307 ifctx = aml_if(aml_equal(aml_arg(0), UUID));
308 ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
309 uint8_t byte_list[1] = {1};
310 buf = aml_buffer(1, byte_list);
311 aml_append(ifctx1, aml_return(buf));
312 aml_append(ifctx, ifctx1);
313 aml_append(method, ifctx);
314
315 byte_list[0] = 0;
316 buf = aml_buffer(1, byte_list);
317 aml_append(method, aml_return(buf));
318 aml_append(dev, method);
319
320 Aml *dev_rp0 = aml_device("%s", "RP0");
321 aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0)));
322 aml_append(dev, dev_rp0);
323
324 Aml *dev_res0 = aml_device("%s", "RES0");
325 aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02")));
326 crs = aml_resource_template();
327 aml_append(crs,
328 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
329 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_ecam,
330 base_ecam + size_ecam - 1, 0x0000, size_ecam));
331 aml_append(dev_res0, aml_name_decl("_CRS", crs));
332 aml_append(dev, dev_res0);
333 aml_append(scope, dev);
334 }
335
336 static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap,
337 uint32_t gpio_irq)
338 {
339 Aml *dev = aml_device("GPO0");
340 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061")));
341 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
342 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
343
344 Aml *crs = aml_resource_template();
345 aml_append(crs, aml_memory32_fixed(gpio_memmap->base, gpio_memmap->size,
346 AML_READ_WRITE));
347 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
348 AML_EXCLUSIVE, &gpio_irq, 1));
349 aml_append(dev, aml_name_decl("_CRS", crs));
350
351 Aml *aei = aml_resource_template();
352 /* Pin 3 for power button */
353 const uint32_t pin_list[1] = {3};
354 aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH,
355 AML_EXCLUSIVE, AML_PULL_UP, 0, pin_list, 1,
356 "GPO0", NULL, 0));
357 aml_append(dev, aml_name_decl("_AEI", aei));
358
359 /* _E03 is handle for power button */
360 Aml *method = aml_method("_E03", 0, AML_NOTSERIALIZED);
361 aml_append(method, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE),
362 aml_int(0x80)));
363 aml_append(dev, method);
364 aml_append(scope, dev);
365 }
366
367 static void acpi_dsdt_add_power_button(Aml *scope)
368 {
369 Aml *dev = aml_device(ACPI_POWER_BUTTON_DEVICE);
370 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C0C")));
371 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
372 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
373 aml_append(scope, dev);
374 }
375
376 static void
377 build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
378 {
379 int nb_nodes, iort_start = table_data->len;
380 AcpiIortIdMapping *idmap;
381 AcpiIortItsGroup *its;
382 AcpiIortTable *iort;
383 AcpiIortSmmu3 *smmu;
384 size_t node_size, iort_node_offset, iort_length, smmu_offset = 0;
385 AcpiIortRC *rc;
386
387 iort = acpi_data_push(table_data, sizeof(*iort));
388
389 if (vms->iommu == VIRT_IOMMU_SMMUV3) {
390 nb_nodes = 3; /* RC, ITS, SMMUv3 */
391 } else {
392 nb_nodes = 2; /* RC, ITS */
393 }
394
395 iort_length = sizeof(*iort);
396 iort->node_count = cpu_to_le32(nb_nodes);
397 /*
398 * Use a copy in case table_data->data moves during acpi_data_push
399 * operations.
400 */
401 iort_node_offset = sizeof(*iort);
402 iort->node_offset = cpu_to_le32(iort_node_offset);
403
404 /* ITS group node */
405 node_size = sizeof(*its) + sizeof(uint32_t);
406 iort_length += node_size;
407 its = acpi_data_push(table_data, node_size);
408
409 its->type = ACPI_IORT_NODE_ITS_GROUP;
410 its->length = cpu_to_le16(node_size);
411 its->its_count = cpu_to_le32(1);
412 its->identifiers[0] = 0; /* MADT translation_id */
413
414 if (vms->iommu == VIRT_IOMMU_SMMUV3) {
415 int irq = vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE;
416
417 /* SMMUv3 node */
418 smmu_offset = iort_node_offset + node_size;
419 node_size = sizeof(*smmu) + sizeof(*idmap);
420 iort_length += node_size;
421 smmu = acpi_data_push(table_data, node_size);
422
423 smmu->type = ACPI_IORT_NODE_SMMU_V3;
424 smmu->length = cpu_to_le16(node_size);
425 smmu->mapping_count = cpu_to_le32(1);
426 smmu->mapping_offset = cpu_to_le32(sizeof(*smmu));
427 smmu->base_address = cpu_to_le64(vms->memmap[VIRT_SMMU].base);
428 smmu->flags = cpu_to_le32(ACPI_IORT_SMMU_V3_COHACC_OVERRIDE);
429 smmu->event_gsiv = cpu_to_le32(irq);
430 smmu->pri_gsiv = cpu_to_le32(irq + 1);
431 smmu->gerr_gsiv = cpu_to_le32(irq + 2);
432 smmu->sync_gsiv = cpu_to_le32(irq + 3);
433
434 /* Identity RID mapping covering the whole input RID range */
435 idmap = &smmu->id_mapping_array[0];
436 idmap->input_base = 0;
437 idmap->id_count = cpu_to_le32(0xFFFF);
438 idmap->output_base = 0;
439 /* output IORT node is the ITS group node (the first node) */
440 idmap->output_reference = cpu_to_le32(iort_node_offset);
441 }
442
443 /* Root Complex Node */
444 node_size = sizeof(*rc) + sizeof(*idmap);
445 iort_length += node_size;
446 rc = acpi_data_push(table_data, node_size);
447
448 rc->type = ACPI_IORT_NODE_PCI_ROOT_COMPLEX;
449 rc->length = cpu_to_le16(node_size);
450 rc->mapping_count = cpu_to_le32(1);
451 rc->mapping_offset = cpu_to_le32(sizeof(*rc));
452
453 /* fully coherent device */
454 rc->memory_properties.cache_coherency = cpu_to_le32(1);
455 rc->memory_properties.memory_flags = 0x3; /* CCA = CPM = DCAS = 1 */
456 rc->pci_segment_number = 0; /* MCFG pci_segment */
457
458 /* Identity RID mapping covering the whole input RID range */
459 idmap = &rc->id_mapping_array[0];
460 idmap->input_base = 0;
461 idmap->id_count = cpu_to_le32(0xFFFF);
462 idmap->output_base = 0;
463
464 if (vms->iommu == VIRT_IOMMU_SMMUV3) {
465 /* output IORT node is the smmuv3 node */
466 idmap->output_reference = cpu_to_le32(smmu_offset);
467 } else {
468 /* output IORT node is the ITS group node (the first node) */
469 idmap->output_reference = cpu_to_le32(iort_node_offset);
470 }
471
472 /*
473 * Update the pointer address in case table_data->data moves during above
474 * acpi_data_push operations.
475 */
476 iort = (AcpiIortTable *)(table_data->data + iort_start);
477 iort->length = cpu_to_le32(iort_length);
478
479 build_header(linker, table_data, (void *)(table_data->data + iort_start),
480 "IORT", table_data->len - iort_start, 0, NULL, NULL);
481 }
482
483 static void
484 build_spcr(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
485 {
486 AcpiSerialPortConsoleRedirection *spcr;
487 const MemMapEntry *uart_memmap = &vms->memmap[VIRT_UART];
488 int irq = vms->irqmap[VIRT_UART] + ARM_SPI_BASE;
489 int spcr_start = table_data->len;
490
491 spcr = acpi_data_push(table_data, sizeof(*spcr));
492
493 spcr->interface_type = 0x3; /* ARM PL011 UART */
494
495 spcr->base_address.space_id = AML_SYSTEM_MEMORY;
496 spcr->base_address.bit_width = 8;
497 spcr->base_address.bit_offset = 0;
498 spcr->base_address.access_width = 1;
499 spcr->base_address.address = cpu_to_le64(uart_memmap->base);
500
501 spcr->interrupt_types = (1 << 3); /* Bit[3] ARMH GIC interrupt */
502 spcr->gsi = cpu_to_le32(irq); /* Global System Interrupt */
503
504 spcr->baud = 3; /* Baud Rate: 3 = 9600 */
505 spcr->parity = 0; /* No Parity */
506 spcr->stopbits = 1; /* 1 Stop bit */
507 spcr->flowctrl = (1 << 1); /* Bit[1] = RTS/CTS hardware flow control */
508 spcr->term_type = 0; /* Terminal Type: 0 = VT100 */
509
510 spcr->pci_device_id = 0xffff; /* PCI Device ID: not a PCI device */
511 spcr->pci_vendor_id = 0xffff; /* PCI Vendor ID: not a PCI device */
512
513 build_header(linker, table_data, (void *)(table_data->data + spcr_start),
514 "SPCR", table_data->len - spcr_start, 2, NULL, NULL);
515 }
516
517 static void
518 build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
519 {
520 AcpiSystemResourceAffinityTable *srat;
521 AcpiSratProcessorGiccAffinity *core;
522 AcpiSratMemoryAffinity *numamem;
523 int i, srat_start;
524 uint64_t mem_base;
525 MachineClass *mc = MACHINE_GET_CLASS(vms);
526 MachineState *ms = MACHINE(vms);
527 const CPUArchIdList *cpu_list = mc->possible_cpu_arch_ids(ms);
528
529 srat_start = table_data->len;
530 srat = acpi_data_push(table_data, sizeof(*srat));
531 srat->reserved1 = cpu_to_le32(1);
532
533 for (i = 0; i < cpu_list->len; ++i) {
534 core = acpi_data_push(table_data, sizeof(*core));
535 core->type = ACPI_SRAT_PROCESSOR_GICC;
536 core->length = sizeof(*core);
537 core->proximity = cpu_to_le32(cpu_list->cpus[i].props.node_id);
538 core->acpi_processor_uid = cpu_to_le32(i);
539 core->flags = cpu_to_le32(1);
540 }
541
542 mem_base = vms->memmap[VIRT_MEM].base;
543 for (i = 0; i < ms->numa_state->num_nodes; ++i) {
544 if (ms->numa_state->nodes[i].node_mem > 0) {
545 numamem = acpi_data_push(table_data, sizeof(*numamem));
546 build_srat_memory(numamem, mem_base,
547 ms->numa_state->nodes[i].node_mem, i,
548 MEM_AFFINITY_ENABLED);
549 mem_base += ms->numa_state->nodes[i].node_mem;
550 }
551 }
552
553 if (ms->device_memory) {
554 numamem = acpi_data_push(table_data, sizeof *numamem);
555 build_srat_memory(numamem, ms->device_memory->base,
556 memory_region_size(&ms->device_memory->mr),
557 ms->numa_state->num_nodes - 1,
558 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
559 }
560
561 build_header(linker, table_data, (void *)(table_data->data + srat_start),
562 "SRAT", table_data->len - srat_start, 3, NULL, NULL);
563 }
564
565 /* GTDT */
566 static void
567 build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
568 {
569 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
570 int gtdt_start = table_data->len;
571 AcpiGenericTimerTable *gtdt;
572 uint32_t irqflags;
573
574 if (vmc->claim_edge_triggered_timers) {
575 irqflags = ACPI_GTDT_INTERRUPT_MODE_EDGE;
576 } else {
577 irqflags = ACPI_GTDT_INTERRUPT_MODE_LEVEL;
578 }
579
580 gtdt = acpi_data_push(table_data, sizeof *gtdt);
581 /* The interrupt values are the same with the device tree when adding 16 */
582 gtdt->secure_el1_interrupt = cpu_to_le32(ARCH_TIMER_S_EL1_IRQ + 16);
583 gtdt->secure_el1_flags = cpu_to_le32(irqflags);
584
585 gtdt->non_secure_el1_interrupt = cpu_to_le32(ARCH_TIMER_NS_EL1_IRQ + 16);
586 gtdt->non_secure_el1_flags = cpu_to_le32(irqflags |
587 ACPI_GTDT_CAP_ALWAYS_ON);
588
589 gtdt->virtual_timer_interrupt = cpu_to_le32(ARCH_TIMER_VIRT_IRQ + 16);
590 gtdt->virtual_timer_flags = cpu_to_le32(irqflags);
591
592 gtdt->non_secure_el2_interrupt = cpu_to_le32(ARCH_TIMER_NS_EL2_IRQ + 16);
593 gtdt->non_secure_el2_flags = cpu_to_le32(irqflags);
594
595 build_header(linker, table_data,
596 (void *)(table_data->data + gtdt_start), "GTDT",
597 table_data->len - gtdt_start, 2, NULL, NULL);
598 }
599
600 /* MADT */
601 static void
602 build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
603 {
604 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
605 int madt_start = table_data->len;
606 const MemMapEntry *memmap = vms->memmap;
607 const int *irqmap = vms->irqmap;
608 AcpiMultipleApicTable *madt;
609 AcpiMadtGenericDistributor *gicd;
610 AcpiMadtGenericMsiFrame *gic_msi;
611 int i;
612
613 madt = acpi_data_push(table_data, sizeof *madt);
614
615 gicd = acpi_data_push(table_data, sizeof *gicd);
616 gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR;
617 gicd->length = sizeof(*gicd);
618 gicd->base_address = cpu_to_le64(memmap[VIRT_GIC_DIST].base);
619 gicd->version = vms->gic_version;
620
621 for (i = 0; i < vms->smp_cpus; i++) {
622 AcpiMadtGenericCpuInterface *gicc = acpi_data_push(table_data,
623 sizeof(*gicc));
624 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));
625
626 gicc->type = ACPI_APIC_GENERIC_CPU_INTERFACE;
627 gicc->length = sizeof(*gicc);
628 if (vms->gic_version == 2) {
629 gicc->base_address = cpu_to_le64(memmap[VIRT_GIC_CPU].base);
630 gicc->gich_base_address = cpu_to_le64(memmap[VIRT_GIC_HYP].base);
631 gicc->gicv_base_address = cpu_to_le64(memmap[VIRT_GIC_VCPU].base);
632 }
633 gicc->cpu_interface_number = cpu_to_le32(i);
634 gicc->arm_mpidr = cpu_to_le64(armcpu->mp_affinity);
635 gicc->uid = cpu_to_le32(i);
636 gicc->flags = cpu_to_le32(ACPI_MADT_GICC_ENABLED);
637
638 if (arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
639 gicc->performance_interrupt = cpu_to_le32(PPI(VIRTUAL_PMU_IRQ));
640 }
641 if (vms->virt) {
642 gicc->vgic_interrupt = cpu_to_le32(PPI(ARCH_GIC_MAINT_IRQ));
643 }
644 }
645
646 if (vms->gic_version == 3) {
647 AcpiMadtGenericTranslator *gic_its;
648 int nb_redist_regions = virt_gicv3_redist_region_count(vms);
649 AcpiMadtGenericRedistributor *gicr = acpi_data_push(table_data,
650 sizeof *gicr);
651
652 gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR;
653 gicr->length = sizeof(*gicr);
654 gicr->base_address = cpu_to_le64(memmap[VIRT_GIC_REDIST].base);
655 gicr->range_length = cpu_to_le32(memmap[VIRT_GIC_REDIST].size);
656
657 if (nb_redist_regions == 2) {
658 gicr = acpi_data_push(table_data, sizeof(*gicr));
659 gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR;
660 gicr->length = sizeof(*gicr);
661 gicr->base_address =
662 cpu_to_le64(memmap[VIRT_HIGH_GIC_REDIST2].base);
663 gicr->range_length =
664 cpu_to_le32(memmap[VIRT_HIGH_GIC_REDIST2].size);
665 }
666
667 if (its_class_name() && !vmc->no_its) {
668 gic_its = acpi_data_push(table_data, sizeof *gic_its);
669 gic_its->type = ACPI_APIC_GENERIC_TRANSLATOR;
670 gic_its->length = sizeof(*gic_its);
671 gic_its->translation_id = 0;
672 gic_its->base_address = cpu_to_le64(memmap[VIRT_GIC_ITS].base);
673 }
674 } else {
675 gic_msi = acpi_data_push(table_data, sizeof *gic_msi);
676 gic_msi->type = ACPI_APIC_GENERIC_MSI_FRAME;
677 gic_msi->length = sizeof(*gic_msi);
678 gic_msi->gic_msi_frame_id = 0;
679 gic_msi->base_address = cpu_to_le64(memmap[VIRT_GIC_V2M].base);
680 gic_msi->flags = cpu_to_le32(1);
681 gic_msi->spi_count = cpu_to_le16(NUM_GICV2M_SPIS);
682 gic_msi->spi_base = cpu_to_le16(irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE);
683 }
684
685 build_header(linker, table_data,
686 (void *)(table_data->data + madt_start), "APIC",
687 table_data->len - madt_start, 3, NULL, NULL);
688 }
689
690 /* FADT */
691 static void build_fadt_rev5(GArray *table_data, BIOSLinker *linker,
692 VirtMachineState *vms, unsigned dsdt_tbl_offset)
693 {
694 /* ACPI v5.1 */
695 AcpiFadtData fadt = {
696 .rev = 5,
697 .minor_ver = 1,
698 .flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI,
699 .xdsdt_tbl_offset = &dsdt_tbl_offset,
700 };
701
702 switch (vms->psci_conduit) {
703 case QEMU_PSCI_CONDUIT_DISABLED:
704 fadt.arm_boot_arch = 0;
705 break;
706 case QEMU_PSCI_CONDUIT_HVC:
707 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT |
708 ACPI_FADT_ARM_PSCI_USE_HVC;
709 break;
710 case QEMU_PSCI_CONDUIT_SMC:
711 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT;
712 break;
713 default:
714 g_assert_not_reached();
715 }
716
717 build_fadt(table_data, linker, &fadt, NULL, NULL);
718 }
719
720 /* DSDT */
721 static void
722 build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
723 {
724 Aml *scope, *dsdt;
725 MachineState *ms = MACHINE(vms);
726 const MemMapEntry *memmap = vms->memmap;
727 const int *irqmap = vms->irqmap;
728
729 dsdt = init_aml_allocator();
730 /* Reserve space for header */
731 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
732
733 /* When booting the VM with UEFI, UEFI takes ownership of the RTC hardware.
734 * While UEFI can use libfdt to disable the RTC device node in the DTB that
735 * it passes to the OS, it cannot modify AML. Therefore, we won't generate
736 * the RTC ACPI device at all when using UEFI.
737 */
738 scope = aml_scope("\\_SB");
739 acpi_dsdt_add_cpus(scope, vms->smp_cpus);
740 acpi_dsdt_add_uart(scope, &memmap[VIRT_UART],
741 (irqmap[VIRT_UART] + ARM_SPI_BASE));
742 acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]);
743 acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]);
744 acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO],
745 (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
746 acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE),
747 vms->highmem, vms->highmem_ecam);
748 if (vms->acpi_dev) {
749 build_ged_aml(scope, "\\_SB."GED_DEVICE,
750 HOTPLUG_HANDLER(vms->acpi_dev),
751 irqmap[VIRT_ACPI_GED] + ARM_SPI_BASE, AML_SYSTEM_MEMORY,
752 memmap[VIRT_ACPI_GED].base);
753 } else {
754 acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO],
755 (irqmap[VIRT_GPIO] + ARM_SPI_BASE));
756 }
757
758 if (vms->acpi_dev) {
759 uint32_t event = object_property_get_uint(OBJECT(vms->acpi_dev),
760 "ged-event", &error_abort);
761
762 if (event & ACPI_GED_MEM_HOTPLUG_EVT) {
763 build_memory_hotplug_aml(scope, ms->ram_slots, "\\_SB", NULL,
764 AML_SYSTEM_MEMORY,
765 memmap[VIRT_PCDIMM_ACPI].base);
766 }
767 }
768
769 acpi_dsdt_add_power_button(scope);
770
771 aml_append(dsdt, scope);
772
773 /* copy AML table into ACPI tables blob and patch header there */
774 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
775 build_header(linker, table_data,
776 (void *)(table_data->data + table_data->len - dsdt->buf->len),
777 "DSDT", dsdt->buf->len, 2, NULL, NULL);
778 free_aml_allocator();
779 }
780
781 typedef
782 struct AcpiBuildState {
783 /* Copy of table in RAM (for patching). */
784 MemoryRegion *table_mr;
785 MemoryRegion *rsdp_mr;
786 MemoryRegion *linker_mr;
787 /* Is table patched? */
788 bool patched;
789 } AcpiBuildState;
790
791 static
792 void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
793 {
794 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
795 GArray *table_offsets;
796 unsigned dsdt, xsdt;
797 GArray *tables_blob = tables->table_data;
798 MachineState *ms = MACHINE(vms);
799
800 table_offsets = g_array_new(false, true /* clear */,
801 sizeof(uint32_t));
802
803 bios_linker_loader_alloc(tables->linker,
804 ACPI_BUILD_TABLE_FILE, tables_blob,
805 64, false /* high memory */);
806
807 /* DSDT is pointed to by FADT */
808 dsdt = tables_blob->len;
809 build_dsdt(tables_blob, tables->linker, vms);
810
811 /* FADT MADT GTDT MCFG SPCR pointed to by RSDT */
812 acpi_add_table(table_offsets, tables_blob);
813 build_fadt_rev5(tables_blob, tables->linker, vms, dsdt);
814
815 acpi_add_table(table_offsets, tables_blob);
816 build_madt(tables_blob, tables->linker, vms);
817
818 acpi_add_table(table_offsets, tables_blob);
819 build_gtdt(tables_blob, tables->linker, vms);
820
821 acpi_add_table(table_offsets, tables_blob);
822 {
823 AcpiMcfgInfo mcfg = {
824 .base = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].base,
825 .size = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].size,
826 };
827 build_mcfg(tables_blob, tables->linker, &mcfg);
828 }
829
830 acpi_add_table(table_offsets, tables_blob);
831 build_spcr(tables_blob, tables->linker, vms);
832
833 if (ms->numa_state->num_nodes > 0) {
834 acpi_add_table(table_offsets, tables_blob);
835 build_srat(tables_blob, tables->linker, vms);
836 if (ms->numa_state->have_numa_distance) {
837 acpi_add_table(table_offsets, tables_blob);
838 build_slit(tables_blob, tables->linker, ms);
839 }
840 }
841
842 if (its_class_name() && !vmc->no_its) {
843 acpi_add_table(table_offsets, tables_blob);
844 build_iort(tables_blob, tables->linker, vms);
845 }
846
847 /* XSDT is pointed to by RSDP */
848 xsdt = tables_blob->len;
849 build_xsdt(tables_blob, tables->linker, table_offsets, NULL, NULL);
850
851 /* RSDP is in FSEG memory, so allocate it separately */
852 {
853 AcpiRsdpData rsdp_data = {
854 .revision = 2,
855 .oem_id = ACPI_BUILD_APPNAME6,
856 .xsdt_tbl_offset = &xsdt,
857 .rsdt_tbl_offset = NULL,
858 };
859 build_rsdp(tables->rsdp, tables->linker, &rsdp_data);
860 }
861
862 /* Cleanup memory that's no longer used. */
863 g_array_free(table_offsets, true);
864 }
865
866 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
867 {
868 uint32_t size = acpi_data_len(data);
869
870 /* Make sure RAM size is correct - in case it got changed
871 * e.g. by migration */
872 memory_region_ram_resize(mr, size, &error_abort);
873
874 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
875 memory_region_set_dirty(mr, 0, size);
876 }
877
878 static void virt_acpi_build_update(void *build_opaque)
879 {
880 AcpiBuildState *build_state = build_opaque;
881 AcpiBuildTables tables;
882
883 /* No state to update or already patched? Nothing to do. */
884 if (!build_state || build_state->patched) {
885 return;
886 }
887 build_state->patched = true;
888
889 acpi_build_tables_init(&tables);
890
891 virt_acpi_build(VIRT_MACHINE(qdev_get_machine()), &tables);
892
893 acpi_ram_update(build_state->table_mr, tables.table_data);
894 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
895 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
896
897 acpi_build_tables_cleanup(&tables, true);
898 }
899
900 static void virt_acpi_build_reset(void *build_opaque)
901 {
902 AcpiBuildState *build_state = build_opaque;
903 build_state->patched = false;
904 }
905
906 static const VMStateDescription vmstate_virt_acpi_build = {
907 .name = "virt_acpi_build",
908 .version_id = 1,
909 .minimum_version_id = 1,
910 .fields = (VMStateField[]) {
911 VMSTATE_BOOL(patched, AcpiBuildState),
912 VMSTATE_END_OF_LIST()
913 },
914 };
915
916 void virt_acpi_setup(VirtMachineState *vms)
917 {
918 AcpiBuildTables tables;
919 AcpiBuildState *build_state;
920
921 if (!vms->fw_cfg) {
922 trace_virt_acpi_setup();
923 return;
924 }
925
926 if (!acpi_enabled) {
927 trace_virt_acpi_setup();
928 return;
929 }
930
931 build_state = g_malloc0(sizeof *build_state);
932
933 acpi_build_tables_init(&tables);
934 virt_acpi_build(vms, &tables);
935
936 /* Now expose it all to Guest */
937 build_state->table_mr = acpi_add_rom_blob(virt_acpi_build_update,
938 build_state, tables.table_data,
939 ACPI_BUILD_TABLE_FILE,
940 ACPI_BUILD_TABLE_MAX_SIZE);
941 assert(build_state->table_mr != NULL);
942
943 build_state->linker_mr =
944 acpi_add_rom_blob(virt_acpi_build_update, build_state,
945 tables.linker->cmd_blob, "etc/table-loader", 0);
946
947 fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data,
948 acpi_data_len(tables.tcpalog));
949
950 build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update,
951 build_state, tables.rsdp,
952 ACPI_BUILD_RSDP_FILE, 0);
953
954 qemu_register_reset(virt_acpi_build_reset, build_state);
955 virt_acpi_build_reset(build_state);
956 vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state);
957
958 /* Cleanup tables but don't free the memory: we track it
959 * in build_state.
960 */
961 acpi_build_tables_cleanup(&tables, false);
962 }
AR7 emulation for QEMU