hw/arm/s3c24xx_iic.c

   1 /* hw/s3c24xx_iic.c
   2  *
   3  * Samsung S3C24XX i2c peripheral emulation
   4  *
   5  * Copyright 2006, 2007, 2008 Daniel Silverstone, Ben Dooks
   6  *  and Vincent Sanders
   7  *
   8  * Copyright 2010, 2013 Stefan Weil
   9  *
  10  * This file is under the terms of the GNU General Public License Version 2.
  11  */
  12
  13 #include "qemu/osdep.h"
  14 #include "cpu.h"
  15 #include "hw/hw.h"
  16 #include "exec/address-spaces.h" /* get_system_memory */
  17 #include "hw/i2c/i2c.h"
  18 #include "migration/register.h"  /* register_savevm_live */
  19
  20 #include "s3c24xx.h"
  21
  22 /* i2c controller registers */
  23 #define S3C_IICCON  (0x00)
  24 #define S3C_IICSTAT (0x04)
  25 #define S3C_IICADD  (0x08)
  26 #define S3C_IICDS   (0x0C)
  27 #define S3C_IICLC   (0x10)
  28
  29 #define S3C_IICCON_ACKEN        (1<<7)
  30 #define S3C_IICCON_TXDIV_16     (0<<6)
  31 #define S3C_IICCON_TXDIV_512    (1<<6)
  32 #define S3C_IICCON_IRQEN        (1<<5)
  33 #define S3C_IICCON_IRQPEND      (1<<4)
  34 #define S3C_IICCON_SCALE(x)     ((x)&15)
  35 #define S3C_IICCON_SCALEMASK    (0xf)
  36
  37 #define S3C_IICSTAT_MASTER_RX   (2<<6)
  38 #define S3C_IICSTAT_MASTER_TX   (3<<6)
  39 #define S3C_IICSTAT_SLAVE_RX    (0<<6)
  40 #define S3C_IICSTAT_SLAVE_TX    (1<<6)
  41 #define S3C_IICSTAT_MODEMASK    (3<<6)
  42
  43 #define S3C_IICSTAT_START       (1<<5)
  44 #define S3C_IICSTAT_BUSBUSY     (1<<5)
  45 #define S3C_IICSTAT_TXRXEN      (1<<4)
  46 #define S3C_IICSTAT_ARBITR      (1<<3)
  47 #define S3C_IICSTAT_ASSLAVE     (1<<2)
  48 #define S3C_IICSTAT_ADDR0        (1<<1)
  49 #define S3C_IICSTAT_LASTBIT      (1<<0)
  50
  51 #define S3C_IICLC_SDA_DELAY0     (0 << 0)
  52 #define S3C_IICLC_SDA_DELAY5     (1 << 0)
  53 #define S3C_IICLC_SDA_DELAY10    (2 << 0)
  54 #define S3C_IICLC_SDA_DELAY15    (3 << 0)
  55 #define S3C_IICLC_SDA_DELAY_MASK (3 << 0)
  56
  57 #define S3C_IICLC_FILTER_ON      (1<<2)
  58
  59 /* IIC-bus serial interface */
  60 struct s3c24xx_i2c_state_s {
  61     MemoryRegion mmio;
  62     I2CBus *bus;
  63     qemu_irq irq;
  64
  65     uint8_t control;
  66     uint8_t status;
  67     uint8_t data;
  68     uint8_t addy;
  69     int busy;
  70     int newstart;
  71 };
  72
  73 static void s3c24xx_i2c_irq(struct s3c24xx_i2c_state_s *s)
  74 {
  75     s->control |= 1 << 4;
  76
  77     if (s->control & (1 << 5)) {
  78         qemu_irq_raise(s->irq);
  79     }
  80 }
  81
  82 static void s3c24xx_i2c_reset(struct s3c24xx_i2c_state_s *s)
  83 {
  84     s->control = 0x00;
  85     s->status = 0x00;
  86     s->busy = 0;
  87     s->newstart = 0;
  88 }
  89
  90
  91 static void s3c_master_work(void *opaque)
  92 {
  93     struct s3c24xx_i2c_state_s *s = opaque;
  94     int start = 0, stop = 0, ack = 1;
  95
  96     if (s->control & (1 << 4))                          /* Interrupt pending */
  97         return;
  98     if ((s->status & 0x90) != 0x90)                     /* Master */
  99         return;
 100
 101     stop = ~s->status & (1 << 5);
 102     if (s->newstart && s->status & (1 << 5)) {          /* START */
 103         s->busy = 1;
 104         start = 1;
 105     }
 106     s->newstart = 0;
 107
 108     if (!s->busy) {
 109         return;
 110     }
 111
 112     if (start) {
 113         ack = !i2c_start_transfer(s->bus, s->data >> 1, (~s->status >> 6) & 1);
 114     } else if (stop) {
 115         i2c_end_transfer(s->bus);
 116     } else if (s->status & (1 << 6)) {
 117         ack = !i2c_send(s->bus, s->data);
 118     } else {
 119         s->data = i2c_recv(s->bus);
 120
 121         if (!(s->control & (1 << 7)))                   /* ACK */
 122             i2c_nack(s->bus);
 123     }
 124
 125     if (!(s->status & (1 << 5))) {
 126         s->busy = 0;
 127         return;
 128     }
 129
 130     s->status &= ~1;
 131     s->status |= !ack;
 132
 133     if (!ack) {
 134         s->busy = 0;
 135     }
 136     s3c24xx_i2c_irq(s);
 137 }
 138
 139 static uint64_t s3c24xx_i2c_read(void *opaque, hwaddr addr,
 140                                  unsigned size)
 141 {
 142     struct s3c24xx_i2c_state_s *s = opaque;
 143
 144     switch (addr) {
 145     case S3C_IICCON:
 146         return s->control;
 147
 148     case S3C_IICSTAT:
 149         return s->status & ~(1 << 5);                   /* Busy signal */
 150
 151     case S3C_IICADD:
 152         return s->addy;
 153
 154     case S3C_IICDS:
 155         return s->data;
 156
 157     default:
 158         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
 159         break;
 160     }
 161     return 0;
 162 }
 163
 164 static void s3c24xx_i2c_write(void *opaque, hwaddr addr,
 165                               uint64_t value, unsigned size)
 166 {
 167     struct s3c24xx_i2c_state_s *s = opaque;
 168
 169     switch (addr) {
 170     case S3C_IICCON:
 171         s->control = (s->control | 0xef) & value;
 172         if (s->busy || ((s->control & (1<<4)) == 0))
 173             s3c_master_work(s);
 174         break;
 175
 176     case S3C_IICSTAT:
 177         s->status &= 0x0f;
 178         s->status |= value & 0xf0;
 179         if (s->status & (1 << 5))
 180             s->newstart = 1;
 181         s3c_master_work(s);
 182         break;
 183
 184     case S3C_IICADD:
 185         s->addy = value & 0x7f;
 186         break;
 187
 188     case S3C_IICDS:
 189         s->data = value & 0xff;
 190         s->busy = 1;
 191         break;
 192
 193     default:
 194         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
 195         break;
 196     }
 197 }
 198
 199 static const MemoryRegionOps s3c24xx_i2c_ops = {
 200     .read = s3c24xx_i2c_read,
 201     .write = s3c24xx_i2c_write,
 202     .endianness = DEVICE_NATIVE_ENDIAN,
 203     .valid = {
 204         .min_access_size = 1,
 205         .max_access_size = 4
 206     }
 207 };
 208
 209 static void s3c24xx_i2c_save(QEMUFile *f, void *opaque)
 210 {
 211     struct s3c24xx_i2c_state_s *s = opaque;
 212     qemu_put_8s(f, &s->control);
 213     qemu_put_8s(f, &s->status);
 214     qemu_put_8s(f, &s->data);
 215     qemu_put_8s(f, &s->addy);
 216
 217     qemu_put_be32(f, s->busy);
 218     qemu_put_be32(f, s->newstart);
 219
 220 }
 221
 222 static int s3c24xx_i2c_load(QEMUFile *f, void *opaque, int version_id)
 223 {
 224     struct s3c24xx_i2c_state_s *s = opaque;
 225     qemu_get_8s(f, &s->control);
 226     qemu_get_8s(f, &s->status);
 227     qemu_get_8s(f, &s->data);
 228     qemu_get_8s(f, &s->addy);
 229
 230     s->busy = qemu_get_be32(f);
 231     s->newstart = qemu_get_be32(f);
 232
 233     return 0;
 234 }
 235
 236 static SaveVMHandlers savevm_s3c24xx_i2c = {
 237     .save_state = s3c24xx_i2c_save,
 238     .load_state = s3c24xx_i2c_load
 239 };
 240
 241 struct s3c24xx_i2c_state_s *s3c24xx_iic_init(qemu_irq irq,
 242                                              hwaddr base_addr)
 243 {
 244     MemoryRegion *system_memory = get_system_memory();
 245     struct s3c24xx_i2c_state_s *s = g_malloc0(sizeof(struct s3c24xx_i2c_state_s));
 246
 247     s->irq = irq;
 248     s->bus = i2c_init_bus(NULL, "i2c");
 249
 250     s3c24xx_i2c_reset(s);
 251
 252     memory_region_init_io(&s->mmio, OBJECT(s),
 253                           &s3c24xx_i2c_ops, s, "s3c24xx-i2c", 0x1000000);
 254     memory_region_add_subregion(system_memory, base_addr, &s->mmio);
 255
 256     register_savevm_live(NULL, "s3c24xx_i2c", 0, 0, &savevm_s3c24xx_i2c, s);
 257
 258     return s;
 259 }
 260
 261 I2CBus *s3c24xx_i2c_bus(struct s3c24xx_i2c_state_s *s)
 262 {
 263     return s->bus;
 264 }