4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
10 #include "qemu/osdep.h"
11 #include "qemu/error-report.h"
12 #include "qapi/error.h"
15 #include "hw/arm/arm.h"
16 #include "hw/arm/linux-boot-if.h"
17 #include "sysemu/kvm.h"
18 #include "sysemu/sysemu.h"
19 #include "sysemu/numa.h"
20 #include "hw/boards.h"
21 #include "hw/loader.h"
23 #include "sysemu/device_tree.h"
24 #include "qemu/config-file.h"
25 #include "qemu/option.h"
26 #include "exec/address-spaces.h"
27 #include "qemu/units.h"
29 /* Kernel boot protocol is specified in the kernel docs
30 * Documentation/arm/Booting and Documentation/arm64/booting.txt
31 * They have different preferred image load offsets from system RAM base.
33 #define KERNEL_ARGS_ADDR 0x100
34 #define KERNEL_LOAD_ADDR 0x00010000
35 #define KERNEL64_LOAD_ADDR 0x00080000
37 #define ARM64_TEXT_OFFSET_OFFSET 8
38 #define ARM64_MAGIC_OFFSET 56
40 #define BOOTLOADER_MAX_SIZE (4 * KiB)
42 AddressSpace
*arm_boot_address_space(ARMCPU
*cpu
,
43 const struct arm_boot_info
*info
)
45 /* Return the address space to use for bootloader reads and writes.
46 * We prefer the secure address space if the CPU has it and we're
47 * going to boot the guest into it.
50 CPUState
*cs
= CPU(cpu
);
52 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL3
) && info
->secure_boot
) {
58 return cpu_get_address_space(cs
, asidx
);
62 FIXUP_NONE
= 0, /* do nothing */
63 FIXUP_TERMINATOR
, /* end of insns */
64 FIXUP_BOARDID
, /* overwrite with board ID number */
65 FIXUP_BOARD_SETUP
, /* overwrite with board specific setup code address */
66 FIXUP_ARGPTR_LO
, /* overwrite with pointer to kernel args */
67 FIXUP_ARGPTR_HI
, /* overwrite with pointer to kernel args (high half) */
68 FIXUP_ENTRYPOINT_LO
, /* overwrite with kernel entry point */
69 FIXUP_ENTRYPOINT_HI
, /* overwrite with kernel entry point (high half) */
70 FIXUP_GIC_CPU_IF
, /* overwrite with GIC CPU interface address */
71 FIXUP_BOOTREG
, /* overwrite with boot register address */
72 FIXUP_DSB
, /* overwrite with correct DSB insn for cpu */
76 typedef struct ARMInsnFixup
{
81 static const ARMInsnFixup bootloader_aarch64
[] = {
82 { 0x580000c0 }, /* ldr x0, arg ; Load the lower 32-bits of DTB */
83 { 0xaa1f03e1 }, /* mov x1, xzr */
84 { 0xaa1f03e2 }, /* mov x2, xzr */
85 { 0xaa1f03e3 }, /* mov x3, xzr */
86 { 0x58000084 }, /* ldr x4, entry ; Load the lower 32-bits of kernel entry */
87 { 0xd61f0080 }, /* br x4 ; Jump to the kernel entry point */
88 { 0, FIXUP_ARGPTR_LO
}, /* arg: .word @DTB Lower 32-bits */
89 { 0, FIXUP_ARGPTR_HI
}, /* .word @DTB Higher 32-bits */
90 { 0, FIXUP_ENTRYPOINT_LO
}, /* entry: .word @Kernel Entry Lower 32-bits */
91 { 0, FIXUP_ENTRYPOINT_HI
}, /* .word @Kernel Entry Higher 32-bits */
92 { 0, FIXUP_TERMINATOR
}
95 /* A very small bootloader: call the board-setup code (if needed),
96 * set r0-r2, then jump to the kernel.
97 * If we're not calling boot setup code then we don't copy across
98 * the first BOOTLOADER_NO_BOARD_SETUP_OFFSET insns in this array.
101 static const ARMInsnFixup bootloader
[] = {
102 { 0xe28fe004 }, /* add lr, pc, #4 */
103 { 0xe51ff004 }, /* ldr pc, [pc, #-4] */
104 { 0, FIXUP_BOARD_SETUP
},
105 #define BOOTLOADER_NO_BOARD_SETUP_OFFSET 3
106 { 0xe3a00000 }, /* mov r0, #0 */
107 { 0xe59f1004 }, /* ldr r1, [pc, #4] */
108 { 0xe59f2004 }, /* ldr r2, [pc, #4] */
109 { 0xe59ff004 }, /* ldr pc, [pc, #4] */
110 { 0, FIXUP_BOARDID
},
111 { 0, FIXUP_ARGPTR_LO
},
112 { 0, FIXUP_ENTRYPOINT_LO
},
113 { 0, FIXUP_TERMINATOR
}
116 /* Handling for secondary CPU boot in a multicore system.
117 * Unlike the uniprocessor/primary CPU boot, this is platform
118 * dependent. The default code here is based on the secondary
119 * CPU boot protocol used on realview/vexpress boards, with
120 * some parameterisation to increase its flexibility.
121 * QEMU platform models for which this code is not appropriate
122 * should override write_secondary_boot and secondary_cpu_reset_hook
125 * This code enables the interrupt controllers for the secondary
126 * CPUs and then puts all the secondary CPUs into a loop waiting
127 * for an interprocessor interrupt and polling a configurable
128 * location for the kernel secondary CPU entry point.
130 #define DSB_INSN 0xf57ff04f
131 #define CP15_DSB_INSN 0xee070f9a /* mcr cp15, 0, r0, c7, c10, 4 */
133 static const ARMInsnFixup smpboot
[] = {
134 { 0xe59f2028 }, /* ldr r2, gic_cpu_if */
135 { 0xe59f0028 }, /* ldr r0, bootreg_addr */
136 { 0xe3a01001 }, /* mov r1, #1 */
137 { 0xe5821000 }, /* str r1, [r2] - set GICC_CTLR.Enable */
138 { 0xe3a010ff }, /* mov r1, #0xff */
139 { 0xe5821004 }, /* str r1, [r2, 4] - set GIC_PMR.Priority to 0xff */
140 { 0, FIXUP_DSB
}, /* dsb */
141 { 0xe320f003 }, /* wfi */
142 { 0xe5901000 }, /* ldr r1, [r0] */
143 { 0xe1110001 }, /* tst r1, r1 */
144 { 0x0afffffb }, /* beq <wfi> */
145 { 0xe12fff11 }, /* bx r1 */
146 { 0, FIXUP_GIC_CPU_IF
}, /* gic_cpu_if: .word 0x.... */
147 { 0, FIXUP_BOOTREG
}, /* bootreg_addr: .word 0x.... */
148 { 0, FIXUP_TERMINATOR
}
151 static void write_bootloader(const char *name
, hwaddr addr
,
152 const ARMInsnFixup
*insns
, uint32_t *fixupcontext
,
155 /* Fix up the specified bootloader fragment and write it into
156 * guest memory using rom_add_blob_fixed(). fixupcontext is
157 * an array giving the values to write in for the fixup types
158 * which write a value into the code array.
164 while (insns
[len
].fixup
!= FIXUP_TERMINATOR
) {
168 code
= g_new0(uint32_t, len
);
170 for (i
= 0; i
< len
; i
++) {
171 uint32_t insn
= insns
[i
].insn
;
172 FixupType fixup
= insns
[i
].fixup
;
178 case FIXUP_BOARD_SETUP
:
179 case FIXUP_ARGPTR_LO
:
180 case FIXUP_ARGPTR_HI
:
181 case FIXUP_ENTRYPOINT_LO
:
182 case FIXUP_ENTRYPOINT_HI
:
183 case FIXUP_GIC_CPU_IF
:
186 insn
= fixupcontext
[fixup
];
191 code
[i
] = tswap32(insn
);
194 assert((len
* sizeof(uint32_t)) < BOOTLOADER_MAX_SIZE
);
196 rom_add_blob_fixed_as(name
, code
, len
* sizeof(uint32_t), addr
, as
);
201 static void default_write_secondary(ARMCPU
*cpu
,
202 const struct arm_boot_info
*info
)
204 uint32_t fixupcontext
[FIXUP_MAX
];
205 AddressSpace
*as
= arm_boot_address_space(cpu
, info
);
207 fixupcontext
[FIXUP_GIC_CPU_IF
] = info
->gic_cpu_if_addr
;
208 fixupcontext
[FIXUP_BOOTREG
] = info
->smp_bootreg_addr
;
209 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
210 fixupcontext
[FIXUP_DSB
] = DSB_INSN
;
212 fixupcontext
[FIXUP_DSB
] = CP15_DSB_INSN
;
215 write_bootloader("smpboot", info
->smp_loader_start
,
216 smpboot
, fixupcontext
, as
);
219 void arm_write_secure_board_setup_dummy_smc(ARMCPU
*cpu
,
220 const struct arm_boot_info
*info
,
223 AddressSpace
*as
= arm_boot_address_space(cpu
, info
);
225 uint32_t mvbar_blob
[] = {
226 /* mvbar_addr: secure monitor vectors
227 * Default unimplemented and unused vectors to spin. Makes it
228 * easier to debug (as opposed to the CPU running away).
230 0xeafffffe, /* (spin) */
231 0xeafffffe, /* (spin) */
232 0xe1b0f00e, /* movs pc, lr ;SMC exception return */
233 0xeafffffe, /* (spin) */
234 0xeafffffe, /* (spin) */
235 0xeafffffe, /* (spin) */
236 0xeafffffe, /* (spin) */
237 0xeafffffe, /* (spin) */
239 uint32_t board_setup_blob
[] = {
240 /* board setup addr */
241 0xe3a00e00 + (mvbar_addr
>> 4), /* mov r0, #mvbar_addr */
242 0xee0c0f30, /* mcr p15, 0, r0, c12, c0, 1 ;set MVBAR */
243 0xee110f11, /* mrc p15, 0, r0, c1 , c1, 0 ;read SCR */
244 0xe3800031, /* orr r0, #0x31 ;enable AW, FW, NS */
245 0xee010f11, /* mcr p15, 0, r0, c1, c1, 0 ;write SCR */
246 0xe1a0100e, /* mov r1, lr ;save LR across SMC */
247 0xe1600070, /* smc #0 ;call monitor to flush SCR */
248 0xe1a0f001, /* mov pc, r1 ;return */
251 /* check that mvbar_addr is correctly aligned and relocatable (using MOV) */
252 assert((mvbar_addr
& 0x1f) == 0 && (mvbar_addr
>> 4) < 0x100);
254 /* check that these blobs don't overlap */
255 assert((mvbar_addr
+ sizeof(mvbar_blob
) <= info
->board_setup_addr
)
256 || (info
->board_setup_addr
+ sizeof(board_setup_blob
) <= mvbar_addr
));
258 for (n
= 0; n
< ARRAY_SIZE(mvbar_blob
); n
++) {
259 mvbar_blob
[n
] = tswap32(mvbar_blob
[n
]);
261 rom_add_blob_fixed_as("board-setup-mvbar", mvbar_blob
, sizeof(mvbar_blob
),
264 for (n
= 0; n
< ARRAY_SIZE(board_setup_blob
); n
++) {
265 board_setup_blob
[n
] = tswap32(board_setup_blob
[n
]);
267 rom_add_blob_fixed_as("board-setup", board_setup_blob
,
268 sizeof(board_setup_blob
), info
->board_setup_addr
, as
);
271 static void default_reset_secondary(ARMCPU
*cpu
,
272 const struct arm_boot_info
*info
)
274 AddressSpace
*as
= arm_boot_address_space(cpu
, info
);
275 CPUState
*cs
= CPU(cpu
);
277 address_space_stl_notdirty(as
, info
->smp_bootreg_addr
,
278 0, MEMTXATTRS_UNSPECIFIED
, NULL
);
279 cpu_set_pc(cs
, info
->smp_loader_start
);
282 static inline bool have_dtb(const struct arm_boot_info
*info
)
284 return info
->dtb_filename
|| info
->get_dtb
;
287 #define WRITE_WORD(p, value) do { \
288 address_space_stl_notdirty(as, p, value, \
289 MEMTXATTRS_UNSPECIFIED, NULL); \
293 static void set_kernel_args(const struct arm_boot_info
*info
, AddressSpace
*as
)
295 int initrd_size
= info
->initrd_size
;
296 hwaddr base
= info
->loader_start
;
299 p
= base
+ KERNEL_ARGS_ADDR
;
302 WRITE_WORD(p
, 0x54410001);
304 WRITE_WORD(p
, 0x1000);
307 /* TODO: handle multiple chips on one ATAG list */
309 WRITE_WORD(p
, 0x54410002);
310 WRITE_WORD(p
, info
->ram_size
);
311 WRITE_WORD(p
, info
->loader_start
);
315 WRITE_WORD(p
, 0x54420005);
316 WRITE_WORD(p
, info
->initrd_start
);
317 WRITE_WORD(p
, initrd_size
);
319 if (info
->atag_revision
) {
322 WRITE_WORD(p
, 0x54410007);
323 WRITE_WORD(p
, info
->atag_revision
);
325 if (info
->kernel_cmdline
&& *info
->kernel_cmdline
) {
329 cmdline_size
= strlen(info
->kernel_cmdline
);
330 address_space_write(as
, p
+ 8, MEMTXATTRS_UNSPECIFIED
,
331 (const uint8_t *)info
->kernel_cmdline
,
333 cmdline_size
= (cmdline_size
>> 2) + 1;
334 WRITE_WORD(p
, cmdline_size
+ 2);
335 WRITE_WORD(p
, 0x54410009);
336 p
+= cmdline_size
* 4;
338 if (info
->atag_board
) {
341 uint8_t atag_board_buf
[0x1000];
343 atag_board_len
= (info
->atag_board(info
, atag_board_buf
) + 3) & ~3;
344 WRITE_WORD(p
, (atag_board_len
+ 8) >> 2);
345 WRITE_WORD(p
, 0x414f4d50);
346 address_space_write(as
, p
, MEMTXATTRS_UNSPECIFIED
,
347 atag_board_buf
, atag_board_len
);
355 static void set_kernel_args_old(const struct arm_boot_info
*info
,
360 int initrd_size
= info
->initrd_size
;
361 hwaddr base
= info
->loader_start
;
363 /* see linux/include/asm-arm/setup.h */
364 p
= base
+ KERNEL_ARGS_ADDR
;
368 WRITE_WORD(p
, info
->ram_size
/ 4096);
371 #define FLAG_READONLY 1
372 #define FLAG_RDLOAD 4
373 #define FLAG_RDPROMPT 8
375 WRITE_WORD(p
, FLAG_READONLY
| FLAG_RDLOAD
| FLAG_RDPROMPT
);
377 WRITE_WORD(p
, (31 << 8) | 0); /* /dev/mtdblock0 */
386 /* memc_control_reg */
388 /* unsigned char sounddefault */
389 /* unsigned char adfsdrives */
390 /* unsigned char bytes_per_char_h */
391 /* unsigned char bytes_per_char_v */
393 /* pages_in_bank[4] */
402 WRITE_WORD(p
, info
->initrd_start
);
407 WRITE_WORD(p
, initrd_size
);
412 /* system_serial_low */
414 /* system_serial_high */
418 /* zero unused fields */
419 while (p
< base
+ KERNEL_ARGS_ADDR
+ 256 + 1024) {
422 s
= info
->kernel_cmdline
;
424 address_space_write(as
, p
, MEMTXATTRS_UNSPECIFIED
,
425 (const uint8_t *)s
, strlen(s
) + 1);
431 static void fdt_add_psci_node(void *fdt
)
433 uint32_t cpu_suspend_fn
;
437 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(0));
438 const char *psci_method
;
439 int64_t psci_conduit
;
442 psci_conduit
= object_property_get_int(OBJECT(armcpu
),
445 switch (psci_conduit
) {
446 case QEMU_PSCI_CONDUIT_DISABLED
:
448 case QEMU_PSCI_CONDUIT_HVC
:
451 case QEMU_PSCI_CONDUIT_SMC
:
455 g_assert_not_reached();
459 * If /psci node is present in provided DTB, assume that no fixup
460 * is necessary and all PSCI configuration should be taken as-is
462 rc
= fdt_path_offset(fdt
, "/psci");
467 qemu_fdt_add_subnode(fdt
, "/psci");
468 if (armcpu
->psci_version
== 2) {
469 const char comp
[] = "arm,psci-0.2\0arm,psci";
470 qemu_fdt_setprop(fdt
, "/psci", "compatible", comp
, sizeof(comp
));
472 cpu_off_fn
= QEMU_PSCI_0_2_FN_CPU_OFF
;
473 if (arm_feature(&armcpu
->env
, ARM_FEATURE_AARCH64
)) {
474 cpu_suspend_fn
= QEMU_PSCI_0_2_FN64_CPU_SUSPEND
;
475 cpu_on_fn
= QEMU_PSCI_0_2_FN64_CPU_ON
;
476 migrate_fn
= QEMU_PSCI_0_2_FN64_MIGRATE
;
478 cpu_suspend_fn
= QEMU_PSCI_0_2_FN_CPU_SUSPEND
;
479 cpu_on_fn
= QEMU_PSCI_0_2_FN_CPU_ON
;
480 migrate_fn
= QEMU_PSCI_0_2_FN_MIGRATE
;
483 qemu_fdt_setprop_string(fdt
, "/psci", "compatible", "arm,psci");
485 cpu_suspend_fn
= QEMU_PSCI_0_1_FN_CPU_SUSPEND
;
486 cpu_off_fn
= QEMU_PSCI_0_1_FN_CPU_OFF
;
487 cpu_on_fn
= QEMU_PSCI_0_1_FN_CPU_ON
;
488 migrate_fn
= QEMU_PSCI_0_1_FN_MIGRATE
;
491 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer
492 * to the instruction that should be used to invoke PSCI functions.
493 * However, the device tree binding uses 'method' instead, so that is
494 * what we should use here.
496 qemu_fdt_setprop_string(fdt
, "/psci", "method", psci_method
);
498 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_suspend", cpu_suspend_fn
);
499 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_off", cpu_off_fn
);
500 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_on", cpu_on_fn
);
501 qemu_fdt_setprop_cell(fdt
, "/psci", "migrate", migrate_fn
);
504 int arm_load_dtb(hwaddr addr
, const struct arm_boot_info
*binfo
,
505 hwaddr addr_limit
, AddressSpace
*as
)
509 uint32_t acells
, scells
;
512 hwaddr mem_base
, mem_len
;
516 if (binfo
->dtb_filename
) {
518 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, binfo
->dtb_filename
);
520 fprintf(stderr
, "Couldn't open dtb file %s\n", binfo
->dtb_filename
);
524 fdt
= load_device_tree(filename
, &size
);
526 fprintf(stderr
, "Couldn't open dtb file %s\n", filename
);
532 fdt
= binfo
->get_dtb(binfo
, &size
);
534 fprintf(stderr
, "Board was unable to create a dtb blob\n");
539 if (addr_limit
> addr
&& size
> (addr_limit
- addr
)) {
540 /* Installing the device tree blob at addr would exceed addr_limit.
541 * Whether this constitutes failure is up to the caller to decide,
542 * so just return 0 as size, i.e., no error.
548 acells
= qemu_fdt_getprop_cell(fdt
, "/", "#address-cells",
550 scells
= qemu_fdt_getprop_cell(fdt
, "/", "#size-cells",
552 if (acells
== 0 || scells
== 0) {
553 fprintf(stderr
, "dtb file invalid (#address-cells or #size-cells 0)\n");
557 if (scells
< 2 && binfo
->ram_size
>= (1ULL << 32)) {
558 /* This is user error so deserves a friendlier error message
559 * than the failure of setprop_sized_cells would provide
561 fprintf(stderr
, "qemu: dtb file not compatible with "
566 /* nop all root nodes matching /memory or /memory@unit-address */
567 node_path
= qemu_fdt_node_unit_path(fdt
, "memory", &err
);
569 error_report_err(err
);
572 while (node_path
[n
]) {
573 if (g_str_has_prefix(node_path
[n
], "/memory")) {
574 qemu_fdt_nop_node(fdt
, node_path
[n
]);
578 g_strfreev(node_path
);
580 if (nb_numa_nodes
> 0) {
581 mem_base
= binfo
->loader_start
;
582 for (i
= 0; i
< nb_numa_nodes
; i
++) {
583 mem_len
= numa_info
[i
].node_mem
;
584 nodename
= g_strdup_printf("/memory@%" PRIx64
, mem_base
);
585 qemu_fdt_add_subnode(fdt
, nodename
);
586 qemu_fdt_setprop_string(fdt
, nodename
, "device_type", "memory");
587 rc
= qemu_fdt_setprop_sized_cells(fdt
, nodename
, "reg",
591 fprintf(stderr
, "couldn't set %s/reg for node %d\n", nodename
,
596 qemu_fdt_setprop_cell(fdt
, nodename
, "numa-node-id", i
);
601 nodename
= g_strdup_printf("/memory@%" PRIx64
, binfo
->loader_start
);
602 qemu_fdt_add_subnode(fdt
, nodename
);
603 qemu_fdt_setprop_string(fdt
, nodename
, "device_type", "memory");
605 rc
= qemu_fdt_setprop_sized_cells(fdt
, nodename
, "reg",
606 acells
, binfo
->loader_start
,
607 scells
, binfo
->ram_size
);
609 fprintf(stderr
, "couldn't set %s reg\n", nodename
);
615 rc
= fdt_path_offset(fdt
, "/chosen");
617 qemu_fdt_add_subnode(fdt
, "/chosen");
620 if (binfo
->kernel_cmdline
&& *binfo
->kernel_cmdline
) {
621 rc
= qemu_fdt_setprop_string(fdt
, "/chosen", "bootargs",
622 binfo
->kernel_cmdline
);
624 fprintf(stderr
, "couldn't set /chosen/bootargs\n");
629 if (binfo
->initrd_size
) {
630 rc
= qemu_fdt_setprop_cell(fdt
, "/chosen", "linux,initrd-start",
631 binfo
->initrd_start
);
633 fprintf(stderr
, "couldn't set /chosen/linux,initrd-start\n");
637 rc
= qemu_fdt_setprop_cell(fdt
, "/chosen", "linux,initrd-end",
638 binfo
->initrd_start
+ binfo
->initrd_size
);
640 fprintf(stderr
, "couldn't set /chosen/linux,initrd-end\n");
645 fdt_add_psci_node(fdt
);
647 if (binfo
->modify_dtb
) {
648 binfo
->modify_dtb(binfo
, fdt
);
651 qemu_fdt_dumpdtb(fdt
, size
);
653 /* Put the DTB into the memory map as a ROM image: this will ensure
654 * the DTB is copied again upon reset, even if addr points into RAM.
656 rom_add_blob_fixed_as("dtb", fdt
, size
, addr
, as
);
667 static void do_cpu_reset(void *opaque
)
669 ARMCPU
*cpu
= opaque
;
670 CPUState
*cs
= CPU(cpu
);
671 CPUARMState
*env
= &cpu
->env
;
672 const struct arm_boot_info
*info
= env
->boot_info
;
676 if (!info
->is_linux
) {
678 /* Jump to the entry point. */
679 uint64_t entry
= info
->entry
;
681 switch (info
->endianness
) {
682 case ARM_ENDIANNESS_LE
:
683 env
->cp15
.sctlr_el
[1] &= ~SCTLR_E0E
;
684 for (i
= 1; i
< 4; ++i
) {
685 env
->cp15
.sctlr_el
[i
] &= ~SCTLR_EE
;
687 env
->uncached_cpsr
&= ~CPSR_E
;
689 case ARM_ENDIANNESS_BE8
:
690 env
->cp15
.sctlr_el
[1] |= SCTLR_E0E
;
691 for (i
= 1; i
< 4; ++i
) {
692 env
->cp15
.sctlr_el
[i
] |= SCTLR_EE
;
694 env
->uncached_cpsr
|= CPSR_E
;
696 case ARM_ENDIANNESS_BE32
:
697 env
->cp15
.sctlr_el
[1] |= SCTLR_B
;
699 case ARM_ENDIANNESS_UNKNOWN
:
700 break; /* Board's decision */
702 g_assert_not_reached();
706 env
->thumb
= info
->entry
& 1;
709 cpu_set_pc(cs
, entry
);
711 /* If we are booting Linux then we need to check whether we are
712 * booting into secure or non-secure state and adjust the state
713 * accordingly. Out of reset, ARM is defined to be in secure state
714 * (SCR.NS = 0), we change that here if non-secure boot has been
717 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
718 /* AArch64 is defined to come out of reset into EL3 if enabled.
719 * If we are booting Linux then we need to adjust our EL as
720 * Linux expects us to be in EL2 or EL1. AArch32 resets into
721 * SVC, which Linux expects, so no privilege/exception level to
725 env
->cp15
.scr_el3
|= SCR_RW
;
726 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
727 env
->cp15
.hcr_el2
|= HCR_RW
;
728 env
->pstate
= PSTATE_MODE_EL2h
;
730 env
->pstate
= PSTATE_MODE_EL1h
;
732 /* AArch64 kernels never boot in secure mode */
733 assert(!info
->secure_boot
);
734 /* This hook is only supported for AArch32 currently:
735 * bootloader_aarch64[] will not call the hook, and
736 * the code above has already dropped us into EL2 or EL1.
738 assert(!info
->secure_board_setup
);
741 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
742 /* If we have EL2 then Linux expects the HVC insn to work */
743 env
->cp15
.scr_el3
|= SCR_HCE
;
746 /* Set to non-secure if not a secure boot */
747 if (!info
->secure_boot
&&
748 (cs
!= first_cpu
|| !info
->secure_board_setup
)) {
749 /* Linux expects non-secure state */
750 env
->cp15
.scr_el3
|= SCR_NS
;
754 if (!env
->aarch64
&& !info
->secure_boot
&&
755 arm_feature(env
, ARM_FEATURE_EL2
)) {
757 * This is an AArch32 boot not to Secure state, and
758 * we have Hyp mode available, so boot the kernel into
759 * Hyp mode. This is not how the CPU comes out of reset,
760 * so we need to manually put it there.
762 cpsr_write(env
, ARM_CPU_MODE_HYP
, CPSR_M
, CPSRWriteRaw
);
765 if (cs
== first_cpu
) {
766 AddressSpace
*as
= arm_boot_address_space(cpu
, info
);
768 cpu_set_pc(cs
, info
->loader_start
);
770 if (!have_dtb(info
)) {
772 set_kernel_args_old(info
, as
);
774 set_kernel_args(info
, as
);
778 info
->secondary_cpu_reset_hook(cpu
, info
);
785 * load_image_to_fw_cfg() - Load an image file into an fw_cfg entry identified
787 * @fw_cfg: The firmware config instance to store the data in.
788 * @size_key: The firmware config key to store the size of the loaded
789 * data under, with fw_cfg_add_i32().
790 * @data_key: The firmware config key to store the loaded data under,
791 * with fw_cfg_add_bytes().
792 * @image_name: The name of the image file to load. If it is NULL, the
793 * function returns without doing anything.
794 * @try_decompress: Whether the image should be decompressed (gunzipped) before
795 * adding it to fw_cfg. If decompression fails, the image is
798 * In case of failure, the function prints an error message to stderr and the
799 * process exits with status 1.
801 static void load_image_to_fw_cfg(FWCfgState
*fw_cfg
, uint16_t size_key
,
802 uint16_t data_key
, const char *image_name
,
808 if (image_name
== NULL
) {
812 if (try_decompress
) {
813 size
= load_image_gzipped_buffer(image_name
,
814 LOAD_IMAGE_MAX_GUNZIP_BYTES
, &data
);
817 if (size
== (size_t)-1) {
821 if (!g_file_get_contents(image_name
, &contents
, &length
, NULL
)) {
822 error_report("failed to load \"%s\"", image_name
);
826 data
= (uint8_t *)contents
;
829 fw_cfg_add_i32(fw_cfg
, size_key
, size
);
830 fw_cfg_add_bytes(fw_cfg
, data_key
, data
, size
);
833 static int do_arm_linux_init(Object
*obj
, void *opaque
)
835 if (object_dynamic_cast(obj
, TYPE_ARM_LINUX_BOOT_IF
)) {
836 ARMLinuxBootIf
*albif
= ARM_LINUX_BOOT_IF(obj
);
837 ARMLinuxBootIfClass
*albifc
= ARM_LINUX_BOOT_IF_GET_CLASS(obj
);
838 struct arm_boot_info
*info
= opaque
;
840 if (albifc
->arm_linux_init
) {
841 albifc
->arm_linux_init(albif
, info
->secure_boot
);
847 static int64_t arm_load_elf(struct arm_boot_info
*info
, uint64_t *pentry
,
848 uint64_t *lowaddr
, uint64_t *highaddr
,
849 int elf_machine
, AddressSpace
*as
)
862 load_elf_hdr(info
->kernel_filename
, &elf_header
, &elf_is64
, &err
);
869 big_endian
= elf_header
.h64
.e_ident
[EI_DATA
] == ELFDATA2MSB
;
870 info
->endianness
= big_endian
? ARM_ENDIANNESS_BE8
873 big_endian
= elf_header
.h32
.e_ident
[EI_DATA
] == ELFDATA2MSB
;
875 if (bswap32(elf_header
.h32
.e_flags
) & EF_ARM_BE8
) {
876 info
->endianness
= ARM_ENDIANNESS_BE8
;
878 info
->endianness
= ARM_ENDIANNESS_BE32
;
879 /* In BE32, the CPU has a different view of the per-byte
880 * address map than the rest of the system. BE32 ELF files
881 * are organised such that they can be programmed through
882 * the CPU's per-word byte-reversed view of the world. QEMU
883 * however loads ELF files independently of the CPU. So
884 * tell the ELF loader to byte reverse the data for us.
889 info
->endianness
= ARM_ENDIANNESS_LE
;
893 ret
= load_elf_as(info
->kernel_filename
, NULL
, NULL
,
894 pentry
, lowaddr
, highaddr
, big_endian
, elf_machine
,
897 /* The header loaded but the image didn't */
904 static uint64_t load_aarch64_image(const char *filename
, hwaddr mem_base
,
905 hwaddr
*entry
, AddressSpace
*as
)
907 hwaddr kernel_load_offset
= KERNEL64_LOAD_ADDR
;
911 /* On aarch64, it's the bootloader's job to uncompress the kernel. */
912 size
= load_image_gzipped_buffer(filename
, LOAD_IMAGE_MAX_GUNZIP_BYTES
,
918 /* Load as raw file otherwise */
919 if (!g_file_get_contents(filename
, (char **)&buffer
, &len
, NULL
)) {
925 /* check the arm64 magic header value -- very old kernels may not have it */
926 if (size
> ARM64_MAGIC_OFFSET
+ 4 &&
927 memcmp(buffer
+ ARM64_MAGIC_OFFSET
, "ARM\x64", 4) == 0) {
930 /* The arm64 Image header has text_offset and image_size fields at 8 and
931 * 16 bytes into the Image header, respectively. The text_offset field
932 * is only valid if the image_size is non-zero.
934 memcpy(&hdrvals
, buffer
+ ARM64_TEXT_OFFSET_OFFSET
, sizeof(hdrvals
));
935 if (hdrvals
[1] != 0) {
936 kernel_load_offset
= le64_to_cpu(hdrvals
[0]);
939 * We write our startup "bootloader" at the very bottom of RAM,
940 * so that bit can't be used for the image. Luckily the Image
941 * format specification is that the image requests only an offset
942 * from a 2MB boundary, not an absolute load address. So if the
943 * image requests an offset that might mean it overlaps with the
944 * bootloader, we can just load it starting at 2MB+offset rather
947 if (kernel_load_offset
< BOOTLOADER_MAX_SIZE
) {
948 kernel_load_offset
+= 2 * MiB
;
953 *entry
= mem_base
+ kernel_load_offset
;
954 rom_add_blob_fixed_as(filename
, buffer
, size
, *entry
, as
);
961 void arm_load_kernel(ARMCPU
*cpu
, struct arm_boot_info
*info
)
967 uint64_t elf_entry
, elf_low_addr
, elf_high_addr
;
970 static const ARMInsnFixup
*primary_loader
;
971 AddressSpace
*as
= arm_boot_address_space(cpu
, info
);
973 /* CPU objects (unlike devices) are not automatically reset on system
974 * reset, so we must always register a handler to do so. If we're
975 * actually loading a kernel, the handler is also responsible for
976 * arranging that we start it correctly.
978 for (cs
= first_cpu
; cs
; cs
= CPU_NEXT(cs
)) {
979 qemu_register_reset(do_cpu_reset
, ARM_CPU(cs
));
982 /* The board code is not supposed to set secure_board_setup unless
983 * running its code in secure mode is actually possible, and KVM
984 * doesn't support secure.
986 assert(!(info
->secure_board_setup
&& kvm_enabled()));
988 info
->dtb_filename
= qemu_opt_get(qemu_get_machine_opts(), "dtb");
991 /* Load the kernel. */
992 if (!info
->kernel_filename
|| info
->firmware_loaded
) {
994 if (have_dtb(info
)) {
995 /* If we have a device tree blob, but no kernel to supply it to (or
996 * the kernel is supposed to be loaded by the bootloader), copy the
997 * DTB to the base of RAM for the bootloader to pick up.
999 info
->dtb_start
= info
->loader_start
;
1002 if (info
->kernel_filename
) {
1004 bool try_decompressing_kernel
;
1006 fw_cfg
= fw_cfg_find();
1007 try_decompressing_kernel
= arm_feature(&cpu
->env
,
1008 ARM_FEATURE_AARCH64
);
1010 /* Expose the kernel, the command line, and the initrd in fw_cfg.
1011 * We don't process them here at all, it's all left to the
1014 load_image_to_fw_cfg(fw_cfg
,
1015 FW_CFG_KERNEL_SIZE
, FW_CFG_KERNEL_DATA
,
1016 info
->kernel_filename
,
1017 try_decompressing_kernel
);
1018 load_image_to_fw_cfg(fw_cfg
,
1019 FW_CFG_INITRD_SIZE
, FW_CFG_INITRD_DATA
,
1020 info
->initrd_filename
, false);
1022 if (info
->kernel_cmdline
) {
1023 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
,
1024 strlen(info
->kernel_cmdline
) + 1);
1025 fw_cfg_add_string(fw_cfg
, FW_CFG_CMDLINE_DATA
,
1026 info
->kernel_cmdline
);
1030 /* We will start from address 0 (typically a boot ROM image) in the
1031 * same way as hardware.
1036 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1037 primary_loader
= bootloader_aarch64
;
1038 elf_machine
= EM_AARCH64
;
1040 primary_loader
= bootloader
;
1041 if (!info
->write_board_setup
) {
1042 primary_loader
+= BOOTLOADER_NO_BOARD_SETUP_OFFSET
;
1044 elf_machine
= EM_ARM
;
1047 if (!info
->secondary_cpu_reset_hook
) {
1048 info
->secondary_cpu_reset_hook
= default_reset_secondary
;
1050 if (!info
->write_secondary_boot
) {
1051 info
->write_secondary_boot
= default_write_secondary
;
1054 if (info
->nb_cpus
== 0)
1057 /* We want to put the initrd far enough into RAM that when the
1058 * kernel is uncompressed it will not clobber the initrd. However
1059 * on boards without much RAM we must ensure that we still leave
1060 * enough room for a decent sized initrd, and on boards with large
1061 * amounts of RAM we must avoid the initrd being so far up in RAM
1062 * that it is outside lowmem and inaccessible to the kernel.
1063 * So for boards with less than 256MB of RAM we put the initrd
1064 * halfway into RAM, and for boards with 256MB of RAM or more we put
1065 * the initrd at 128MB.
1067 info
->initrd_start
= info
->loader_start
+
1068 MIN(info
->ram_size
/ 2, 128 * 1024 * 1024);
1070 /* Assume that raw images are linux kernels, and ELF images are not. */
1071 /* If the filename contains 'vmlinux', assume ELF images are linux, too. */
1072 is_linux
= (strstr(info
->kernel_filename
, "vmlinux") != NULL
);
1073 kernel_size
= arm_load_elf(info
, &elf_entry
, &elf_low_addr
,
1074 &elf_high_addr
, elf_machine
, as
);
1075 if (kernel_size
> 0 && have_dtb(info
)) {
1076 /* If there is still some room left at the base of RAM, try and put
1077 * the DTB there like we do for images loaded with -bios or -pflash.
1079 if (elf_low_addr
> info
->loader_start
1080 || elf_high_addr
< info
->loader_start
) {
1081 /* Set elf_low_addr as address limit for arm_load_dtb if it may be
1082 * pointing into RAM, otherwise pass '0' (no limit)
1084 if (elf_low_addr
< info
->loader_start
) {
1087 info
->dtb_start
= info
->loader_start
;
1088 info
->dtb_limit
= elf_low_addr
;
1092 if (kernel_size
< 0) {
1093 kernel_size
= load_uimage_as(info
->kernel_filename
, &entry
, NULL
,
1094 &is_linux
, NULL
, NULL
, as
);
1096 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
) && kernel_size
< 0) {
1097 kernel_size
= load_aarch64_image(info
->kernel_filename
,
1098 info
->loader_start
, &entry
, as
);
1100 } else if (entry
== info
->loader_start
) {
1101 /* Don't map bootloader memory if it conflicts with the kernel image. */
1103 } else if (kernel_size
< 0) {
1105 entry
= info
->loader_start
+ KERNEL_LOAD_ADDR
;
1106 kernel_size
= load_image_targphys_as(info
->kernel_filename
, entry
,
1107 info
->ram_size
- KERNEL_LOAD_ADDR
,
1111 if (kernel_size
< 0) {
1112 error_report("could not load kernel '%s'", info
->kernel_filename
);
1115 info
->entry
= entry
;
1117 uint32_t fixupcontext
[FIXUP_MAX
];
1119 if (info
->initrd_filename
) {
1120 initrd_size
= load_ramdisk_as(info
->initrd_filename
,
1122 info
->ram_size
- info
->initrd_start
,
1124 if (initrd_size
< 0) {
1125 initrd_size
= load_image_targphys_as(info
->initrd_filename
,
1131 if (initrd_size
< 0) {
1132 error_report("could not load initrd '%s'",
1133 info
->initrd_filename
);
1139 info
->initrd_size
= initrd_size
;
1141 fixupcontext
[FIXUP_BOARDID
] = info
->board_id
;
1142 fixupcontext
[FIXUP_BOARD_SETUP
] = info
->board_setup_addr
;
1144 /* for device tree boot, we pass the DTB directly in r2. Otherwise
1145 * we point to the kernel args.
1147 if (have_dtb(info
)) {
1150 if (elf_machine
== EM_AARCH64
) {
1152 * Some AArch64 kernels on early bootup map the fdt region as
1154 * [ ALIGN_DOWN(fdt, 2MB) ... ALIGN_DOWN(fdt, 2MB) + 2MB ]
1156 * Let's play safe and prealign it to 2MB to give us some space.
1158 align
= 2 * 1024 * 1024;
1161 * Some 32bit kernels will trash anything in the 4K page the
1162 * initrd ends in, so make sure the DTB isn't caught up in that.
1167 /* Place the DTB after the initrd in memory with alignment. */
1168 info
->dtb_start
= QEMU_ALIGN_UP(info
->initrd_start
+ initrd_size
,
1170 fixupcontext
[FIXUP_ARGPTR_LO
] = info
->dtb_start
;
1171 fixupcontext
[FIXUP_ARGPTR_HI
] = info
->dtb_start
>> 32;
1173 fixupcontext
[FIXUP_ARGPTR_LO
] =
1174 info
->loader_start
+ KERNEL_ARGS_ADDR
;
1175 fixupcontext
[FIXUP_ARGPTR_HI
] =
1176 (info
->loader_start
+ KERNEL_ARGS_ADDR
) >> 32;
1177 if (info
->ram_size
>= (1ULL << 32)) {
1178 error_report("RAM size must be less than 4GB to boot"
1179 " Linux kernel using ATAGS (try passing a device tree"
1184 fixupcontext
[FIXUP_ENTRYPOINT_LO
] = entry
;
1185 fixupcontext
[FIXUP_ENTRYPOINT_HI
] = entry
>> 32;
1187 write_bootloader("bootloader", info
->loader_start
,
1188 primary_loader
, fixupcontext
, as
);
1190 if (info
->nb_cpus
> 1) {
1191 info
->write_secondary_boot(cpu
, info
);
1193 if (info
->write_board_setup
) {
1194 info
->write_board_setup(cpu
, info
);
1197 /* Notify devices which need to fake up firmware initialization
1198 * that we're doing a direct kernel boot.
1200 object_child_foreach_recursive(object_get_root(),
1201 do_arm_linux_init
, info
);
1203 info
->is_linux
= is_linux
;
1205 for (cs
= first_cpu
; cs
; cs
= CPU_NEXT(cs
)) {
1206 ARM_CPU(cs
)->env
.boot_info
= info
;
1209 if (!info
->skip_dtb_autoload
&& have_dtb(info
)) {
1210 if (arm_load_dtb(info
->dtb_start
, info
, info
->dtb_limit
, as
) < 0) {
1216 static const TypeInfo arm_linux_boot_if_info
= {
1217 .name
= TYPE_ARM_LINUX_BOOT_IF
,
1218 .parent
= TYPE_INTERFACE
,
1219 .class_size
= sizeof(ARMLinuxBootIfClass
),
1222 static void arm_linux_boot_register_types(void)
1224 type_register_static(&arm_linux_boot_if_info
);
1227 type_init(arm_linux_boot_register_types
)