4 * This code is licensed under the GNU GPL v2 or later.
6 * SPDX-License-Identifier: GPL-2.0-or-later
9 #include "qemu/osdep.h"
13 #include "internals.h"
14 #include "cpu-features.h"
15 #include "exec/helper-proto.h"
16 #include "qemu/main-loop.h"
17 #include "qemu/timer.h"
18 #include "qemu/bitops.h"
19 #include "qemu/crc32c.h"
20 #include "qemu/qemu-print.h"
21 #include "exec/exec-all.h"
22 #include <zlib.h> /* For crc32 */
24 #include "sysemu/cpu-timers.h"
25 #include "sysemu/kvm.h"
26 #include "sysemu/tcg.h"
27 #include "qapi/error.h"
28 #include "qemu/guest-random.h"
30 #include "semihosting/common-semi.h"
34 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
36 static void switch_mode(CPUARMState
*env
, int mode
);
38 static uint64_t raw_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
40 assert(ri
->fieldoffset
);
41 if (cpreg_field_is_64bit(ri
)) {
42 return CPREG_FIELD64(env
, ri
);
44 return CPREG_FIELD32(env
, ri
);
48 void raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
50 assert(ri
->fieldoffset
);
51 if (cpreg_field_is_64bit(ri
)) {
52 CPREG_FIELD64(env
, ri
) = value
;
54 CPREG_FIELD32(env
, ri
) = value
;
58 static void *raw_ptr(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
60 return (char *)env
+ ri
->fieldoffset
;
63 uint64_t read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
65 /* Raw read of a coprocessor register (as needed for migration, etc). */
66 if (ri
->type
& ARM_CP_CONST
) {
67 return ri
->resetvalue
;
68 } else if (ri
->raw_readfn
) {
69 return ri
->raw_readfn(env
, ri
);
70 } else if (ri
->readfn
) {
71 return ri
->readfn(env
, ri
);
73 return raw_read(env
, ri
);
77 static void write_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
81 * Raw write of a coprocessor register (as needed for migration, etc).
82 * Note that constant registers are treated as write-ignored; the
83 * caller should check for success by whether a readback gives the
86 if (ri
->type
& ARM_CP_CONST
) {
88 } else if (ri
->raw_writefn
) {
89 ri
->raw_writefn(env
, ri
, v
);
90 } else if (ri
->writefn
) {
91 ri
->writefn(env
, ri
, v
);
93 raw_write(env
, ri
, v
);
97 static bool raw_accessors_invalid(const ARMCPRegInfo
*ri
)
100 * Return true if the regdef would cause an assertion if you called
101 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
102 * program bug for it not to have the NO_RAW flag).
103 * NB that returning false here doesn't necessarily mean that calling
104 * read/write_raw_cp_reg() is safe, because we can't distinguish "has
105 * read/write access functions which are safe for raw use" from "has
106 * read/write access functions which have side effects but has forgotten
107 * to provide raw access functions".
108 * The tests here line up with the conditions in read/write_raw_cp_reg()
109 * and assertions in raw_read()/raw_write().
111 if ((ri
->type
& ARM_CP_CONST
) ||
113 ((ri
->raw_writefn
|| ri
->writefn
) && (ri
->raw_readfn
|| ri
->readfn
))) {
119 bool write_cpustate_to_list(ARMCPU
*cpu
, bool kvm_sync
)
121 /* Write the coprocessor state from cpu->env to the (index,value) list. */
125 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
126 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
127 const ARMCPRegInfo
*ri
;
130 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
135 if (ri
->type
& ARM_CP_NO_RAW
) {
139 newval
= read_raw_cp_reg(&cpu
->env
, ri
);
142 * Only sync if the previous list->cpustate sync succeeded.
143 * Rather than tracking the success/failure state for every
144 * item in the list, we just recheck "does the raw write we must
145 * have made in write_list_to_cpustate() read back OK" here.
147 uint64_t oldval
= cpu
->cpreg_values
[i
];
149 if (oldval
== newval
) {
153 write_raw_cp_reg(&cpu
->env
, ri
, oldval
);
154 if (read_raw_cp_reg(&cpu
->env
, ri
) != oldval
) {
158 write_raw_cp_reg(&cpu
->env
, ri
, newval
);
160 cpu
->cpreg_values
[i
] = newval
;
165 bool write_list_to_cpustate(ARMCPU
*cpu
)
170 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
171 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
172 uint64_t v
= cpu
->cpreg_values
[i
];
173 const ARMCPRegInfo
*ri
;
175 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
180 if (ri
->type
& ARM_CP_NO_RAW
) {
184 * Write value and confirm it reads back as written
185 * (to catch read-only registers and partially read-only
186 * registers where the incoming migration value doesn't match)
188 write_raw_cp_reg(&cpu
->env
, ri
, v
);
189 if (read_raw_cp_reg(&cpu
->env
, ri
) != v
) {
196 static void add_cpreg_to_list(gpointer key
, gpointer opaque
)
198 ARMCPU
*cpu
= opaque
;
199 uint32_t regidx
= (uintptr_t)key
;
200 const ARMCPRegInfo
*ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
202 if (!(ri
->type
& (ARM_CP_NO_RAW
| ARM_CP_ALIAS
))) {
203 cpu
->cpreg_indexes
[cpu
->cpreg_array_len
] = cpreg_to_kvm_id(regidx
);
204 /* The value array need not be initialized at this point */
205 cpu
->cpreg_array_len
++;
209 static void count_cpreg(gpointer key
, gpointer opaque
)
211 ARMCPU
*cpu
= opaque
;
212 const ARMCPRegInfo
*ri
;
214 ri
= g_hash_table_lookup(cpu
->cp_regs
, key
);
216 if (!(ri
->type
& (ARM_CP_NO_RAW
| ARM_CP_ALIAS
))) {
217 cpu
->cpreg_array_len
++;
221 static gint
cpreg_key_compare(gconstpointer a
, gconstpointer b
)
223 uint64_t aidx
= cpreg_to_kvm_id((uintptr_t)a
);
224 uint64_t bidx
= cpreg_to_kvm_id((uintptr_t)b
);
235 void init_cpreg_list(ARMCPU
*cpu
)
238 * Initialise the cpreg_tuples[] array based on the cp_regs hash.
239 * Note that we require cpreg_tuples[] to be sorted by key ID.
244 keys
= g_hash_table_get_keys(cpu
->cp_regs
);
245 keys
= g_list_sort(keys
, cpreg_key_compare
);
247 cpu
->cpreg_array_len
= 0;
249 g_list_foreach(keys
, count_cpreg
, cpu
);
251 arraylen
= cpu
->cpreg_array_len
;
252 cpu
->cpreg_indexes
= g_new(uint64_t, arraylen
);
253 cpu
->cpreg_values
= g_new(uint64_t, arraylen
);
254 cpu
->cpreg_vmstate_indexes
= g_new(uint64_t, arraylen
);
255 cpu
->cpreg_vmstate_values
= g_new(uint64_t, arraylen
);
256 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
257 cpu
->cpreg_array_len
= 0;
259 g_list_foreach(keys
, add_cpreg_to_list
, cpu
);
261 assert(cpu
->cpreg_array_len
== arraylen
);
267 * Some registers are not accessible from AArch32 EL3 if SCR.NS == 0.
269 static CPAccessResult
access_el3_aa32ns(CPUARMState
*env
,
270 const ARMCPRegInfo
*ri
,
273 if (!is_a64(env
) && arm_current_el(env
) == 3 &&
274 arm_is_secure_below_el3(env
)) {
275 return CP_ACCESS_TRAP_UNCATEGORIZED
;
281 * Some secure-only AArch32 registers trap to EL3 if used from
282 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
283 * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
284 * We assume that the .access field is set to PL1_RW.
286 static CPAccessResult
access_trap_aa32s_el1(CPUARMState
*env
,
287 const ARMCPRegInfo
*ri
,
290 if (arm_current_el(env
) == 3) {
293 if (arm_is_secure_below_el3(env
)) {
294 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
295 return CP_ACCESS_TRAP_EL2
;
297 return CP_ACCESS_TRAP_EL3
;
299 /* This will be EL1 NS and EL2 NS, which just UNDEF */
300 return CP_ACCESS_TRAP_UNCATEGORIZED
;
304 * Check for traps to performance monitor registers, which are controlled
305 * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
307 static CPAccessResult
access_tpm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
310 int el
= arm_current_el(env
);
311 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
313 if (el
< 2 && (mdcr_el2
& MDCR_TPM
)) {
314 return CP_ACCESS_TRAP_EL2
;
316 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
317 return CP_ACCESS_TRAP_EL3
;
322 /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */
323 CPAccessResult
access_tvm_trvm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
326 if (arm_current_el(env
) == 1) {
327 uint64_t trap
= isread
? HCR_TRVM
: HCR_TVM
;
328 if (arm_hcr_el2_eff(env
) & trap
) {
329 return CP_ACCESS_TRAP_EL2
;
335 /* Check for traps from EL1 due to HCR_EL2.TSW. */
336 static CPAccessResult
access_tsw(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
339 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TSW
)) {
340 return CP_ACCESS_TRAP_EL2
;
345 /* Check for traps from EL1 due to HCR_EL2.TACR. */
346 static CPAccessResult
access_tacr(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
349 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TACR
)) {
350 return CP_ACCESS_TRAP_EL2
;
355 /* Check for traps from EL1 due to HCR_EL2.TTLB. */
356 static CPAccessResult
access_ttlb(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
359 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TTLB
)) {
360 return CP_ACCESS_TRAP_EL2
;
365 /* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBIS. */
366 static CPAccessResult
access_ttlbis(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
369 if (arm_current_el(env
) == 1 &&
370 (arm_hcr_el2_eff(env
) & (HCR_TTLB
| HCR_TTLBIS
))) {
371 return CP_ACCESS_TRAP_EL2
;
376 #ifdef TARGET_AARCH64
377 /* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBOS. */
378 static CPAccessResult
access_ttlbos(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
381 if (arm_current_el(env
) == 1 &&
382 (arm_hcr_el2_eff(env
) & (HCR_TTLB
| HCR_TTLBOS
))) {
383 return CP_ACCESS_TRAP_EL2
;
389 static void dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
391 ARMCPU
*cpu
= env_archcpu(env
);
393 raw_write(env
, ri
, value
);
394 tlb_flush(CPU(cpu
)); /* Flush TLB as domain not tracked in TLB */
397 static void fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
399 ARMCPU
*cpu
= env_archcpu(env
);
401 if (raw_read(env
, ri
) != value
) {
403 * Unlike real hardware the qemu TLB uses virtual addresses,
404 * not modified virtual addresses, so this causes a TLB flush.
407 raw_write(env
, ri
, value
);
411 static void contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
414 ARMCPU
*cpu
= env_archcpu(env
);
416 if (raw_read(env
, ri
) != value
&& !arm_feature(env
, ARM_FEATURE_PMSA
)
417 && !extended_addresses_enabled(env
)) {
419 * For VMSA (when not using the LPAE long descriptor page table
420 * format) this register includes the ASID, so do a TLB flush.
421 * For PMSA it is purely a process ID and no action is needed.
425 raw_write(env
, ri
, value
);
428 static int alle1_tlbmask(CPUARMState
*env
)
431 * Note that the 'ALL' scope must invalidate both stage 1 and
432 * stage 2 translations, whereas most other scopes only invalidate
433 * stage 1 translations.
435 return (ARMMMUIdxBit_E10_1
|
436 ARMMMUIdxBit_E10_1_PAN
|
438 ARMMMUIdxBit_Stage2
|
439 ARMMMUIdxBit_Stage2_S
);
443 /* IS variants of TLB operations must affect all cores */
444 static void tlbiall_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
447 CPUState
*cs
= env_cpu(env
);
449 tlb_flush_all_cpus_synced(cs
);
452 static void tlbiasid_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
455 CPUState
*cs
= env_cpu(env
);
457 tlb_flush_all_cpus_synced(cs
);
460 static void tlbimva_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
463 CPUState
*cs
= env_cpu(env
);
465 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
468 static void tlbimvaa_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
471 CPUState
*cs
= env_cpu(env
);
473 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
477 * Non-IS variants of TLB operations are upgraded to
478 * IS versions if we are at EL1 and HCR_EL2.FB is effectively set to
479 * force broadcast of these operations.
481 static bool tlb_force_broadcast(CPUARMState
*env
)
483 return arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_FB
);
486 static void tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
489 /* Invalidate all (TLBIALL) */
490 CPUState
*cs
= env_cpu(env
);
492 if (tlb_force_broadcast(env
)) {
493 tlb_flush_all_cpus_synced(cs
);
499 static void tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
502 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
503 CPUState
*cs
= env_cpu(env
);
505 value
&= TARGET_PAGE_MASK
;
506 if (tlb_force_broadcast(env
)) {
507 tlb_flush_page_all_cpus_synced(cs
, value
);
509 tlb_flush_page(cs
, value
);
513 static void tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
516 /* Invalidate by ASID (TLBIASID) */
517 CPUState
*cs
= env_cpu(env
);
519 if (tlb_force_broadcast(env
)) {
520 tlb_flush_all_cpus_synced(cs
);
526 static void tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
529 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
530 CPUState
*cs
= env_cpu(env
);
532 value
&= TARGET_PAGE_MASK
;
533 if (tlb_force_broadcast(env
)) {
534 tlb_flush_page_all_cpus_synced(cs
, value
);
536 tlb_flush_page(cs
, value
);
540 static void tlbiall_nsnh_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
543 CPUState
*cs
= env_cpu(env
);
545 tlb_flush_by_mmuidx(cs
, alle1_tlbmask(env
));
548 static void tlbiall_nsnh_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
551 CPUState
*cs
= env_cpu(env
);
553 tlb_flush_by_mmuidx_all_cpus_synced(cs
, alle1_tlbmask(env
));
557 static void tlbiall_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
560 CPUState
*cs
= env_cpu(env
);
562 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_E2
);
565 static void tlbiall_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
568 CPUState
*cs
= env_cpu(env
);
570 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_E2
);
573 static void tlbimva_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
576 CPUState
*cs
= env_cpu(env
);
577 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
579 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_E2
);
582 static void tlbimva_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
585 CPUState
*cs
= env_cpu(env
);
586 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
588 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
592 static void tlbiipas2_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
595 CPUState
*cs
= env_cpu(env
);
596 uint64_t pageaddr
= (value
& MAKE_64BIT_MASK(0, 28)) << 12;
598 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_Stage2
);
601 static void tlbiipas2is_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
604 CPUState
*cs
= env_cpu(env
);
605 uint64_t pageaddr
= (value
& MAKE_64BIT_MASK(0, 28)) << 12;
607 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
, ARMMMUIdxBit_Stage2
);
610 static const ARMCPRegInfo cp_reginfo
[] = {
612 * Define the secure and non-secure FCSE identifier CP registers
613 * separately because there is no secure bank in V8 (no _EL3). This allows
614 * the secure register to be properly reset and migrated. There is also no
615 * v8 EL1 version of the register so the non-secure instance stands alone.
618 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
619 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
620 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_ns
),
621 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
622 { .name
= "FCSEIDR_S",
623 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
624 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
625 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_s
),
626 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
628 * Define the secure and non-secure context identifier CP registers
629 * separately because there is no secure bank in V8 (no _EL3). This allows
630 * the secure register to be properly reset and migrated. In the
631 * non-secure case, the 32-bit register will have reset and migration
632 * disabled during registration as it is handled by the 64-bit instance.
634 { .name
= "CONTEXTIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
635 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
636 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
637 .fgt
= FGT_CONTEXTIDR_EL1
,
638 .secure
= ARM_CP_SECSTATE_NS
,
639 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[1]),
640 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
641 { .name
= "CONTEXTIDR_S", .state
= ARM_CP_STATE_AA32
,
642 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
643 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
644 .secure
= ARM_CP_SECSTATE_S
,
645 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_s
),
646 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
649 static const ARMCPRegInfo not_v8_cp_reginfo
[] = {
651 * NB: Some of these registers exist in v8 but with more precise
652 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
654 /* MMU Domain access control / MPU write buffer control */
656 .cp
= 15, .opc1
= CP_ANY
, .crn
= 3, .crm
= CP_ANY
, .opc2
= CP_ANY
,
657 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
658 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
659 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
660 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
662 * ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
663 * For v6 and v5, these mappings are overly broad.
665 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 0,
666 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
667 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 1,
668 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
669 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 4,
670 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
671 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 8,
672 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
673 /* Cache maintenance ops; some of this space may be overridden later. */
674 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
675 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
676 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
679 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
681 * Not all pre-v6 cores implemented this WFI, so this is slightly
684 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
685 .access
= PL1_W
, .type
= ARM_CP_WFI
},
688 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
690 * Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
691 * is UNPREDICTABLE; we choose to NOP as most implementations do).
693 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
694 .access
= PL1_W
, .type
= ARM_CP_WFI
},
696 * L1 cache lockdown. Not architectural in v6 and earlier but in practice
697 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
698 * OMAPCP will override this space.
700 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
701 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
703 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
704 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
706 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
707 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
708 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
711 * We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
712 * implementing it as RAZ means the "debug architecture version" bits
713 * will read as a reserved value, which should cause Linux to not try
714 * to use the debug hardware.
716 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
717 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
719 * MMU TLB control. Note that the wildcarding means we cover not just
720 * the unified TLB ops but also the dside/iside/inner-shareable variants.
722 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
723 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
,
724 .type
= ARM_CP_NO_RAW
},
725 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
726 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
,
727 .type
= ARM_CP_NO_RAW
},
728 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
729 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
,
730 .type
= ARM_CP_NO_RAW
},
731 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
732 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
,
733 .type
= ARM_CP_NO_RAW
},
734 { .name
= "PRRR", .cp
= 15, .crn
= 10, .crm
= 2,
735 .opc1
= 0, .opc2
= 0, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
736 { .name
= "NMRR", .cp
= 15, .crn
= 10, .crm
= 2,
737 .opc1
= 0, .opc2
= 1, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
740 static void cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
745 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
746 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
748 * ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
749 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
750 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
752 if (cpu_isar_feature(aa32_vfp_simd
, env_archcpu(env
))) {
753 /* VFP coprocessor: cp10 & cp11 [23:20] */
754 mask
|= R_CPACR_ASEDIS_MASK
|
755 R_CPACR_D32DIS_MASK
|
759 if (!arm_feature(env
, ARM_FEATURE_NEON
)) {
760 /* ASEDIS [31] bit is RAO/WI */
761 value
|= R_CPACR_ASEDIS_MASK
;
765 * VFPv3 and upwards with NEON implement 32 double precision
766 * registers (D0-D31).
768 if (!cpu_isar_feature(aa32_simd_r32
, env_archcpu(env
))) {
769 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
770 value
|= R_CPACR_D32DIS_MASK
;
777 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
778 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
780 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
781 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
782 mask
= R_CPACR_CP11_MASK
| R_CPACR_CP10_MASK
;
783 value
= (value
& ~mask
) | (env
->cp15
.cpacr_el1
& mask
);
786 env
->cp15
.cpacr_el1
= value
;
789 static uint64_t cpacr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
792 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
793 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
795 uint64_t value
= env
->cp15
.cpacr_el1
;
797 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
798 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
799 value
= ~(R_CPACR_CP11_MASK
| R_CPACR_CP10_MASK
);
805 static void cpacr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
808 * Call cpacr_write() so that we reset with the correct RAO bits set
809 * for our CPU features.
811 cpacr_write(env
, ri
, 0);
814 static CPAccessResult
cpacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
817 if (arm_feature(env
, ARM_FEATURE_V8
)) {
818 /* Check if CPACR accesses are to be trapped to EL2 */
819 if (arm_current_el(env
) == 1 && arm_is_el2_enabled(env
) &&
820 FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TCPAC
)) {
821 return CP_ACCESS_TRAP_EL2
;
822 /* Check if CPACR accesses are to be trapped to EL3 */
823 } else if (arm_current_el(env
) < 3 &&
824 FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TCPAC
)) {
825 return CP_ACCESS_TRAP_EL3
;
832 static CPAccessResult
cptr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
835 /* Check if CPTR accesses are set to trap to EL3 */
836 if (arm_current_el(env
) == 2 &&
837 FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TCPAC
)) {
838 return CP_ACCESS_TRAP_EL3
;
844 static const ARMCPRegInfo v6_cp_reginfo
[] = {
845 /* prefetch by MVA in v6, NOP in v7 */
846 { .name
= "MVA_prefetch",
847 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
848 .access
= PL1_W
, .type
= ARM_CP_NOP
},
850 * We need to break the TB after ISB to execute self-modifying code
851 * correctly and also to take any pending interrupts immediately.
852 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
854 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
855 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
, .writefn
= arm_cp_write_ignore
},
856 { .name
= "DSB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
857 .access
= PL0_W
, .type
= ARM_CP_NOP
},
858 { .name
= "DMB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
859 .access
= PL0_W
, .type
= ARM_CP_NOP
},
860 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
861 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
862 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ifar_s
),
863 offsetof(CPUARMState
, cp15
.ifar_ns
) },
866 * Watchpoint Fault Address Register : should actually only be present
867 * for 1136, 1176, 11MPCore.
869 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
870 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
871 { .name
= "CPACR", .state
= ARM_CP_STATE_BOTH
, .opc0
= 3,
872 .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2, .accessfn
= cpacr_access
,
873 .fgt
= FGT_CPACR_EL1
,
874 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.cpacr_el1
),
875 .resetfn
= cpacr_reset
, .writefn
= cpacr_write
, .readfn
= cpacr_read
},
878 typedef struct pm_event
{
879 uint16_t number
; /* PMEVTYPER.evtCount is 16 bits wide */
880 /* If the event is supported on this CPU (used to generate PMCEID[01]) */
881 bool (*supported
)(CPUARMState
*);
883 * Retrieve the current count of the underlying event. The programmed
884 * counters hold a difference from the return value from this function
886 uint64_t (*get_count
)(CPUARMState
*);
888 * Return how many nanoseconds it will take (at a minimum) for count events
889 * to occur. A negative value indicates the counter will never overflow, or
890 * that the counter has otherwise arranged for the overflow bit to be set
891 * and the PMU interrupt to be raised on overflow.
893 int64_t (*ns_per_count
)(uint64_t);
896 static bool event_always_supported(CPUARMState
*env
)
901 static uint64_t swinc_get_count(CPUARMState
*env
)
904 * SW_INCR events are written directly to the pmevcntr's by writes to
905 * PMSWINC, so there is no underlying count maintained by the PMU itself
910 static int64_t swinc_ns_per(uint64_t ignored
)
916 * Return the underlying cycle count for the PMU cycle counters. If we're in
917 * usermode, simply return 0.
919 static uint64_t cycles_get_count(CPUARMState
*env
)
921 #ifndef CONFIG_USER_ONLY
922 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
923 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
925 return cpu_get_host_ticks();
929 #ifndef CONFIG_USER_ONLY
930 static int64_t cycles_ns_per(uint64_t cycles
)
932 return (ARM_CPU_FREQ
/ NANOSECONDS_PER_SECOND
) * cycles
;
935 static bool instructions_supported(CPUARMState
*env
)
937 return icount_enabled() == 1; /* Precise instruction counting */
940 static uint64_t instructions_get_count(CPUARMState
*env
)
942 return (uint64_t)icount_get_raw();
945 static int64_t instructions_ns_per(uint64_t icount
)
947 return icount_to_ns((int64_t)icount
);
951 static bool pmuv3p1_events_supported(CPUARMState
*env
)
953 /* For events which are supported in any v8.1 PMU */
954 return cpu_isar_feature(any_pmuv3p1
, env_archcpu(env
));
957 static bool pmuv3p4_events_supported(CPUARMState
*env
)
959 /* For events which are supported in any v8.1 PMU */
960 return cpu_isar_feature(any_pmuv3p4
, env_archcpu(env
));
963 static uint64_t zero_event_get_count(CPUARMState
*env
)
965 /* For events which on QEMU never fire, so their count is always zero */
969 static int64_t zero_event_ns_per(uint64_t cycles
)
971 /* An event which never fires can never overflow */
975 static const pm_event pm_events
[] = {
976 { .number
= 0x000, /* SW_INCR */
977 .supported
= event_always_supported
,
978 .get_count
= swinc_get_count
,
979 .ns_per_count
= swinc_ns_per
,
981 #ifndef CONFIG_USER_ONLY
982 { .number
= 0x008, /* INST_RETIRED, Instruction architecturally executed */
983 .supported
= instructions_supported
,
984 .get_count
= instructions_get_count
,
985 .ns_per_count
= instructions_ns_per
,
987 { .number
= 0x011, /* CPU_CYCLES, Cycle */
988 .supported
= event_always_supported
,
989 .get_count
= cycles_get_count
,
990 .ns_per_count
= cycles_ns_per
,
993 { .number
= 0x023, /* STALL_FRONTEND */
994 .supported
= pmuv3p1_events_supported
,
995 .get_count
= zero_event_get_count
,
996 .ns_per_count
= zero_event_ns_per
,
998 { .number
= 0x024, /* STALL_BACKEND */
999 .supported
= pmuv3p1_events_supported
,
1000 .get_count
= zero_event_get_count
,
1001 .ns_per_count
= zero_event_ns_per
,
1003 { .number
= 0x03c, /* STALL */
1004 .supported
= pmuv3p4_events_supported
,
1005 .get_count
= zero_event_get_count
,
1006 .ns_per_count
= zero_event_ns_per
,
1011 * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range of
1012 * events (i.e. the statistical profiling extension), this implementation
1013 * should first be updated to something sparse instead of the current
1014 * supported_event_map[] array.
1016 #define MAX_EVENT_ID 0x3c
1017 #define UNSUPPORTED_EVENT UINT16_MAX
1018 static uint16_t supported_event_map
[MAX_EVENT_ID
+ 1];
1021 * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a map
1022 * of ARM event numbers to indices in our pm_events array.
1024 * Note: Events in the 0x40XX range are not currently supported.
1026 void pmu_init(ARMCPU
*cpu
)
1031 * Empty supported_event_map and cpu->pmceid[01] before adding supported
1034 for (i
= 0; i
< ARRAY_SIZE(supported_event_map
); i
++) {
1035 supported_event_map
[i
] = UNSUPPORTED_EVENT
;
1040 for (i
= 0; i
< ARRAY_SIZE(pm_events
); i
++) {
1041 const pm_event
*cnt
= &pm_events
[i
];
1042 assert(cnt
->number
<= MAX_EVENT_ID
);
1043 /* We do not currently support events in the 0x40xx range */
1044 assert(cnt
->number
<= 0x3f);
1046 if (cnt
->supported(&cpu
->env
)) {
1047 supported_event_map
[cnt
->number
] = i
;
1048 uint64_t event_mask
= 1ULL << (cnt
->number
& 0x1f);
1049 if (cnt
->number
& 0x20) {
1050 cpu
->pmceid1
|= event_mask
;
1052 cpu
->pmceid0
|= event_mask
;
1059 * Check at runtime whether a PMU event is supported for the current machine
1061 static bool event_supported(uint16_t number
)
1063 if (number
> MAX_EVENT_ID
) {
1066 return supported_event_map
[number
] != UNSUPPORTED_EVENT
;
1069 static CPAccessResult
pmreg_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1073 * Performance monitor registers user accessibility is controlled
1074 * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
1075 * trapping to EL2 or EL3 for other accesses.
1077 int el
= arm_current_el(env
);
1078 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
1080 if (el
== 0 && !(env
->cp15
.c9_pmuserenr
& 1)) {
1081 return CP_ACCESS_TRAP
;
1083 if (el
< 2 && (mdcr_el2
& MDCR_TPM
)) {
1084 return CP_ACCESS_TRAP_EL2
;
1086 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
1087 return CP_ACCESS_TRAP_EL3
;
1090 return CP_ACCESS_OK
;
1093 static CPAccessResult
pmreg_access_xevcntr(CPUARMState
*env
,
1094 const ARMCPRegInfo
*ri
,
1097 /* ER: event counter read trap control */
1098 if (arm_feature(env
, ARM_FEATURE_V8
)
1099 && arm_current_el(env
) == 0
1100 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0
1102 return CP_ACCESS_OK
;
1105 return pmreg_access(env
, ri
, isread
);
1108 static CPAccessResult
pmreg_access_swinc(CPUARMState
*env
,
1109 const ARMCPRegInfo
*ri
,
1112 /* SW: software increment write trap control */
1113 if (arm_feature(env
, ARM_FEATURE_V8
)
1114 && arm_current_el(env
) == 0
1115 && (env
->cp15
.c9_pmuserenr
& (1 << 1)) != 0
1117 return CP_ACCESS_OK
;
1120 return pmreg_access(env
, ri
, isread
);
1123 static CPAccessResult
pmreg_access_selr(CPUARMState
*env
,
1124 const ARMCPRegInfo
*ri
,
1127 /* ER: event counter read trap control */
1128 if (arm_feature(env
, ARM_FEATURE_V8
)
1129 && arm_current_el(env
) == 0
1130 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0) {
1131 return CP_ACCESS_OK
;
1134 return pmreg_access(env
, ri
, isread
);
1137 static CPAccessResult
pmreg_access_ccntr(CPUARMState
*env
,
1138 const ARMCPRegInfo
*ri
,
1141 /* CR: cycle counter read trap control */
1142 if (arm_feature(env
, ARM_FEATURE_V8
)
1143 && arm_current_el(env
) == 0
1144 && (env
->cp15
.c9_pmuserenr
& (1 << 2)) != 0
1146 return CP_ACCESS_OK
;
1149 return pmreg_access(env
, ri
, isread
);
1153 * Bits in MDCR_EL2 and MDCR_EL3 which pmu_counter_enabled() looks at.
1154 * We use these to decide whether we need to wrap a write to MDCR_EL2
1155 * or MDCR_EL3 in pmu_op_start()/pmu_op_finish() calls.
1157 #define MDCR_EL2_PMU_ENABLE_BITS \
1158 (MDCR_HPME | MDCR_HPMD | MDCR_HPMN | MDCR_HCCD | MDCR_HLP)
1159 #define MDCR_EL3_PMU_ENABLE_BITS (MDCR_SPME | MDCR_SCCD)
1162 * Returns true if the counter (pass 31 for PMCCNTR) should count events using
1163 * the current EL, security state, and register configuration.
1165 static bool pmu_counter_enabled(CPUARMState
*env
, uint8_t counter
)
1168 bool e
, p
, u
, nsk
, nsu
, nsh
, m
;
1169 bool enabled
, prohibited
= false, filtered
;
1170 bool secure
= arm_is_secure(env
);
1171 int el
= arm_current_el(env
);
1172 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
1173 uint8_t hpmn
= mdcr_el2
& MDCR_HPMN
;
1175 if (!arm_feature(env
, ARM_FEATURE_PMU
)) {
1179 if (!arm_feature(env
, ARM_FEATURE_EL2
) ||
1180 (counter
< hpmn
|| counter
== 31)) {
1181 e
= env
->cp15
.c9_pmcr
& PMCRE
;
1183 e
= mdcr_el2
& MDCR_HPME
;
1185 enabled
= e
&& (env
->cp15
.c9_pmcnten
& (1 << counter
));
1187 /* Is event counting prohibited? */
1188 if (el
== 2 && (counter
< hpmn
|| counter
== 31)) {
1189 prohibited
= mdcr_el2
& MDCR_HPMD
;
1192 prohibited
= prohibited
|| !(env
->cp15
.mdcr_el3
& MDCR_SPME
);
1195 if (counter
== 31) {
1197 * The cycle counter defaults to running. PMCR.DP says "disable
1198 * the cycle counter when event counting is prohibited".
1199 * Some MDCR bits disable the cycle counter specifically.
1201 prohibited
= prohibited
&& env
->cp15
.c9_pmcr
& PMCRDP
;
1202 if (cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1204 prohibited
= prohibited
|| (env
->cp15
.mdcr_el3
& MDCR_SCCD
);
1207 prohibited
= prohibited
|| (mdcr_el2
& MDCR_HCCD
);
1212 if (counter
== 31) {
1213 filter
= env
->cp15
.pmccfiltr_el0
;
1215 filter
= env
->cp15
.c14_pmevtyper
[counter
];
1218 p
= filter
& PMXEVTYPER_P
;
1219 u
= filter
& PMXEVTYPER_U
;
1220 nsk
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSK
);
1221 nsu
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSU
);
1222 nsh
= arm_feature(env
, ARM_FEATURE_EL2
) && (filter
& PMXEVTYPER_NSH
);
1223 m
= arm_el_is_aa64(env
, 1) &&
1224 arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_M
);
1227 filtered
= secure
? u
: u
!= nsu
;
1228 } else if (el
== 1) {
1229 filtered
= secure
? p
: p
!= nsk
;
1230 } else if (el
== 2) {
1236 if (counter
!= 31) {
1238 * If not checking PMCCNTR, ensure the counter is setup to an event we
1241 uint16_t event
= filter
& PMXEVTYPER_EVTCOUNT
;
1242 if (!event_supported(event
)) {
1247 return enabled
&& !prohibited
&& !filtered
;
1250 static void pmu_update_irq(CPUARMState
*env
)
1252 ARMCPU
*cpu
= env_archcpu(env
);
1253 qemu_set_irq(cpu
->pmu_interrupt
, (env
->cp15
.c9_pmcr
& PMCRE
) &&
1254 (env
->cp15
.c9_pminten
& env
->cp15
.c9_pmovsr
));
1257 static bool pmccntr_clockdiv_enabled(CPUARMState
*env
)
1260 * Return true if the clock divider is enabled and the cycle counter
1261 * is supposed to tick only once every 64 clock cycles. This is
1262 * controlled by PMCR.D, but if PMCR.LC is set to enable the long
1263 * (64-bit) cycle counter PMCR.D has no effect.
1265 return (env
->cp15
.c9_pmcr
& (PMCRD
| PMCRLC
)) == PMCRD
;
1268 static bool pmevcntr_is_64_bit(CPUARMState
*env
, int counter
)
1270 /* Return true if the specified event counter is configured to be 64 bit */
1272 /* This isn't intended to be used with the cycle counter */
1273 assert(counter
< 31);
1275 if (!cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1279 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
1281 * MDCR_EL2.HLP still applies even when EL2 is disabled in the
1282 * current security state, so we don't use arm_mdcr_el2_eff() here.
1284 bool hlp
= env
->cp15
.mdcr_el2
& MDCR_HLP
;
1285 int hpmn
= env
->cp15
.mdcr_el2
& MDCR_HPMN
;
1287 if (counter
>= hpmn
) {
1291 return env
->cp15
.c9_pmcr
& PMCRLP
;
1295 * Ensure c15_ccnt is the guest-visible count so that operations such as
1296 * enabling/disabling the counter or filtering, modifying the count itself,
1297 * etc. can be done logically. This is essentially a no-op if the counter is
1298 * not enabled at the time of the call.
1300 static void pmccntr_op_start(CPUARMState
*env
)
1302 uint64_t cycles
= cycles_get_count(env
);
1304 if (pmu_counter_enabled(env
, 31)) {
1305 uint64_t eff_cycles
= cycles
;
1306 if (pmccntr_clockdiv_enabled(env
)) {
1310 uint64_t new_pmccntr
= eff_cycles
- env
->cp15
.c15_ccnt_delta
;
1312 uint64_t overflow_mask
= env
->cp15
.c9_pmcr
& PMCRLC
? \
1313 1ull << 63 : 1ull << 31;
1314 if (env
->cp15
.c15_ccnt
& ~new_pmccntr
& overflow_mask
) {
1315 env
->cp15
.c9_pmovsr
|= (1ULL << 31);
1316 pmu_update_irq(env
);
1319 env
->cp15
.c15_ccnt
= new_pmccntr
;
1321 env
->cp15
.c15_ccnt_delta
= cycles
;
1325 * If PMCCNTR is enabled, recalculate the delta between the clock and the
1326 * guest-visible count. A call to pmccntr_op_finish should follow every call to
1329 static void pmccntr_op_finish(CPUARMState
*env
)
1331 if (pmu_counter_enabled(env
, 31)) {
1332 #ifndef CONFIG_USER_ONLY
1333 /* Calculate when the counter will next overflow */
1334 uint64_t remaining_cycles
= -env
->cp15
.c15_ccnt
;
1335 if (!(env
->cp15
.c9_pmcr
& PMCRLC
)) {
1336 remaining_cycles
= (uint32_t)remaining_cycles
;
1338 int64_t overflow_in
= cycles_ns_per(remaining_cycles
);
1340 if (overflow_in
> 0) {
1341 int64_t overflow_at
;
1343 if (!sadd64_overflow(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1344 overflow_in
, &overflow_at
)) {
1345 ARMCPU
*cpu
= env_archcpu(env
);
1346 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1351 uint64_t prev_cycles
= env
->cp15
.c15_ccnt_delta
;
1352 if (pmccntr_clockdiv_enabled(env
)) {
1355 env
->cp15
.c15_ccnt_delta
= prev_cycles
- env
->cp15
.c15_ccnt
;
1359 static void pmevcntr_op_start(CPUARMState
*env
, uint8_t counter
)
1362 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1364 if (event_supported(event
)) {
1365 uint16_t event_idx
= supported_event_map
[event
];
1366 count
= pm_events
[event_idx
].get_count(env
);
1369 if (pmu_counter_enabled(env
, counter
)) {
1370 uint64_t new_pmevcntr
= count
- env
->cp15
.c14_pmevcntr_delta
[counter
];
1371 uint64_t overflow_mask
= pmevcntr_is_64_bit(env
, counter
) ?
1372 1ULL << 63 : 1ULL << 31;
1374 if (env
->cp15
.c14_pmevcntr
[counter
] & ~new_pmevcntr
& overflow_mask
) {
1375 env
->cp15
.c9_pmovsr
|= (1 << counter
);
1376 pmu_update_irq(env
);
1378 env
->cp15
.c14_pmevcntr
[counter
] = new_pmevcntr
;
1380 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1383 static void pmevcntr_op_finish(CPUARMState
*env
, uint8_t counter
)
1385 if (pmu_counter_enabled(env
, counter
)) {
1386 #ifndef CONFIG_USER_ONLY
1387 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1388 uint16_t event_idx
= supported_event_map
[event
];
1389 uint64_t delta
= -(env
->cp15
.c14_pmevcntr
[counter
] + 1);
1390 int64_t overflow_in
;
1392 if (!pmevcntr_is_64_bit(env
, counter
)) {
1393 delta
= (uint32_t)delta
;
1395 overflow_in
= pm_events
[event_idx
].ns_per_count(delta
);
1397 if (overflow_in
> 0) {
1398 int64_t overflow_at
;
1400 if (!sadd64_overflow(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1401 overflow_in
, &overflow_at
)) {
1402 ARMCPU
*cpu
= env_archcpu(env
);
1403 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1408 env
->cp15
.c14_pmevcntr_delta
[counter
] -=
1409 env
->cp15
.c14_pmevcntr
[counter
];
1413 void pmu_op_start(CPUARMState
*env
)
1416 pmccntr_op_start(env
);
1417 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1418 pmevcntr_op_start(env
, i
);
1422 void pmu_op_finish(CPUARMState
*env
)
1425 pmccntr_op_finish(env
);
1426 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1427 pmevcntr_op_finish(env
, i
);
1431 void pmu_pre_el_change(ARMCPU
*cpu
, void *ignored
)
1433 pmu_op_start(&cpu
->env
);
1436 void pmu_post_el_change(ARMCPU
*cpu
, void *ignored
)
1438 pmu_op_finish(&cpu
->env
);
1441 void arm_pmu_timer_cb(void *opaque
)
1443 ARMCPU
*cpu
= opaque
;
1446 * Update all the counter values based on the current underlying counts,
1447 * triggering interrupts to be raised, if necessary. pmu_op_finish() also
1448 * has the effect of setting the cpu->pmu_timer to the next earliest time a
1449 * counter may expire.
1451 pmu_op_start(&cpu
->env
);
1452 pmu_op_finish(&cpu
->env
);
1455 static void pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1460 if (value
& PMCRC
) {
1461 /* The counter has been reset */
1462 env
->cp15
.c15_ccnt
= 0;
1465 if (value
& PMCRP
) {
1467 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1468 env
->cp15
.c14_pmevcntr
[i
] = 0;
1472 env
->cp15
.c9_pmcr
&= ~PMCR_WRITABLE_MASK
;
1473 env
->cp15
.c9_pmcr
|= (value
& PMCR_WRITABLE_MASK
);
1478 static void pmswinc_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1482 uint64_t overflow_mask
, new_pmswinc
;
1484 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1485 /* Increment a counter's count iff: */
1486 if ((value
& (1 << i
)) && /* counter's bit is set */
1487 /* counter is enabled and not filtered */
1488 pmu_counter_enabled(env
, i
) &&
1489 /* counter is SW_INCR */
1490 (env
->cp15
.c14_pmevtyper
[i
] & PMXEVTYPER_EVTCOUNT
) == 0x0) {
1491 pmevcntr_op_start(env
, i
);
1494 * Detect if this write causes an overflow since we can't predict
1495 * PMSWINC overflows like we can for other events
1497 new_pmswinc
= env
->cp15
.c14_pmevcntr
[i
] + 1;
1499 overflow_mask
= pmevcntr_is_64_bit(env
, i
) ?
1500 1ULL << 63 : 1ULL << 31;
1502 if (env
->cp15
.c14_pmevcntr
[i
] & ~new_pmswinc
& overflow_mask
) {
1503 env
->cp15
.c9_pmovsr
|= (1 << i
);
1504 pmu_update_irq(env
);
1507 env
->cp15
.c14_pmevcntr
[i
] = new_pmswinc
;
1509 pmevcntr_op_finish(env
, i
);
1514 static uint64_t pmccntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1517 pmccntr_op_start(env
);
1518 ret
= env
->cp15
.c15_ccnt
;
1519 pmccntr_op_finish(env
);
1523 static void pmselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1527 * The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
1528 * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
1529 * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
1532 env
->cp15
.c9_pmselr
= value
& 0x1f;
1535 static void pmccntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1538 pmccntr_op_start(env
);
1539 env
->cp15
.c15_ccnt
= value
;
1540 pmccntr_op_finish(env
);
1543 static void pmccntr_write32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1546 uint64_t cur_val
= pmccntr_read(env
, NULL
);
1548 pmccntr_write(env
, ri
, deposit64(cur_val
, 0, 32, value
));
1551 static void pmccfiltr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1554 pmccntr_op_start(env
);
1555 env
->cp15
.pmccfiltr_el0
= value
& PMCCFILTR_EL0
;
1556 pmccntr_op_finish(env
);
1559 static void pmccfiltr_write_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1562 pmccntr_op_start(env
);
1563 /* M is not accessible from AArch32 */
1564 env
->cp15
.pmccfiltr_el0
= (env
->cp15
.pmccfiltr_el0
& PMCCFILTR_M
) |
1565 (value
& PMCCFILTR
);
1566 pmccntr_op_finish(env
);
1569 static uint64_t pmccfiltr_read_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1571 /* M is not visible in AArch32 */
1572 return env
->cp15
.pmccfiltr_el0
& PMCCFILTR
;
1575 static void pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1579 value
&= pmu_counter_mask(env
);
1580 env
->cp15
.c9_pmcnten
|= value
;
1584 static void pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1588 value
&= pmu_counter_mask(env
);
1589 env
->cp15
.c9_pmcnten
&= ~value
;
1593 static void pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1596 value
&= pmu_counter_mask(env
);
1597 env
->cp15
.c9_pmovsr
&= ~value
;
1598 pmu_update_irq(env
);
1601 static void pmovsset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1604 value
&= pmu_counter_mask(env
);
1605 env
->cp15
.c9_pmovsr
|= value
;
1606 pmu_update_irq(env
);
1609 static void pmevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1610 uint64_t value
, const uint8_t counter
)
1612 if (counter
== 31) {
1613 pmccfiltr_write(env
, ri
, value
);
1614 } else if (counter
< pmu_num_counters(env
)) {
1615 pmevcntr_op_start(env
, counter
);
1618 * If this counter's event type is changing, store the current
1619 * underlying count for the new type in c14_pmevcntr_delta[counter] so
1620 * pmevcntr_op_finish has the correct baseline when it converts back to
1623 uint16_t old_event
= env
->cp15
.c14_pmevtyper
[counter
] &
1624 PMXEVTYPER_EVTCOUNT
;
1625 uint16_t new_event
= value
& PMXEVTYPER_EVTCOUNT
;
1626 if (old_event
!= new_event
) {
1628 if (event_supported(new_event
)) {
1629 uint16_t event_idx
= supported_event_map
[new_event
];
1630 count
= pm_events
[event_idx
].get_count(env
);
1632 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1635 env
->cp15
.c14_pmevtyper
[counter
] = value
& PMXEVTYPER_MASK
;
1636 pmevcntr_op_finish(env
, counter
);
1639 * Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
1640 * PMSELR value is equal to or greater than the number of implemented
1641 * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
1645 static uint64_t pmevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1646 const uint8_t counter
)
1648 if (counter
== 31) {
1649 return env
->cp15
.pmccfiltr_el0
;
1650 } else if (counter
< pmu_num_counters(env
)) {
1651 return env
->cp15
.c14_pmevtyper
[counter
];
1654 * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
1655 * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write().
1661 static void pmevtyper_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1664 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1665 pmevtyper_write(env
, ri
, value
, counter
);
1668 static void pmevtyper_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1671 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1672 env
->cp15
.c14_pmevtyper
[counter
] = value
;
1675 * pmevtyper_rawwrite is called between a pair of pmu_op_start and
1676 * pmu_op_finish calls when loading saved state for a migration. Because
1677 * we're potentially updating the type of event here, the value written to
1678 * c14_pmevcntr_delta by the preceding pmu_op_start call may be for a
1679 * different counter type. Therefore, we need to set this value to the
1680 * current count for the counter type we're writing so that pmu_op_finish
1681 * has the correct count for its calculation.
1683 uint16_t event
= value
& PMXEVTYPER_EVTCOUNT
;
1684 if (event_supported(event
)) {
1685 uint16_t event_idx
= supported_event_map
[event
];
1686 env
->cp15
.c14_pmevcntr_delta
[counter
] =
1687 pm_events
[event_idx
].get_count(env
);
1691 static uint64_t pmevtyper_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1693 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1694 return pmevtyper_read(env
, ri
, counter
);
1697 static void pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1700 pmevtyper_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1703 static uint64_t pmxevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1705 return pmevtyper_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1708 static void pmevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1709 uint64_t value
, uint8_t counter
)
1711 if (!cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1712 /* Before FEAT_PMUv3p5, top 32 bits of event counters are RES0 */
1713 value
&= MAKE_64BIT_MASK(0, 32);
1715 if (counter
< pmu_num_counters(env
)) {
1716 pmevcntr_op_start(env
, counter
);
1717 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1718 pmevcntr_op_finish(env
, counter
);
1721 * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1722 * are CONSTRAINED UNPREDICTABLE.
1726 static uint64_t pmevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1729 if (counter
< pmu_num_counters(env
)) {
1731 pmevcntr_op_start(env
, counter
);
1732 ret
= env
->cp15
.c14_pmevcntr
[counter
];
1733 pmevcntr_op_finish(env
, counter
);
1734 if (!cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1735 /* Before FEAT_PMUv3p5, top 32 bits of event counters are RES0 */
1736 ret
&= MAKE_64BIT_MASK(0, 32);
1741 * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1742 * are CONSTRAINED UNPREDICTABLE.
1748 static void pmevcntr_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1751 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1752 pmevcntr_write(env
, ri
, value
, counter
);
1755 static uint64_t pmevcntr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1757 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1758 return pmevcntr_read(env
, ri
, counter
);
1761 static void pmevcntr_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1764 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1765 assert(counter
< pmu_num_counters(env
));
1766 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1767 pmevcntr_write(env
, ri
, value
, counter
);
1770 static uint64_t pmevcntr_rawread(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1772 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1773 assert(counter
< pmu_num_counters(env
));
1774 return env
->cp15
.c14_pmevcntr
[counter
];
1777 static void pmxevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1780 pmevcntr_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1783 static uint64_t pmxevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1785 return pmevcntr_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1788 static void pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1791 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1792 env
->cp15
.c9_pmuserenr
= value
& 0xf;
1794 env
->cp15
.c9_pmuserenr
= value
& 1;
1798 static void pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1801 /* We have no event counters so only the C bit can be changed */
1802 value
&= pmu_counter_mask(env
);
1803 env
->cp15
.c9_pminten
|= value
;
1804 pmu_update_irq(env
);
1807 static void pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1810 value
&= pmu_counter_mask(env
);
1811 env
->cp15
.c9_pminten
&= ~value
;
1812 pmu_update_irq(env
);
1815 static void vbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1819 * Note that even though the AArch64 view of this register has bits
1820 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
1821 * architectural requirements for bits which are RES0 only in some
1822 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
1823 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
1825 raw_write(env
, ri
, value
& ~0x1FULL
);
1828 static void scr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1830 /* Begin with base v8.0 state. */
1831 uint64_t valid_mask
= 0x3fff;
1832 ARMCPU
*cpu
= env_archcpu(env
);
1836 * Because SCR_EL3 is the "real" cpreg and SCR is the alias, reset always
1837 * passes the reginfo for SCR_EL3, which has type ARM_CP_STATE_AA64.
1838 * Instead, choose the format based on the mode of EL3.
1840 if (arm_el_is_aa64(env
, 3)) {
1841 value
|= SCR_FW
| SCR_AW
; /* RES1 */
1842 valid_mask
&= ~SCR_NET
; /* RES0 */
1844 if (!cpu_isar_feature(aa64_aa32_el1
, cpu
) &&
1845 !cpu_isar_feature(aa64_aa32_el2
, cpu
)) {
1846 value
|= SCR_RW
; /* RAO/WI */
1848 if (cpu_isar_feature(aa64_ras
, cpu
)) {
1849 valid_mask
|= SCR_TERR
;
1851 if (cpu_isar_feature(aa64_lor
, cpu
)) {
1852 valid_mask
|= SCR_TLOR
;
1854 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
1855 valid_mask
|= SCR_API
| SCR_APK
;
1857 if (cpu_isar_feature(aa64_sel2
, cpu
)) {
1858 valid_mask
|= SCR_EEL2
;
1859 } else if (cpu_isar_feature(aa64_rme
, cpu
)) {
1860 /* With RME and without SEL2, NS is RES1 (R_GSWWH, I_DJJQJ). */
1863 if (cpu_isar_feature(aa64_mte
, cpu
)) {
1864 valid_mask
|= SCR_ATA
;
1866 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
1867 valid_mask
|= SCR_ENSCXT
;
1869 if (cpu_isar_feature(aa64_doublefault
, cpu
)) {
1870 valid_mask
|= SCR_EASE
| SCR_NMEA
;
1872 if (cpu_isar_feature(aa64_sme
, cpu
)) {
1873 valid_mask
|= SCR_ENTP2
;
1875 if (cpu_isar_feature(aa64_hcx
, cpu
)) {
1876 valid_mask
|= SCR_HXEN
;
1878 if (cpu_isar_feature(aa64_fgt
, cpu
)) {
1879 valid_mask
|= SCR_FGTEN
;
1881 if (cpu_isar_feature(aa64_rme
, cpu
)) {
1882 valid_mask
|= SCR_NSE
| SCR_GPF
;
1885 valid_mask
&= ~(SCR_RW
| SCR_ST
);
1886 if (cpu_isar_feature(aa32_ras
, cpu
)) {
1887 valid_mask
|= SCR_TERR
;
1891 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
1892 valid_mask
&= ~SCR_HCE
;
1895 * On ARMv7, SMD (or SCD as it is called in v7) is only
1896 * supported if EL2 exists. The bit is UNK/SBZP when
1897 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
1898 * when EL2 is unavailable.
1899 * On ARMv8, this bit is always available.
1901 if (arm_feature(env
, ARM_FEATURE_V7
) &&
1902 !arm_feature(env
, ARM_FEATURE_V8
)) {
1903 valid_mask
&= ~SCR_SMD
;
1907 /* Clear all-context RES0 bits. */
1908 value
&= valid_mask
;
1909 changed
= env
->cp15
.scr_el3
^ value
;
1910 env
->cp15
.scr_el3
= value
;
1913 * If SCR_EL3.{NS,NSE} changes, i.e. change of security state,
1914 * we must invalidate all TLBs below EL3.
1916 if (changed
& (SCR_NS
| SCR_NSE
)) {
1917 tlb_flush_by_mmuidx(env_cpu(env
), (ARMMMUIdxBit_E10_0
|
1918 ARMMMUIdxBit_E20_0
|
1919 ARMMMUIdxBit_E10_1
|
1920 ARMMMUIdxBit_E20_2
|
1921 ARMMMUIdxBit_E10_1_PAN
|
1922 ARMMMUIdxBit_E20_2_PAN
|
1927 static void scr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1930 * scr_write will set the RES1 bits on an AArch64-only CPU.
1931 * The reset value will be 0x30 on an AArch64-only CPU and 0 otherwise.
1933 scr_write(env
, ri
, 0);
1936 static CPAccessResult
access_tid4(CPUARMState
*env
,
1937 const ARMCPRegInfo
*ri
,
1940 if (arm_current_el(env
) == 1 &&
1941 (arm_hcr_el2_eff(env
) & (HCR_TID2
| HCR_TID4
))) {
1942 return CP_ACCESS_TRAP_EL2
;
1945 return CP_ACCESS_OK
;
1948 static uint64_t ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1950 ARMCPU
*cpu
= env_archcpu(env
);
1953 * Acquire the CSSELR index from the bank corresponding to the CCSIDR
1956 uint32_t index
= A32_BANKED_REG_GET(env
, csselr
,
1957 ri
->secure
& ARM_CP_SECSTATE_S
);
1959 return cpu
->ccsidr
[index
];
1962 static void csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1965 raw_write(env
, ri
, value
& 0xf);
1968 static uint64_t isr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1970 CPUState
*cs
= env_cpu(env
);
1971 bool el1
= arm_current_el(env
) == 1;
1972 uint64_t hcr_el2
= el1
? arm_hcr_el2_eff(env
) : 0;
1975 if (hcr_el2
& HCR_IMO
) {
1976 if (cs
->interrupt_request
& CPU_INTERRUPT_VIRQ
) {
1980 if (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) {
1985 if (hcr_el2
& HCR_FMO
) {
1986 if (cs
->interrupt_request
& CPU_INTERRUPT_VFIQ
) {
1990 if (cs
->interrupt_request
& CPU_INTERRUPT_FIQ
) {
1995 if (hcr_el2
& HCR_AMO
) {
1996 if (cs
->interrupt_request
& CPU_INTERRUPT_VSERR
) {
2004 static CPAccessResult
access_aa64_tid1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2007 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID1
)) {
2008 return CP_ACCESS_TRAP_EL2
;
2011 return CP_ACCESS_OK
;
2014 static CPAccessResult
access_aa32_tid1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2017 if (arm_feature(env
, ARM_FEATURE_V8
)) {
2018 return access_aa64_tid1(env
, ri
, isread
);
2021 return CP_ACCESS_OK
;
2024 static const ARMCPRegInfo v7_cp_reginfo
[] = {
2025 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
2026 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
2027 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2029 * Performance monitors are implementation defined in v7,
2030 * but with an ARM recommended set of registers, which we
2033 * Performance registers fall into three categories:
2034 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
2035 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
2036 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
2037 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
2038 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
2040 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
2041 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2042 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
2043 .writefn
= pmcntenset_write
,
2044 .accessfn
= pmreg_access
,
2046 .raw_writefn
= raw_write
},
2047 { .name
= "PMCNTENSET_EL0", .state
= ARM_CP_STATE_AA64
, .type
= ARM_CP_IO
,
2048 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 1,
2049 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2051 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
), .resetvalue
= 0,
2052 .writefn
= pmcntenset_write
, .raw_writefn
= raw_write
},
2053 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
2055 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
2056 .accessfn
= pmreg_access
,
2058 .writefn
= pmcntenclr_write
,
2059 .type
= ARM_CP_ALIAS
| ARM_CP_IO
},
2060 { .name
= "PMCNTENCLR_EL0", .state
= ARM_CP_STATE_AA64
,
2061 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 2,
2062 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2064 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2065 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
2066 .writefn
= pmcntenclr_write
},
2067 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
2068 .access
= PL0_RW
, .type
= ARM_CP_IO
,
2069 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
2070 .accessfn
= pmreg_access
,
2072 .writefn
= pmovsr_write
,
2073 .raw_writefn
= raw_write
},
2074 { .name
= "PMOVSCLR_EL0", .state
= ARM_CP_STATE_AA64
,
2075 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 3,
2076 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2078 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2079 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
2080 .writefn
= pmovsr_write
,
2081 .raw_writefn
= raw_write
},
2082 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
2083 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
2084 .fgt
= FGT_PMSWINC_EL0
,
2085 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2086 .writefn
= pmswinc_write
},
2087 { .name
= "PMSWINC_EL0", .state
= ARM_CP_STATE_AA64
,
2088 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 4,
2089 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
2090 .fgt
= FGT_PMSWINC_EL0
,
2091 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2092 .writefn
= pmswinc_write
},
2093 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
2094 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
2095 .fgt
= FGT_PMSELR_EL0
,
2096 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmselr
),
2097 .accessfn
= pmreg_access_selr
, .writefn
= pmselr_write
,
2098 .raw_writefn
= raw_write
},
2099 { .name
= "PMSELR_EL0", .state
= ARM_CP_STATE_AA64
,
2100 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 5,
2101 .access
= PL0_RW
, .accessfn
= pmreg_access_selr
,
2102 .fgt
= FGT_PMSELR_EL0
,
2103 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmselr
),
2104 .writefn
= pmselr_write
, .raw_writefn
= raw_write
, },
2105 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
2106 .access
= PL0_RW
, .resetvalue
= 0, .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2107 .fgt
= FGT_PMCCNTR_EL0
,
2108 .readfn
= pmccntr_read
, .writefn
= pmccntr_write32
,
2109 .accessfn
= pmreg_access_ccntr
},
2110 { .name
= "PMCCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
2111 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 0,
2112 .access
= PL0_RW
, .accessfn
= pmreg_access_ccntr
,
2113 .fgt
= FGT_PMCCNTR_EL0
,
2115 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ccnt
),
2116 .readfn
= pmccntr_read
, .writefn
= pmccntr_write
,
2117 .raw_readfn
= raw_read
, .raw_writefn
= raw_write
, },
2118 { .name
= "PMCCFILTR", .cp
= 15, .opc1
= 0, .crn
= 14, .crm
= 15, .opc2
= 7,
2119 .writefn
= pmccfiltr_write_a32
, .readfn
= pmccfiltr_read_a32
,
2120 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2121 .fgt
= FGT_PMCCFILTR_EL0
,
2122 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2124 { .name
= "PMCCFILTR_EL0", .state
= ARM_CP_STATE_AA64
,
2125 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 15, .opc2
= 7,
2126 .writefn
= pmccfiltr_write
, .raw_writefn
= raw_write
,
2127 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2128 .fgt
= FGT_PMCCFILTR_EL0
,
2130 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmccfiltr_el0
),
2132 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
2133 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2134 .accessfn
= pmreg_access
,
2135 .fgt
= FGT_PMEVTYPERN_EL0
,
2136 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
2137 { .name
= "PMXEVTYPER_EL0", .state
= ARM_CP_STATE_AA64
,
2138 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 1,
2139 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2140 .accessfn
= pmreg_access
,
2141 .fgt
= FGT_PMEVTYPERN_EL0
,
2142 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
2143 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
2144 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2145 .accessfn
= pmreg_access_xevcntr
,
2146 .fgt
= FGT_PMEVCNTRN_EL0
,
2147 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2148 { .name
= "PMXEVCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
2149 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 2,
2150 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2151 .accessfn
= pmreg_access_xevcntr
,
2152 .fgt
= FGT_PMEVCNTRN_EL0
,
2153 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2154 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
2155 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
,
2156 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmuserenr
),
2158 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2159 { .name
= "PMUSERENR_EL0", .state
= ARM_CP_STATE_AA64
,
2160 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 0,
2161 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
2162 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
2164 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2165 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
2166 .access
= PL1_RW
, .accessfn
= access_tpm
,
2168 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2169 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pminten
),
2171 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
},
2172 { .name
= "PMINTENSET_EL1", .state
= ARM_CP_STATE_AA64
,
2173 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 1,
2174 .access
= PL1_RW
, .accessfn
= access_tpm
,
2177 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2178 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
,
2179 .resetvalue
= 0x0 },
2180 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
2181 .access
= PL1_RW
, .accessfn
= access_tpm
,
2183 .type
= ARM_CP_ALIAS
| ARM_CP_IO
| ARM_CP_NO_RAW
,
2184 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2185 .writefn
= pmintenclr_write
, },
2186 { .name
= "PMINTENCLR_EL1", .state
= ARM_CP_STATE_AA64
,
2187 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 2,
2188 .access
= PL1_RW
, .accessfn
= access_tpm
,
2190 .type
= ARM_CP_ALIAS
| ARM_CP_IO
| ARM_CP_NO_RAW
,
2191 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2192 .writefn
= pmintenclr_write
},
2193 { .name
= "CCSIDR", .state
= ARM_CP_STATE_BOTH
,
2194 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
2196 .accessfn
= access_tid4
,
2197 .fgt
= FGT_CCSIDR_EL1
,
2198 .readfn
= ccsidr_read
, .type
= ARM_CP_NO_RAW
},
2199 { .name
= "CSSELR", .state
= ARM_CP_STATE_BOTH
,
2200 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
2202 .accessfn
= access_tid4
,
2203 .fgt
= FGT_CSSELR_EL1
,
2204 .writefn
= csselr_write
, .resetvalue
= 0,
2205 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.csselr_s
),
2206 offsetof(CPUARMState
, cp15
.csselr_ns
) } },
2208 * Auxiliary ID register: this actually has an IMPDEF value but for now
2209 * just RAZ for all cores:
2211 { .name
= "AIDR", .state
= ARM_CP_STATE_BOTH
,
2212 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 7,
2213 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2214 .accessfn
= access_aa64_tid1
,
2215 .fgt
= FGT_AIDR_EL1
,
2218 * Auxiliary fault status registers: these also are IMPDEF, and we
2219 * choose to RAZ/WI for all cores.
2221 { .name
= "AFSR0_EL1", .state
= ARM_CP_STATE_BOTH
,
2222 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 0,
2223 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2224 .fgt
= FGT_AFSR0_EL1
,
2225 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2226 { .name
= "AFSR1_EL1", .state
= ARM_CP_STATE_BOTH
,
2227 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 1,
2228 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2229 .fgt
= FGT_AFSR1_EL1
,
2230 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2232 * MAIR can just read-as-written because we don't implement caches
2233 * and so don't need to care about memory attributes.
2235 { .name
= "MAIR_EL1", .state
= ARM_CP_STATE_AA64
,
2236 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
2237 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2238 .fgt
= FGT_MAIR_EL1
,
2239 .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[1]),
2241 { .name
= "MAIR_EL3", .state
= ARM_CP_STATE_AA64
,
2242 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 2, .opc2
= 0,
2243 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[3]),
2246 * For non-long-descriptor page tables these are PRRR and NMRR;
2247 * regardless they still act as reads-as-written for QEMU.
2250 * MAIR0/1 are defined separately from their 64-bit counterpart which
2251 * allows them to assign the correct fieldoffset based on the endianness
2252 * handled in the field definitions.
2254 { .name
= "MAIR0", .state
= ARM_CP_STATE_AA32
,
2255 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
2256 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2257 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair0_s
),
2258 offsetof(CPUARMState
, cp15
.mair0_ns
) },
2259 .resetfn
= arm_cp_reset_ignore
},
2260 { .name
= "MAIR1", .state
= ARM_CP_STATE_AA32
,
2261 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 1,
2262 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2263 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair1_s
),
2264 offsetof(CPUARMState
, cp15
.mair1_ns
) },
2265 .resetfn
= arm_cp_reset_ignore
},
2266 { .name
= "ISR_EL1", .state
= ARM_CP_STATE_BOTH
,
2267 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 0,
2269 .type
= ARM_CP_NO_RAW
, .access
= PL1_R
, .readfn
= isr_read
},
2270 /* 32 bit ITLB invalidates */
2271 { .name
= "ITLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 0,
2272 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2273 .writefn
= tlbiall_write
},
2274 { .name
= "ITLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
2275 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2276 .writefn
= tlbimva_write
},
2277 { .name
= "ITLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 2,
2278 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2279 .writefn
= tlbiasid_write
},
2280 /* 32 bit DTLB invalidates */
2281 { .name
= "DTLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 0,
2282 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2283 .writefn
= tlbiall_write
},
2284 { .name
= "DTLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
2285 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2286 .writefn
= tlbimva_write
},
2287 { .name
= "DTLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 2,
2288 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2289 .writefn
= tlbiasid_write
},
2290 /* 32 bit TLB invalidates */
2291 { .name
= "TLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
2292 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2293 .writefn
= tlbiall_write
},
2294 { .name
= "TLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
2295 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2296 .writefn
= tlbimva_write
},
2297 { .name
= "TLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
2298 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2299 .writefn
= tlbiasid_write
},
2300 { .name
= "TLBIMVAA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
2301 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2302 .writefn
= tlbimvaa_write
},
2305 static const ARMCPRegInfo v7mp_cp_reginfo
[] = {
2306 /* 32 bit TLB invalidates, Inner Shareable */
2307 { .name
= "TLBIALLIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
2308 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
2309 .writefn
= tlbiall_is_write
},
2310 { .name
= "TLBIMVAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
2311 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
2312 .writefn
= tlbimva_is_write
},
2313 { .name
= "TLBIASIDIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
2314 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
2315 .writefn
= tlbiasid_is_write
},
2316 { .name
= "TLBIMVAAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
2317 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
2318 .writefn
= tlbimvaa_is_write
},
2321 static const ARMCPRegInfo pmovsset_cp_reginfo
[] = {
2322 /* PMOVSSET is not implemented in v7 before v7ve */
2323 { .name
= "PMOVSSET", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 3,
2324 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2326 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2327 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
2328 .writefn
= pmovsset_write
,
2329 .raw_writefn
= raw_write
},
2330 { .name
= "PMOVSSET_EL0", .state
= ARM_CP_STATE_AA64
,
2331 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 3,
2332 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2334 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2335 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
2336 .writefn
= pmovsset_write
,
2337 .raw_writefn
= raw_write
},
2340 static void teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2347 static CPAccessResult
teecr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2351 * HSTR.TTEE only exists in v7A, not v8A, but v8A doesn't have T2EE
2352 * at all, so we don't need to check whether we're v8A.
2354 if (arm_current_el(env
) < 2 && !arm_is_secure_below_el3(env
) &&
2355 (env
->cp15
.hstr_el2
& HSTR_TTEE
)) {
2356 return CP_ACCESS_TRAP_EL2
;
2358 return CP_ACCESS_OK
;
2361 static CPAccessResult
teehbr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2364 if (arm_current_el(env
) == 0 && (env
->teecr
& 1)) {
2365 return CP_ACCESS_TRAP
;
2367 return teecr_access(env
, ri
, isread
);
2370 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
2371 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
2372 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
2374 .writefn
= teecr_write
, .accessfn
= teecr_access
},
2375 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
2376 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
2377 .accessfn
= teehbr_access
, .resetvalue
= 0 },
2380 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
2381 { .name
= "TPIDR_EL0", .state
= ARM_CP_STATE_AA64
,
2382 .opc0
= 3, .opc1
= 3, .opc2
= 2, .crn
= 13, .crm
= 0,
2384 .fgt
= FGT_TPIDR_EL0
,
2385 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[0]), .resetvalue
= 0 },
2386 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
2388 .fgt
= FGT_TPIDR_EL0
,
2389 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrurw_s
),
2390 offsetoflow32(CPUARMState
, cp15
.tpidrurw_ns
) },
2391 .resetfn
= arm_cp_reset_ignore
},
2392 { .name
= "TPIDRRO_EL0", .state
= ARM_CP_STATE_AA64
,
2393 .opc0
= 3, .opc1
= 3, .opc2
= 3, .crn
= 13, .crm
= 0,
2394 .access
= PL0_R
| PL1_W
,
2395 .fgt
= FGT_TPIDRRO_EL0
,
2396 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidrro_el
[0]),
2398 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
2399 .access
= PL0_R
| PL1_W
,
2400 .fgt
= FGT_TPIDRRO_EL0
,
2401 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidruro_s
),
2402 offsetoflow32(CPUARMState
, cp15
.tpidruro_ns
) },
2403 .resetfn
= arm_cp_reset_ignore
},
2404 { .name
= "TPIDR_EL1", .state
= ARM_CP_STATE_AA64
,
2405 .opc0
= 3, .opc1
= 0, .opc2
= 4, .crn
= 13, .crm
= 0,
2407 .fgt
= FGT_TPIDR_EL1
,
2408 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[1]), .resetvalue
= 0 },
2409 { .name
= "TPIDRPRW", .opc1
= 0, .cp
= 15, .crn
= 13, .crm
= 0, .opc2
= 4,
2411 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrprw_s
),
2412 offsetoflow32(CPUARMState
, cp15
.tpidrprw_ns
) },
2416 #ifndef CONFIG_USER_ONLY
2418 static CPAccessResult
gt_cntfrq_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2422 * CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
2423 * Writable only at the highest implemented exception level.
2425 int el
= arm_current_el(env
);
2431 hcr
= arm_hcr_el2_eff(env
);
2432 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2433 cntkctl
= env
->cp15
.cnthctl_el2
;
2435 cntkctl
= env
->cp15
.c14_cntkctl
;
2437 if (!extract32(cntkctl
, 0, 2)) {
2438 return CP_ACCESS_TRAP
;
2442 if (!isread
&& ri
->state
== ARM_CP_STATE_AA32
&&
2443 arm_is_secure_below_el3(env
)) {
2444 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
2445 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2453 if (!isread
&& el
< arm_highest_el(env
)) {
2454 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2457 return CP_ACCESS_OK
;
2460 static CPAccessResult
gt_counter_access(CPUARMState
*env
, int timeridx
,
2463 unsigned int cur_el
= arm_current_el(env
);
2464 bool has_el2
= arm_is_el2_enabled(env
);
2465 uint64_t hcr
= arm_hcr_el2_eff(env
);
2469 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]CTEN. */
2470 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2471 return (extract32(env
->cp15
.cnthctl_el2
, timeridx
, 1)
2472 ? CP_ACCESS_OK
: CP_ACCESS_TRAP_EL2
);
2475 /* CNT[PV]CT: not visible from PL0 if EL0[PV]CTEN is zero */
2476 if (!extract32(env
->cp15
.c14_cntkctl
, timeridx
, 1)) {
2477 return CP_ACCESS_TRAP
;
2481 /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H. */
2482 if (has_el2
&& timeridx
== GTIMER_PHYS
&&
2484 ? !extract32(env
->cp15
.cnthctl_el2
, 10, 1)
2485 : !extract32(env
->cp15
.cnthctl_el2
, 0, 1))) {
2486 return CP_ACCESS_TRAP_EL2
;
2490 return CP_ACCESS_OK
;
2493 static CPAccessResult
gt_timer_access(CPUARMState
*env
, int timeridx
,
2496 unsigned int cur_el
= arm_current_el(env
);
2497 bool has_el2
= arm_is_el2_enabled(env
);
2498 uint64_t hcr
= arm_hcr_el2_eff(env
);
2502 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2503 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]TEN. */
2504 return (extract32(env
->cp15
.cnthctl_el2
, 9 - timeridx
, 1)
2505 ? CP_ACCESS_OK
: CP_ACCESS_TRAP_EL2
);
2509 * CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from
2510 * EL0 if EL0[PV]TEN is zero.
2512 if (!extract32(env
->cp15
.c14_cntkctl
, 9 - timeridx
, 1)) {
2513 return CP_ACCESS_TRAP
;
2518 if (has_el2
&& timeridx
== GTIMER_PHYS
) {
2519 if (hcr
& HCR_E2H
) {
2520 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PTEN. */
2521 if (!extract32(env
->cp15
.cnthctl_el2
, 11, 1)) {
2522 return CP_ACCESS_TRAP_EL2
;
2525 /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
2526 if (!extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
2527 return CP_ACCESS_TRAP_EL2
;
2533 return CP_ACCESS_OK
;
2536 static CPAccessResult
gt_pct_access(CPUARMState
*env
,
2537 const ARMCPRegInfo
*ri
,
2540 return gt_counter_access(env
, GTIMER_PHYS
, isread
);
2543 static CPAccessResult
gt_vct_access(CPUARMState
*env
,
2544 const ARMCPRegInfo
*ri
,
2547 return gt_counter_access(env
, GTIMER_VIRT
, isread
);
2550 static CPAccessResult
gt_ptimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2553 return gt_timer_access(env
, GTIMER_PHYS
, isread
);
2556 static CPAccessResult
gt_vtimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2559 return gt_timer_access(env
, GTIMER_VIRT
, isread
);
2562 static CPAccessResult
gt_stimer_access(CPUARMState
*env
,
2563 const ARMCPRegInfo
*ri
,
2567 * The AArch64 register view of the secure physical timer is
2568 * always accessible from EL3, and configurably accessible from
2571 switch (arm_current_el(env
)) {
2573 if (!arm_is_secure(env
)) {
2574 return CP_ACCESS_TRAP
;
2576 if (!(env
->cp15
.scr_el3
& SCR_ST
)) {
2577 return CP_ACCESS_TRAP_EL3
;
2579 return CP_ACCESS_OK
;
2582 return CP_ACCESS_TRAP
;
2584 return CP_ACCESS_OK
;
2586 g_assert_not_reached();
2590 static uint64_t gt_get_countervalue(CPUARMState
*env
)
2592 ARMCPU
*cpu
= env_archcpu(env
);
2594 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / gt_cntfrq_period_ns(cpu
);
2597 static void gt_update_irq(ARMCPU
*cpu
, int timeridx
)
2599 CPUARMState
*env
= &cpu
->env
;
2600 uint64_t cnthctl
= env
->cp15
.cnthctl_el2
;
2601 ARMSecuritySpace ss
= arm_security_space(env
);
2602 /* ISTATUS && !IMASK */
2603 int irqstate
= (env
->cp15
.c14_timer
[timeridx
].ctl
& 6) == 4;
2606 * If bit CNTHCTL_EL2.CNT[VP]MASK is set, it overrides IMASK.
2607 * It is RES0 in Secure and NonSecure state.
2609 if ((ss
== ARMSS_Root
|| ss
== ARMSS_Realm
) &&
2610 ((timeridx
== GTIMER_VIRT
&& (cnthctl
& CNTHCTL_CNTVMASK
)) ||
2611 (timeridx
== GTIMER_PHYS
&& (cnthctl
& CNTHCTL_CNTPMASK
)))) {
2615 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
2616 trace_arm_gt_update_irq(timeridx
, irqstate
);
2619 void gt_rme_post_el_change(ARMCPU
*cpu
, void *ignored
)
2622 * Changing security state between Root and Secure/NonSecure, which may
2623 * happen when switching EL, can change the effective value of CNTHCTL_EL2
2624 * mask bits. Update the IRQ state accordingly.
2626 gt_update_irq(cpu
, GTIMER_VIRT
);
2627 gt_update_irq(cpu
, GTIMER_PHYS
);
2630 static void gt_recalc_timer(ARMCPU
*cpu
, int timeridx
)
2632 ARMGenericTimer
*gt
= &cpu
->env
.cp15
.c14_timer
[timeridx
];
2636 * Timer enabled: calculate and set current ISTATUS, irq, and
2637 * reset timer to when ISTATUS next has to change
2639 uint64_t offset
= timeridx
== GTIMER_VIRT
?
2640 cpu
->env
.cp15
.cntvoff_el2
: 0;
2641 uint64_t count
= gt_get_countervalue(&cpu
->env
);
2642 /* Note that this must be unsigned 64 bit arithmetic: */
2643 int istatus
= count
- offset
>= gt
->cval
;
2646 gt
->ctl
= deposit32(gt
->ctl
, 2, 1, istatus
);
2649 /* Next transition is when count rolls back over to zero */
2650 nexttick
= UINT64_MAX
;
2652 /* Next transition is when we hit cval */
2653 nexttick
= gt
->cval
+ offset
;
2656 * Note that the desired next expiry time might be beyond the
2657 * signed-64-bit range of a QEMUTimer -- in this case we just
2658 * set the timer for as far in the future as possible. When the
2659 * timer expires we will reset the timer for any remaining period.
2661 if (nexttick
> INT64_MAX
/ gt_cntfrq_period_ns(cpu
)) {
2662 timer_mod_ns(cpu
->gt_timer
[timeridx
], INT64_MAX
);
2664 timer_mod(cpu
->gt_timer
[timeridx
], nexttick
);
2666 trace_arm_gt_recalc(timeridx
, nexttick
);
2668 /* Timer disabled: ISTATUS and timer output always clear */
2670 timer_del(cpu
->gt_timer
[timeridx
]);
2671 trace_arm_gt_recalc_disabled(timeridx
);
2673 gt_update_irq(cpu
, timeridx
);
2676 static void gt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2679 ARMCPU
*cpu
= env_archcpu(env
);
2681 timer_del(cpu
->gt_timer
[timeridx
]);
2684 static uint64_t gt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2686 return gt_get_countervalue(env
);
2689 static uint64_t gt_virt_cnt_offset(CPUARMState
*env
)
2693 switch (arm_current_el(env
)) {
2695 hcr
= arm_hcr_el2_eff(env
);
2696 if (hcr
& HCR_E2H
) {
2701 hcr
= arm_hcr_el2_eff(env
);
2702 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2708 return env
->cp15
.cntvoff_el2
;
2711 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2713 return gt_get_countervalue(env
) - gt_virt_cnt_offset(env
);
2716 static void gt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2720 trace_arm_gt_cval_write(timeridx
, value
);
2721 env
->cp15
.c14_timer
[timeridx
].cval
= value
;
2722 gt_recalc_timer(env_archcpu(env
), timeridx
);
2725 static uint64_t gt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2728 uint64_t offset
= 0;
2732 case GTIMER_HYPVIRT
:
2733 offset
= gt_virt_cnt_offset(env
);
2737 return (uint32_t)(env
->cp15
.c14_timer
[timeridx
].cval
-
2738 (gt_get_countervalue(env
) - offset
));
2741 static void gt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2745 uint64_t offset
= 0;
2749 case GTIMER_HYPVIRT
:
2750 offset
= gt_virt_cnt_offset(env
);
2754 trace_arm_gt_tval_write(timeridx
, value
);
2755 env
->cp15
.c14_timer
[timeridx
].cval
= gt_get_countervalue(env
) - offset
+
2756 sextract64(value
, 0, 32);
2757 gt_recalc_timer(env_archcpu(env
), timeridx
);
2760 static void gt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2764 ARMCPU
*cpu
= env_archcpu(env
);
2765 uint32_t oldval
= env
->cp15
.c14_timer
[timeridx
].ctl
;
2767 trace_arm_gt_ctl_write(timeridx
, value
);
2768 env
->cp15
.c14_timer
[timeridx
].ctl
= deposit64(oldval
, 0, 2, value
);
2769 if ((oldval
^ value
) & 1) {
2770 /* Enable toggled */
2771 gt_recalc_timer(cpu
, timeridx
);
2772 } else if ((oldval
^ value
) & 2) {
2774 * IMASK toggled: don't need to recalculate,
2775 * just set the interrupt line based on ISTATUS
2777 trace_arm_gt_imask_toggle(timeridx
);
2778 gt_update_irq(cpu
, timeridx
);
2782 static void gt_phys_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2784 gt_timer_reset(env
, ri
, GTIMER_PHYS
);
2787 static void gt_phys_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2790 gt_cval_write(env
, ri
, GTIMER_PHYS
, value
);
2793 static uint64_t gt_phys_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2795 return gt_tval_read(env
, ri
, GTIMER_PHYS
);
2798 static void gt_phys_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2801 gt_tval_write(env
, ri
, GTIMER_PHYS
, value
);
2804 static void gt_phys_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2807 gt_ctl_write(env
, ri
, GTIMER_PHYS
, value
);
2810 static int gt_phys_redir_timeridx(CPUARMState
*env
)
2812 switch (arm_mmu_idx(env
)) {
2813 case ARMMMUIdx_E20_0
:
2814 case ARMMMUIdx_E20_2
:
2815 case ARMMMUIdx_E20_2_PAN
:
2822 static int gt_virt_redir_timeridx(CPUARMState
*env
)
2824 switch (arm_mmu_idx(env
)) {
2825 case ARMMMUIdx_E20_0
:
2826 case ARMMMUIdx_E20_2
:
2827 case ARMMMUIdx_E20_2_PAN
:
2828 return GTIMER_HYPVIRT
;
2834 static uint64_t gt_phys_redir_cval_read(CPUARMState
*env
,
2835 const ARMCPRegInfo
*ri
)
2837 int timeridx
= gt_phys_redir_timeridx(env
);
2838 return env
->cp15
.c14_timer
[timeridx
].cval
;
2841 static void gt_phys_redir_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2844 int timeridx
= gt_phys_redir_timeridx(env
);
2845 gt_cval_write(env
, ri
, timeridx
, value
);
2848 static uint64_t gt_phys_redir_tval_read(CPUARMState
*env
,
2849 const ARMCPRegInfo
*ri
)
2851 int timeridx
= gt_phys_redir_timeridx(env
);
2852 return gt_tval_read(env
, ri
, timeridx
);
2855 static void gt_phys_redir_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2858 int timeridx
= gt_phys_redir_timeridx(env
);
2859 gt_tval_write(env
, ri
, timeridx
, value
);
2862 static uint64_t gt_phys_redir_ctl_read(CPUARMState
*env
,
2863 const ARMCPRegInfo
*ri
)
2865 int timeridx
= gt_phys_redir_timeridx(env
);
2866 return env
->cp15
.c14_timer
[timeridx
].ctl
;
2869 static void gt_phys_redir_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2872 int timeridx
= gt_phys_redir_timeridx(env
);
2873 gt_ctl_write(env
, ri
, timeridx
, value
);
2876 static void gt_virt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2878 gt_timer_reset(env
, ri
, GTIMER_VIRT
);
2881 static void gt_virt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2884 gt_cval_write(env
, ri
, GTIMER_VIRT
, value
);
2887 static uint64_t gt_virt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2889 return gt_tval_read(env
, ri
, GTIMER_VIRT
);
2892 static void gt_virt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2895 gt_tval_write(env
, ri
, GTIMER_VIRT
, value
);
2898 static void gt_virt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2901 gt_ctl_write(env
, ri
, GTIMER_VIRT
, value
);
2904 static void gt_cnthctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2907 ARMCPU
*cpu
= env_archcpu(env
);
2908 uint32_t oldval
= env
->cp15
.cnthctl_el2
;
2910 raw_write(env
, ri
, value
);
2912 if ((oldval
^ value
) & CNTHCTL_CNTVMASK
) {
2913 gt_update_irq(cpu
, GTIMER_VIRT
);
2914 } else if ((oldval
^ value
) & CNTHCTL_CNTPMASK
) {
2915 gt_update_irq(cpu
, GTIMER_PHYS
);
2919 static void gt_cntvoff_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2922 ARMCPU
*cpu
= env_archcpu(env
);
2924 trace_arm_gt_cntvoff_write(value
);
2925 raw_write(env
, ri
, value
);
2926 gt_recalc_timer(cpu
, GTIMER_VIRT
);
2929 static uint64_t gt_virt_redir_cval_read(CPUARMState
*env
,
2930 const ARMCPRegInfo
*ri
)
2932 int timeridx
= gt_virt_redir_timeridx(env
);
2933 return env
->cp15
.c14_timer
[timeridx
].cval
;
2936 static void gt_virt_redir_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2939 int timeridx
= gt_virt_redir_timeridx(env
);
2940 gt_cval_write(env
, ri
, timeridx
, value
);
2943 static uint64_t gt_virt_redir_tval_read(CPUARMState
*env
,
2944 const ARMCPRegInfo
*ri
)
2946 int timeridx
= gt_virt_redir_timeridx(env
);
2947 return gt_tval_read(env
, ri
, timeridx
);
2950 static void gt_virt_redir_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2953 int timeridx
= gt_virt_redir_timeridx(env
);
2954 gt_tval_write(env
, ri
, timeridx
, value
);
2957 static uint64_t gt_virt_redir_ctl_read(CPUARMState
*env
,
2958 const ARMCPRegInfo
*ri
)
2960 int timeridx
= gt_virt_redir_timeridx(env
);
2961 return env
->cp15
.c14_timer
[timeridx
].ctl
;
2964 static void gt_virt_redir_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2967 int timeridx
= gt_virt_redir_timeridx(env
);
2968 gt_ctl_write(env
, ri
, timeridx
, value
);
2971 static void gt_hyp_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2973 gt_timer_reset(env
, ri
, GTIMER_HYP
);
2976 static void gt_hyp_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2979 gt_cval_write(env
, ri
, GTIMER_HYP
, value
);
2982 static uint64_t gt_hyp_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2984 return gt_tval_read(env
, ri
, GTIMER_HYP
);
2987 static void gt_hyp_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2990 gt_tval_write(env
, ri
, GTIMER_HYP
, value
);
2993 static void gt_hyp_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2996 gt_ctl_write(env
, ri
, GTIMER_HYP
, value
);
2999 static void gt_sec_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3001 gt_timer_reset(env
, ri
, GTIMER_SEC
);
3004 static void gt_sec_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3007 gt_cval_write(env
, ri
, GTIMER_SEC
, value
);
3010 static uint64_t gt_sec_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3012 return gt_tval_read(env
, ri
, GTIMER_SEC
);
3015 static void gt_sec_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3018 gt_tval_write(env
, ri
, GTIMER_SEC
, value
);
3021 static void gt_sec_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3024 gt_ctl_write(env
, ri
, GTIMER_SEC
, value
);
3027 static void gt_hv_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3029 gt_timer_reset(env
, ri
, GTIMER_HYPVIRT
);
3032 static void gt_hv_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3035 gt_cval_write(env
, ri
, GTIMER_HYPVIRT
, value
);
3038 static uint64_t gt_hv_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3040 return gt_tval_read(env
, ri
, GTIMER_HYPVIRT
);
3043 static void gt_hv_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3046 gt_tval_write(env
, ri
, GTIMER_HYPVIRT
, value
);
3049 static void gt_hv_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3052 gt_ctl_write(env
, ri
, GTIMER_HYPVIRT
, value
);
3055 void arm_gt_ptimer_cb(void *opaque
)
3057 ARMCPU
*cpu
= opaque
;
3059 gt_recalc_timer(cpu
, GTIMER_PHYS
);
3062 void arm_gt_vtimer_cb(void *opaque
)
3064 ARMCPU
*cpu
= opaque
;
3066 gt_recalc_timer(cpu
, GTIMER_VIRT
);
3069 void arm_gt_htimer_cb(void *opaque
)
3071 ARMCPU
*cpu
= opaque
;
3073 gt_recalc_timer(cpu
, GTIMER_HYP
);
3076 void arm_gt_stimer_cb(void *opaque
)
3078 ARMCPU
*cpu
= opaque
;
3080 gt_recalc_timer(cpu
, GTIMER_SEC
);
3083 void arm_gt_hvtimer_cb(void *opaque
)
3085 ARMCPU
*cpu
= opaque
;
3087 gt_recalc_timer(cpu
, GTIMER_HYPVIRT
);
3090 static void arm_gt_cntfrq_reset(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
3092 ARMCPU
*cpu
= env_archcpu(env
);
3094 cpu
->env
.cp15
.c14_cntfrq
= cpu
->gt_cntfrq_hz
;
3097 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
3099 * Note that CNTFRQ is purely reads-as-written for the benefit
3100 * of software; writing it doesn't actually change the timer frequency.
3101 * Our reset value matches the fixed frequency we implement the timer at.
3103 { .name
= "CNTFRQ", .cp
= 15, .crn
= 14, .crm
= 0, .opc1
= 0, .opc2
= 0,
3104 .type
= ARM_CP_ALIAS
,
3105 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
3106 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c14_cntfrq
),
3108 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
3109 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
3110 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
3111 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
3112 .resetfn
= arm_gt_cntfrq_reset
,
3114 /* overall control: mostly access permissions */
3115 { .name
= "CNTKCTL", .state
= ARM_CP_STATE_BOTH
,
3116 .opc0
= 3, .opc1
= 0, .crn
= 14, .crm
= 1, .opc2
= 0,
3118 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntkctl
),
3121 /* per-timer control */
3122 { .name
= "CNTP_CTL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
3123 .secure
= ARM_CP_SECSTATE_NS
,
3124 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3125 .accessfn
= gt_ptimer_access
,
3126 .fieldoffset
= offsetoflow32(CPUARMState
,
3127 cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
3128 .readfn
= gt_phys_redir_ctl_read
, .raw_readfn
= raw_read
,
3129 .writefn
= gt_phys_redir_ctl_write
, .raw_writefn
= raw_write
,
3131 { .name
= "CNTP_CTL_S",
3132 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
3133 .secure
= ARM_CP_SECSTATE_S
,
3134 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3135 .accessfn
= gt_ptimer_access
,
3136 .fieldoffset
= offsetoflow32(CPUARMState
,
3137 cp15
.c14_timer
[GTIMER_SEC
].ctl
),
3138 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
3140 { .name
= "CNTP_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
3141 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 1,
3142 .type
= ARM_CP_IO
, .access
= PL0_RW
,
3143 .accessfn
= gt_ptimer_access
,
3144 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
3146 .readfn
= gt_phys_redir_ctl_read
, .raw_readfn
= raw_read
,
3147 .writefn
= gt_phys_redir_ctl_write
, .raw_writefn
= raw_write
,
3149 { .name
= "CNTV_CTL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 1,
3150 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3151 .accessfn
= gt_vtimer_access
,
3152 .fieldoffset
= offsetoflow32(CPUARMState
,
3153 cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
3154 .readfn
= gt_virt_redir_ctl_read
, .raw_readfn
= raw_read
,
3155 .writefn
= gt_virt_redir_ctl_write
, .raw_writefn
= raw_write
,
3157 { .name
= "CNTV_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
3158 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 1,
3159 .type
= ARM_CP_IO
, .access
= PL0_RW
,
3160 .accessfn
= gt_vtimer_access
,
3161 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
3163 .readfn
= gt_virt_redir_ctl_read
, .raw_readfn
= raw_read
,
3164 .writefn
= gt_virt_redir_ctl_write
, .raw_writefn
= raw_write
,
3166 /* TimerValue views: a 32 bit downcounting view of the underlying state */
3167 { .name
= "CNTP_TVAL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
3168 .secure
= ARM_CP_SECSTATE_NS
,
3169 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3170 .accessfn
= gt_ptimer_access
,
3171 .readfn
= gt_phys_redir_tval_read
, .writefn
= gt_phys_redir_tval_write
,
3173 { .name
= "CNTP_TVAL_S",
3174 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
3175 .secure
= ARM_CP_SECSTATE_S
,
3176 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3177 .accessfn
= gt_ptimer_access
,
3178 .readfn
= gt_sec_tval_read
, .writefn
= gt_sec_tval_write
,
3180 { .name
= "CNTP_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3181 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 0,
3182 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3183 .accessfn
= gt_ptimer_access
, .resetfn
= gt_phys_timer_reset
,
3184 .readfn
= gt_phys_redir_tval_read
, .writefn
= gt_phys_redir_tval_write
,
3186 { .name
= "CNTV_TVAL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 0,
3187 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3188 .accessfn
= gt_vtimer_access
,
3189 .readfn
= gt_virt_redir_tval_read
, .writefn
= gt_virt_redir_tval_write
,
3191 { .name
= "CNTV_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3192 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 0,
3193 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3194 .accessfn
= gt_vtimer_access
, .resetfn
= gt_virt_timer_reset
,
3195 .readfn
= gt_virt_redir_tval_read
, .writefn
= gt_virt_redir_tval_write
,
3197 /* The counter itself */
3198 { .name
= "CNTPCT", .cp
= 15, .crm
= 14, .opc1
= 0,
3199 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
3200 .accessfn
= gt_pct_access
,
3201 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
3203 { .name
= "CNTPCT_EL0", .state
= ARM_CP_STATE_AA64
,
3204 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 1,
3205 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3206 .accessfn
= gt_pct_access
, .readfn
= gt_cnt_read
,
3208 { .name
= "CNTVCT", .cp
= 15, .crm
= 14, .opc1
= 1,
3209 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
3210 .accessfn
= gt_vct_access
,
3211 .readfn
= gt_virt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
3213 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
3214 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
3215 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3216 .accessfn
= gt_vct_access
, .readfn
= gt_virt_cnt_read
,
3218 /* Comparison value, indicating when the timer goes off */
3219 { .name
= "CNTP_CVAL", .cp
= 15, .crm
= 14, .opc1
= 2,
3220 .secure
= ARM_CP_SECSTATE_NS
,
3222 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3223 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
3224 .accessfn
= gt_ptimer_access
,
3225 .readfn
= gt_phys_redir_cval_read
, .raw_readfn
= raw_read
,
3226 .writefn
= gt_phys_redir_cval_write
, .raw_writefn
= raw_write
,
3228 { .name
= "CNTP_CVAL_S", .cp
= 15, .crm
= 14, .opc1
= 2,
3229 .secure
= ARM_CP_SECSTATE_S
,
3231 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3232 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
3233 .accessfn
= gt_ptimer_access
,
3234 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
3236 { .name
= "CNTP_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3237 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 2,
3240 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
3241 .resetvalue
= 0, .accessfn
= gt_ptimer_access
,
3242 .readfn
= gt_phys_redir_cval_read
, .raw_readfn
= raw_read
,
3243 .writefn
= gt_phys_redir_cval_write
, .raw_writefn
= raw_write
,
3245 { .name
= "CNTV_CVAL", .cp
= 15, .crm
= 14, .opc1
= 3,
3247 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3248 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
3249 .accessfn
= gt_vtimer_access
,
3250 .readfn
= gt_virt_redir_cval_read
, .raw_readfn
= raw_read
,
3251 .writefn
= gt_virt_redir_cval_write
, .raw_writefn
= raw_write
,
3253 { .name
= "CNTV_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3254 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 2,
3257 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
3258 .resetvalue
= 0, .accessfn
= gt_vtimer_access
,
3259 .readfn
= gt_virt_redir_cval_read
, .raw_readfn
= raw_read
,
3260 .writefn
= gt_virt_redir_cval_write
, .raw_writefn
= raw_write
,
3263 * Secure timer -- this is actually restricted to only EL3
3264 * and configurably Secure-EL1 via the accessfn.
3266 { .name
= "CNTPS_TVAL_EL1", .state
= ARM_CP_STATE_AA64
,
3267 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 0,
3268 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
,
3269 .accessfn
= gt_stimer_access
,
3270 .readfn
= gt_sec_tval_read
,
3271 .writefn
= gt_sec_tval_write
,
3272 .resetfn
= gt_sec_timer_reset
,
3274 { .name
= "CNTPS_CTL_EL1", .state
= ARM_CP_STATE_AA64
,
3275 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 1,
3276 .type
= ARM_CP_IO
, .access
= PL1_RW
,
3277 .accessfn
= gt_stimer_access
,
3278 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].ctl
),
3280 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
3282 { .name
= "CNTPS_CVAL_EL1", .state
= ARM_CP_STATE_AA64
,
3283 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 2,
3284 .type
= ARM_CP_IO
, .access
= PL1_RW
,
3285 .accessfn
= gt_stimer_access
,
3286 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
3287 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
3291 static CPAccessResult
e2h_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3294 if (!(arm_hcr_el2_eff(env
) & HCR_E2H
)) {
3295 return CP_ACCESS_TRAP
;
3297 return CP_ACCESS_OK
;
3303 * In user-mode most of the generic timer registers are inaccessible
3304 * however modern kernels (4.12+) allow access to cntvct_el0
3307 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3309 ARMCPU
*cpu
= env_archcpu(env
);
3312 * Currently we have no support for QEMUTimer in linux-user so we
3313 * can't call gt_get_countervalue(env), instead we directly
3314 * call the lower level functions.
3316 return cpu_get_clock() / gt_cntfrq_period_ns(cpu
);
3319 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
3320 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
3321 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
3322 .type
= ARM_CP_CONST
, .access
= PL0_R
/* no PL1_RW in linux-user */,
3323 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
3324 .resetvalue
= NANOSECONDS_PER_SECOND
/ GTIMER_SCALE
,
3326 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
3327 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
3328 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3329 .readfn
= gt_virt_cnt_read
,
3335 static void par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3337 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3338 raw_write(env
, ri
, value
);
3339 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
3340 raw_write(env
, ri
, value
& 0xfffff6ff);
3342 raw_write(env
, ri
, value
& 0xfffff1ff);
3346 #ifndef CONFIG_USER_ONLY
3347 /* get_phys_addr() isn't present for user-mode-only targets */
3349 static CPAccessResult
ats_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3354 * The ATS12NSO* operations must trap to EL3 or EL2 if executed in
3355 * Secure EL1 (which can only happen if EL3 is AArch64).
3356 * They are simply UNDEF if executed from NS EL1.
3357 * They function normally from EL2 or EL3.
3359 if (arm_current_el(env
) == 1) {
3360 if (arm_is_secure_below_el3(env
)) {
3361 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
3362 return CP_ACCESS_TRAP_EL2
;
3364 return CP_ACCESS_TRAP_EL3
;
3366 return CP_ACCESS_TRAP_UNCATEGORIZED
;
3369 return CP_ACCESS_OK
;
3373 static int par_el1_shareability(GetPhysAddrResult
*res
)
3376 * The PAR_EL1.SH field must be 0b10 for Device or Normal-NC
3377 * memory -- see pseudocode PAREncodeShareability().
3379 if (((res
->cacheattrs
.attrs
& 0xf0) == 0) ||
3380 res
->cacheattrs
.attrs
== 0x44 || res
->cacheattrs
.attrs
== 0x40) {
3383 return res
->cacheattrs
.shareability
;
3386 static uint64_t do_ats_write(CPUARMState
*env
, uint64_t value
,
3387 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
3388 ARMSecuritySpace ss
)
3392 bool format64
= false;
3393 ARMMMUFaultInfo fi
= {};
3394 GetPhysAddrResult res
= {};
3397 * I_MXTJT: Granule protection checks are not performed on the final address
3398 * of a successful translation.
3400 ret
= get_phys_addr_with_space_nogpc(env
, value
, access_type
, mmu_idx
, ss
,
3404 * ATS operations only do S1 or S1+S2 translations, so we never
3405 * have to deal with the ARMCacheAttrs format for S2 only.
3407 assert(!res
.cacheattrs
.is_s2_format
);
3411 * Some kinds of translation fault must cause exceptions rather
3412 * than being reported in the PAR.
3414 int current_el
= arm_current_el(env
);
3416 uint32_t syn
, fsr
, fsc
;
3417 bool take_exc
= false;
3419 if (fi
.s1ptw
&& current_el
== 1
3420 && arm_mmu_idx_is_stage1_of_2(mmu_idx
)) {
3422 * Synchronous stage 2 fault on an access made as part of the
3423 * translation table walk for AT S1E0* or AT S1E1* insn
3424 * executed from NS EL1. If this is a synchronous external abort
3425 * and SCR_EL3.EA == 1, then we take a synchronous external abort
3426 * to EL3. Otherwise the fault is taken as an exception to EL2,
3427 * and HPFAR_EL2 holds the faulting IPA.
3429 if (fi
.type
== ARMFault_SyncExternalOnWalk
&&
3430 (env
->cp15
.scr_el3
& SCR_EA
)) {
3433 env
->cp15
.hpfar_el2
= extract64(fi
.s2addr
, 12, 47) << 4;
3434 if (arm_is_secure_below_el3(env
) && fi
.s1ns
) {
3435 env
->cp15
.hpfar_el2
|= HPFAR_NS
;
3440 } else if (fi
.type
== ARMFault_SyncExternalOnWalk
) {
3442 * Synchronous external aborts during a translation table walk
3443 * are taken as Data Abort exceptions.
3446 if (current_el
== 3) {
3452 target_el
= exception_target_el(env
);
3458 /* Construct FSR and FSC using same logic as arm_deliver_fault() */
3459 if (target_el
== 2 || arm_el_is_aa64(env
, target_el
) ||
3460 arm_s1_regime_using_lpae_format(env
, mmu_idx
)) {
3461 fsr
= arm_fi_to_lfsc(&fi
);
3462 fsc
= extract32(fsr
, 0, 6);
3464 fsr
= arm_fi_to_sfsc(&fi
);
3468 * Report exception with ESR indicating a fault due to a
3469 * translation table walk for a cache maintenance instruction.
3471 syn
= syn_data_abort_no_iss(current_el
== target_el
, 0,
3472 fi
.ea
, 1, fi
.s1ptw
, 1, fsc
);
3473 env
->exception
.vaddress
= value
;
3474 env
->exception
.fsr
= fsr
;
3475 raise_exception(env
, EXCP_DATA_ABORT
, syn
, target_el
);
3481 } else if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3484 * * TTBCR.EAE determines whether the result is returned using the
3485 * 32-bit or the 64-bit PAR format
3486 * * Instructions executed in Hyp mode always use the 64bit format
3488 * ATS1S2NSOxx uses the 64bit format if any of the following is true:
3489 * * The Non-secure TTBCR.EAE bit is set to 1
3490 * * The implementation includes EL2, and the value of HCR.VM is 1
3492 * (Note that HCR.DC makes HCR.VM behave as if it is 1.)
3494 * ATS1Hx always uses the 64bit format.
3496 format64
= arm_s1_regime_using_lpae_format(env
, mmu_idx
);
3498 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
3499 if (mmu_idx
== ARMMMUIdx_E10_0
||
3500 mmu_idx
== ARMMMUIdx_E10_1
||
3501 mmu_idx
== ARMMMUIdx_E10_1_PAN
) {
3502 format64
|= env
->cp15
.hcr_el2
& (HCR_VM
| HCR_DC
);
3504 format64
|= arm_current_el(env
) == 2;
3510 /* Create a 64-bit PAR */
3511 par64
= (1 << 11); /* LPAE bit always set */
3513 par64
|= res
.f
.phys_addr
& ~0xfffULL
;
3514 if (!res
.f
.attrs
.secure
) {
3515 par64
|= (1 << 9); /* NS */
3517 par64
|= (uint64_t)res
.cacheattrs
.attrs
<< 56; /* ATTR */
3518 par64
|= par_el1_shareability(&res
) << 7; /* SH */
3520 uint32_t fsr
= arm_fi_to_lfsc(&fi
);
3523 par64
|= (fsr
& 0x3f) << 1; /* FS */
3525 par64
|= (1 << 9); /* S */
3528 par64
|= (1 << 8); /* PTW */
3533 * fsr is a DFSR/IFSR value for the short descriptor
3534 * translation table format (with WnR always clear).
3535 * Convert it to a 32-bit PAR.
3538 /* We do not set any attribute bits in the PAR */
3539 if (res
.f
.lg_page_size
== 24
3540 && arm_feature(env
, ARM_FEATURE_V7
)) {
3541 par64
= (res
.f
.phys_addr
& 0xff000000) | (1 << 1);
3543 par64
= res
.f
.phys_addr
& 0xfffff000;
3545 if (!res
.f
.attrs
.secure
) {
3546 par64
|= (1 << 9); /* NS */
3549 uint32_t fsr
= arm_fi_to_sfsc(&fi
);
3551 par64
= ((fsr
& (1 << 10)) >> 5) | ((fsr
& (1 << 12)) >> 6) |
3552 ((fsr
& 0xf) << 1) | 1;
3557 #endif /* CONFIG_TCG */
3559 static void ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3562 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3565 int el
= arm_current_el(env
);
3566 ARMSecuritySpace ss
= arm_security_space(env
);
3568 switch (ri
->opc2
& 6) {
3570 /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP */
3573 mmu_idx
= ARMMMUIdx_E3
;
3576 g_assert(ss
!= ARMSS_Secure
); /* ARMv8.4-SecEL2 is 64-bit only */
3579 if (ri
->crm
== 9 && (env
->uncached_cpsr
& CPSR_PAN
)) {
3580 mmu_idx
= ARMMMUIdx_Stage1_E1_PAN
;
3582 mmu_idx
= ARMMMUIdx_Stage1_E1
;
3586 g_assert_not_reached();
3590 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
3593 mmu_idx
= ARMMMUIdx_E10_0
;
3596 g_assert(ss
!= ARMSS_Secure
); /* ARMv8.4-SecEL2 is 64-bit only */
3597 mmu_idx
= ARMMMUIdx_Stage1_E0
;
3600 mmu_idx
= ARMMMUIdx_Stage1_E0
;
3603 g_assert_not_reached();
3607 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
3608 mmu_idx
= ARMMMUIdx_E10_1
;
3609 ss
= ARMSS_NonSecure
;
3612 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
3613 mmu_idx
= ARMMMUIdx_E10_0
;
3614 ss
= ARMSS_NonSecure
;
3617 g_assert_not_reached();
3620 par64
= do_ats_write(env
, value
, access_type
, mmu_idx
, ss
);
3622 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3624 /* Handled by hardware accelerator. */
3625 g_assert_not_reached();
3626 #endif /* CONFIG_TCG */
3629 static void ats1h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3633 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3636 /* There is no SecureEL2 for AArch32. */
3637 par64
= do_ats_write(env
, value
, access_type
, ARMMMUIdx_E2
,
3640 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3642 /* Handled by hardware accelerator. */
3643 g_assert_not_reached();
3644 #endif /* CONFIG_TCG */
3647 static CPAccessResult
at_e012_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3651 * R_NYXTL: instruction is UNDEFINED if it applies to an Exception level
3652 * lower than EL3 and the combination SCR_EL3.{NSE,NS} is reserved. This can
3653 * only happen when executing at EL3 because that combination also causes an
3654 * illegal exception return. We don't need to check FEAT_RME either, because
3655 * scr_write() ensures that the NSE bit is not set otherwise.
3657 if ((env
->cp15
.scr_el3
& (SCR_NSE
| SCR_NS
)) == SCR_NSE
) {
3658 return CP_ACCESS_TRAP
;
3660 return CP_ACCESS_OK
;
3663 static CPAccessResult
at_s1e2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3666 if (arm_current_el(env
) == 3 &&
3667 !(env
->cp15
.scr_el3
& (SCR_NS
| SCR_EEL2
))) {
3668 return CP_ACCESS_TRAP
;
3670 return at_e012_access(env
, ri
, isread
);
3673 static void ats_write64(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3677 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3679 uint64_t hcr_el2
= arm_hcr_el2_eff(env
);
3680 bool regime_e20
= (hcr_el2
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
);
3682 switch (ri
->opc2
& 6) {
3685 case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */
3686 if (ri
->crm
== 9 && (env
->pstate
& PSTATE_PAN
)) {
3687 mmu_idx
= regime_e20
?
3688 ARMMMUIdx_E20_2_PAN
: ARMMMUIdx_Stage1_E1_PAN
;
3690 mmu_idx
= regime_e20
? ARMMMUIdx_E20_2
: ARMMMUIdx_Stage1_E1
;
3693 case 4: /* AT S1E2R, AT S1E2W */
3694 mmu_idx
= hcr_el2
& HCR_E2H
? ARMMMUIdx_E20_2
: ARMMMUIdx_E2
;
3696 case 6: /* AT S1E3R, AT S1E3W */
3697 mmu_idx
= ARMMMUIdx_E3
;
3700 g_assert_not_reached();
3703 case 2: /* AT S1E0R, AT S1E0W */
3704 mmu_idx
= regime_e20
? ARMMMUIdx_E20_0
: ARMMMUIdx_Stage1_E0
;
3706 case 4: /* AT S12E1R, AT S12E1W */
3707 mmu_idx
= regime_e20
? ARMMMUIdx_E20_2
: ARMMMUIdx_E10_1
;
3709 case 6: /* AT S12E0R, AT S12E0W */
3710 mmu_idx
= regime_e20
? ARMMMUIdx_E20_0
: ARMMMUIdx_E10_0
;
3713 g_assert_not_reached();
3716 env
->cp15
.par_el
[1] = do_ats_write(env
, value
, access_type
,
3717 mmu_idx
, arm_security_space(env
));
3719 /* Handled by hardware accelerator. */
3720 g_assert_not_reached();
3721 #endif /* CONFIG_TCG */
3725 /* Return basic MPU access permission bits. */
3726 static uint32_t simple_mpu_ap_bits(uint32_t val
)
3733 for (i
= 0; i
< 16; i
+= 2) {
3734 ret
|= (val
>> i
) & mask
;
3740 /* Pad basic MPU access permission bits to extended format. */
3741 static uint32_t extended_mpu_ap_bits(uint32_t val
)
3748 for (i
= 0; i
< 16; i
+= 2) {
3749 ret
|= (val
& mask
) << i
;
3755 static void pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3758 env
->cp15
.pmsav5_data_ap
= extended_mpu_ap_bits(value
);
3761 static uint64_t pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3763 return simple_mpu_ap_bits(env
->cp15
.pmsav5_data_ap
);
3766 static void pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3769 env
->cp15
.pmsav5_insn_ap
= extended_mpu_ap_bits(value
);
3772 static uint64_t pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3774 return simple_mpu_ap_bits(env
->cp15
.pmsav5_insn_ap
);
3777 static uint64_t pmsav7_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3779 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3785 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3789 static void pmsav7_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3792 ARMCPU
*cpu
= env_archcpu(env
);
3793 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3799 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3800 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3804 static void pmsav7_rgnr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3807 ARMCPU
*cpu
= env_archcpu(env
);
3808 uint32_t nrgs
= cpu
->pmsav7_dregion
;
3810 if (value
>= nrgs
) {
3811 qemu_log_mask(LOG_GUEST_ERROR
,
3812 "PMSAv7 RGNR write >= # supported regions, %" PRIu32
3813 " > %" PRIu32
"\n", (uint32_t)value
, nrgs
);
3817 raw_write(env
, ri
, value
);
3820 static void prbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3823 ARMCPU
*cpu
= env_archcpu(env
);
3825 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3826 env
->pmsav8
.rbar
[M_REG_NS
][env
->pmsav7
.rnr
[M_REG_NS
]] = value
;
3829 static uint64_t prbar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3831 return env
->pmsav8
.rbar
[M_REG_NS
][env
->pmsav7
.rnr
[M_REG_NS
]];
3834 static void prlar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3837 ARMCPU
*cpu
= env_archcpu(env
);
3839 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3840 env
->pmsav8
.rlar
[M_REG_NS
][env
->pmsav7
.rnr
[M_REG_NS
]] = value
;
3843 static uint64_t prlar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3845 return env
->pmsav8
.rlar
[M_REG_NS
][env
->pmsav7
.rnr
[M_REG_NS
]];
3848 static void prselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3851 ARMCPU
*cpu
= env_archcpu(env
);
3854 * Ignore writes that would select not implemented region.
3855 * This is architecturally UNPREDICTABLE.
3857 if (value
>= cpu
->pmsav7_dregion
) {
3861 env
->pmsav7
.rnr
[M_REG_NS
] = value
;
3864 static void hprbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3867 ARMCPU
*cpu
= env_archcpu(env
);
3869 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3870 env
->pmsav8
.hprbar
[env
->pmsav8
.hprselr
] = value
;
3873 static uint64_t hprbar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3875 return env
->pmsav8
.hprbar
[env
->pmsav8
.hprselr
];
3878 static void hprlar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3881 ARMCPU
*cpu
= env_archcpu(env
);
3883 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3884 env
->pmsav8
.hprlar
[env
->pmsav8
.hprselr
] = value
;
3887 static uint64_t hprlar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3889 return env
->pmsav8
.hprlar
[env
->pmsav8
.hprselr
];
3892 static void hprenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3897 ARMCPU
*cpu
= env_archcpu(env
);
3899 /* Ignore writes to unimplemented regions */
3900 int rmax
= MIN(cpu
->pmsav8r_hdregion
, 32);
3901 value
&= MAKE_64BIT_MASK(0, rmax
);
3903 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3905 /* Register alias is only valid for first 32 indexes */
3906 for (n
= 0; n
< rmax
; ++n
) {
3907 bit
= extract32(value
, n
, 1);
3908 env
->pmsav8
.hprlar
[n
] = deposit32(
3909 env
->pmsav8
.hprlar
[n
], 0, 1, bit
);
3913 static uint64_t hprenr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3916 uint32_t result
= 0x0;
3917 ARMCPU
*cpu
= env_archcpu(env
);
3919 /* Register alias is only valid for first 32 indexes */
3920 for (n
= 0; n
< MIN(cpu
->pmsav8r_hdregion
, 32); ++n
) {
3921 if (env
->pmsav8
.hprlar
[n
] & 0x1) {
3922 result
|= (0x1 << n
);
3928 static void hprselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3931 ARMCPU
*cpu
= env_archcpu(env
);
3934 * Ignore writes that would select not implemented region.
3935 * This is architecturally UNPREDICTABLE.
3937 if (value
>= cpu
->pmsav8r_hdregion
) {
3941 env
->pmsav8
.hprselr
= value
;
3944 static void pmsav8r_regn_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3947 ARMCPU
*cpu
= env_archcpu(env
);
3948 uint8_t index
= (extract32(ri
->opc0
, 0, 1) << 4) |
3949 (extract32(ri
->crm
, 0, 3) << 1) | extract32(ri
->opc2
, 2, 1);
3951 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3954 if (index
>= cpu
->pmsav8r_hdregion
) {
3957 if (ri
->opc2
& 0x1) {
3958 env
->pmsav8
.hprlar
[index
] = value
;
3960 env
->pmsav8
.hprbar
[index
] = value
;
3963 if (index
>= cpu
->pmsav7_dregion
) {
3966 if (ri
->opc2
& 0x1) {
3967 env
->pmsav8
.rlar
[M_REG_NS
][index
] = value
;
3969 env
->pmsav8
.rbar
[M_REG_NS
][index
] = value
;
3974 static uint64_t pmsav8r_regn_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3976 ARMCPU
*cpu
= env_archcpu(env
);
3977 uint8_t index
= (extract32(ri
->opc0
, 0, 1) << 4) |
3978 (extract32(ri
->crm
, 0, 3) << 1) | extract32(ri
->opc2
, 2, 1);
3981 if (index
>= cpu
->pmsav8r_hdregion
) {
3984 if (ri
->opc2
& 0x1) {
3985 return env
->pmsav8
.hprlar
[index
];
3987 return env
->pmsav8
.hprbar
[index
];
3990 if (index
>= cpu
->pmsav7_dregion
) {
3993 if (ri
->opc2
& 0x1) {
3994 return env
->pmsav8
.rlar
[M_REG_NS
][index
];
3996 return env
->pmsav8
.rbar
[M_REG_NS
][index
];
4001 static const ARMCPRegInfo pmsav8r_cp_reginfo
[] = {
4003 .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 3, .opc2
= 0,
4004 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
4005 .accessfn
= access_tvm_trvm
,
4006 .readfn
= prbar_read
, .writefn
= prbar_write
},
4008 .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 3, .opc2
= 1,
4009 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
4010 .accessfn
= access_tvm_trvm
,
4011 .readfn
= prlar_read
, .writefn
= prlar_write
},
4012 { .name
= "PRSELR", .resetvalue
= 0,
4013 .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 2, .opc2
= 1,
4014 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4015 .writefn
= prselr_write
,
4016 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.rnr
[M_REG_NS
]) },
4017 { .name
= "HPRBAR", .resetvalue
= 0,
4018 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 3, .opc2
= 0,
4019 .access
= PL2_RW
, .type
= ARM_CP_NO_RAW
,
4020 .readfn
= hprbar_read
, .writefn
= hprbar_write
},
4022 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 3, .opc2
= 1,
4023 .access
= PL2_RW
, .type
= ARM_CP_NO_RAW
,
4024 .readfn
= hprlar_read
, .writefn
= hprlar_write
},
4025 { .name
= "HPRSELR", .resetvalue
= 0,
4026 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 2, .opc2
= 1,
4028 .writefn
= hprselr_write
,
4029 .fieldoffset
= offsetof(CPUARMState
, pmsav8
.hprselr
) },
4031 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 1, .opc2
= 1,
4032 .access
= PL2_RW
, .type
= ARM_CP_NO_RAW
,
4033 .readfn
= hprenr_read
, .writefn
= hprenr_write
},
4036 static const ARMCPRegInfo pmsav7_cp_reginfo
[] = {
4038 * Reset for all these registers is handled in arm_cpu_reset(),
4039 * because the PMSAv7 is also used by M-profile CPUs, which do
4040 * not register cpregs but still need the state to be reset.
4042 { .name
= "DRBAR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 0,
4043 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
4044 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drbar
),
4045 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
4046 .resetfn
= arm_cp_reset_ignore
},
4047 { .name
= "DRSR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 2,
4048 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
4049 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drsr
),
4050 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
4051 .resetfn
= arm_cp_reset_ignore
},
4052 { .name
= "DRACR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 4,
4053 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
4054 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.dracr
),
4055 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
4056 .resetfn
= arm_cp_reset_ignore
},
4057 { .name
= "RGNR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 2, .opc2
= 0,
4059 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.rnr
[M_REG_NS
]),
4060 .writefn
= pmsav7_rgnr_write
,
4061 .resetfn
= arm_cp_reset_ignore
},
4064 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
4065 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
4066 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
4067 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
4068 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
4069 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
4070 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
4071 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
4072 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
4073 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
4075 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
4077 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
4079 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
4081 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
4083 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
4084 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
4086 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
4087 /* Protection region base and size registers */
4088 { .name
= "946_PRBS0", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0,
4089 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4090 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[0]) },
4091 { .name
= "946_PRBS1", .cp
= 15, .crn
= 6, .crm
= 1, .opc1
= 0,
4092 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4093 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[1]) },
4094 { .name
= "946_PRBS2", .cp
= 15, .crn
= 6, .crm
= 2, .opc1
= 0,
4095 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4096 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[2]) },
4097 { .name
= "946_PRBS3", .cp
= 15, .crn
= 6, .crm
= 3, .opc1
= 0,
4098 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4099 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[3]) },
4100 { .name
= "946_PRBS4", .cp
= 15, .crn
= 6, .crm
= 4, .opc1
= 0,
4101 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4102 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[4]) },
4103 { .name
= "946_PRBS5", .cp
= 15, .crn
= 6, .crm
= 5, .opc1
= 0,
4104 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4105 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[5]) },
4106 { .name
= "946_PRBS6", .cp
= 15, .crn
= 6, .crm
= 6, .opc1
= 0,
4107 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4108 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[6]) },
4109 { .name
= "946_PRBS7", .cp
= 15, .crn
= 6, .crm
= 7, .opc1
= 0,
4110 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4111 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[7]) },
4114 static void vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4117 ARMCPU
*cpu
= env_archcpu(env
);
4119 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
4120 if (arm_feature(env
, ARM_FEATURE_LPAE
) && (value
& TTBCR_EAE
)) {
4122 * Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
4123 * using Long-descriptor translation table format
4125 value
&= ~((7 << 19) | (3 << 14) | (0xf << 3));
4126 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
4128 * In an implementation that includes the Security Extensions
4129 * TTBCR has additional fields PD0 [4] and PD1 [5] for
4130 * Short-descriptor translation table format.
4132 value
&= TTBCR_PD1
| TTBCR_PD0
| TTBCR_N
;
4138 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
4140 * With LPAE the TTBCR could result in a change of ASID
4141 * via the TTBCR.A1 bit, so do a TLB flush.
4143 tlb_flush(CPU(cpu
));
4145 raw_write(env
, ri
, value
);
4148 static void vmsa_tcr_el12_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4151 ARMCPU
*cpu
= env_archcpu(env
);
4153 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
4154 tlb_flush(CPU(cpu
));
4155 raw_write(env
, ri
, value
);
4158 static void vmsa_ttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4161 /* If the ASID changes (with a 64-bit write), we must flush the TLB. */
4162 if (cpreg_field_is_64bit(ri
) &&
4163 extract64(raw_read(env
, ri
) ^ value
, 48, 16) != 0) {
4164 ARMCPU
*cpu
= env_archcpu(env
);
4165 tlb_flush(CPU(cpu
));
4167 raw_write(env
, ri
, value
);
4170 static void vmsa_tcr_ttbr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4174 * If we are running with E2&0 regime, then an ASID is active.
4175 * Flush if that might be changing. Note we're not checking
4176 * TCR_EL2.A1 to know if this is really the TTBRx_EL2 that
4177 * holds the active ASID, only checking the field that might.
4179 if (extract64(raw_read(env
, ri
) ^ value
, 48, 16) &&
4180 (arm_hcr_el2_eff(env
) & HCR_E2H
)) {
4181 uint16_t mask
= ARMMMUIdxBit_E20_2
|
4182 ARMMMUIdxBit_E20_2_PAN
|
4184 tlb_flush_by_mmuidx(env_cpu(env
), mask
);
4186 raw_write(env
, ri
, value
);
4189 static void vttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4192 ARMCPU
*cpu
= env_archcpu(env
);
4193 CPUState
*cs
= CPU(cpu
);
4196 * A change in VMID to the stage2 page table (Stage2) invalidates
4197 * the stage2 and combined stage 1&2 tlbs (EL10_1 and EL10_0).
4199 if (extract64(raw_read(env
, ri
) ^ value
, 48, 16) != 0) {
4200 tlb_flush_by_mmuidx(cs
, alle1_tlbmask(env
));
4202 raw_write(env
, ri
, value
);
4205 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo
[] = {
4206 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
4207 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .type
= ARM_CP_ALIAS
,
4208 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dfsr_s
),
4209 offsetoflow32(CPUARMState
, cp15
.dfsr_ns
) }, },
4210 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
4211 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
4212 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.ifsr_s
),
4213 offsetoflow32(CPUARMState
, cp15
.ifsr_ns
) } },
4214 { .name
= "DFAR", .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 0, .opc2
= 0,
4215 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
4216 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.dfar_s
),
4217 offsetof(CPUARMState
, cp15
.dfar_ns
) } },
4218 { .name
= "FAR_EL1", .state
= ARM_CP_STATE_AA64
,
4219 .opc0
= 3, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
4220 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4222 .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[1]),
4226 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
4227 { .name
= "ESR_EL1", .state
= ARM_CP_STATE_AA64
,
4228 .opc0
= 3, .crn
= 5, .crm
= 2, .opc1
= 0, .opc2
= 0,
4229 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4231 .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[1]), .resetvalue
= 0, },
4232 { .name
= "TTBR0_EL1", .state
= ARM_CP_STATE_BOTH
,
4233 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 0,
4234 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4235 .fgt
= FGT_TTBR0_EL1
,
4236 .writefn
= vmsa_ttbr_write
, .resetvalue
= 0, .raw_writefn
= raw_write
,
4237 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
4238 offsetof(CPUARMState
, cp15
.ttbr0_ns
) } },
4239 { .name
= "TTBR1_EL1", .state
= ARM_CP_STATE_BOTH
,
4240 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 1,
4241 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4242 .fgt
= FGT_TTBR1_EL1
,
4243 .writefn
= vmsa_ttbr_write
, .resetvalue
= 0, .raw_writefn
= raw_write
,
4244 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
4245 offsetof(CPUARMState
, cp15
.ttbr1_ns
) } },
4246 { .name
= "TCR_EL1", .state
= ARM_CP_STATE_AA64
,
4247 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
4248 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4250 .writefn
= vmsa_tcr_el12_write
,
4251 .raw_writefn
= raw_write
,
4253 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[1]) },
4254 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
4255 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4256 .type
= ARM_CP_ALIAS
, .writefn
= vmsa_ttbcr_write
,
4257 .raw_writefn
= raw_write
,
4258 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tcr_el
[3]),
4259 offsetoflow32(CPUARMState
, cp15
.tcr_el
[1])} },
4263 * Note that unlike TTBCR, writing to TTBCR2 does not require flushing
4264 * qemu tlbs nor adjusting cached masks.
4266 static const ARMCPRegInfo ttbcr2_reginfo
= {
4267 .name
= "TTBCR2", .cp
= 15, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 3,
4268 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4269 .type
= ARM_CP_ALIAS
,
4270 .bank_fieldoffsets
= {
4271 offsetofhigh32(CPUARMState
, cp15
.tcr_el
[3]),
4272 offsetofhigh32(CPUARMState
, cp15
.tcr_el
[1]),
4276 static void omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4279 env
->cp15
.c15_ticonfig
= value
& 0xe7;
4280 /* The OS_TYPE bit in this register changes the reported CPUID! */
4281 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
4282 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
4285 static void omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4288 env
->cp15
.c15_threadid
= value
& 0xffff;
4291 static void omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4294 /* Wait-for-interrupt (deprecated) */
4295 cpu_interrupt(env_cpu(env
), CPU_INTERRUPT_HALT
);
4298 static void omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4302 * On OMAP there are registers indicating the max/min index of dcache lines
4303 * containing a dirty line; cache flush operations have to reset these.
4305 env
->cp15
.c15_i_max
= 0x000;
4306 env
->cp15
.c15_i_min
= 0xff0;
4309 static const ARMCPRegInfo omap_cp_reginfo
[] = {
4310 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
4311 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
4312 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.esr_el
[1]),
4314 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
4315 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
4316 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
4318 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
4319 .writefn
= omap_ticonfig_write
},
4320 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
4322 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
4323 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
4324 .access
= PL1_RW
, .resetvalue
= 0xff0,
4325 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
4326 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
4328 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
4329 .writefn
= omap_threadid_write
},
4330 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
4331 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
4332 .type
= ARM_CP_NO_RAW
,
4333 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
4335 * TODO: Peripheral port remap register:
4336 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
4337 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
4340 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
4341 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
4342 .type
= ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
,
4343 .writefn
= omap_cachemaint_write
},
4344 { .name
= "C9", .cp
= 15, .crn
= 9,
4345 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
4346 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
4349 static void xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4352 env
->cp15
.c15_cpar
= value
& 0x3fff;
4355 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
4356 { .name
= "XSCALE_CPAR",
4357 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
4358 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
4359 .writefn
= xscale_cpar_write
, },
4360 { .name
= "XSCALE_AUXCR",
4361 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
4362 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
4365 * XScale specific cache-lockdown: since we have no cache we NOP these
4366 * and hope the guest does not really rely on cache behaviour.
4368 { .name
= "XSCALE_LOCK_ICACHE_LINE",
4369 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
4370 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4371 { .name
= "XSCALE_UNLOCK_ICACHE",
4372 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
4373 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4374 { .name
= "XSCALE_DCACHE_LOCK",
4375 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 0,
4376 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
4377 { .name
= "XSCALE_UNLOCK_DCACHE",
4378 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 1,
4379 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4382 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
4384 * RAZ/WI the whole crn=15 space, when we don't have a more specific
4385 * implementation of this implementation-defined space.
4386 * Ideally this should eventually disappear in favour of actually
4387 * implementing the correct behaviour for all cores.
4389 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
4390 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
4392 .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
| ARM_CP_OVERRIDE
,
4396 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
4397 /* Cache status: RAZ because we have no cache so it's always clean */
4398 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
4399 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4403 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
4404 /* We never have a block transfer operation in progress */
4405 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
4406 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4408 /* The cache ops themselves: these all NOP for QEMU */
4409 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
4410 .access
= PL1_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4411 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
4412 .access
= PL1_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4413 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
4414 .access
= PL0_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4415 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
4416 .access
= PL0_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4417 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
4418 .access
= PL0_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4419 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
4420 .access
= PL1_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4423 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
4425 * The cache test-and-clean instructions always return (1 << 30)
4426 * to indicate that there are no dirty cache lines.
4428 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
4429 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4430 .resetvalue
= (1 << 30) },
4431 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
4432 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4433 .resetvalue
= (1 << 30) },
4436 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
4437 /* Ignore ReadBuffer accesses */
4438 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
4439 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
4440 .access
= PL1_RW
, .resetvalue
= 0,
4441 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
},
4444 static uint64_t midr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4446 unsigned int cur_el
= arm_current_el(env
);
4448 if (arm_is_el2_enabled(env
) && cur_el
== 1) {
4449 return env
->cp15
.vpidr_el2
;
4451 return raw_read(env
, ri
);
4454 static uint64_t mpidr_read_val(CPUARMState
*env
)
4456 ARMCPU
*cpu
= env_archcpu(env
);
4457 uint64_t mpidr
= cpu
->mp_affinity
;
4459 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
4460 mpidr
|= (1U << 31);
4462 * Cores which are uniprocessor (non-coherent)
4463 * but still implement the MP extensions set
4464 * bit 30. (For instance, Cortex-R5).
4466 if (cpu
->mp_is_up
) {
4467 mpidr
|= (1u << 30);
4473 static uint64_t mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4475 unsigned int cur_el
= arm_current_el(env
);
4477 if (arm_is_el2_enabled(env
) && cur_el
== 1) {
4478 return env
->cp15
.vmpidr_el2
;
4480 return mpidr_read_val(env
);
4483 static const ARMCPRegInfo lpae_cp_reginfo
[] = {
4485 { .name
= "AMAIR0", .state
= ARM_CP_STATE_BOTH
,
4486 .opc0
= 3, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 0,
4487 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4488 .fgt
= FGT_AMAIR_EL1
,
4489 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4490 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
4491 { .name
= "AMAIR1", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 1,
4492 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4493 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4494 { .name
= "PAR", .cp
= 15, .crm
= 7, .opc1
= 0,
4495 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .resetvalue
= 0,
4496 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.par_s
),
4497 offsetof(CPUARMState
, cp15
.par_ns
)} },
4498 { .name
= "TTBR0", .cp
= 15, .crm
= 2, .opc1
= 0,
4499 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4500 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4501 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
4502 offsetof(CPUARMState
, cp15
.ttbr0_ns
) },
4503 .writefn
= vmsa_ttbr_write
, .raw_writefn
= raw_write
},
4504 { .name
= "TTBR1", .cp
= 15, .crm
= 2, .opc1
= 1,
4505 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4506 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4507 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
4508 offsetof(CPUARMState
, cp15
.ttbr1_ns
) },
4509 .writefn
= vmsa_ttbr_write
, .raw_writefn
= raw_write
},
4512 static uint64_t aa64_fpcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4514 return vfp_get_fpcr(env
);
4517 static void aa64_fpcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4520 vfp_set_fpcr(env
, value
);
4523 static uint64_t aa64_fpsr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4525 return vfp_get_fpsr(env
);
4528 static void aa64_fpsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4531 vfp_set_fpsr(env
, value
);
4534 static CPAccessResult
aa64_daif_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4537 if (arm_current_el(env
) == 0 && !(arm_sctlr(env
, 0) & SCTLR_UMA
)) {
4538 return CP_ACCESS_TRAP
;
4540 return CP_ACCESS_OK
;
4543 static void aa64_daif_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4546 env
->daif
= value
& PSTATE_DAIF
;
4549 static uint64_t aa64_pan_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4551 return env
->pstate
& PSTATE_PAN
;
4554 static void aa64_pan_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4557 env
->pstate
= (env
->pstate
& ~PSTATE_PAN
) | (value
& PSTATE_PAN
);
4560 static const ARMCPRegInfo pan_reginfo
= {
4561 .name
= "PAN", .state
= ARM_CP_STATE_AA64
,
4562 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 3,
4563 .type
= ARM_CP_NO_RAW
, .access
= PL1_RW
,
4564 .readfn
= aa64_pan_read
, .writefn
= aa64_pan_write
4567 static uint64_t aa64_uao_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4569 return env
->pstate
& PSTATE_UAO
;
4572 static void aa64_uao_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4575 env
->pstate
= (env
->pstate
& ~PSTATE_UAO
) | (value
& PSTATE_UAO
);
4578 static const ARMCPRegInfo uao_reginfo
= {
4579 .name
= "UAO", .state
= ARM_CP_STATE_AA64
,
4580 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 4,
4581 .type
= ARM_CP_NO_RAW
, .access
= PL1_RW
,
4582 .readfn
= aa64_uao_read
, .writefn
= aa64_uao_write
4585 static uint64_t aa64_dit_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4587 return env
->pstate
& PSTATE_DIT
;
4590 static void aa64_dit_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4593 env
->pstate
= (env
->pstate
& ~PSTATE_DIT
) | (value
& PSTATE_DIT
);
4596 static const ARMCPRegInfo dit_reginfo
= {
4597 .name
= "DIT", .state
= ARM_CP_STATE_AA64
,
4598 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 5,
4599 .type
= ARM_CP_NO_RAW
, .access
= PL0_RW
,
4600 .readfn
= aa64_dit_read
, .writefn
= aa64_dit_write
4603 static uint64_t aa64_ssbs_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4605 return env
->pstate
& PSTATE_SSBS
;
4608 static void aa64_ssbs_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4611 env
->pstate
= (env
->pstate
& ~PSTATE_SSBS
) | (value
& PSTATE_SSBS
);
4614 static const ARMCPRegInfo ssbs_reginfo
= {
4615 .name
= "SSBS", .state
= ARM_CP_STATE_AA64
,
4616 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 6,
4617 .type
= ARM_CP_NO_RAW
, .access
= PL0_RW
,
4618 .readfn
= aa64_ssbs_read
, .writefn
= aa64_ssbs_write
4621 static CPAccessResult
aa64_cacheop_poc_access(CPUARMState
*env
,
4622 const ARMCPRegInfo
*ri
,
4625 /* Cache invalidate/clean to Point of Coherency or Persistence... */
4626 switch (arm_current_el(env
)) {
4628 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
4629 if (!(arm_sctlr(env
, 0) & SCTLR_UCI
)) {
4630 return CP_ACCESS_TRAP
;
4634 /* ... EL1 must trap to EL2 if HCR_EL2.TPCP is set. */
4635 if (arm_hcr_el2_eff(env
) & HCR_TPCP
) {
4636 return CP_ACCESS_TRAP_EL2
;
4640 return CP_ACCESS_OK
;
4643 static CPAccessResult
do_cacheop_pou_access(CPUARMState
*env
, uint64_t hcrflags
)
4645 /* Cache invalidate/clean to Point of Unification... */
4646 switch (arm_current_el(env
)) {
4648 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
4649 if (!(arm_sctlr(env
, 0) & SCTLR_UCI
)) {
4650 return CP_ACCESS_TRAP
;
4654 /* ... EL1 must trap to EL2 if relevant HCR_EL2 flags are set. */
4655 if (arm_hcr_el2_eff(env
) & hcrflags
) {
4656 return CP_ACCESS_TRAP_EL2
;
4660 return CP_ACCESS_OK
;
4663 static CPAccessResult
access_ticab(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4666 return do_cacheop_pou_access(env
, HCR_TICAB
| HCR_TPU
);
4669 static CPAccessResult
access_tocu(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4672 return do_cacheop_pou_access(env
, HCR_TOCU
| HCR_TPU
);
4676 * See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
4677 * Page D4-1736 (DDI0487A.b)
4680 static int vae1_tlbmask(CPUARMState
*env
)
4682 uint64_t hcr
= arm_hcr_el2_eff(env
);
4685 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4686 mask
= ARMMMUIdxBit_E20_2
|
4687 ARMMMUIdxBit_E20_2_PAN
|
4690 mask
= ARMMMUIdxBit_E10_1
|
4691 ARMMMUIdxBit_E10_1_PAN
|
4697 static int vae2_tlbmask(CPUARMState
*env
)
4699 uint64_t hcr
= arm_hcr_el2_eff(env
);
4702 if (hcr
& HCR_E2H
) {
4703 mask
= ARMMMUIdxBit_E20_2
|
4704 ARMMMUIdxBit_E20_2_PAN
|
4707 mask
= ARMMMUIdxBit_E2
;
4712 /* Return 56 if TBI is enabled, 64 otherwise. */
4713 static int tlbbits_for_regime(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
4716 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
4717 int tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
4718 int select
= extract64(addr
, 55, 1);
4720 return (tbi
>> select
) & 1 ? 56 : 64;
4723 static int vae1_tlbbits(CPUARMState
*env
, uint64_t addr
)
4725 uint64_t hcr
= arm_hcr_el2_eff(env
);
4728 /* Only the regime of the mmu_idx below is significant. */
4729 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4730 mmu_idx
= ARMMMUIdx_E20_0
;
4732 mmu_idx
= ARMMMUIdx_E10_0
;
4735 return tlbbits_for_regime(env
, mmu_idx
, addr
);
4738 static int vae2_tlbbits(CPUARMState
*env
, uint64_t addr
)
4740 uint64_t hcr
= arm_hcr_el2_eff(env
);
4744 * Only the regime of the mmu_idx below is significant.
4745 * Regime EL2&0 has two ranges with separate TBI configuration, while EL2
4748 if (hcr
& HCR_E2H
) {
4749 mmu_idx
= ARMMMUIdx_E20_2
;
4751 mmu_idx
= ARMMMUIdx_E2
;
4754 return tlbbits_for_regime(env
, mmu_idx
, addr
);
4757 static void tlbi_aa64_vmalle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4760 CPUState
*cs
= env_cpu(env
);
4761 int mask
= vae1_tlbmask(env
);
4763 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4766 static void tlbi_aa64_vmalle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4769 CPUState
*cs
= env_cpu(env
);
4770 int mask
= vae1_tlbmask(env
);
4772 if (tlb_force_broadcast(env
)) {
4773 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4775 tlb_flush_by_mmuidx(cs
, mask
);
4779 static int e2_tlbmask(CPUARMState
*env
)
4781 return (ARMMMUIdxBit_E20_0
|
4782 ARMMMUIdxBit_E20_2
|
4783 ARMMMUIdxBit_E20_2_PAN
|
4787 static void tlbi_aa64_alle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4790 CPUState
*cs
= env_cpu(env
);
4791 int mask
= alle1_tlbmask(env
);
4793 tlb_flush_by_mmuidx(cs
, mask
);
4796 static void tlbi_aa64_alle2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4799 CPUState
*cs
= env_cpu(env
);
4800 int mask
= e2_tlbmask(env
);
4802 tlb_flush_by_mmuidx(cs
, mask
);
4805 static void tlbi_aa64_alle3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4808 ARMCPU
*cpu
= env_archcpu(env
);
4809 CPUState
*cs
= CPU(cpu
);
4811 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_E3
);
4814 static void tlbi_aa64_alle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4817 CPUState
*cs
= env_cpu(env
);
4818 int mask
= alle1_tlbmask(env
);
4820 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4823 static void tlbi_aa64_alle2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4826 CPUState
*cs
= env_cpu(env
);
4827 int mask
= e2_tlbmask(env
);
4829 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4832 static void tlbi_aa64_alle3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4835 CPUState
*cs
= env_cpu(env
);
4837 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_E3
);
4840 static void tlbi_aa64_vae2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4844 * Invalidate by VA, EL2
4845 * Currently handles both VAE2 and VALE2, since we don't support
4846 * flush-last-level-only.
4848 CPUState
*cs
= env_cpu(env
);
4849 int mask
= vae2_tlbmask(env
);
4850 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4851 int bits
= vae2_tlbbits(env
, pageaddr
);
4853 tlb_flush_page_bits_by_mmuidx(cs
, pageaddr
, mask
, bits
);
4856 static void tlbi_aa64_vae3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4860 * Invalidate by VA, EL3
4861 * Currently handles both VAE3 and VALE3, since we don't support
4862 * flush-last-level-only.
4864 ARMCPU
*cpu
= env_archcpu(env
);
4865 CPUState
*cs
= CPU(cpu
);
4866 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4868 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_E3
);
4871 static void tlbi_aa64_vae1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4874 CPUState
*cs
= env_cpu(env
);
4875 int mask
= vae1_tlbmask(env
);
4876 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4877 int bits
= vae1_tlbbits(env
, pageaddr
);
4879 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4882 static void tlbi_aa64_vae1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4886 * Invalidate by VA, EL1&0 (AArch64 version).
4887 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
4888 * since we don't support flush-for-specific-ASID-only or
4889 * flush-last-level-only.
4891 CPUState
*cs
= env_cpu(env
);
4892 int mask
= vae1_tlbmask(env
);
4893 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4894 int bits
= vae1_tlbbits(env
, pageaddr
);
4896 if (tlb_force_broadcast(env
)) {
4897 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4899 tlb_flush_page_bits_by_mmuidx(cs
, pageaddr
, mask
, bits
);
4903 static void tlbi_aa64_vae2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4906 CPUState
*cs
= env_cpu(env
);
4907 int mask
= vae2_tlbmask(env
);
4908 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4909 int bits
= vae2_tlbbits(env
, pageaddr
);
4911 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4914 static void tlbi_aa64_vae3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4917 CPUState
*cs
= env_cpu(env
);
4918 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4919 int bits
= tlbbits_for_regime(env
, ARMMMUIdx_E3
, pageaddr
);
4921 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
4922 ARMMMUIdxBit_E3
, bits
);
4925 static int ipas2e1_tlbmask(CPUARMState
*env
, int64_t value
)
4928 * The MSB of value is the NS field, which only applies if SEL2
4929 * is implemented and SCR_EL3.NS is not set (i.e. in secure mode).
4932 && cpu_isar_feature(aa64_sel2
, env_archcpu(env
))
4933 && arm_is_secure_below_el3(env
)
4934 ? ARMMMUIdxBit_Stage2_S
4935 : ARMMMUIdxBit_Stage2
);
4938 static void tlbi_aa64_ipas2e1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4941 CPUState
*cs
= env_cpu(env
);
4942 int mask
= ipas2e1_tlbmask(env
, value
);
4943 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4945 if (tlb_force_broadcast(env
)) {
4946 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
);
4948 tlb_flush_page_by_mmuidx(cs
, pageaddr
, mask
);
4952 static void tlbi_aa64_ipas2e1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4955 CPUState
*cs
= env_cpu(env
);
4956 int mask
= ipas2e1_tlbmask(env
, value
);
4957 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4959 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
);
4962 #ifdef TARGET_AARCH64
4968 static ARMGranuleSize
tlbi_range_tg_to_gran_size(int tg
)
4971 * Note that the TLBI range TG field encoding differs from both
4972 * TG0 and TG1 encodings.
4986 static TLBIRange
tlbi_aa64_get_range(CPUARMState
*env
, ARMMMUIdx mmuidx
,
4989 unsigned int page_size_granule
, page_shift
, num
, scale
, exponent
;
4990 /* Extract one bit to represent the va selector in use. */
4991 uint64_t select
= sextract64(value
, 36, 1);
4992 ARMVAParameters param
= aa64_va_parameters(env
, select
, mmuidx
, true, false);
4993 TLBIRange ret
= { };
4994 ARMGranuleSize gran
;
4996 page_size_granule
= extract64(value
, 46, 2);
4997 gran
= tlbi_range_tg_to_gran_size(page_size_granule
);
4999 /* The granule encoded in value must match the granule in use. */
5000 if (gran
!= param
.gran
) {
5001 qemu_log_mask(LOG_GUEST_ERROR
, "Invalid tlbi page size granule %d\n",
5006 page_shift
= arm_granule_bits(gran
);
5007 num
= extract64(value
, 39, 5);
5008 scale
= extract64(value
, 44, 2);
5009 exponent
= (5 * scale
) + 1;
5011 ret
.length
= (num
+ 1) << (exponent
+ page_shift
);
5014 ret
.base
= sextract64(value
, 0, 37);
5016 ret
.base
= extract64(value
, 0, 37);
5020 * With DS=1, BaseADDR is always shifted 16 so that it is able
5021 * to address all 52 va bits. The input address is perforce
5022 * aligned on a 64k boundary regardless of translation granule.
5026 ret
.base
<<= page_shift
;
5031 static void do_rvae_write(CPUARMState
*env
, uint64_t value
,
5032 int idxmap
, bool synced
)
5034 ARMMMUIdx one_idx
= ARM_MMU_IDX_A
| ctz32(idxmap
);
5038 range
= tlbi_aa64_get_range(env
, one_idx
, value
);
5039 bits
= tlbbits_for_regime(env
, one_idx
, range
.base
);
5042 tlb_flush_range_by_mmuidx_all_cpus_synced(env_cpu(env
),
5048 tlb_flush_range_by_mmuidx(env_cpu(env
), range
.base
,
5049 range
.length
, idxmap
, bits
);
5053 static void tlbi_aa64_rvae1_write(CPUARMState
*env
,
5054 const ARMCPRegInfo
*ri
,
5058 * Invalidate by VA range, EL1&0.
5059 * Currently handles all of RVAE1, RVAAE1, RVAALE1 and RVALE1,
5060 * since we don't support flush-for-specific-ASID-only or
5061 * flush-last-level-only.
5064 do_rvae_write(env
, value
, vae1_tlbmask(env
),
5065 tlb_force_broadcast(env
));
5068 static void tlbi_aa64_rvae1is_write(CPUARMState
*env
,
5069 const ARMCPRegInfo
*ri
,
5073 * Invalidate by VA range, Inner/Outer Shareable EL1&0.
5074 * Currently handles all of RVAE1IS, RVAE1OS, RVAAE1IS, RVAAE1OS,
5075 * RVAALE1IS, RVAALE1OS, RVALE1IS and RVALE1OS, since we don't support
5076 * flush-for-specific-ASID-only, flush-last-level-only or inner/outer
5077 * shareable specific flushes.
5080 do_rvae_write(env
, value
, vae1_tlbmask(env
), true);
5083 static void tlbi_aa64_rvae2_write(CPUARMState
*env
,
5084 const ARMCPRegInfo
*ri
,
5088 * Invalidate by VA range, EL2.
5089 * Currently handles all of RVAE2 and RVALE2,
5090 * since we don't support flush-for-specific-ASID-only or
5091 * flush-last-level-only.
5094 do_rvae_write(env
, value
, vae2_tlbmask(env
),
5095 tlb_force_broadcast(env
));
5100 static void tlbi_aa64_rvae2is_write(CPUARMState
*env
,
5101 const ARMCPRegInfo
*ri
,
5105 * Invalidate by VA range, Inner/Outer Shareable, EL2.
5106 * Currently handles all of RVAE2IS, RVAE2OS, RVALE2IS and RVALE2OS,
5107 * since we don't support flush-for-specific-ASID-only,
5108 * flush-last-level-only or inner/outer shareable specific flushes.
5111 do_rvae_write(env
, value
, vae2_tlbmask(env
), true);
5115 static void tlbi_aa64_rvae3_write(CPUARMState
*env
,
5116 const ARMCPRegInfo
*ri
,
5120 * Invalidate by VA range, EL3.
5121 * Currently handles all of RVAE3 and RVALE3,
5122 * since we don't support flush-for-specific-ASID-only or
5123 * flush-last-level-only.
5126 do_rvae_write(env
, value
, ARMMMUIdxBit_E3
, tlb_force_broadcast(env
));
5129 static void tlbi_aa64_rvae3is_write(CPUARMState
*env
,
5130 const ARMCPRegInfo
*ri
,
5134 * Invalidate by VA range, EL3, Inner/Outer Shareable.
5135 * Currently handles all of RVAE3IS, RVAE3OS, RVALE3IS and RVALE3OS,
5136 * since we don't support flush-for-specific-ASID-only,
5137 * flush-last-level-only or inner/outer specific flushes.
5140 do_rvae_write(env
, value
, ARMMMUIdxBit_E3
, true);
5143 static void tlbi_aa64_ripas2e1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5146 do_rvae_write(env
, value
, ipas2e1_tlbmask(env
, value
),
5147 tlb_force_broadcast(env
));
5150 static void tlbi_aa64_ripas2e1is_write(CPUARMState
*env
,
5151 const ARMCPRegInfo
*ri
,
5154 do_rvae_write(env
, value
, ipas2e1_tlbmask(env
, value
), true);
5158 static CPAccessResult
aa64_zva_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5161 int cur_el
= arm_current_el(env
);
5164 uint64_t hcr
= arm_hcr_el2_eff(env
);
5167 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
5168 if (!(env
->cp15
.sctlr_el
[2] & SCTLR_DZE
)) {
5169 return CP_ACCESS_TRAP_EL2
;
5172 if (!(env
->cp15
.sctlr_el
[1] & SCTLR_DZE
)) {
5173 return CP_ACCESS_TRAP
;
5175 if (hcr
& HCR_TDZ
) {
5176 return CP_ACCESS_TRAP_EL2
;
5179 } else if (hcr
& HCR_TDZ
) {
5180 return CP_ACCESS_TRAP_EL2
;
5183 return CP_ACCESS_OK
;
5186 static uint64_t aa64_dczid_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5188 ARMCPU
*cpu
= env_archcpu(env
);
5189 int dzp_bit
= 1 << 4;
5191 /* DZP indicates whether DC ZVA access is allowed */
5192 if (aa64_zva_access(env
, NULL
, false) == CP_ACCESS_OK
) {
5195 return cpu
->dcz_blocksize
| dzp_bit
;
5198 static CPAccessResult
sp_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5201 if (!(env
->pstate
& PSTATE_SP
)) {
5203 * Access to SP_EL0 is undefined if it's being used as
5204 * the stack pointer.
5206 return CP_ACCESS_TRAP_UNCATEGORIZED
;
5208 return CP_ACCESS_OK
;
5211 static uint64_t spsel_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5213 return env
->pstate
& PSTATE_SP
;
5216 static void spsel_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
5218 update_spsel(env
, val
);
5221 static void sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5224 ARMCPU
*cpu
= env_archcpu(env
);
5226 if (arm_feature(env
, ARM_FEATURE_PMSA
) && !cpu
->has_mpu
) {
5227 /* M bit is RAZ/WI for PMSA with no MPU implemented */
5231 /* ??? Lots of these bits are not implemented. */
5233 if (ri
->state
== ARM_CP_STATE_AA64
&& !cpu_isar_feature(aa64_mte
, cpu
)) {
5234 if (ri
->opc1
== 6) { /* SCTLR_EL3 */
5235 value
&= ~(SCTLR_ITFSB
| SCTLR_TCF
| SCTLR_ATA
);
5237 value
&= ~(SCTLR_ITFSB
| SCTLR_TCF0
| SCTLR_TCF
|
5238 SCTLR_ATA0
| SCTLR_ATA
);
5242 if (raw_read(env
, ri
) == value
) {
5244 * Skip the TLB flush if nothing actually changed; Linux likes
5245 * to do a lot of pointless SCTLR writes.
5250 raw_write(env
, ri
, value
);
5252 /* This may enable/disable the MMU, so do a TLB flush. */
5253 tlb_flush(CPU(cpu
));
5255 if (tcg_enabled() && ri
->type
& ARM_CP_SUPPRESS_TB_END
) {
5257 * Normally we would always end the TB on an SCTLR write; see the
5258 * comment in ARMCPRegInfo sctlr initialization below for why Xscale
5259 * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebuild
5260 * of hflags from the translator, so do it here.
5262 arm_rebuild_hflags(env
);
5266 static void mdcr_el3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5270 * Some MDCR_EL3 bits affect whether PMU counters are running:
5271 * if we are trying to change any of those then we must
5272 * bracket this update with PMU start/finish calls.
5274 bool pmu_op
= (env
->cp15
.mdcr_el3
^ value
) & MDCR_EL3_PMU_ENABLE_BITS
;
5279 env
->cp15
.mdcr_el3
= value
;
5285 static void sdcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5288 /* Not all bits defined for MDCR_EL3 exist in the AArch32 SDCR */
5289 mdcr_el3_write(env
, ri
, value
& SDCR_VALID_MASK
);
5292 static void mdcr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5296 * Some MDCR_EL2 bits affect whether PMU counters are running:
5297 * if we are trying to change any of those then we must
5298 * bracket this update with PMU start/finish calls.
5300 bool pmu_op
= (env
->cp15
.mdcr_el2
^ value
) & MDCR_EL2_PMU_ENABLE_BITS
;
5305 env
->cp15
.mdcr_el2
= value
;
5311 #ifdef CONFIG_USER_ONLY
5313 * `IC IVAU` is handled to improve compatibility with JITs that dual-map their
5314 * code to get around W^X restrictions, where one region is writable and the
5315 * other is executable.
5317 * Since the executable region is never written to we cannot detect code
5318 * changes when running in user mode, and rely on the emulated JIT telling us
5319 * that the code has changed by executing this instruction.
5321 static void ic_ivau_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5324 uint64_t icache_line_mask
, start_address
, end_address
;
5327 cpu
= env_archcpu(env
);
5329 icache_line_mask
= (4 << extract32(cpu
->ctr
, 0, 4)) - 1;
5330 start_address
= value
& ~icache_line_mask
;
5331 end_address
= value
| icache_line_mask
;
5335 tb_invalidate_phys_range(start_address
, end_address
);
5341 static const ARMCPRegInfo v8_cp_reginfo
[] = {
5343 * Minimal set of EL0-visible registers. This will need to be expanded
5344 * significantly for system emulation of AArch64 CPUs.
5346 { .name
= "NZCV", .state
= ARM_CP_STATE_AA64
,
5347 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 2,
5348 .access
= PL0_RW
, .type
= ARM_CP_NZCV
},
5349 { .name
= "DAIF", .state
= ARM_CP_STATE_AA64
,
5350 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 2,
5351 .type
= ARM_CP_NO_RAW
,
5352 .access
= PL0_RW
, .accessfn
= aa64_daif_access
,
5353 .fieldoffset
= offsetof(CPUARMState
, daif
),
5354 .writefn
= aa64_daif_write
, .resetfn
= arm_cp_reset_ignore
},
5355 { .name
= "FPCR", .state
= ARM_CP_STATE_AA64
,
5356 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 4,
5357 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
5358 .readfn
= aa64_fpcr_read
, .writefn
= aa64_fpcr_write
},
5359 { .name
= "FPSR", .state
= ARM_CP_STATE_AA64
,
5360 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 4,
5361 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
5362 .readfn
= aa64_fpsr_read
, .writefn
= aa64_fpsr_write
},
5363 { .name
= "DCZID_EL0", .state
= ARM_CP_STATE_AA64
,
5364 .opc0
= 3, .opc1
= 3, .opc2
= 7, .crn
= 0, .crm
= 0,
5365 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
,
5366 .fgt
= FGT_DCZID_EL0
,
5367 .readfn
= aa64_dczid_read
},
5368 { .name
= "DC_ZVA", .state
= ARM_CP_STATE_AA64
,
5369 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 1,
5370 .access
= PL0_W
, .type
= ARM_CP_DC_ZVA
,
5371 #ifndef CONFIG_USER_ONLY
5372 /* Avoid overhead of an access check that always passes in user-mode */
5373 .accessfn
= aa64_zva_access
,
5377 { .name
= "CURRENTEL", .state
= ARM_CP_STATE_AA64
,
5378 .opc0
= 3, .opc1
= 0, .opc2
= 2, .crn
= 4, .crm
= 2,
5379 .access
= PL1_R
, .type
= ARM_CP_CURRENTEL
},
5381 * Instruction cache ops. All of these except `IC IVAU` NOP because we
5382 * don't emulate caches.
5384 { .name
= "IC_IALLUIS", .state
= ARM_CP_STATE_AA64
,
5385 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
5386 .access
= PL1_W
, .type
= ARM_CP_NOP
,
5387 .fgt
= FGT_ICIALLUIS
,
5388 .accessfn
= access_ticab
},
5389 { .name
= "IC_IALLU", .state
= ARM_CP_STATE_AA64
,
5390 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
5391 .access
= PL1_W
, .type
= ARM_CP_NOP
,
5393 .accessfn
= access_tocu
},
5394 { .name
= "IC_IVAU", .state
= ARM_CP_STATE_AA64
,
5395 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 5, .opc2
= 1,
5398 .accessfn
= access_tocu
,
5399 #ifdef CONFIG_USER_ONLY
5400 .type
= ARM_CP_NO_RAW
,
5401 .writefn
= ic_ivau_write
5406 /* Cache ops: all NOPs since we don't emulate caches */
5407 { .name
= "DC_IVAC", .state
= ARM_CP_STATE_AA64
,
5408 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
5409 .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
,
5411 .type
= ARM_CP_NOP
},
5412 { .name
= "DC_ISW", .state
= ARM_CP_STATE_AA64
,
5413 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
5415 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
5416 { .name
= "DC_CVAC", .state
= ARM_CP_STATE_AA64
,
5417 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 1,
5418 .access
= PL0_W
, .type
= ARM_CP_NOP
,
5420 .accessfn
= aa64_cacheop_poc_access
},
5421 { .name
= "DC_CSW", .state
= ARM_CP_STATE_AA64
,
5422 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
5424 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
5425 { .name
= "DC_CVAU", .state
= ARM_CP_STATE_AA64
,
5426 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 11, .opc2
= 1,
5427 .access
= PL0_W
, .type
= ARM_CP_NOP
,
5429 .accessfn
= access_tocu
},
5430 { .name
= "DC_CIVAC", .state
= ARM_CP_STATE_AA64
,
5431 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 1,
5432 .access
= PL0_W
, .type
= ARM_CP_NOP
,
5434 .accessfn
= aa64_cacheop_poc_access
},
5435 { .name
= "DC_CISW", .state
= ARM_CP_STATE_AA64
,
5436 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
5438 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
5439 /* TLBI operations */
5440 { .name
= "TLBI_VMALLE1IS", .state
= ARM_CP_STATE_AA64
,
5441 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
5442 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5443 .fgt
= FGT_TLBIVMALLE1IS
,
5444 .writefn
= tlbi_aa64_vmalle1is_write
},
5445 { .name
= "TLBI_VAE1IS", .state
= ARM_CP_STATE_AA64
,
5446 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
5447 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5448 .fgt
= FGT_TLBIVAE1IS
,
5449 .writefn
= tlbi_aa64_vae1is_write
},
5450 { .name
= "TLBI_ASIDE1IS", .state
= ARM_CP_STATE_AA64
,
5451 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
5452 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5453 .fgt
= FGT_TLBIASIDE1IS
,
5454 .writefn
= tlbi_aa64_vmalle1is_write
},
5455 { .name
= "TLBI_VAAE1IS", .state
= ARM_CP_STATE_AA64
,
5456 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
5457 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5458 .fgt
= FGT_TLBIVAAE1IS
,
5459 .writefn
= tlbi_aa64_vae1is_write
},
5460 { .name
= "TLBI_VALE1IS", .state
= ARM_CP_STATE_AA64
,
5461 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
5462 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5463 .fgt
= FGT_TLBIVALE1IS
,
5464 .writefn
= tlbi_aa64_vae1is_write
},
5465 { .name
= "TLBI_VAALE1IS", .state
= ARM_CP_STATE_AA64
,
5466 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
5467 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5468 .fgt
= FGT_TLBIVAALE1IS
,
5469 .writefn
= tlbi_aa64_vae1is_write
},
5470 { .name
= "TLBI_VMALLE1", .state
= ARM_CP_STATE_AA64
,
5471 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
5472 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5473 .fgt
= FGT_TLBIVMALLE1
,
5474 .writefn
= tlbi_aa64_vmalle1_write
},
5475 { .name
= "TLBI_VAE1", .state
= ARM_CP_STATE_AA64
,
5476 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
5477 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5478 .fgt
= FGT_TLBIVAE1
,
5479 .writefn
= tlbi_aa64_vae1_write
},
5480 { .name
= "TLBI_ASIDE1", .state
= ARM_CP_STATE_AA64
,
5481 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
5482 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5483 .fgt
= FGT_TLBIASIDE1
,
5484 .writefn
= tlbi_aa64_vmalle1_write
},
5485 { .name
= "TLBI_VAAE1", .state
= ARM_CP_STATE_AA64
,
5486 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
5487 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5488 .fgt
= FGT_TLBIVAAE1
,
5489 .writefn
= tlbi_aa64_vae1_write
},
5490 { .name
= "TLBI_VALE1", .state
= ARM_CP_STATE_AA64
,
5491 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
5492 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5493 .fgt
= FGT_TLBIVALE1
,
5494 .writefn
= tlbi_aa64_vae1_write
},
5495 { .name
= "TLBI_VAALE1", .state
= ARM_CP_STATE_AA64
,
5496 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
5497 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5498 .fgt
= FGT_TLBIVAALE1
,
5499 .writefn
= tlbi_aa64_vae1_write
},
5500 { .name
= "TLBI_IPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
5501 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
5502 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5503 .writefn
= tlbi_aa64_ipas2e1is_write
},
5504 { .name
= "TLBI_IPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
5505 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
5506 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5507 .writefn
= tlbi_aa64_ipas2e1is_write
},
5508 { .name
= "TLBI_ALLE1IS", .state
= ARM_CP_STATE_AA64
,
5509 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
5510 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5511 .writefn
= tlbi_aa64_alle1is_write
},
5512 { .name
= "TLBI_VMALLS12E1IS", .state
= ARM_CP_STATE_AA64
,
5513 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 6,
5514 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5515 .writefn
= tlbi_aa64_alle1is_write
},
5516 { .name
= "TLBI_IPAS2E1", .state
= ARM_CP_STATE_AA64
,
5517 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
5518 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5519 .writefn
= tlbi_aa64_ipas2e1_write
},
5520 { .name
= "TLBI_IPAS2LE1", .state
= ARM_CP_STATE_AA64
,
5521 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
5522 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5523 .writefn
= tlbi_aa64_ipas2e1_write
},
5524 { .name
= "TLBI_ALLE1", .state
= ARM_CP_STATE_AA64
,
5525 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
5526 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5527 .writefn
= tlbi_aa64_alle1_write
},
5528 { .name
= "TLBI_VMALLS12E1", .state
= ARM_CP_STATE_AA64
,
5529 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 6,
5530 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5531 .writefn
= tlbi_aa64_alle1is_write
},
5532 #ifndef CONFIG_USER_ONLY
5533 /* 64 bit address translation operations */
5534 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
5535 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 0,
5536 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5538 .accessfn
= at_e012_access
, .writefn
= ats_write64
},
5539 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
5540 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 1,
5541 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5543 .accessfn
= at_e012_access
, .writefn
= ats_write64
},
5544 { .name
= "AT_S1E0R", .state
= ARM_CP_STATE_AA64
,
5545 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 2,
5546 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5548 .accessfn
= at_e012_access
, .writefn
= ats_write64
},
5549 { .name
= "AT_S1E0W", .state
= ARM_CP_STATE_AA64
,
5550 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 3,
5551 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5553 .accessfn
= at_e012_access
, .writefn
= ats_write64
},
5554 { .name
= "AT_S12E1R", .state
= ARM_CP_STATE_AA64
,
5555 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 4,
5556 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5557 .accessfn
= at_e012_access
, .writefn
= ats_write64
},
5558 { .name
= "AT_S12E1W", .state
= ARM_CP_STATE_AA64
,
5559 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 5,
5560 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5561 .accessfn
= at_e012_access
, .writefn
= ats_write64
},
5562 { .name
= "AT_S12E0R", .state
= ARM_CP_STATE_AA64
,
5563 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 6,
5564 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5565 .accessfn
= at_e012_access
, .writefn
= ats_write64
},
5566 { .name
= "AT_S12E0W", .state
= ARM_CP_STATE_AA64
,
5567 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 7,
5568 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5569 .accessfn
= at_e012_access
, .writefn
= ats_write64
},
5570 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
5571 { .name
= "AT_S1E3R", .state
= ARM_CP_STATE_AA64
,
5572 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 0,
5573 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5574 .writefn
= ats_write64
},
5575 { .name
= "AT_S1E3W", .state
= ARM_CP_STATE_AA64
,
5576 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 1,
5577 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5578 .writefn
= ats_write64
},
5579 { .name
= "PAR_EL1", .state
= ARM_CP_STATE_AA64
,
5580 .type
= ARM_CP_ALIAS
,
5581 .opc0
= 3, .opc1
= 0, .crn
= 7, .crm
= 4, .opc2
= 0,
5582 .access
= PL1_RW
, .resetvalue
= 0,
5584 .fieldoffset
= offsetof(CPUARMState
, cp15
.par_el
[1]),
5585 .writefn
= par_write
},
5587 /* TLB invalidate last level of translation table walk */
5588 { .name
= "TLBIMVALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
5589 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
5590 .writefn
= tlbimva_is_write
},
5591 { .name
= "TLBIMVAALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
5592 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
5593 .writefn
= tlbimvaa_is_write
},
5594 { .name
= "TLBIMVAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
5595 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
5596 .writefn
= tlbimva_write
},
5597 { .name
= "TLBIMVAAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
5598 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
5599 .writefn
= tlbimvaa_write
},
5600 { .name
= "TLBIMVALH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
5601 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5602 .writefn
= tlbimva_hyp_write
},
5603 { .name
= "TLBIMVALHIS",
5604 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
5605 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5606 .writefn
= tlbimva_hyp_is_write
},
5607 { .name
= "TLBIIPAS2",
5608 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
5609 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5610 .writefn
= tlbiipas2_hyp_write
},
5611 { .name
= "TLBIIPAS2IS",
5612 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
5613 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5614 .writefn
= tlbiipas2is_hyp_write
},
5615 { .name
= "TLBIIPAS2L",
5616 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
5617 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5618 .writefn
= tlbiipas2_hyp_write
},
5619 { .name
= "TLBIIPAS2LIS",
5620 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
5621 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5622 .writefn
= tlbiipas2is_hyp_write
},
5623 /* 32 bit cache operations */
5624 { .name
= "ICIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
5625 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_ticab
},
5626 { .name
= "BPIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 6,
5627 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5628 { .name
= "ICIALLU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
5629 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tocu
},
5630 { .name
= "ICIMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 1,
5631 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tocu
},
5632 { .name
= "BPIALL", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 6,
5633 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5634 { .name
= "BPIMVA", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 7,
5635 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5636 { .name
= "DCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
5637 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5638 { .name
= "DCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
5639 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5640 { .name
= "DCCMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 1,
5641 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5642 { .name
= "DCCSW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
5643 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5644 { .name
= "DCCMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 11, .opc2
= 1,
5645 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tocu
},
5646 { .name
= "DCCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 1,
5647 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5648 { .name
= "DCCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
5649 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5650 /* MMU Domain access control / MPU write buffer control */
5651 { .name
= "DACR", .cp
= 15, .opc1
= 0, .crn
= 3, .crm
= 0, .opc2
= 0,
5652 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
5653 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
5654 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
5655 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
5656 { .name
= "ELR_EL1", .state
= ARM_CP_STATE_AA64
,
5657 .type
= ARM_CP_ALIAS
,
5658 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 1,
5660 .fieldoffset
= offsetof(CPUARMState
, elr_el
[1]) },
5661 { .name
= "SPSR_EL1", .state
= ARM_CP_STATE_AA64
,
5662 .type
= ARM_CP_ALIAS
,
5663 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 0,
5665 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_SVC
]) },
5667 * We rely on the access checks not allowing the guest to write to the
5668 * state field when SPSel indicates that it's being used as the stack
5671 { .name
= "SP_EL0", .state
= ARM_CP_STATE_AA64
,
5672 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 1, .opc2
= 0,
5673 .access
= PL1_RW
, .accessfn
= sp_el0_access
,
5674 .type
= ARM_CP_ALIAS
,
5675 .fieldoffset
= offsetof(CPUARMState
, sp_el
[0]) },
5676 { .name
= "SP_EL1", .state
= ARM_CP_STATE_AA64
,
5677 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 1, .opc2
= 0,
5678 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
| ARM_CP_EL3_NO_EL2_KEEP
,
5679 .fieldoffset
= offsetof(CPUARMState
, sp_el
[1]) },
5680 { .name
= "SPSel", .state
= ARM_CP_STATE_AA64
,
5681 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 0,
5682 .type
= ARM_CP_NO_RAW
,
5683 .access
= PL1_RW
, .readfn
= spsel_read
, .writefn
= spsel_write
},
5684 { .name
= "FPEXC32_EL2", .state
= ARM_CP_STATE_AA64
,
5685 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 3, .opc2
= 0,
5687 .type
= ARM_CP_ALIAS
| ARM_CP_FPU
| ARM_CP_EL3_NO_EL2_KEEP
,
5688 .fieldoffset
= offsetof(CPUARMState
, vfp
.xregs
[ARM_VFP_FPEXC
]) },
5689 { .name
= "DACR32_EL2", .state
= ARM_CP_STATE_AA64
,
5690 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 0, .opc2
= 0,
5691 .access
= PL2_RW
, .resetvalue
= 0, .type
= ARM_CP_EL3_NO_EL2_KEEP
,
5692 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
5693 .fieldoffset
= offsetof(CPUARMState
, cp15
.dacr32_el2
) },
5694 { .name
= "IFSR32_EL2", .state
= ARM_CP_STATE_AA64
,
5695 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 0, .opc2
= 1,
5696 .access
= PL2_RW
, .resetvalue
= 0, .type
= ARM_CP_EL3_NO_EL2_KEEP
,
5697 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifsr32_el2
) },
5698 { .name
= "SPSR_IRQ", .state
= ARM_CP_STATE_AA64
,
5699 .type
= ARM_CP_ALIAS
,
5700 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 0,
5702 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_IRQ
]) },
5703 { .name
= "SPSR_ABT", .state
= ARM_CP_STATE_AA64
,
5704 .type
= ARM_CP_ALIAS
,
5705 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 1,
5707 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_ABT
]) },
5708 { .name
= "SPSR_UND", .state
= ARM_CP_STATE_AA64
,
5709 .type
= ARM_CP_ALIAS
,
5710 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 2,
5712 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_UND
]) },
5713 { .name
= "SPSR_FIQ", .state
= ARM_CP_STATE_AA64
,
5714 .type
= ARM_CP_ALIAS
,
5715 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 3,
5717 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_FIQ
]) },
5718 { .name
= "MDCR_EL3", .state
= ARM_CP_STATE_AA64
,
5720 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 3, .opc2
= 1,
5723 .writefn
= mdcr_el3_write
,
5724 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el3
) },
5725 { .name
= "SDCR", .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
5726 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 1,
5727 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
5728 .writefn
= sdcr_write
,
5729 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.mdcr_el3
) },
5732 static void do_hcr_write(CPUARMState
*env
, uint64_t value
, uint64_t valid_mask
)
5734 ARMCPU
*cpu
= env_archcpu(env
);
5736 if (arm_feature(env
, ARM_FEATURE_V8
)) {
5737 valid_mask
|= MAKE_64BIT_MASK(0, 34); /* ARMv8.0 */
5739 valid_mask
|= MAKE_64BIT_MASK(0, 28); /* ARMv7VE */
5742 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
5743 valid_mask
&= ~HCR_HCD
;
5744 } else if (cpu
->psci_conduit
!= QEMU_PSCI_CONDUIT_SMC
) {
5746 * Architecturally HCR.TSC is RES0 if EL3 is not implemented.
5747 * However, if we're using the SMC PSCI conduit then QEMU is
5748 * effectively acting like EL3 firmware and so the guest at
5749 * EL2 should retain the ability to prevent EL1 from being
5750 * able to make SMC calls into the ersatz firmware, so in
5751 * that case HCR.TSC should be read/write.
5753 valid_mask
&= ~HCR_TSC
;
5756 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
5757 if (cpu_isar_feature(aa64_vh
, cpu
)) {
5758 valid_mask
|= HCR_E2H
;
5760 if (cpu_isar_feature(aa64_ras
, cpu
)) {
5761 valid_mask
|= HCR_TERR
| HCR_TEA
;
5763 if (cpu_isar_feature(aa64_lor
, cpu
)) {
5764 valid_mask
|= HCR_TLOR
;
5766 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
5767 valid_mask
|= HCR_API
| HCR_APK
;
5769 if (cpu_isar_feature(aa64_mte
, cpu
)) {
5770 valid_mask
|= HCR_ATA
| HCR_DCT
| HCR_TID5
;
5772 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
5773 valid_mask
|= HCR_ENSCXT
;
5775 if (cpu_isar_feature(aa64_fwb
, cpu
)) {
5776 valid_mask
|= HCR_FWB
;
5778 if (cpu_isar_feature(aa64_rme
, cpu
)) {
5779 valid_mask
|= HCR_GPF
;
5783 if (cpu_isar_feature(any_evt
, cpu
)) {
5784 valid_mask
|= HCR_TTLBIS
| HCR_TTLBOS
| HCR_TICAB
| HCR_TOCU
| HCR_TID4
;
5785 } else if (cpu_isar_feature(any_half_evt
, cpu
)) {
5786 valid_mask
|= HCR_TICAB
| HCR_TOCU
| HCR_TID4
;
5789 /* Clear RES0 bits. */
5790 value
&= valid_mask
;
5793 * These bits change the MMU setup:
5794 * HCR_VM enables stage 2 translation
5795 * HCR_PTW forbids certain page-table setups
5796 * HCR_DC disables stage1 and enables stage2 translation
5797 * HCR_DCT enables tagging on (disabled) stage1 translation
5798 * HCR_FWB changes the interpretation of stage2 descriptor bits
5800 if ((env
->cp15
.hcr_el2
^ value
) &
5801 (HCR_VM
| HCR_PTW
| HCR_DC
| HCR_DCT
| HCR_FWB
)) {
5802 tlb_flush(CPU(cpu
));
5804 env
->cp15
.hcr_el2
= value
;
5807 * Updates to VI and VF require us to update the status of
5808 * virtual interrupts, which are the logical OR of these bits
5809 * and the state of the input lines from the GIC. (This requires
5810 * that we have the iothread lock, which is done by marking the
5811 * reginfo structs as ARM_CP_IO.)
5812 * Note that if a write to HCR pends a VIRQ or VFIQ it is never
5813 * possible for it to be taken immediately, because VIRQ and
5814 * VFIQ are masked unless running at EL0 or EL1, and HCR
5815 * can only be written at EL2.
5817 g_assert(qemu_mutex_iothread_locked());
5818 arm_cpu_update_virq(cpu
);
5819 arm_cpu_update_vfiq(cpu
);
5820 arm_cpu_update_vserr(cpu
);
5823 static void hcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
5825 do_hcr_write(env
, value
, 0);
5828 static void hcr_writehigh(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5831 /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */
5832 value
= deposit64(env
->cp15
.hcr_el2
, 32, 32, value
);
5833 do_hcr_write(env
, value
, MAKE_64BIT_MASK(0, 32));
5836 static void hcr_writelow(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5839 /* Handle HCR write, i.e. write to low half of HCR_EL2 */
5840 value
= deposit64(env
->cp15
.hcr_el2
, 0, 32, value
);
5841 do_hcr_write(env
, value
, MAKE_64BIT_MASK(32, 32));
5845 * Return the effective value of HCR_EL2, at the given security state.
5846 * Bits that are not included here:
5847 * RW (read from SCR_EL3.RW as needed)
5849 uint64_t arm_hcr_el2_eff_secstate(CPUARMState
*env
, ARMSecuritySpace space
)
5851 uint64_t ret
= env
->cp15
.hcr_el2
;
5853 assert(space
!= ARMSS_Root
);
5855 if (!arm_is_el2_enabled_secstate(env
, space
)) {
5857 * "This register has no effect if EL2 is not enabled in the
5858 * current Security state". This is ARMv8.4-SecEL2 speak for
5859 * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1).
5861 * Prior to that, the language was "In an implementation that
5862 * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves
5863 * as if this field is 0 for all purposes other than a direct
5864 * read or write access of HCR_EL2". With lots of enumeration
5865 * on a per-field basis. In current QEMU, this is condition
5866 * is arm_is_secure_below_el3.
5868 * Since the v8.4 language applies to the entire register, and
5869 * appears to be backward compatible, use that.
5875 * For a cpu that supports both aarch64 and aarch32, we can set bits
5876 * in HCR_EL2 (e.g. via EL3) that are RES0 when we enter EL2 as aa32.
5877 * Ignore all of the bits in HCR+HCR2 that are not valid for aarch32.
5879 if (!arm_el_is_aa64(env
, 2)) {
5880 uint64_t aa32_valid
;
5883 * These bits are up-to-date as of ARMv8.6.
5884 * For HCR, it's easiest to list just the 2 bits that are invalid.
5885 * For HCR2, list those that are valid.
5887 aa32_valid
= MAKE_64BIT_MASK(0, 32) & ~(HCR_RW
| HCR_TDZ
);
5888 aa32_valid
|= (HCR_CD
| HCR_ID
| HCR_TERR
| HCR_TEA
| HCR_MIOCNCE
|
5889 HCR_TID4
| HCR_TICAB
| HCR_TOCU
| HCR_TTLBIS
);
5893 if (ret
& HCR_TGE
) {
5894 /* These bits are up-to-date as of ARMv8.6. */
5895 if (ret
& HCR_E2H
) {
5896 ret
&= ~(HCR_VM
| HCR_FMO
| HCR_IMO
| HCR_AMO
|
5897 HCR_BSU_MASK
| HCR_DC
| HCR_TWI
| HCR_TWE
|
5898 HCR_TID0
| HCR_TID2
| HCR_TPCP
| HCR_TPU
|
5899 HCR_TDZ
| HCR_CD
| HCR_ID
| HCR_MIOCNCE
|
5900 HCR_TID4
| HCR_TICAB
| HCR_TOCU
| HCR_ENSCXT
|
5901 HCR_TTLBIS
| HCR_TTLBOS
| HCR_TID5
);
5903 ret
|= HCR_FMO
| HCR_IMO
| HCR_AMO
;
5905 ret
&= ~(HCR_SWIO
| HCR_PTW
| HCR_VF
| HCR_VI
| HCR_VSE
|
5906 HCR_FB
| HCR_TID1
| HCR_TID3
| HCR_TSC
| HCR_TACR
|
5907 HCR_TSW
| HCR_TTLB
| HCR_TVM
| HCR_HCD
| HCR_TRVM
|
5914 uint64_t arm_hcr_el2_eff(CPUARMState
*env
)
5916 if (arm_feature(env
, ARM_FEATURE_M
)) {
5919 return arm_hcr_el2_eff_secstate(env
, arm_security_space_below_el3(env
));
5923 * Corresponds to ARM pseudocode function ELIsInHost().
5925 bool el_is_in_host(CPUARMState
*env
, int el
)
5930 * Since we only care about E2H and TGE, we can skip arm_hcr_el2_eff().
5931 * Perform the simplest bit tests first, and validate EL2 afterward.
5934 return false; /* EL1 or EL3 */
5938 * Note that hcr_write() checks isar_feature_aa64_vh(),
5939 * aka HaveVirtHostExt(), in allowing HCR_E2H to be set.
5941 mask
= el
? HCR_E2H
: HCR_E2H
| HCR_TGE
;
5942 if ((env
->cp15
.hcr_el2
& mask
) != mask
) {
5946 /* TGE and/or E2H set: double check those bits are currently legal. */
5947 return arm_is_el2_enabled(env
) && arm_el_is_aa64(env
, 2);
5950 static void hcrx_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5953 uint64_t valid_mask
= 0;
5955 /* FEAT_MOPS adds MSCEn and MCE2 */
5956 if (cpu_isar_feature(aa64_mops
, env_archcpu(env
))) {
5957 valid_mask
|= HCRX_MSCEN
| HCRX_MCE2
;
5960 /* Clear RES0 bits. */
5961 env
->cp15
.hcrx_el2
= value
& valid_mask
;
5964 static CPAccessResult
access_hxen(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5967 if (arm_current_el(env
) < 3
5968 && arm_feature(env
, ARM_FEATURE_EL3
)
5969 && !(env
->cp15
.scr_el3
& SCR_HXEN
)) {
5970 return CP_ACCESS_TRAP_EL3
;
5972 return CP_ACCESS_OK
;
5975 static const ARMCPRegInfo hcrx_el2_reginfo
= {
5976 .name
= "HCRX_EL2", .state
= ARM_CP_STATE_AA64
,
5977 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 2,
5978 .access
= PL2_RW
, .writefn
= hcrx_write
, .accessfn
= access_hxen
,
5979 .fieldoffset
= offsetof(CPUARMState
, cp15
.hcrx_el2
),
5982 /* Return the effective value of HCRX_EL2. */
5983 uint64_t arm_hcrx_el2_eff(CPUARMState
*env
)
5986 * The bits in this register behave as 0 for all purposes other than
5987 * direct reads of the register if SCR_EL3.HXEn is 0.
5988 * If EL2 is not enabled in the current security state, then the
5989 * bit may behave as if 0, or as if 1, depending on the bit.
5990 * For the moment, we treat the EL2-disabled case as taking
5991 * priority over the HXEn-disabled case. This is true for the only
5992 * bit for a feature which we implement where the answer is different
5993 * for the two cases (MSCEn for FEAT_MOPS).
5994 * This may need to be revisited for future bits.
5996 if (!arm_is_el2_enabled(env
)) {
5998 if (cpu_isar_feature(aa64_mops
, env_archcpu(env
))) {
5999 /* MSCEn behaves as 1 if EL2 is not enabled */
6004 if (arm_feature(env
, ARM_FEATURE_EL3
) && !(env
->cp15
.scr_el3
& SCR_HXEN
)) {
6007 return env
->cp15
.hcrx_el2
;
6010 static void cptr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6014 * For A-profile AArch32 EL3, if NSACR.CP10
6015 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
6017 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
6018 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
6019 uint64_t mask
= R_HCPTR_TCP11_MASK
| R_HCPTR_TCP10_MASK
;
6020 value
= (value
& ~mask
) | (env
->cp15
.cptr_el
[2] & mask
);
6022 env
->cp15
.cptr_el
[2] = value
;
6025 static uint64_t cptr_el2_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6028 * For A-profile AArch32 EL3, if NSACR.CP10
6029 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
6031 uint64_t value
= env
->cp15
.cptr_el
[2];
6033 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
6034 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
6035 value
|= R_HCPTR_TCP11_MASK
| R_HCPTR_TCP10_MASK
;
6040 static const ARMCPRegInfo el2_cp_reginfo
[] = {
6041 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
6043 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
6044 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
6045 .writefn
= hcr_write
, .raw_writefn
= raw_write
},
6046 { .name
= "HCR", .state
= ARM_CP_STATE_AA32
,
6047 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
6048 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
6049 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
6050 .writefn
= hcr_writelow
},
6051 { .name
= "HACR_EL2", .state
= ARM_CP_STATE_BOTH
,
6052 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 7,
6053 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6054 { .name
= "ELR_EL2", .state
= ARM_CP_STATE_AA64
,
6055 .type
= ARM_CP_ALIAS
,
6056 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 1,
6058 .fieldoffset
= offsetof(CPUARMState
, elr_el
[2]) },
6059 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_BOTH
,
6060 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
6061 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[2]) },
6062 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_BOTH
,
6063 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
6064 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[2]) },
6065 { .name
= "HIFAR", .state
= ARM_CP_STATE_AA32
,
6066 .type
= ARM_CP_ALIAS
,
6067 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 2,
6069 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.far_el
[2]) },
6070 { .name
= "SPSR_EL2", .state
= ARM_CP_STATE_AA64
,
6071 .type
= ARM_CP_ALIAS
,
6072 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 0,
6074 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_HYP
]) },
6075 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_BOTH
,
6076 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
6077 .access
= PL2_RW
, .writefn
= vbar_write
,
6078 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[2]),
6080 { .name
= "SP_EL2", .state
= ARM_CP_STATE_AA64
,
6081 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 1, .opc2
= 0,
6082 .access
= PL3_RW
, .type
= ARM_CP_ALIAS
,
6083 .fieldoffset
= offsetof(CPUARMState
, sp_el
[2]) },
6084 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
6085 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
6086 .access
= PL2_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
6087 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[2]),
6088 .readfn
= cptr_el2_read
, .writefn
= cptr_el2_write
},
6089 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
6090 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
6091 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[2]),
6093 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
6094 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
6095 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
6096 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.mair_el
[2]) },
6097 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
6098 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
6099 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
6101 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
6102 { .name
= "HAMAIR1", .state
= ARM_CP_STATE_AA32
,
6103 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
6104 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
6106 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
6107 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
6108 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
6110 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
6111 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
6112 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
6114 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
6115 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
6116 .access
= PL2_RW
, .writefn
= vmsa_tcr_el12_write
,
6117 .raw_writefn
= raw_write
,
6118 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[2]) },
6119 { .name
= "VTCR", .state
= ARM_CP_STATE_AA32
,
6120 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
6121 .type
= ARM_CP_ALIAS
,
6122 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
6123 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vtcr_el2
) },
6124 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_AA64
,
6125 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
6127 /* no .writefn needed as this can't cause an ASID change */
6128 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
6129 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
6130 .cp
= 15, .opc1
= 6, .crm
= 2,
6131 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
6132 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
6133 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
),
6134 .writefn
= vttbr_write
, .raw_writefn
= raw_write
},
6135 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
6136 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
6137 .access
= PL2_RW
, .writefn
= vttbr_write
, .raw_writefn
= raw_write
,
6138 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
) },
6139 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
6140 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
6141 .access
= PL2_RW
, .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
6142 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[2]) },
6143 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
6144 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
6145 .access
= PL2_RW
, .resetvalue
= 0,
6146 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[2]) },
6147 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
6148 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
6149 .access
= PL2_RW
, .resetvalue
= 0,
6150 .writefn
= vmsa_tcr_ttbr_el2_write
, .raw_writefn
= raw_write
,
6151 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
6152 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
6153 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
6154 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
6155 { .name
= "TLBIALLNSNH",
6156 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
6157 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6158 .writefn
= tlbiall_nsnh_write
},
6159 { .name
= "TLBIALLNSNHIS",
6160 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
6161 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6162 .writefn
= tlbiall_nsnh_is_write
},
6163 { .name
= "TLBIALLH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
6164 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6165 .writefn
= tlbiall_hyp_write
},
6166 { .name
= "TLBIALLHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
6167 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6168 .writefn
= tlbiall_hyp_is_write
},
6169 { .name
= "TLBIMVAH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
6170 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6171 .writefn
= tlbimva_hyp_write
},
6172 { .name
= "TLBIMVAHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
6173 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6174 .writefn
= tlbimva_hyp_is_write
},
6175 { .name
= "TLBI_ALLE2", .state
= ARM_CP_STATE_AA64
,
6176 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
6177 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6178 .writefn
= tlbi_aa64_alle2_write
},
6179 { .name
= "TLBI_VAE2", .state
= ARM_CP_STATE_AA64
,
6180 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
6181 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6182 .writefn
= tlbi_aa64_vae2_write
},
6183 { .name
= "TLBI_VALE2", .state
= ARM_CP_STATE_AA64
,
6184 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
6185 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6186 .writefn
= tlbi_aa64_vae2_write
},
6187 { .name
= "TLBI_ALLE2IS", .state
= ARM_CP_STATE_AA64
,
6188 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
6189 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6190 .writefn
= tlbi_aa64_alle2is_write
},
6191 { .name
= "TLBI_VAE2IS", .state
= ARM_CP_STATE_AA64
,
6192 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
6193 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6194 .writefn
= tlbi_aa64_vae2is_write
},
6195 { .name
= "TLBI_VALE2IS", .state
= ARM_CP_STATE_AA64
,
6196 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
6197 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6198 .writefn
= tlbi_aa64_vae2is_write
},
6199 #ifndef CONFIG_USER_ONLY
6201 * Unlike the other EL2-related AT operations, these must
6202 * UNDEF from EL3 if EL2 is not implemented, which is why we
6203 * define them here rather than with the rest of the AT ops.
6205 { .name
= "AT_S1E2R", .state
= ARM_CP_STATE_AA64
,
6206 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
6207 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
6208 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
| ARM_CP_EL3_NO_EL2_UNDEF
,
6209 .writefn
= ats_write64
},
6210 { .name
= "AT_S1E2W", .state
= ARM_CP_STATE_AA64
,
6211 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
6212 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
6213 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
| ARM_CP_EL3_NO_EL2_UNDEF
,
6214 .writefn
= ats_write64
},
6216 * The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
6217 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
6218 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
6219 * to behave as if SCR.NS was 1.
6221 { .name
= "ATS1HR", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
6223 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
6224 { .name
= "ATS1HW", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
6226 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
6227 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
6228 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
6230 * ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
6231 * reset values as IMPDEF. We choose to reset to 3 to comply with
6232 * both ARMv7 and ARMv8.
6234 .access
= PL2_RW
, .type
= ARM_CP_IO
, .resetvalue
= 3,
6235 .writefn
= gt_cnthctl_write
, .raw_writefn
= raw_write
,
6236 .fieldoffset
= offsetof(CPUARMState
, cp15
.cnthctl_el2
) },
6237 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
6238 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
6239 .access
= PL2_RW
, .type
= ARM_CP_IO
, .resetvalue
= 0,
6240 .writefn
= gt_cntvoff_write
,
6241 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
6242 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
6243 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
| ARM_CP_IO
,
6244 .writefn
= gt_cntvoff_write
,
6245 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
6246 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
6247 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
6248 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
6249 .type
= ARM_CP_IO
, .access
= PL2_RW
,
6250 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
6251 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
6252 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
6253 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_IO
,
6254 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
6255 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
6256 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
6257 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
6258 .resetfn
= gt_hyp_timer_reset
,
6259 .readfn
= gt_hyp_tval_read
, .writefn
= gt_hyp_tval_write
},
6260 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
6262 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
6264 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].ctl
),
6266 .writefn
= gt_hyp_ctl_write
, .raw_writefn
= raw_write
},
6268 { .name
= "HPFAR", .state
= ARM_CP_STATE_AA32
,
6269 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
6270 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
6271 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
6272 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_AA64
,
6273 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
6275 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
6276 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
6277 .cp
= 15, .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
6279 .fieldoffset
= offsetof(CPUARMState
, cp15
.hstr_el2
) },
6282 static const ARMCPRegInfo el2_v8_cp_reginfo
[] = {
6283 { .name
= "HCR2", .state
= ARM_CP_STATE_AA32
,
6284 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
6285 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
6287 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.hcr_el2
),
6288 .writefn
= hcr_writehigh
},
6291 static CPAccessResult
sel2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6294 if (arm_current_el(env
) == 3 || arm_is_secure_below_el3(env
)) {
6295 return CP_ACCESS_OK
;
6297 return CP_ACCESS_TRAP_UNCATEGORIZED
;
6300 static const ARMCPRegInfo el2_sec_cp_reginfo
[] = {
6301 { .name
= "VSTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
6302 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 6, .opc2
= 0,
6303 .access
= PL2_RW
, .accessfn
= sel2_access
,
6304 .fieldoffset
= offsetof(CPUARMState
, cp15
.vsttbr_el2
) },
6305 { .name
= "VSTCR_EL2", .state
= ARM_CP_STATE_AA64
,
6306 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 6, .opc2
= 2,
6307 .access
= PL2_RW
, .accessfn
= sel2_access
,
6308 .fieldoffset
= offsetof(CPUARMState
, cp15
.vstcr_el2
) },
6311 static CPAccessResult
nsacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6315 * The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
6316 * At Secure EL1 it traps to EL3 or EL2.
6318 if (arm_current_el(env
) == 3) {
6319 return CP_ACCESS_OK
;
6321 if (arm_is_secure_below_el3(env
)) {
6322 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
6323 return CP_ACCESS_TRAP_EL2
;
6325 return CP_ACCESS_TRAP_EL3
;
6327 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
6329 return CP_ACCESS_OK
;
6331 return CP_ACCESS_TRAP_UNCATEGORIZED
;
6334 static const ARMCPRegInfo el3_cp_reginfo
[] = {
6335 { .name
= "SCR_EL3", .state
= ARM_CP_STATE_AA64
,
6336 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 0,
6337 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.scr_el3
),
6338 .resetfn
= scr_reset
, .writefn
= scr_write
, .raw_writefn
= raw_write
},
6339 { .name
= "SCR", .type
= ARM_CP_ALIAS
| ARM_CP_NEWEL
,
6340 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 0,
6341 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
6342 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.scr_el3
),
6343 .writefn
= scr_write
, .raw_writefn
= raw_write
},
6344 { .name
= "SDER32_EL3", .state
= ARM_CP_STATE_AA64
,
6345 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 1,
6346 .access
= PL3_RW
, .resetvalue
= 0,
6347 .fieldoffset
= offsetof(CPUARMState
, cp15
.sder
) },
6349 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 1,
6350 .access
= PL3_RW
, .resetvalue
= 0,
6351 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.sder
) },
6352 { .name
= "MVBAR", .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
6353 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
6354 .writefn
= vbar_write
, .resetvalue
= 0,
6355 .fieldoffset
= offsetof(CPUARMState
, cp15
.mvbar
) },
6356 { .name
= "TTBR0_EL3", .state
= ARM_CP_STATE_AA64
,
6357 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 0,
6358 .access
= PL3_RW
, .resetvalue
= 0,
6359 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[3]) },
6360 { .name
= "TCR_EL3", .state
= ARM_CP_STATE_AA64
,
6361 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 2,
6363 /* no .writefn needed as this can't cause an ASID change */
6365 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[3]) },
6366 { .name
= "ELR_EL3", .state
= ARM_CP_STATE_AA64
,
6367 .type
= ARM_CP_ALIAS
,
6368 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 1,
6370 .fieldoffset
= offsetof(CPUARMState
, elr_el
[3]) },
6371 { .name
= "ESR_EL3", .state
= ARM_CP_STATE_AA64
,
6372 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 2, .opc2
= 0,
6373 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[3]) },
6374 { .name
= "FAR_EL3", .state
= ARM_CP_STATE_AA64
,
6375 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 0,
6376 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[3]) },
6377 { .name
= "SPSR_EL3", .state
= ARM_CP_STATE_AA64
,
6378 .type
= ARM_CP_ALIAS
,
6379 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 0,
6381 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_MON
]) },
6382 { .name
= "VBAR_EL3", .state
= ARM_CP_STATE_AA64
,
6383 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 0,
6384 .access
= PL3_RW
, .writefn
= vbar_write
,
6385 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[3]),
6387 { .name
= "CPTR_EL3", .state
= ARM_CP_STATE_AA64
,
6388 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 2,
6389 .access
= PL3_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
6390 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[3]) },
6391 { .name
= "TPIDR_EL3", .state
= ARM_CP_STATE_AA64
,
6392 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 2,
6393 .access
= PL3_RW
, .resetvalue
= 0,
6394 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[3]) },
6395 { .name
= "AMAIR_EL3", .state
= ARM_CP_STATE_AA64
,
6396 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 3, .opc2
= 0,
6397 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
6399 { .name
= "AFSR0_EL3", .state
= ARM_CP_STATE_BOTH
,
6400 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 0,
6401 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
6403 { .name
= "AFSR1_EL3", .state
= ARM_CP_STATE_BOTH
,
6404 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 1,
6405 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
6407 { .name
= "TLBI_ALLE3IS", .state
= ARM_CP_STATE_AA64
,
6408 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 0,
6409 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6410 .writefn
= tlbi_aa64_alle3is_write
},
6411 { .name
= "TLBI_VAE3IS", .state
= ARM_CP_STATE_AA64
,
6412 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 1,
6413 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6414 .writefn
= tlbi_aa64_vae3is_write
},
6415 { .name
= "TLBI_VALE3IS", .state
= ARM_CP_STATE_AA64
,
6416 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 5,
6417 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6418 .writefn
= tlbi_aa64_vae3is_write
},
6419 { .name
= "TLBI_ALLE3", .state
= ARM_CP_STATE_AA64
,
6420 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 0,
6421 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6422 .writefn
= tlbi_aa64_alle3_write
},
6423 { .name
= "TLBI_VAE3", .state
= ARM_CP_STATE_AA64
,
6424 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 1,
6425 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6426 .writefn
= tlbi_aa64_vae3_write
},
6427 { .name
= "TLBI_VALE3", .state
= ARM_CP_STATE_AA64
,
6428 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 5,
6429 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6430 .writefn
= tlbi_aa64_vae3_write
},
6433 #ifndef CONFIG_USER_ONLY
6434 /* Test if system register redirection is to occur in the current state. */
6435 static bool redirect_for_e2h(CPUARMState
*env
)
6437 return arm_current_el(env
) == 2 && (arm_hcr_el2_eff(env
) & HCR_E2H
);
6440 static uint64_t el2_e2h_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6444 if (redirect_for_e2h(env
)) {
6445 /* Switch to the saved EL2 version of the register. */
6447 readfn
= ri
->readfn
;
6449 readfn
= ri
->orig_readfn
;
6451 if (readfn
== NULL
) {
6454 return readfn(env
, ri
);
6457 static void el2_e2h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6462 if (redirect_for_e2h(env
)) {
6463 /* Switch to the saved EL2 version of the register. */
6465 writefn
= ri
->writefn
;
6467 writefn
= ri
->orig_writefn
;
6469 if (writefn
== NULL
) {
6470 writefn
= raw_write
;
6472 writefn(env
, ri
, value
);
6475 static void define_arm_vh_e2h_redirects_aliases(ARMCPU
*cpu
)
6478 uint32_t src_key
, dst_key
, new_key
;
6479 const char *src_name
, *dst_name
, *new_name
;
6480 bool (*feature
)(const ARMISARegisters
*id
);
6483 #define K(op0, op1, crn, crm, op2) \
6484 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)
6486 static const struct E2HAlias aliases
[] = {
6487 { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0),
6488 "SCTLR", "SCTLR_EL2", "SCTLR_EL12" },
6489 { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2),
6490 "CPACR", "CPTR_EL2", "CPACR_EL12" },
6491 { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0),
6492 "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" },
6493 { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1),
6494 "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" },
6495 { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2),
6496 "TCR_EL1", "TCR_EL2", "TCR_EL12" },
6497 { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0),
6498 "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" },
6499 { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1),
6500 "ELR_EL1", "ELR_EL2", "ELR_EL12" },
6501 { K(3, 0, 5, 1, 0), K(3, 4, 5, 1, 0), K(3, 5, 5, 1, 0),
6502 "AFSR0_EL1", "AFSR0_EL2", "AFSR0_EL12" },
6503 { K(3, 0, 5, 1, 1), K(3, 4, 5, 1, 1), K(3, 5, 5, 1, 1),
6504 "AFSR1_EL1", "AFSR1_EL2", "AFSR1_EL12" },
6505 { K(3, 0, 5, 2, 0), K(3, 4, 5, 2, 0), K(3, 5, 5, 2, 0),
6506 "ESR_EL1", "ESR_EL2", "ESR_EL12" },
6507 { K(3, 0, 6, 0, 0), K(3, 4, 6, 0, 0), K(3, 5, 6, 0, 0),
6508 "FAR_EL1", "FAR_EL2", "FAR_EL12" },
6509 { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0),
6510 "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" },
6511 { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0),
6512 "AMAIR0", "AMAIR_EL2", "AMAIR_EL12" },
6513 { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0),
6514 "VBAR", "VBAR_EL2", "VBAR_EL12" },
6515 { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1),
6516 "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" },
6517 { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0),
6518 "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" },
6521 * Note that redirection of ZCR is mentioned in the description
6522 * of ZCR_EL2, and aliasing in the description of ZCR_EL1, but
6523 * not in the summary table.
6525 { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0),
6526 "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve
},
6527 { K(3, 0, 1, 2, 6), K(3, 4, 1, 2, 6), K(3, 5, 1, 2, 6),
6528 "SMCR_EL1", "SMCR_EL2", "SMCR_EL12", isar_feature_aa64_sme
},
6530 { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0),
6531 "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte
},
6533 { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7),
6534 "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12",
6535 isar_feature_aa64_scxtnum
},
6537 /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */
6538 /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */
6544 for (i
= 0; i
< ARRAY_SIZE(aliases
); i
++) {
6545 const struct E2HAlias
*a
= &aliases
[i
];
6546 ARMCPRegInfo
*src_reg
, *dst_reg
, *new_reg
;
6549 if (a
->feature
&& !a
->feature(&cpu
->isar
)) {
6553 src_reg
= g_hash_table_lookup(cpu
->cp_regs
,
6554 (gpointer
)(uintptr_t)a
->src_key
);
6555 dst_reg
= g_hash_table_lookup(cpu
->cp_regs
,
6556 (gpointer
)(uintptr_t)a
->dst_key
);
6557 g_assert(src_reg
!= NULL
);
6558 g_assert(dst_reg
!= NULL
);
6560 /* Cross-compare names to detect typos in the keys. */
6561 g_assert(strcmp(src_reg
->name
, a
->src_name
) == 0);
6562 g_assert(strcmp(dst_reg
->name
, a
->dst_name
) == 0);
6564 /* None of the core system registers use opaque; we will. */
6565 g_assert(src_reg
->opaque
== NULL
);
6567 /* Create alias before redirection so we dup the right data. */
6568 new_reg
= g_memdup(src_reg
, sizeof(ARMCPRegInfo
));
6570 new_reg
->name
= a
->new_name
;
6571 new_reg
->type
|= ARM_CP_ALIAS
;
6572 /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */
6573 new_reg
->access
&= PL2_RW
| PL3_RW
;
6575 ok
= g_hash_table_insert(cpu
->cp_regs
,
6576 (gpointer
)(uintptr_t)a
->new_key
, new_reg
);
6579 src_reg
->opaque
= dst_reg
;
6580 src_reg
->orig_readfn
= src_reg
->readfn
?: raw_read
;
6581 src_reg
->orig_writefn
= src_reg
->writefn
?: raw_write
;
6582 if (!src_reg
->raw_readfn
) {
6583 src_reg
->raw_readfn
= raw_read
;
6585 if (!src_reg
->raw_writefn
) {
6586 src_reg
->raw_writefn
= raw_write
;
6588 src_reg
->readfn
= el2_e2h_read
;
6589 src_reg
->writefn
= el2_e2h_write
;
6594 static CPAccessResult
ctr_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6597 int cur_el
= arm_current_el(env
);
6600 uint64_t hcr
= arm_hcr_el2_eff(env
);
6603 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
6604 if (!(env
->cp15
.sctlr_el
[2] & SCTLR_UCT
)) {
6605 return CP_ACCESS_TRAP_EL2
;
6608 if (!(env
->cp15
.sctlr_el
[1] & SCTLR_UCT
)) {
6609 return CP_ACCESS_TRAP
;
6611 if (hcr
& HCR_TID2
) {
6612 return CP_ACCESS_TRAP_EL2
;
6615 } else if (hcr
& HCR_TID2
) {
6616 return CP_ACCESS_TRAP_EL2
;
6620 if (arm_current_el(env
) < 2 && arm_hcr_el2_eff(env
) & HCR_TID2
) {
6621 return CP_ACCESS_TRAP_EL2
;
6624 return CP_ACCESS_OK
;
6628 * Check for traps to RAS registers, which are controlled
6629 * by HCR_EL2.TERR and SCR_EL3.TERR.
6631 static CPAccessResult
access_terr(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6634 int el
= arm_current_el(env
);
6636 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_TERR
)) {
6637 return CP_ACCESS_TRAP_EL2
;
6639 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_TERR
)) {
6640 return CP_ACCESS_TRAP_EL3
;
6642 return CP_ACCESS_OK
;
6645 static uint64_t disr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6647 int el
= arm_current_el(env
);
6649 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_AMO
)) {
6650 return env
->cp15
.vdisr_el2
;
6652 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_EA
)) {
6653 return 0; /* RAZ/WI */
6655 return env
->cp15
.disr_el1
;
6658 static void disr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
6660 int el
= arm_current_el(env
);
6662 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_AMO
)) {
6663 env
->cp15
.vdisr_el2
= val
;
6666 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_EA
)) {
6667 return; /* RAZ/WI */
6669 env
->cp15
.disr_el1
= val
;
6673 * Minimal RAS implementation with no Error Records.
6674 * Which means that all of the Error Record registers:
6682 * ERXPFGCDN_EL1 (RASv1p1)
6683 * ERXPFGCTL_EL1 (RASv1p1)
6684 * ERXPFGF_EL1 (RASv1p1)
6688 * may generate UNDEFINED, which is the effect we get by not
6689 * listing them at all.
6691 * These registers have fine-grained trap bits, but UNDEF-to-EL1
6692 * is higher priority than FGT-to-EL2 so we do not need to list them
6693 * in order to check for an FGT.
6695 static const ARMCPRegInfo minimal_ras_reginfo
[] = {
6696 { .name
= "DISR_EL1", .state
= ARM_CP_STATE_BOTH
,
6697 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 1,
6698 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.disr_el1
),
6699 .readfn
= disr_read
, .writefn
= disr_write
, .raw_writefn
= raw_write
},
6700 { .name
= "ERRIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
6701 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 3, .opc2
= 0,
6702 .access
= PL1_R
, .accessfn
= access_terr
,
6703 .fgt
= FGT_ERRIDR_EL1
,
6704 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6705 { .name
= "VDISR_EL2", .state
= ARM_CP_STATE_BOTH
,
6706 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 1, .opc2
= 1,
6707 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.vdisr_el2
) },
6708 { .name
= "VSESR_EL2", .state
= ARM_CP_STATE_BOTH
,
6709 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 3,
6710 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.vsesr_el2
) },
6714 * Return the exception level to which exceptions should be taken
6715 * via SVEAccessTrap. This excludes the check for whether the exception
6716 * should be routed through AArch64.AdvSIMDFPAccessTrap. That can easily
6717 * be found by testing 0 < fp_exception_el < sve_exception_el.
6719 * C.f. the ARM pseudocode function CheckSVEEnabled. Note that the
6720 * pseudocode does *not* separate out the FP trap checks, but has them
6721 * all in one function.
6723 int sve_exception_el(CPUARMState
*env
, int el
)
6725 #ifndef CONFIG_USER_ONLY
6726 if (el
<= 1 && !el_is_in_host(env
, el
)) {
6727 switch (FIELD_EX64(env
->cp15
.cpacr_el1
, CPACR_EL1
, ZEN
)) {
6739 if (el
<= 2 && arm_is_el2_enabled(env
)) {
6740 /* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */
6741 if (env
->cp15
.hcr_el2
& HCR_E2H
) {
6742 switch (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, ZEN
)) {
6744 if (el
!= 0 || !(env
->cp15
.hcr_el2
& HCR_TGE
)) {
6753 if (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TZ
)) {
6759 /* CPTR_EL3. Since EZ is negative we must check for EL3. */
6760 if (arm_feature(env
, ARM_FEATURE_EL3
)
6761 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, EZ
)) {
6769 * Return the exception level to which exceptions should be taken for SME.
6770 * C.f. the ARM pseudocode function CheckSMEAccess.
6772 int sme_exception_el(CPUARMState
*env
, int el
)
6774 #ifndef CONFIG_USER_ONLY
6775 if (el
<= 1 && !el_is_in_host(env
, el
)) {
6776 switch (FIELD_EX64(env
->cp15
.cpacr_el1
, CPACR_EL1
, SMEN
)) {
6788 if (el
<= 2 && arm_is_el2_enabled(env
)) {
6789 /* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */
6790 if (env
->cp15
.hcr_el2
& HCR_E2H
) {
6791 switch (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, SMEN
)) {
6793 if (el
!= 0 || !(env
->cp15
.hcr_el2
& HCR_TGE
)) {
6802 if (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TSM
)) {
6808 /* CPTR_EL3. Since ESM is negative we must check for EL3. */
6809 if (arm_feature(env
, ARM_FEATURE_EL3
)
6810 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, ESM
)) {
6818 * Given that SVE is enabled, return the vector length for EL.
6820 uint32_t sve_vqm1_for_el_sm(CPUARMState
*env
, int el
, bool sm
)
6822 ARMCPU
*cpu
= env_archcpu(env
);
6823 uint64_t *cr
= env
->vfp
.zcr_el
;
6824 uint32_t map
= cpu
->sve_vq
.map
;
6825 uint32_t len
= ARM_MAX_VQ
- 1;
6828 cr
= env
->vfp
.smcr_el
;
6829 map
= cpu
->sme_vq
.map
;
6832 if (el
<= 1 && !el_is_in_host(env
, el
)) {
6833 len
= MIN(len
, 0xf & (uint32_t)cr
[1]);
6835 if (el
<= 2 && arm_feature(env
, ARM_FEATURE_EL2
)) {
6836 len
= MIN(len
, 0xf & (uint32_t)cr
[2]);
6838 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
6839 len
= MIN(len
, 0xf & (uint32_t)cr
[3]);
6842 map
&= MAKE_64BIT_MASK(0, len
+ 1);
6844 return 31 - clz32(map
);
6847 /* Bit 0 is always set for Normal SVE -- not so for Streaming SVE. */
6849 return ctz32(cpu
->sme_vq
.map
);
6852 uint32_t sve_vqm1_for_el(CPUARMState
*env
, int el
)
6854 return sve_vqm1_for_el_sm(env
, el
, FIELD_EX64(env
->svcr
, SVCR
, SM
));
6857 static void zcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6860 int cur_el
= arm_current_el(env
);
6861 int old_len
= sve_vqm1_for_el(env
, cur_el
);
6864 /* Bits other than [3:0] are RAZ/WI. */
6865 QEMU_BUILD_BUG_ON(ARM_MAX_VQ
> 16);
6866 raw_write(env
, ri
, value
& 0xf);
6869 * Because we arrived here, we know both FP and SVE are enabled;
6870 * otherwise we would have trapped access to the ZCR_ELn register.
6872 new_len
= sve_vqm1_for_el(env
, cur_el
);
6873 if (new_len
< old_len
) {
6874 aarch64_sve_narrow_vq(env
, new_len
+ 1);
6878 static const ARMCPRegInfo zcr_reginfo
[] = {
6879 { .name
= "ZCR_EL1", .state
= ARM_CP_STATE_AA64
,
6880 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 0,
6881 .access
= PL1_RW
, .type
= ARM_CP_SVE
,
6882 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[1]),
6883 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
6884 { .name
= "ZCR_EL2", .state
= ARM_CP_STATE_AA64
,
6885 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 0,
6886 .access
= PL2_RW
, .type
= ARM_CP_SVE
,
6887 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[2]),
6888 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
6889 { .name
= "ZCR_EL3", .state
= ARM_CP_STATE_AA64
,
6890 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 2, .opc2
= 0,
6891 .access
= PL3_RW
, .type
= ARM_CP_SVE
,
6892 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[3]),
6893 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
6896 #ifdef TARGET_AARCH64
6897 static CPAccessResult
access_tpidr2(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6900 int el
= arm_current_el(env
);
6903 uint64_t sctlr
= arm_sctlr(env
, el
);
6904 if (!(sctlr
& SCTLR_EnTP2
)) {
6905 return CP_ACCESS_TRAP
;
6908 /* TODO: FEAT_FGT */
6910 && arm_feature(env
, ARM_FEATURE_EL3
)
6911 && !(env
->cp15
.scr_el3
& SCR_ENTP2
)) {
6912 return CP_ACCESS_TRAP_EL3
;
6914 return CP_ACCESS_OK
;
6917 static CPAccessResult
access_esm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6920 /* TODO: FEAT_FGT for SMPRI_EL1 but not SMPRIMAP_EL2 */
6921 if (arm_current_el(env
) < 3
6922 && arm_feature(env
, ARM_FEATURE_EL3
)
6923 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, ESM
)) {
6924 return CP_ACCESS_TRAP_EL3
;
6926 return CP_ACCESS_OK
;
6930 static void arm_reset_sve_state(CPUARMState
*env
)
6932 memset(env
->vfp
.zregs
, 0, sizeof(env
->vfp
.zregs
));
6933 /* Recall that FFR is stored as pregs[16]. */
6934 memset(env
->vfp
.pregs
, 0, sizeof(env
->vfp
.pregs
));
6935 vfp_set_fpcr(env
, 0x0800009f);
6938 void aarch64_set_svcr(CPUARMState
*env
, uint64_t new, uint64_t mask
)
6940 uint64_t change
= (env
->svcr
^ new) & mask
;
6945 env
->svcr
^= change
;
6947 if (change
& R_SVCR_SM_MASK
) {
6948 arm_reset_sve_state(env
);
6954 * SetPSTATE_ZA zeros on enable and disable. We can zero this only
6955 * on enable: while disabled, the storage is inaccessible and the
6956 * value does not matter. We're not saving the storage in vmstate
6957 * when disabled either.
6959 if (change
& new & R_SVCR_ZA_MASK
) {
6960 memset(env
->zarray
, 0, sizeof(env
->zarray
));
6963 if (tcg_enabled()) {
6964 arm_rebuild_hflags(env
);
6968 static void svcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6971 aarch64_set_svcr(env
, value
, -1);
6974 static void smcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6977 int cur_el
= arm_current_el(env
);
6978 int old_len
= sve_vqm1_for_el(env
, cur_el
);
6981 QEMU_BUILD_BUG_ON(ARM_MAX_VQ
> R_SMCR_LEN_MASK
+ 1);
6982 value
&= R_SMCR_LEN_MASK
| R_SMCR_FA64_MASK
;
6983 raw_write(env
, ri
, value
);
6986 * Note that it is CONSTRAINED UNPREDICTABLE what happens to ZA storage
6987 * when SVL is widened (old values kept, or zeros). Choose to keep the
6988 * current values for simplicity. But for QEMU internals, we must still
6989 * apply the narrower SVL to the Zregs and Pregs -- see the comment
6990 * above aarch64_sve_narrow_vq.
6992 new_len
= sve_vqm1_for_el(env
, cur_el
);
6993 if (new_len
< old_len
) {
6994 aarch64_sve_narrow_vq(env
, new_len
+ 1);
6998 static const ARMCPRegInfo sme_reginfo
[] = {
6999 { .name
= "TPIDR2_EL0", .state
= ARM_CP_STATE_AA64
,
7000 .opc0
= 3, .opc1
= 3, .crn
= 13, .crm
= 0, .opc2
= 5,
7001 .access
= PL0_RW
, .accessfn
= access_tpidr2
,
7002 .fgt
= FGT_NTPIDR2_EL0
,
7003 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr2_el0
) },
7004 { .name
= "SVCR", .state
= ARM_CP_STATE_AA64
,
7005 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 2,
7006 .access
= PL0_RW
, .type
= ARM_CP_SME
,
7007 .fieldoffset
= offsetof(CPUARMState
, svcr
),
7008 .writefn
= svcr_write
, .raw_writefn
= raw_write
},
7009 { .name
= "SMCR_EL1", .state
= ARM_CP_STATE_AA64
,
7010 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 6,
7011 .access
= PL1_RW
, .type
= ARM_CP_SME
,
7012 .fieldoffset
= offsetof(CPUARMState
, vfp
.smcr_el
[1]),
7013 .writefn
= smcr_write
, .raw_writefn
= raw_write
},
7014 { .name
= "SMCR_EL2", .state
= ARM_CP_STATE_AA64
,
7015 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 6,
7016 .access
= PL2_RW
, .type
= ARM_CP_SME
,
7017 .fieldoffset
= offsetof(CPUARMState
, vfp
.smcr_el
[2]),
7018 .writefn
= smcr_write
, .raw_writefn
= raw_write
},
7019 { .name
= "SMCR_EL3", .state
= ARM_CP_STATE_AA64
,
7020 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 2, .opc2
= 6,
7021 .access
= PL3_RW
, .type
= ARM_CP_SME
,
7022 .fieldoffset
= offsetof(CPUARMState
, vfp
.smcr_el
[3]),
7023 .writefn
= smcr_write
, .raw_writefn
= raw_write
},
7024 { .name
= "SMIDR_EL1", .state
= ARM_CP_STATE_AA64
,
7025 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 6,
7026 .access
= PL1_R
, .accessfn
= access_aa64_tid1
,
7028 * IMPLEMENTOR = 0 (software)
7029 * REVISION = 0 (implementation defined)
7030 * SMPS = 0 (no streaming execution priority in QEMU)
7031 * AFFINITY = 0 (streaming sve mode not shared with other PEs)
7033 .type
= ARM_CP_CONST
, .resetvalue
= 0, },
7035 * Because SMIDR_EL1.SMPS is 0, SMPRI_EL1 and SMPRIMAP_EL2 are RES 0.
7037 { .name
= "SMPRI_EL1", .state
= ARM_CP_STATE_AA64
,
7038 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 4,
7039 .access
= PL1_RW
, .accessfn
= access_esm
,
7040 .fgt
= FGT_NSMPRI_EL1
,
7041 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7042 { .name
= "SMPRIMAP_EL2", .state
= ARM_CP_STATE_AA64
,
7043 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 5,
7044 .access
= PL2_RW
, .accessfn
= access_esm
,
7045 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7048 static void tlbi_aa64_paall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7051 CPUState
*cs
= env_cpu(env
);
7056 static void gpccr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7059 /* L0GPTSZ is RO; other bits not mentioned are RES0. */
7060 uint64_t rw_mask
= R_GPCCR_PPS_MASK
| R_GPCCR_IRGN_MASK
|
7061 R_GPCCR_ORGN_MASK
| R_GPCCR_SH_MASK
| R_GPCCR_PGS_MASK
|
7062 R_GPCCR_GPC_MASK
| R_GPCCR_GPCP_MASK
;
7064 env
->cp15
.gpccr_el3
= (value
& rw_mask
) | (env
->cp15
.gpccr_el3
& ~rw_mask
);
7067 static void gpccr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7069 env
->cp15
.gpccr_el3
= FIELD_DP64(0, GPCCR
, L0GPTSZ
,
7070 env_archcpu(env
)->reset_l0gptsz
);
7073 static void tlbi_aa64_paallos_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7076 CPUState
*cs
= env_cpu(env
);
7078 tlb_flush_all_cpus_synced(cs
);
7081 static const ARMCPRegInfo rme_reginfo
[] = {
7082 { .name
= "GPCCR_EL3", .state
= ARM_CP_STATE_AA64
,
7083 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 1, .opc2
= 6,
7084 .access
= PL3_RW
, .writefn
= gpccr_write
, .resetfn
= gpccr_reset
,
7085 .fieldoffset
= offsetof(CPUARMState
, cp15
.gpccr_el3
) },
7086 { .name
= "GPTBR_EL3", .state
= ARM_CP_STATE_AA64
,
7087 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 1, .opc2
= 4,
7088 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.gptbr_el3
) },
7089 { .name
= "MFAR_EL3", .state
= ARM_CP_STATE_AA64
,
7090 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 5,
7091 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mfar_el3
) },
7092 { .name
= "TLBI_PAALL", .state
= ARM_CP_STATE_AA64
,
7093 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 4,
7094 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7095 .writefn
= tlbi_aa64_paall_write
},
7096 { .name
= "TLBI_PAALLOS", .state
= ARM_CP_STATE_AA64
,
7097 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 4,
7098 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7099 .writefn
= tlbi_aa64_paallos_write
},
7101 * QEMU does not have a way to invalidate by physical address, thus
7102 * invalidating a range of physical addresses is accomplished by
7103 * flushing all tlb entries in the outer shareable domain,
7104 * just like PAALLOS.
7106 { .name
= "TLBI_RPALOS", .state
= ARM_CP_STATE_AA64
,
7107 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 4, .opc2
= 7,
7108 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7109 .writefn
= tlbi_aa64_paallos_write
},
7110 { .name
= "TLBI_RPAOS", .state
= ARM_CP_STATE_AA64
,
7111 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 4, .opc2
= 3,
7112 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7113 .writefn
= tlbi_aa64_paallos_write
},
7114 { .name
= "DC_CIPAPA", .state
= ARM_CP_STATE_AA64
,
7115 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 14, .opc2
= 1,
7116 .access
= PL3_W
, .type
= ARM_CP_NOP
},
7119 static const ARMCPRegInfo rme_mte_reginfo
[] = {
7120 { .name
= "DC_CIGDPAPA", .state
= ARM_CP_STATE_AA64
,
7121 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 14, .opc2
= 5,
7122 .access
= PL3_W
, .type
= ARM_CP_NOP
},
7124 #endif /* TARGET_AARCH64 */
7126 static void define_pmu_regs(ARMCPU
*cpu
)
7129 * v7 performance monitor control register: same implementor
7130 * field as main ID register, and we implement four counters in
7131 * addition to the cycle count register.
7133 unsigned int i
, pmcrn
= pmu_num_counters(&cpu
->env
);
7134 ARMCPRegInfo pmcr
= {
7135 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
7137 .fgt
= FGT_PMCR_EL0
,
7138 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7139 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcr
),
7140 .accessfn
= pmreg_access
, .writefn
= pmcr_write
,
7141 .raw_writefn
= raw_write
,
7143 ARMCPRegInfo pmcr64
= {
7144 .name
= "PMCR_EL0", .state
= ARM_CP_STATE_AA64
,
7145 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 0,
7146 .access
= PL0_RW
, .accessfn
= pmreg_access
,
7147 .fgt
= FGT_PMCR_EL0
,
7149 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
7150 .resetvalue
= cpu
->isar
.reset_pmcr_el0
,
7151 .writefn
= pmcr_write
, .raw_writefn
= raw_write
,
7154 define_one_arm_cp_reg(cpu
, &pmcr
);
7155 define_one_arm_cp_reg(cpu
, &pmcr64
);
7156 for (i
= 0; i
< pmcrn
; i
++) {
7157 char *pmevcntr_name
= g_strdup_printf("PMEVCNTR%d", i
);
7158 char *pmevcntr_el0_name
= g_strdup_printf("PMEVCNTR%d_EL0", i
);
7159 char *pmevtyper_name
= g_strdup_printf("PMEVTYPER%d", i
);
7160 char *pmevtyper_el0_name
= g_strdup_printf("PMEVTYPER%d_EL0", i
);
7161 ARMCPRegInfo pmev_regs
[] = {
7162 { .name
= pmevcntr_name
, .cp
= 15, .crn
= 14,
7163 .crm
= 8 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
7164 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7165 .fgt
= FGT_PMEVCNTRN_EL0
,
7166 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
7167 .accessfn
= pmreg_access_xevcntr
},
7168 { .name
= pmevcntr_el0_name
, .state
= ARM_CP_STATE_AA64
,
7169 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 8 | (3 & (i
>> 3)),
7170 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access_xevcntr
,
7172 .fgt
= FGT_PMEVCNTRN_EL0
,
7173 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
7174 .raw_readfn
= pmevcntr_rawread
,
7175 .raw_writefn
= pmevcntr_rawwrite
},
7176 { .name
= pmevtyper_name
, .cp
= 15, .crn
= 14,
7177 .crm
= 12 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
7178 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7179 .fgt
= FGT_PMEVTYPERN_EL0
,
7180 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
7181 .accessfn
= pmreg_access
},
7182 { .name
= pmevtyper_el0_name
, .state
= ARM_CP_STATE_AA64
,
7183 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 12 | (3 & (i
>> 3)),
7184 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access
,
7185 .fgt
= FGT_PMEVTYPERN_EL0
,
7187 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
7188 .raw_writefn
= pmevtyper_rawwrite
},
7190 define_arm_cp_regs(cpu
, pmev_regs
);
7191 g_free(pmevcntr_name
);
7192 g_free(pmevcntr_el0_name
);
7193 g_free(pmevtyper_name
);
7194 g_free(pmevtyper_el0_name
);
7196 if (cpu_isar_feature(aa32_pmuv3p1
, cpu
)) {
7197 ARMCPRegInfo v81_pmu_regs
[] = {
7198 { .name
= "PMCEID2", .state
= ARM_CP_STATE_AA32
,
7199 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 4,
7200 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7201 .fgt
= FGT_PMCEIDN_EL0
,
7202 .resetvalue
= extract64(cpu
->pmceid0
, 32, 32) },
7203 { .name
= "PMCEID3", .state
= ARM_CP_STATE_AA32
,
7204 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 5,
7205 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7206 .fgt
= FGT_PMCEIDN_EL0
,
7207 .resetvalue
= extract64(cpu
->pmceid1
, 32, 32) },
7209 define_arm_cp_regs(cpu
, v81_pmu_regs
);
7211 if (cpu_isar_feature(any_pmuv3p4
, cpu
)) {
7212 static const ARMCPRegInfo v84_pmmir
= {
7213 .name
= "PMMIR_EL1", .state
= ARM_CP_STATE_BOTH
,
7214 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 6,
7215 .access
= PL1_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7216 .fgt
= FGT_PMMIR_EL1
,
7219 define_one_arm_cp_reg(cpu
, &v84_pmmir
);
7223 #ifndef CONFIG_USER_ONLY
7225 * We don't know until after realize whether there's a GICv3
7226 * attached, and that is what registers the gicv3 sysregs.
7227 * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1
7230 static uint64_t id_pfr1_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7232 ARMCPU
*cpu
= env_archcpu(env
);
7233 uint64_t pfr1
= cpu
->isar
.id_pfr1
;
7235 if (env
->gicv3state
) {
7241 static uint64_t id_aa64pfr0_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7243 ARMCPU
*cpu
= env_archcpu(env
);
7244 uint64_t pfr0
= cpu
->isar
.id_aa64pfr0
;
7246 if (env
->gicv3state
) {
7254 * Shared logic between LORID and the rest of the LOR* registers.
7255 * Secure state exclusion has already been dealt with.
7257 static CPAccessResult
access_lor_ns(CPUARMState
*env
,
7258 const ARMCPRegInfo
*ri
, bool isread
)
7260 int el
= arm_current_el(env
);
7262 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_TLOR
)) {
7263 return CP_ACCESS_TRAP_EL2
;
7265 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_TLOR
)) {
7266 return CP_ACCESS_TRAP_EL3
;
7268 return CP_ACCESS_OK
;
7271 static CPAccessResult
access_lor_other(CPUARMState
*env
,
7272 const ARMCPRegInfo
*ri
, bool isread
)
7274 if (arm_is_secure_below_el3(env
)) {
7275 /* Access denied in secure mode. */
7276 return CP_ACCESS_TRAP
;
7278 return access_lor_ns(env
, ri
, isread
);
7282 * A trivial implementation of ARMv8.1-LOR leaves all of these
7283 * registers fixed at 0, which indicates that there are zero
7284 * supported Limited Ordering regions.
7286 static const ARMCPRegInfo lor_reginfo
[] = {
7287 { .name
= "LORSA_EL1", .state
= ARM_CP_STATE_AA64
,
7288 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 0,
7289 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7290 .fgt
= FGT_LORSA_EL1
,
7291 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7292 { .name
= "LOREA_EL1", .state
= ARM_CP_STATE_AA64
,
7293 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 1,
7294 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7295 .fgt
= FGT_LOREA_EL1
,
7296 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7297 { .name
= "LORN_EL1", .state
= ARM_CP_STATE_AA64
,
7298 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 2,
7299 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7300 .fgt
= FGT_LORN_EL1
,
7301 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7302 { .name
= "LORC_EL1", .state
= ARM_CP_STATE_AA64
,
7303 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 3,
7304 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7305 .fgt
= FGT_LORC_EL1
,
7306 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7307 { .name
= "LORID_EL1", .state
= ARM_CP_STATE_AA64
,
7308 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 7,
7309 .access
= PL1_R
, .accessfn
= access_lor_ns
,
7310 .fgt
= FGT_LORID_EL1
,
7311 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7314 #ifdef TARGET_AARCH64
7315 static CPAccessResult
access_pauth(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7318 int el
= arm_current_el(env
);
7321 arm_is_el2_enabled(env
) &&
7322 !(arm_hcr_el2_eff(env
) & HCR_APK
)) {
7323 return CP_ACCESS_TRAP_EL2
;
7326 arm_feature(env
, ARM_FEATURE_EL3
) &&
7327 !(env
->cp15
.scr_el3
& SCR_APK
)) {
7328 return CP_ACCESS_TRAP_EL3
;
7330 return CP_ACCESS_OK
;
7333 static const ARMCPRegInfo pauth_reginfo
[] = {
7334 { .name
= "APDAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7335 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 0,
7336 .access
= PL1_RW
, .accessfn
= access_pauth
,
7338 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.lo
) },
7339 { .name
= "APDAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7340 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 1,
7341 .access
= PL1_RW
, .accessfn
= access_pauth
,
7343 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.hi
) },
7344 { .name
= "APDBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7345 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 2,
7346 .access
= PL1_RW
, .accessfn
= access_pauth
,
7348 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.lo
) },
7349 { .name
= "APDBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7350 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 3,
7351 .access
= PL1_RW
, .accessfn
= access_pauth
,
7353 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.hi
) },
7354 { .name
= "APGAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7355 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 0,
7356 .access
= PL1_RW
, .accessfn
= access_pauth
,
7358 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.lo
) },
7359 { .name
= "APGAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7360 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 1,
7361 .access
= PL1_RW
, .accessfn
= access_pauth
,
7363 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.hi
) },
7364 { .name
= "APIAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7365 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 0,
7366 .access
= PL1_RW
, .accessfn
= access_pauth
,
7368 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.lo
) },
7369 { .name
= "APIAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7370 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 1,
7371 .access
= PL1_RW
, .accessfn
= access_pauth
,
7373 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.hi
) },
7374 { .name
= "APIBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7375 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 2,
7376 .access
= PL1_RW
, .accessfn
= access_pauth
,
7378 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.lo
) },
7379 { .name
= "APIBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7380 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 3,
7381 .access
= PL1_RW
, .accessfn
= access_pauth
,
7383 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.hi
) },
7386 static const ARMCPRegInfo tlbirange_reginfo
[] = {
7387 { .name
= "TLBI_RVAE1IS", .state
= ARM_CP_STATE_AA64
,
7388 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 1,
7389 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
7390 .fgt
= FGT_TLBIRVAE1IS
,
7391 .writefn
= tlbi_aa64_rvae1is_write
},
7392 { .name
= "TLBI_RVAAE1IS", .state
= ARM_CP_STATE_AA64
,
7393 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 3,
7394 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
7395 .fgt
= FGT_TLBIRVAAE1IS
,
7396 .writefn
= tlbi_aa64_rvae1is_write
},
7397 { .name
= "TLBI_RVALE1IS", .state
= ARM_CP_STATE_AA64
,
7398 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 5,
7399 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
7400 .fgt
= FGT_TLBIRVALE1IS
,
7401 .writefn
= tlbi_aa64_rvae1is_write
},
7402 { .name
= "TLBI_RVAALE1IS", .state
= ARM_CP_STATE_AA64
,
7403 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 7,
7404 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
7405 .fgt
= FGT_TLBIRVAALE1IS
,
7406 .writefn
= tlbi_aa64_rvae1is_write
},
7407 { .name
= "TLBI_RVAE1OS", .state
= ARM_CP_STATE_AA64
,
7408 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
7409 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7410 .fgt
= FGT_TLBIRVAE1OS
,
7411 .writefn
= tlbi_aa64_rvae1is_write
},
7412 { .name
= "TLBI_RVAAE1OS", .state
= ARM_CP_STATE_AA64
,
7413 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 3,
7414 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7415 .fgt
= FGT_TLBIRVAAE1OS
,
7416 .writefn
= tlbi_aa64_rvae1is_write
},
7417 { .name
= "TLBI_RVALE1OS", .state
= ARM_CP_STATE_AA64
,
7418 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 5,
7419 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7420 .fgt
= FGT_TLBIRVALE1OS
,
7421 .writefn
= tlbi_aa64_rvae1is_write
},
7422 { .name
= "TLBI_RVAALE1OS", .state
= ARM_CP_STATE_AA64
,
7423 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 7,
7424 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7425 .fgt
= FGT_TLBIRVAALE1OS
,
7426 .writefn
= tlbi_aa64_rvae1is_write
},
7427 { .name
= "TLBI_RVAE1", .state
= ARM_CP_STATE_AA64
,
7428 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
7429 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
7430 .fgt
= FGT_TLBIRVAE1
,
7431 .writefn
= tlbi_aa64_rvae1_write
},
7432 { .name
= "TLBI_RVAAE1", .state
= ARM_CP_STATE_AA64
,
7433 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 3,
7434 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
7435 .fgt
= FGT_TLBIRVAAE1
,
7436 .writefn
= tlbi_aa64_rvae1_write
},
7437 { .name
= "TLBI_RVALE1", .state
= ARM_CP_STATE_AA64
,
7438 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 5,
7439 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
7440 .fgt
= FGT_TLBIRVALE1
,
7441 .writefn
= tlbi_aa64_rvae1_write
},
7442 { .name
= "TLBI_RVAALE1", .state
= ARM_CP_STATE_AA64
,
7443 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 7,
7444 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
7445 .fgt
= FGT_TLBIRVAALE1
,
7446 .writefn
= tlbi_aa64_rvae1_write
},
7447 { .name
= "TLBI_RIPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
7448 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 2,
7449 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7450 .writefn
= tlbi_aa64_ripas2e1is_write
},
7451 { .name
= "TLBI_RIPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
7452 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 6,
7453 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7454 .writefn
= tlbi_aa64_ripas2e1is_write
},
7455 { .name
= "TLBI_RVAE2IS", .state
= ARM_CP_STATE_AA64
,
7456 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 2, .opc2
= 1,
7457 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7458 .writefn
= tlbi_aa64_rvae2is_write
},
7459 { .name
= "TLBI_RVALE2IS", .state
= ARM_CP_STATE_AA64
,
7460 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 2, .opc2
= 5,
7461 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7462 .writefn
= tlbi_aa64_rvae2is_write
},
7463 { .name
= "TLBI_RIPAS2E1", .state
= ARM_CP_STATE_AA64
,
7464 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 2,
7465 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7466 .writefn
= tlbi_aa64_ripas2e1_write
},
7467 { .name
= "TLBI_RIPAS2LE1", .state
= ARM_CP_STATE_AA64
,
7468 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 6,
7469 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7470 .writefn
= tlbi_aa64_ripas2e1_write
},
7471 { .name
= "TLBI_RVAE2OS", .state
= ARM_CP_STATE_AA64
,
7472 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 5, .opc2
= 1,
7473 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7474 .writefn
= tlbi_aa64_rvae2is_write
},
7475 { .name
= "TLBI_RVALE2OS", .state
= ARM_CP_STATE_AA64
,
7476 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 5, .opc2
= 5,
7477 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7478 .writefn
= tlbi_aa64_rvae2is_write
},
7479 { .name
= "TLBI_RVAE2", .state
= ARM_CP_STATE_AA64
,
7480 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 6, .opc2
= 1,
7481 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7482 .writefn
= tlbi_aa64_rvae2_write
},
7483 { .name
= "TLBI_RVALE2", .state
= ARM_CP_STATE_AA64
,
7484 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 6, .opc2
= 5,
7485 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7486 .writefn
= tlbi_aa64_rvae2_write
},
7487 { .name
= "TLBI_RVAE3IS", .state
= ARM_CP_STATE_AA64
,
7488 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 2, .opc2
= 1,
7489 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7490 .writefn
= tlbi_aa64_rvae3is_write
},
7491 { .name
= "TLBI_RVALE3IS", .state
= ARM_CP_STATE_AA64
,
7492 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 2, .opc2
= 5,
7493 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7494 .writefn
= tlbi_aa64_rvae3is_write
},
7495 { .name
= "TLBI_RVAE3OS", .state
= ARM_CP_STATE_AA64
,
7496 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 5, .opc2
= 1,
7497 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7498 .writefn
= tlbi_aa64_rvae3is_write
},
7499 { .name
= "TLBI_RVALE3OS", .state
= ARM_CP_STATE_AA64
,
7500 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 5, .opc2
= 5,
7501 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7502 .writefn
= tlbi_aa64_rvae3is_write
},
7503 { .name
= "TLBI_RVAE3", .state
= ARM_CP_STATE_AA64
,
7504 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 6, .opc2
= 1,
7505 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7506 .writefn
= tlbi_aa64_rvae3_write
},
7507 { .name
= "TLBI_RVALE3", .state
= ARM_CP_STATE_AA64
,
7508 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 6, .opc2
= 5,
7509 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7510 .writefn
= tlbi_aa64_rvae3_write
},
7513 static const ARMCPRegInfo tlbios_reginfo
[] = {
7514 { .name
= "TLBI_VMALLE1OS", .state
= ARM_CP_STATE_AA64
,
7515 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 0,
7516 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7517 .fgt
= FGT_TLBIVMALLE1OS
,
7518 .writefn
= tlbi_aa64_vmalle1is_write
},
7519 { .name
= "TLBI_VAE1OS", .state
= ARM_CP_STATE_AA64
,
7520 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 1,
7521 .fgt
= FGT_TLBIVAE1OS
,
7522 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7523 .writefn
= tlbi_aa64_vae1is_write
},
7524 { .name
= "TLBI_ASIDE1OS", .state
= ARM_CP_STATE_AA64
,
7525 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 2,
7526 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7527 .fgt
= FGT_TLBIASIDE1OS
,
7528 .writefn
= tlbi_aa64_vmalle1is_write
},
7529 { .name
= "TLBI_VAAE1OS", .state
= ARM_CP_STATE_AA64
,
7530 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 3,
7531 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7532 .fgt
= FGT_TLBIVAAE1OS
,
7533 .writefn
= tlbi_aa64_vae1is_write
},
7534 { .name
= "TLBI_VALE1OS", .state
= ARM_CP_STATE_AA64
,
7535 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 5,
7536 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7537 .fgt
= FGT_TLBIVALE1OS
,
7538 .writefn
= tlbi_aa64_vae1is_write
},
7539 { .name
= "TLBI_VAALE1OS", .state
= ARM_CP_STATE_AA64
,
7540 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 7,
7541 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7542 .fgt
= FGT_TLBIVAALE1OS
,
7543 .writefn
= tlbi_aa64_vae1is_write
},
7544 { .name
= "TLBI_ALLE2OS", .state
= ARM_CP_STATE_AA64
,
7545 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 0,
7546 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7547 .writefn
= tlbi_aa64_alle2is_write
},
7548 { .name
= "TLBI_VAE2OS", .state
= ARM_CP_STATE_AA64
,
7549 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 1,
7550 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7551 .writefn
= tlbi_aa64_vae2is_write
},
7552 { .name
= "TLBI_ALLE1OS", .state
= ARM_CP_STATE_AA64
,
7553 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 4,
7554 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7555 .writefn
= tlbi_aa64_alle1is_write
},
7556 { .name
= "TLBI_VALE2OS", .state
= ARM_CP_STATE_AA64
,
7557 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 5,
7558 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7559 .writefn
= tlbi_aa64_vae2is_write
},
7560 { .name
= "TLBI_VMALLS12E1OS", .state
= ARM_CP_STATE_AA64
,
7561 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 6,
7562 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7563 .writefn
= tlbi_aa64_alle1is_write
},
7564 { .name
= "TLBI_IPAS2E1OS", .state
= ARM_CP_STATE_AA64
,
7565 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 0,
7566 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7567 { .name
= "TLBI_RIPAS2E1OS", .state
= ARM_CP_STATE_AA64
,
7568 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 3,
7569 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7570 { .name
= "TLBI_IPAS2LE1OS", .state
= ARM_CP_STATE_AA64
,
7571 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 4,
7572 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7573 { .name
= "TLBI_RIPAS2LE1OS", .state
= ARM_CP_STATE_AA64
,
7574 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 7,
7575 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7576 { .name
= "TLBI_ALLE3OS", .state
= ARM_CP_STATE_AA64
,
7577 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 0,
7578 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7579 .writefn
= tlbi_aa64_alle3is_write
},
7580 { .name
= "TLBI_VAE3OS", .state
= ARM_CP_STATE_AA64
,
7581 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 1,
7582 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7583 .writefn
= tlbi_aa64_vae3is_write
},
7584 { .name
= "TLBI_VALE3OS", .state
= ARM_CP_STATE_AA64
,
7585 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 5,
7586 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7587 .writefn
= tlbi_aa64_vae3is_write
},
7590 static uint64_t rndr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7595 /* Success sets NZCV = 0000. */
7596 env
->NF
= env
->CF
= env
->VF
= 0, env
->ZF
= 1;
7598 if (qemu_guest_getrandom(&ret
, sizeof(ret
), &err
) < 0) {
7600 * ??? Failed, for unknown reasons in the crypto subsystem.
7601 * The best we can do is log the reason and return the
7602 * timed-out indication to the guest. There is no reason
7603 * we know to expect this failure to be transitory, so the
7604 * guest may well hang retrying the operation.
7606 qemu_log_mask(LOG_UNIMP
, "%s: Crypto failure: %s",
7607 ri
->name
, error_get_pretty(err
));
7610 env
->ZF
= 0; /* NZCF = 0100 */
7616 /* We do not support re-seeding, so the two registers operate the same. */
7617 static const ARMCPRegInfo rndr_reginfo
[] = {
7618 { .name
= "RNDR", .state
= ARM_CP_STATE_AA64
,
7619 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
7620 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 0,
7621 .access
= PL0_R
, .readfn
= rndr_readfn
},
7622 { .name
= "RNDRRS", .state
= ARM_CP_STATE_AA64
,
7623 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
7624 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 1,
7625 .access
= PL0_R
, .readfn
= rndr_readfn
},
7628 static void dccvap_writefn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
,
7631 ARMCPU
*cpu
= env_archcpu(env
);
7632 /* CTR_EL0 System register -> DminLine, bits [19:16] */
7633 uint64_t dline_size
= 4 << ((cpu
->ctr
>> 16) & 0xF);
7634 uint64_t vaddr_in
= (uint64_t) value
;
7635 uint64_t vaddr
= vaddr_in
& ~(dline_size
- 1);
7637 int mem_idx
= cpu_mmu_index(env
, false);
7639 /* This won't be crossing page boundaries */
7640 haddr
= probe_read(env
, vaddr
, dline_size
, mem_idx
, GETPC());
7642 #ifndef CONFIG_USER_ONLY
7647 /* RCU lock is already being held */
7648 mr
= memory_region_from_host(haddr
, &offset
);
7651 memory_region_writeback(mr
, offset
, dline_size
);
7653 #endif /*CONFIG_USER_ONLY*/
7657 static const ARMCPRegInfo dcpop_reg
[] = {
7658 { .name
= "DC_CVAP", .state
= ARM_CP_STATE_AA64
,
7659 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 1,
7660 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
,
7662 .accessfn
= aa64_cacheop_poc_access
, .writefn
= dccvap_writefn
},
7665 static const ARMCPRegInfo dcpodp_reg
[] = {
7666 { .name
= "DC_CVADP", .state
= ARM_CP_STATE_AA64
,
7667 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 1,
7668 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
,
7670 .accessfn
= aa64_cacheop_poc_access
, .writefn
= dccvap_writefn
},
7673 static CPAccessResult
access_aa64_tid5(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7676 if ((arm_current_el(env
) < 2) && (arm_hcr_el2_eff(env
) & HCR_TID5
)) {
7677 return CP_ACCESS_TRAP_EL2
;
7680 return CP_ACCESS_OK
;
7683 static CPAccessResult
access_mte(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7686 int el
= arm_current_el(env
);
7688 if (el
< 2 && arm_is_el2_enabled(env
)) {
7689 uint64_t hcr
= arm_hcr_el2_eff(env
);
7690 if (!(hcr
& HCR_ATA
) && (!(hcr
& HCR_E2H
) || !(hcr
& HCR_TGE
))) {
7691 return CP_ACCESS_TRAP_EL2
;
7695 arm_feature(env
, ARM_FEATURE_EL3
) &&
7696 !(env
->cp15
.scr_el3
& SCR_ATA
)) {
7697 return CP_ACCESS_TRAP_EL3
;
7699 return CP_ACCESS_OK
;
7702 static uint64_t tco_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7704 return env
->pstate
& PSTATE_TCO
;
7707 static void tco_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
7709 env
->pstate
= (env
->pstate
& ~PSTATE_TCO
) | (val
& PSTATE_TCO
);
7712 static const ARMCPRegInfo mte_reginfo
[] = {
7713 { .name
= "TFSRE0_EL1", .state
= ARM_CP_STATE_AA64
,
7714 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 6, .opc2
= 1,
7715 .access
= PL1_RW
, .accessfn
= access_mte
,
7716 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[0]) },
7717 { .name
= "TFSR_EL1", .state
= ARM_CP_STATE_AA64
,
7718 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 6, .opc2
= 0,
7719 .access
= PL1_RW
, .accessfn
= access_mte
,
7720 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[1]) },
7721 { .name
= "TFSR_EL2", .state
= ARM_CP_STATE_AA64
,
7722 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 6, .opc2
= 0,
7723 .access
= PL2_RW
, .accessfn
= access_mte
,
7724 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[2]) },
7725 { .name
= "TFSR_EL3", .state
= ARM_CP_STATE_AA64
,
7726 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 6, .opc2
= 0,
7728 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[3]) },
7729 { .name
= "RGSR_EL1", .state
= ARM_CP_STATE_AA64
,
7730 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 5,
7731 .access
= PL1_RW
, .accessfn
= access_mte
,
7732 .fieldoffset
= offsetof(CPUARMState
, cp15
.rgsr_el1
) },
7733 { .name
= "GCR_EL1", .state
= ARM_CP_STATE_AA64
,
7734 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 6,
7735 .access
= PL1_RW
, .accessfn
= access_mte
,
7736 .fieldoffset
= offsetof(CPUARMState
, cp15
.gcr_el1
) },
7737 { .name
= "TCO", .state
= ARM_CP_STATE_AA64
,
7738 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 7,
7739 .type
= ARM_CP_NO_RAW
,
7740 .access
= PL0_RW
, .readfn
= tco_read
, .writefn
= tco_write
},
7741 { .name
= "DC_IGVAC", .state
= ARM_CP_STATE_AA64
,
7742 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 3,
7743 .type
= ARM_CP_NOP
, .access
= PL1_W
,
7745 .accessfn
= aa64_cacheop_poc_access
},
7746 { .name
= "DC_IGSW", .state
= ARM_CP_STATE_AA64
,
7747 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 4,
7749 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7750 { .name
= "DC_IGDVAC", .state
= ARM_CP_STATE_AA64
,
7751 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 5,
7752 .type
= ARM_CP_NOP
, .access
= PL1_W
,
7754 .accessfn
= aa64_cacheop_poc_access
},
7755 { .name
= "DC_IGDSW", .state
= ARM_CP_STATE_AA64
,
7756 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 6,
7758 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7759 { .name
= "DC_CGSW", .state
= ARM_CP_STATE_AA64
,
7760 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 4,
7762 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7763 { .name
= "DC_CGDSW", .state
= ARM_CP_STATE_AA64
,
7764 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 6,
7766 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7767 { .name
= "DC_CIGSW", .state
= ARM_CP_STATE_AA64
,
7768 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 4,
7770 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7771 { .name
= "DC_CIGDSW", .state
= ARM_CP_STATE_AA64
,
7772 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 6,
7774 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7777 static const ARMCPRegInfo mte_tco_ro_reginfo
[] = {
7778 { .name
= "TCO", .state
= ARM_CP_STATE_AA64
,
7779 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 7,
7780 .type
= ARM_CP_CONST
, .access
= PL0_RW
, },
7783 static const ARMCPRegInfo mte_el0_cacheop_reginfo
[] = {
7784 { .name
= "DC_CGVAC", .state
= ARM_CP_STATE_AA64
,
7785 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 3,
7786 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7788 .accessfn
= aa64_cacheop_poc_access
},
7789 { .name
= "DC_CGDVAC", .state
= ARM_CP_STATE_AA64
,
7790 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 5,
7791 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7793 .accessfn
= aa64_cacheop_poc_access
},
7794 { .name
= "DC_CGVAP", .state
= ARM_CP_STATE_AA64
,
7795 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 3,
7796 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7798 .accessfn
= aa64_cacheop_poc_access
},
7799 { .name
= "DC_CGDVAP", .state
= ARM_CP_STATE_AA64
,
7800 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 5,
7801 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7803 .accessfn
= aa64_cacheop_poc_access
},
7804 { .name
= "DC_CGVADP", .state
= ARM_CP_STATE_AA64
,
7805 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 3,
7806 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7808 .accessfn
= aa64_cacheop_poc_access
},
7809 { .name
= "DC_CGDVADP", .state
= ARM_CP_STATE_AA64
,
7810 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 5,
7811 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7813 .accessfn
= aa64_cacheop_poc_access
},
7814 { .name
= "DC_CIGVAC", .state
= ARM_CP_STATE_AA64
,
7815 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 3,
7816 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7818 .accessfn
= aa64_cacheop_poc_access
},
7819 { .name
= "DC_CIGDVAC", .state
= ARM_CP_STATE_AA64
,
7820 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 5,
7821 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7823 .accessfn
= aa64_cacheop_poc_access
},
7824 { .name
= "DC_GVA", .state
= ARM_CP_STATE_AA64
,
7825 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 3,
7826 .access
= PL0_W
, .type
= ARM_CP_DC_GVA
,
7827 #ifndef CONFIG_USER_ONLY
7828 /* Avoid overhead of an access check that always passes in user-mode */
7829 .accessfn
= aa64_zva_access
,
7833 { .name
= "DC_GZVA", .state
= ARM_CP_STATE_AA64
,
7834 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 4,
7835 .access
= PL0_W
, .type
= ARM_CP_DC_GZVA
,
7836 #ifndef CONFIG_USER_ONLY
7837 /* Avoid overhead of an access check that always passes in user-mode */
7838 .accessfn
= aa64_zva_access
,
7844 static CPAccessResult
access_scxtnum(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7847 uint64_t hcr
= arm_hcr_el2_eff(env
);
7848 int el
= arm_current_el(env
);
7850 if (el
== 0 && !((hcr
& HCR_E2H
) && (hcr
& HCR_TGE
))) {
7851 if (env
->cp15
.sctlr_el
[1] & SCTLR_TSCXT
) {
7852 if (hcr
& HCR_TGE
) {
7853 return CP_ACCESS_TRAP_EL2
;
7855 return CP_ACCESS_TRAP
;
7857 } else if (el
< 2 && (env
->cp15
.sctlr_el
[2] & SCTLR_TSCXT
)) {
7858 return CP_ACCESS_TRAP_EL2
;
7860 if (el
< 2 && arm_is_el2_enabled(env
) && !(hcr
& HCR_ENSCXT
)) {
7861 return CP_ACCESS_TRAP_EL2
;
7864 && arm_feature(env
, ARM_FEATURE_EL3
)
7865 && !(env
->cp15
.scr_el3
& SCR_ENSCXT
)) {
7866 return CP_ACCESS_TRAP_EL3
;
7868 return CP_ACCESS_OK
;
7871 static const ARMCPRegInfo scxtnum_reginfo
[] = {
7872 { .name
= "SCXTNUM_EL0", .state
= ARM_CP_STATE_AA64
,
7873 .opc0
= 3, .opc1
= 3, .crn
= 13, .crm
= 0, .opc2
= 7,
7874 .access
= PL0_RW
, .accessfn
= access_scxtnum
,
7875 .fgt
= FGT_SCXTNUM_EL0
,
7876 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[0]) },
7877 { .name
= "SCXTNUM_EL1", .state
= ARM_CP_STATE_AA64
,
7878 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 7,
7879 .access
= PL1_RW
, .accessfn
= access_scxtnum
,
7880 .fgt
= FGT_SCXTNUM_EL1
,
7881 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[1]) },
7882 { .name
= "SCXTNUM_EL2", .state
= ARM_CP_STATE_AA64
,
7883 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 7,
7884 .access
= PL2_RW
, .accessfn
= access_scxtnum
,
7885 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[2]) },
7886 { .name
= "SCXTNUM_EL3", .state
= ARM_CP_STATE_AA64
,
7887 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 7,
7889 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[3]) },
7892 static CPAccessResult
access_fgt(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7895 if (arm_current_el(env
) == 2 &&
7896 arm_feature(env
, ARM_FEATURE_EL3
) && !(env
->cp15
.scr_el3
& SCR_FGTEN
)) {
7897 return CP_ACCESS_TRAP_EL3
;
7899 return CP_ACCESS_OK
;
7902 static const ARMCPRegInfo fgt_reginfo
[] = {
7903 { .name
= "HFGRTR_EL2", .state
= ARM_CP_STATE_AA64
,
7904 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
7905 .access
= PL2_RW
, .accessfn
= access_fgt
,
7906 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_read
[FGTREG_HFGRTR
]) },
7907 { .name
= "HFGWTR_EL2", .state
= ARM_CP_STATE_AA64
,
7908 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 5,
7909 .access
= PL2_RW
, .accessfn
= access_fgt
,
7910 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_write
[FGTREG_HFGWTR
]) },
7911 { .name
= "HDFGRTR_EL2", .state
= ARM_CP_STATE_AA64
,
7912 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 1, .opc2
= 4,
7913 .access
= PL2_RW
, .accessfn
= access_fgt
,
7914 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_read
[FGTREG_HDFGRTR
]) },
7915 { .name
= "HDFGWTR_EL2", .state
= ARM_CP_STATE_AA64
,
7916 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 1, .opc2
= 5,
7917 .access
= PL2_RW
, .accessfn
= access_fgt
,
7918 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_write
[FGTREG_HDFGWTR
]) },
7919 { .name
= "HFGITR_EL2", .state
= ARM_CP_STATE_AA64
,
7920 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 6,
7921 .access
= PL2_RW
, .accessfn
= access_fgt
,
7922 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_exec
[FGTREG_HFGITR
]) },
7924 #endif /* TARGET_AARCH64 */
7926 static CPAccessResult
access_predinv(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7929 int el
= arm_current_el(env
);
7932 uint64_t sctlr
= arm_sctlr(env
, el
);
7933 if (!(sctlr
& SCTLR_EnRCTX
)) {
7934 return CP_ACCESS_TRAP
;
7936 } else if (el
== 1) {
7937 uint64_t hcr
= arm_hcr_el2_eff(env
);
7939 return CP_ACCESS_TRAP_EL2
;
7942 return CP_ACCESS_OK
;
7945 static const ARMCPRegInfo predinv_reginfo
[] = {
7946 { .name
= "CFP_RCTX", .state
= ARM_CP_STATE_AA64
,
7947 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 4,
7949 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7950 { .name
= "DVP_RCTX", .state
= ARM_CP_STATE_AA64
,
7951 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 5,
7953 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7954 { .name
= "CPP_RCTX", .state
= ARM_CP_STATE_AA64
,
7955 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 7,
7957 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7959 * Note the AArch32 opcodes have a different OPC1.
7961 { .name
= "CFPRCTX", .state
= ARM_CP_STATE_AA32
,
7962 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 4,
7964 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7965 { .name
= "DVPRCTX", .state
= ARM_CP_STATE_AA32
,
7966 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 5,
7968 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7969 { .name
= "CPPRCTX", .state
= ARM_CP_STATE_AA32
,
7970 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 7,
7972 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7975 static uint64_t ccsidr2_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7977 /* Read the high 32 bits of the current CCSIDR */
7978 return extract64(ccsidr_read(env
, ri
), 32, 32);
7981 static const ARMCPRegInfo ccsidr2_reginfo
[] = {
7982 { .name
= "CCSIDR2", .state
= ARM_CP_STATE_BOTH
,
7983 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 2,
7985 .accessfn
= access_tid4
,
7986 .readfn
= ccsidr2_read
, .type
= ARM_CP_NO_RAW
},
7989 static CPAccessResult
access_aa64_tid3(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7992 if ((arm_current_el(env
) < 2) && (arm_hcr_el2_eff(env
) & HCR_TID3
)) {
7993 return CP_ACCESS_TRAP_EL2
;
7996 return CP_ACCESS_OK
;
7999 static CPAccessResult
access_aa32_tid3(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8002 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8003 return access_aa64_tid3(env
, ri
, isread
);
8006 return CP_ACCESS_OK
;
8009 static CPAccessResult
access_jazelle(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8012 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID0
)) {
8013 return CP_ACCESS_TRAP_EL2
;
8016 return CP_ACCESS_OK
;
8019 static CPAccessResult
access_joscr_jmcr(CPUARMState
*env
,
8020 const ARMCPRegInfo
*ri
, bool isread
)
8023 * HSTR.TJDBX traps JOSCR and JMCR accesses, but it exists only
8024 * in v7A, not in v8A.
8026 if (!arm_feature(env
, ARM_FEATURE_V8
) &&
8027 arm_current_el(env
) < 2 && !arm_is_secure_below_el3(env
) &&
8028 (env
->cp15
.hstr_el2
& HSTR_TJDBX
)) {
8029 return CP_ACCESS_TRAP_EL2
;
8031 return CP_ACCESS_OK
;
8034 static const ARMCPRegInfo jazelle_regs
[] = {
8036 .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 7, .opc2
= 0,
8037 .access
= PL1_R
, .accessfn
= access_jazelle
,
8038 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8040 .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 7, .opc2
= 0,
8041 .accessfn
= access_joscr_jmcr
,
8042 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8044 .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 7, .opc2
= 0,
8045 .accessfn
= access_joscr_jmcr
,
8046 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8049 static const ARMCPRegInfo contextidr_el2
= {
8050 .name
= "CONTEXTIDR_EL2", .state
= ARM_CP_STATE_AA64
,
8051 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 1,
8053 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[2])
8056 static const ARMCPRegInfo vhe_reginfo
[] = {
8057 { .name
= "TTBR1_EL2", .state
= ARM_CP_STATE_AA64
,
8058 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 1,
8059 .access
= PL2_RW
, .writefn
= vmsa_tcr_ttbr_el2_write
,
8060 .raw_writefn
= raw_write
,
8061 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr1_el
[2]) },
8062 #ifndef CONFIG_USER_ONLY
8063 { .name
= "CNTHV_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
8064 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 2,
8066 offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYPVIRT
].cval
),
8067 .type
= ARM_CP_IO
, .access
= PL2_RW
,
8068 .writefn
= gt_hv_cval_write
, .raw_writefn
= raw_write
},
8069 { .name
= "CNTHV_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
8070 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 0,
8071 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
8072 .resetfn
= gt_hv_timer_reset
,
8073 .readfn
= gt_hv_tval_read
, .writefn
= gt_hv_tval_write
},
8074 { .name
= "CNTHV_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
8076 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 1,
8078 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYPVIRT
].ctl
),
8079 .writefn
= gt_hv_ctl_write
, .raw_writefn
= raw_write
},
8080 { .name
= "CNTP_CTL_EL02", .state
= ARM_CP_STATE_AA64
,
8081 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 1,
8082 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
8083 .access
= PL2_RW
, .accessfn
= e2h_access
,
8084 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
8085 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
},
8086 { .name
= "CNTV_CTL_EL02", .state
= ARM_CP_STATE_AA64
,
8087 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 1,
8088 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
8089 .access
= PL2_RW
, .accessfn
= e2h_access
,
8090 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
8091 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
},
8092 { .name
= "CNTP_TVAL_EL02", .state
= ARM_CP_STATE_AA64
,
8093 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 0,
8094 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
| ARM_CP_ALIAS
,
8095 .access
= PL2_RW
, .accessfn
= e2h_access
,
8096 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
},
8097 { .name
= "CNTV_TVAL_EL02", .state
= ARM_CP_STATE_AA64
,
8098 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 0,
8099 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
| ARM_CP_ALIAS
,
8100 .access
= PL2_RW
, .accessfn
= e2h_access
,
8101 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
},
8102 { .name
= "CNTP_CVAL_EL02", .state
= ARM_CP_STATE_AA64
,
8103 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 2,
8104 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
8105 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
8106 .access
= PL2_RW
, .accessfn
= e2h_access
,
8107 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
},
8108 { .name
= "CNTV_CVAL_EL02", .state
= ARM_CP_STATE_AA64
,
8109 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 2,
8110 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
8111 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
8112 .access
= PL2_RW
, .accessfn
= e2h_access
,
8113 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
},
8117 #ifndef CONFIG_USER_ONLY
8118 static const ARMCPRegInfo ats1e1_reginfo
[] = {
8119 { .name
= "AT_S1E1RP", .state
= ARM_CP_STATE_AA64
,
8120 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 0,
8121 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
8122 .fgt
= FGT_ATS1E1RP
,
8123 .accessfn
= at_e012_access
, .writefn
= ats_write64
},
8124 { .name
= "AT_S1E1WP", .state
= ARM_CP_STATE_AA64
,
8125 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 1,
8126 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
8127 .fgt
= FGT_ATS1E1WP
,
8128 .accessfn
= at_e012_access
, .writefn
= ats_write64
},
8131 static const ARMCPRegInfo ats1cp_reginfo
[] = {
8132 { .name
= "ATS1CPRP",
8133 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 0,
8134 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
8135 .writefn
= ats_write
},
8136 { .name
= "ATS1CPWP",
8137 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 1,
8138 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
8139 .writefn
= ats_write
},
8144 * ACTLR2 and HACTLR2 map to ACTLR_EL1[63:32] and
8145 * ACTLR_EL2[63:32]. They exist only if the ID_MMFR4.AC2 field
8146 * is non-zero, which is never for ARMv7, optionally in ARMv8
8147 * and mandatorily for ARMv8.2 and up.
8148 * ACTLR2 is banked for S and NS if EL3 is AArch32. Since QEMU's
8149 * implementation is RAZ/WI we can ignore this detail, as we
8152 static const ARMCPRegInfo actlr2_hactlr2_reginfo
[] = {
8153 { .name
= "ACTLR2", .state
= ARM_CP_STATE_AA32
,
8154 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 3,
8155 .access
= PL1_RW
, .accessfn
= access_tacr
,
8156 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8157 { .name
= "HACTLR2", .state
= ARM_CP_STATE_AA32
,
8158 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 3,
8159 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
8163 void register_cp_regs_for_features(ARMCPU
*cpu
)
8165 /* Register all the coprocessor registers based on feature bits */
8166 CPUARMState
*env
= &cpu
->env
;
8167 if (arm_feature(env
, ARM_FEATURE_M
)) {
8168 /* M profile has no coprocessor registers */
8172 define_arm_cp_regs(cpu
, cp_reginfo
);
8173 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
8175 * Must go early as it is full of wildcards that may be
8176 * overridden by later definitions.
8178 define_arm_cp_regs(cpu
, not_v8_cp_reginfo
);
8181 if (arm_feature(env
, ARM_FEATURE_V6
)) {
8182 /* The ID registers all have impdef reset values */
8183 ARMCPRegInfo v6_idregs
[] = {
8184 { .name
= "ID_PFR0", .state
= ARM_CP_STATE_BOTH
,
8185 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
8186 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8187 .accessfn
= access_aa32_tid3
,
8188 .resetvalue
= cpu
->isar
.id_pfr0
},
8190 * ID_PFR1 is not a plain ARM_CP_CONST because we don't know
8191 * the value of the GIC field until after we define these regs.
8193 { .name
= "ID_PFR1", .state
= ARM_CP_STATE_BOTH
,
8194 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 1,
8195 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
,
8196 .accessfn
= access_aa32_tid3
,
8197 #ifdef CONFIG_USER_ONLY
8198 .type
= ARM_CP_CONST
,
8199 .resetvalue
= cpu
->isar
.id_pfr1
,
8201 .type
= ARM_CP_NO_RAW
,
8202 .accessfn
= access_aa32_tid3
,
8203 .readfn
= id_pfr1_read
,
8204 .writefn
= arm_cp_write_ignore
8207 { .name
= "ID_DFR0", .state
= ARM_CP_STATE_BOTH
,
8208 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 2,
8209 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8210 .accessfn
= access_aa32_tid3
,
8211 .resetvalue
= cpu
->isar
.id_dfr0
},
8212 { .name
= "ID_AFR0", .state
= ARM_CP_STATE_BOTH
,
8213 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 3,
8214 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8215 .accessfn
= access_aa32_tid3
,
8216 .resetvalue
= cpu
->id_afr0
},
8217 { .name
= "ID_MMFR0", .state
= ARM_CP_STATE_BOTH
,
8218 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 4,
8219 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8220 .accessfn
= access_aa32_tid3
,
8221 .resetvalue
= cpu
->isar
.id_mmfr0
},
8222 { .name
= "ID_MMFR1", .state
= ARM_CP_STATE_BOTH
,
8223 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 5,
8224 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8225 .accessfn
= access_aa32_tid3
,
8226 .resetvalue
= cpu
->isar
.id_mmfr1
},
8227 { .name
= "ID_MMFR2", .state
= ARM_CP_STATE_BOTH
,
8228 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 6,
8229 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8230 .accessfn
= access_aa32_tid3
,
8231 .resetvalue
= cpu
->isar
.id_mmfr2
},
8232 { .name
= "ID_MMFR3", .state
= ARM_CP_STATE_BOTH
,
8233 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 7,
8234 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8235 .accessfn
= access_aa32_tid3
,
8236 .resetvalue
= cpu
->isar
.id_mmfr3
},
8237 { .name
= "ID_ISAR0", .state
= ARM_CP_STATE_BOTH
,
8238 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
8239 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8240 .accessfn
= access_aa32_tid3
,
8241 .resetvalue
= cpu
->isar
.id_isar0
},
8242 { .name
= "ID_ISAR1", .state
= ARM_CP_STATE_BOTH
,
8243 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 1,
8244 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8245 .accessfn
= access_aa32_tid3
,
8246 .resetvalue
= cpu
->isar
.id_isar1
},
8247 { .name
= "ID_ISAR2", .state
= ARM_CP_STATE_BOTH
,
8248 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
8249 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8250 .accessfn
= access_aa32_tid3
,
8251 .resetvalue
= cpu
->isar
.id_isar2
},
8252 { .name
= "ID_ISAR3", .state
= ARM_CP_STATE_BOTH
,
8253 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 3,
8254 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8255 .accessfn
= access_aa32_tid3
,
8256 .resetvalue
= cpu
->isar
.id_isar3
},
8257 { .name
= "ID_ISAR4", .state
= ARM_CP_STATE_BOTH
,
8258 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 4,
8259 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8260 .accessfn
= access_aa32_tid3
,
8261 .resetvalue
= cpu
->isar
.id_isar4
},
8262 { .name
= "ID_ISAR5", .state
= ARM_CP_STATE_BOTH
,
8263 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 5,
8264 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8265 .accessfn
= access_aa32_tid3
,
8266 .resetvalue
= cpu
->isar
.id_isar5
},
8267 { .name
= "ID_MMFR4", .state
= ARM_CP_STATE_BOTH
,
8268 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 6,
8269 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8270 .accessfn
= access_aa32_tid3
,
8271 .resetvalue
= cpu
->isar
.id_mmfr4
},
8272 { .name
= "ID_ISAR6", .state
= ARM_CP_STATE_BOTH
,
8273 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 7,
8274 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8275 .accessfn
= access_aa32_tid3
,
8276 .resetvalue
= cpu
->isar
.id_isar6
},
8278 define_arm_cp_regs(cpu
, v6_idregs
);
8279 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
8281 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
8283 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
8284 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
8286 if (arm_feature(env
, ARM_FEATURE_V7MP
) &&
8287 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
8288 define_arm_cp_regs(cpu
, v7mp_cp_reginfo
);
8290 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
8291 define_arm_cp_regs(cpu
, pmovsset_cp_reginfo
);
8293 if (arm_feature(env
, ARM_FEATURE_V7
)) {
8294 ARMCPRegInfo clidr
= {
8295 .name
= "CLIDR", .state
= ARM_CP_STATE_BOTH
,
8296 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
8297 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8298 .accessfn
= access_tid4
,
8299 .fgt
= FGT_CLIDR_EL1
,
8300 .resetvalue
= cpu
->clidr
8302 define_one_arm_cp_reg(cpu
, &clidr
);
8303 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
8304 define_debug_regs(cpu
);
8305 define_pmu_regs(cpu
);
8307 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
8309 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8311 * v8 ID registers, which all have impdef reset values.
8312 * Note that within the ID register ranges the unused slots
8313 * must all RAZ, not UNDEF; future architecture versions may
8314 * define new registers here.
8315 * ID registers which are AArch64 views of the AArch32 ID registers
8316 * which already existed in v6 and v7 are handled elsewhere,
8320 ARMCPRegInfo v8_idregs
[] = {
8322 * ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST in system
8323 * emulation because we don't know the right value for the
8324 * GIC field until after we define these regs.
8326 { .name
= "ID_AA64PFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8327 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 0,
8329 #ifdef CONFIG_USER_ONLY
8330 .type
= ARM_CP_CONST
,
8331 .resetvalue
= cpu
->isar
.id_aa64pfr0
8333 .type
= ARM_CP_NO_RAW
,
8334 .accessfn
= access_aa64_tid3
,
8335 .readfn
= id_aa64pfr0_read
,
8336 .writefn
= arm_cp_write_ignore
8339 { .name
= "ID_AA64PFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8340 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 1,
8341 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8342 .accessfn
= access_aa64_tid3
,
8343 .resetvalue
= cpu
->isar
.id_aa64pfr1
},
8344 { .name
= "ID_AA64PFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8345 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 2,
8346 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8347 .accessfn
= access_aa64_tid3
,
8349 { .name
= "ID_AA64PFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8350 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 3,
8351 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8352 .accessfn
= access_aa64_tid3
,
8354 { .name
= "ID_AA64ZFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8355 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 4,
8356 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8357 .accessfn
= access_aa64_tid3
,
8358 .resetvalue
= cpu
->isar
.id_aa64zfr0
},
8359 { .name
= "ID_AA64SMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8360 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 5,
8361 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8362 .accessfn
= access_aa64_tid3
,
8363 .resetvalue
= cpu
->isar
.id_aa64smfr0
},
8364 { .name
= "ID_AA64PFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8365 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 6,
8366 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8367 .accessfn
= access_aa64_tid3
,
8369 { .name
= "ID_AA64PFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8370 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 7,
8371 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8372 .accessfn
= access_aa64_tid3
,
8374 { .name
= "ID_AA64DFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8375 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 0,
8376 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8377 .accessfn
= access_aa64_tid3
,
8378 .resetvalue
= cpu
->isar
.id_aa64dfr0
},
8379 { .name
= "ID_AA64DFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8380 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 1,
8381 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8382 .accessfn
= access_aa64_tid3
,
8383 .resetvalue
= cpu
->isar
.id_aa64dfr1
},
8384 { .name
= "ID_AA64DFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8385 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 2,
8386 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8387 .accessfn
= access_aa64_tid3
,
8389 { .name
= "ID_AA64DFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8390 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 3,
8391 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8392 .accessfn
= access_aa64_tid3
,
8394 { .name
= "ID_AA64AFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8395 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 4,
8396 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8397 .accessfn
= access_aa64_tid3
,
8398 .resetvalue
= cpu
->id_aa64afr0
},
8399 { .name
= "ID_AA64AFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8400 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 5,
8401 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8402 .accessfn
= access_aa64_tid3
,
8403 .resetvalue
= cpu
->id_aa64afr1
},
8404 { .name
= "ID_AA64AFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8405 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 6,
8406 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8407 .accessfn
= access_aa64_tid3
,
8409 { .name
= "ID_AA64AFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8410 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 7,
8411 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8412 .accessfn
= access_aa64_tid3
,
8414 { .name
= "ID_AA64ISAR0_EL1", .state
= ARM_CP_STATE_AA64
,
8415 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 0,
8416 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8417 .accessfn
= access_aa64_tid3
,
8418 .resetvalue
= cpu
->isar
.id_aa64isar0
},
8419 { .name
= "ID_AA64ISAR1_EL1", .state
= ARM_CP_STATE_AA64
,
8420 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 1,
8421 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8422 .accessfn
= access_aa64_tid3
,
8423 .resetvalue
= cpu
->isar
.id_aa64isar1
},
8424 { .name
= "ID_AA64ISAR2_EL1", .state
= ARM_CP_STATE_AA64
,
8425 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 2,
8426 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8427 .accessfn
= access_aa64_tid3
,
8428 .resetvalue
= cpu
->isar
.id_aa64isar2
},
8429 { .name
= "ID_AA64ISAR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8430 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 3,
8431 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8432 .accessfn
= access_aa64_tid3
,
8434 { .name
= "ID_AA64ISAR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8435 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 4,
8436 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8437 .accessfn
= access_aa64_tid3
,
8439 { .name
= "ID_AA64ISAR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8440 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 5,
8441 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8442 .accessfn
= access_aa64_tid3
,
8444 { .name
= "ID_AA64ISAR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8445 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 6,
8446 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8447 .accessfn
= access_aa64_tid3
,
8449 { .name
= "ID_AA64ISAR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8450 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 7,
8451 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8452 .accessfn
= access_aa64_tid3
,
8454 { .name
= "ID_AA64MMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8455 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
8456 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8457 .accessfn
= access_aa64_tid3
,
8458 .resetvalue
= cpu
->isar
.id_aa64mmfr0
},
8459 { .name
= "ID_AA64MMFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8460 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 1,
8461 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8462 .accessfn
= access_aa64_tid3
,
8463 .resetvalue
= cpu
->isar
.id_aa64mmfr1
},
8464 { .name
= "ID_AA64MMFR2_EL1", .state
= ARM_CP_STATE_AA64
,
8465 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 2,
8466 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8467 .accessfn
= access_aa64_tid3
,
8468 .resetvalue
= cpu
->isar
.id_aa64mmfr2
},
8469 { .name
= "ID_AA64MMFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8470 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 3,
8471 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8472 .accessfn
= access_aa64_tid3
,
8474 { .name
= "ID_AA64MMFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8475 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 4,
8476 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8477 .accessfn
= access_aa64_tid3
,
8479 { .name
= "ID_AA64MMFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8480 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 5,
8481 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8482 .accessfn
= access_aa64_tid3
,
8484 { .name
= "ID_AA64MMFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8485 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 6,
8486 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8487 .accessfn
= access_aa64_tid3
,
8489 { .name
= "ID_AA64MMFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8490 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 7,
8491 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8492 .accessfn
= access_aa64_tid3
,
8494 { .name
= "MVFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8495 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
8496 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8497 .accessfn
= access_aa64_tid3
,
8498 .resetvalue
= cpu
->isar
.mvfr0
},
8499 { .name
= "MVFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8500 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
8501 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8502 .accessfn
= access_aa64_tid3
,
8503 .resetvalue
= cpu
->isar
.mvfr1
},
8504 { .name
= "MVFR2_EL1", .state
= ARM_CP_STATE_AA64
,
8505 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
8506 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8507 .accessfn
= access_aa64_tid3
,
8508 .resetvalue
= cpu
->isar
.mvfr2
},
8510 * "0, c0, c3, {0,1,2}" are the encodings corresponding to
8511 * AArch64 MVFR[012]_EL1. Define the STATE_AA32 encoding
8512 * as RAZ, since it is in the "reserved for future ID
8513 * registers, RAZ" part of the AArch32 encoding space.
8515 { .name
= "RES_0_C0_C3_0", .state
= ARM_CP_STATE_AA32
,
8516 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
8517 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8518 .accessfn
= access_aa64_tid3
,
8520 { .name
= "RES_0_C0_C3_1", .state
= ARM_CP_STATE_AA32
,
8521 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
8522 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8523 .accessfn
= access_aa64_tid3
,
8525 { .name
= "RES_0_C0_C3_2", .state
= ARM_CP_STATE_AA32
,
8526 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
8527 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8528 .accessfn
= access_aa64_tid3
,
8531 * Other encodings in "0, c0, c3, ..." are STATE_BOTH because
8532 * they're also RAZ for AArch64, and in v8 are gradually
8533 * being filled with AArch64-view-of-AArch32-ID-register
8534 * for new ID registers.
8536 { .name
= "RES_0_C0_C3_3", .state
= ARM_CP_STATE_BOTH
,
8537 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 3,
8538 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8539 .accessfn
= access_aa64_tid3
,
8541 { .name
= "ID_PFR2", .state
= ARM_CP_STATE_BOTH
,
8542 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 4,
8543 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8544 .accessfn
= access_aa64_tid3
,
8545 .resetvalue
= cpu
->isar
.id_pfr2
},
8546 { .name
= "ID_DFR1", .state
= ARM_CP_STATE_BOTH
,
8547 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 5,
8548 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8549 .accessfn
= access_aa64_tid3
,
8550 .resetvalue
= cpu
->isar
.id_dfr1
},
8551 { .name
= "ID_MMFR5", .state
= ARM_CP_STATE_BOTH
,
8552 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 6,
8553 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8554 .accessfn
= access_aa64_tid3
,
8555 .resetvalue
= cpu
->isar
.id_mmfr5
},
8556 { .name
= "RES_0_C0_C3_7", .state
= ARM_CP_STATE_BOTH
,
8557 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 7,
8558 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8559 .accessfn
= access_aa64_tid3
,
8561 { .name
= "PMCEID0", .state
= ARM_CP_STATE_AA32
,
8562 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 6,
8563 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8564 .fgt
= FGT_PMCEIDN_EL0
,
8565 .resetvalue
= extract64(cpu
->pmceid0
, 0, 32) },
8566 { .name
= "PMCEID0_EL0", .state
= ARM_CP_STATE_AA64
,
8567 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 6,
8568 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8569 .fgt
= FGT_PMCEIDN_EL0
,
8570 .resetvalue
= cpu
->pmceid0
},
8571 { .name
= "PMCEID1", .state
= ARM_CP_STATE_AA32
,
8572 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 7,
8573 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8574 .fgt
= FGT_PMCEIDN_EL0
,
8575 .resetvalue
= extract64(cpu
->pmceid1
, 0, 32) },
8576 { .name
= "PMCEID1_EL0", .state
= ARM_CP_STATE_AA64
,
8577 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 7,
8578 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8579 .fgt
= FGT_PMCEIDN_EL0
,
8580 .resetvalue
= cpu
->pmceid1
},
8582 #ifdef CONFIG_USER_ONLY
8583 static const ARMCPRegUserSpaceInfo v8_user_idregs
[] = {
8584 { .name
= "ID_AA64PFR0_EL1",
8585 .exported_bits
= R_ID_AA64PFR0_FP_MASK
|
8586 R_ID_AA64PFR0_ADVSIMD_MASK
|
8587 R_ID_AA64PFR0_SVE_MASK
|
8588 R_ID_AA64PFR0_DIT_MASK
,
8589 .fixed_bits
= (0x1u
<< R_ID_AA64PFR0_EL0_SHIFT
) |
8590 (0x1u
<< R_ID_AA64PFR0_EL1_SHIFT
) },
8591 { .name
= "ID_AA64PFR1_EL1",
8592 .exported_bits
= R_ID_AA64PFR1_BT_MASK
|
8593 R_ID_AA64PFR1_SSBS_MASK
|
8594 R_ID_AA64PFR1_MTE_MASK
|
8595 R_ID_AA64PFR1_SME_MASK
},
8596 { .name
= "ID_AA64PFR*_EL1_RESERVED",
8598 { .name
= "ID_AA64ZFR0_EL1",
8599 .exported_bits
= R_ID_AA64ZFR0_SVEVER_MASK
|
8600 R_ID_AA64ZFR0_AES_MASK
|
8601 R_ID_AA64ZFR0_BITPERM_MASK
|
8602 R_ID_AA64ZFR0_BFLOAT16_MASK
|
8603 R_ID_AA64ZFR0_SHA3_MASK
|
8604 R_ID_AA64ZFR0_SM4_MASK
|
8605 R_ID_AA64ZFR0_I8MM_MASK
|
8606 R_ID_AA64ZFR0_F32MM_MASK
|
8607 R_ID_AA64ZFR0_F64MM_MASK
},
8608 { .name
= "ID_AA64SMFR0_EL1",
8609 .exported_bits
= R_ID_AA64SMFR0_F32F32_MASK
|
8610 R_ID_AA64SMFR0_BI32I32_MASK
|
8611 R_ID_AA64SMFR0_B16F32_MASK
|
8612 R_ID_AA64SMFR0_F16F32_MASK
|
8613 R_ID_AA64SMFR0_I8I32_MASK
|
8614 R_ID_AA64SMFR0_F16F16_MASK
|
8615 R_ID_AA64SMFR0_B16B16_MASK
|
8616 R_ID_AA64SMFR0_I16I32_MASK
|
8617 R_ID_AA64SMFR0_F64F64_MASK
|
8618 R_ID_AA64SMFR0_I16I64_MASK
|
8619 R_ID_AA64SMFR0_SMEVER_MASK
|
8620 R_ID_AA64SMFR0_FA64_MASK
},
8621 { .name
= "ID_AA64MMFR0_EL1",
8622 .exported_bits
= R_ID_AA64MMFR0_ECV_MASK
,
8623 .fixed_bits
= (0xfu
<< R_ID_AA64MMFR0_TGRAN64_SHIFT
) |
8624 (0xfu
<< R_ID_AA64MMFR0_TGRAN4_SHIFT
) },
8625 { .name
= "ID_AA64MMFR1_EL1",
8626 .exported_bits
= R_ID_AA64MMFR1_AFP_MASK
},
8627 { .name
= "ID_AA64MMFR2_EL1",
8628 .exported_bits
= R_ID_AA64MMFR2_AT_MASK
},
8629 { .name
= "ID_AA64MMFR*_EL1_RESERVED",
8631 { .name
= "ID_AA64DFR0_EL1",
8632 .fixed_bits
= (0x6u
<< R_ID_AA64DFR0_DEBUGVER_SHIFT
) },
8633 { .name
= "ID_AA64DFR1_EL1" },
8634 { .name
= "ID_AA64DFR*_EL1_RESERVED",
8636 { .name
= "ID_AA64AFR*",
8638 { .name
= "ID_AA64ISAR0_EL1",
8639 .exported_bits
= R_ID_AA64ISAR0_AES_MASK
|
8640 R_ID_AA64ISAR0_SHA1_MASK
|
8641 R_ID_AA64ISAR0_SHA2_MASK
|
8642 R_ID_AA64ISAR0_CRC32_MASK
|
8643 R_ID_AA64ISAR0_ATOMIC_MASK
|
8644 R_ID_AA64ISAR0_RDM_MASK
|
8645 R_ID_AA64ISAR0_SHA3_MASK
|
8646 R_ID_AA64ISAR0_SM3_MASK
|
8647 R_ID_AA64ISAR0_SM4_MASK
|
8648 R_ID_AA64ISAR0_DP_MASK
|
8649 R_ID_AA64ISAR0_FHM_MASK
|
8650 R_ID_AA64ISAR0_TS_MASK
|
8651 R_ID_AA64ISAR0_RNDR_MASK
},
8652 { .name
= "ID_AA64ISAR1_EL1",
8653 .exported_bits
= R_ID_AA64ISAR1_DPB_MASK
|
8654 R_ID_AA64ISAR1_APA_MASK
|
8655 R_ID_AA64ISAR1_API_MASK
|
8656 R_ID_AA64ISAR1_JSCVT_MASK
|
8657 R_ID_AA64ISAR1_FCMA_MASK
|
8658 R_ID_AA64ISAR1_LRCPC_MASK
|
8659 R_ID_AA64ISAR1_GPA_MASK
|
8660 R_ID_AA64ISAR1_GPI_MASK
|
8661 R_ID_AA64ISAR1_FRINTTS_MASK
|
8662 R_ID_AA64ISAR1_SB_MASK
|
8663 R_ID_AA64ISAR1_BF16_MASK
|
8664 R_ID_AA64ISAR1_DGH_MASK
|
8665 R_ID_AA64ISAR1_I8MM_MASK
},
8666 { .name
= "ID_AA64ISAR2_EL1",
8667 .exported_bits
= R_ID_AA64ISAR2_WFXT_MASK
|
8668 R_ID_AA64ISAR2_RPRES_MASK
|
8669 R_ID_AA64ISAR2_GPA3_MASK
|
8670 R_ID_AA64ISAR2_APA3_MASK
|
8671 R_ID_AA64ISAR2_MOPS_MASK
|
8672 R_ID_AA64ISAR2_BC_MASK
|
8673 R_ID_AA64ISAR2_RPRFM_MASK
|
8674 R_ID_AA64ISAR2_CSSC_MASK
},
8675 { .name
= "ID_AA64ISAR*_EL1_RESERVED",
8678 modify_arm_cp_regs(v8_idregs
, v8_user_idregs
);
8681 * RVBAR_EL1 and RMR_EL1 only implemented if EL1 is the highest EL.
8682 * TODO: For RMR, a write with bit 1 set should do something with
8683 * cpu_reset(). In the meantime, "the bit is strictly a request",
8684 * so we are in spec just ignoring writes.
8686 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
8687 !arm_feature(env
, ARM_FEATURE_EL2
)) {
8688 ARMCPRegInfo el1_reset_regs
[] = {
8689 { .name
= "RVBAR_EL1", .state
= ARM_CP_STATE_BOTH
,
8690 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
8692 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
) },
8693 { .name
= "RMR_EL1", .state
= ARM_CP_STATE_BOTH
,
8694 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 2,
8695 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
8696 .resetvalue
= arm_feature(env
, ARM_FEATURE_AARCH64
) }
8698 define_arm_cp_regs(cpu
, el1_reset_regs
);
8700 define_arm_cp_regs(cpu
, v8_idregs
);
8701 define_arm_cp_regs(cpu
, v8_cp_reginfo
);
8703 for (i
= 4; i
< 16; i
++) {
8705 * Encodings in "0, c0, {c4-c7}, {0-7}" are RAZ for AArch32.
8706 * For pre-v8 cores there are RAZ patterns for these in
8707 * id_pre_v8_midr_cp_reginfo[]; for v8 we do that here.
8708 * v8 extends the "must RAZ" part of the ID register space
8709 * to also cover c0, 0, c{8-15}, {0-7}.
8710 * These are STATE_AA32 because in the AArch64 sysreg space
8711 * c4-c7 is where the AArch64 ID registers live (and we've
8712 * already defined those in v8_idregs[]), and c8-c15 are not
8713 * "must RAZ" for AArch64.
8715 g_autofree
char *name
= g_strdup_printf("RES_0_C0_C%d_X", i
);
8716 ARMCPRegInfo v8_aa32_raz_idregs
= {
8718 .state
= ARM_CP_STATE_AA32
,
8719 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= CP_ANY
,
8720 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8721 .accessfn
= access_aa64_tid3
,
8723 define_one_arm_cp_reg(cpu
, &v8_aa32_raz_idregs
);
8728 * Register the base EL2 cpregs.
8729 * Pre v8, these registers are implemented only as part of the
8730 * Virtualization Extensions (EL2 present). Beginning with v8,
8731 * if EL2 is missing but EL3 is enabled, mostly these become
8732 * RES0 from EL3, with some specific exceptions.
8734 if (arm_feature(env
, ARM_FEATURE_EL2
)
8735 || (arm_feature(env
, ARM_FEATURE_EL3
)
8736 && arm_feature(env
, ARM_FEATURE_V8
))) {
8737 uint64_t vmpidr_def
= mpidr_read_val(env
);
8738 ARMCPRegInfo vpidr_regs
[] = {
8739 { .name
= "VPIDR", .state
= ARM_CP_STATE_AA32
,
8740 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
8741 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
8742 .resetvalue
= cpu
->midr
,
8743 .type
= ARM_CP_ALIAS
| ARM_CP_EL3_NO_EL2_C_NZ
,
8744 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vpidr_el2
) },
8745 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
8746 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
8747 .access
= PL2_RW
, .resetvalue
= cpu
->midr
,
8748 .type
= ARM_CP_EL3_NO_EL2_C_NZ
,
8749 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
8750 { .name
= "VMPIDR", .state
= ARM_CP_STATE_AA32
,
8751 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
8752 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
8753 .resetvalue
= vmpidr_def
,
8754 .type
= ARM_CP_ALIAS
| ARM_CP_EL3_NO_EL2_C_NZ
,
8755 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vmpidr_el2
) },
8756 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
8757 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
8758 .access
= PL2_RW
, .resetvalue
= vmpidr_def
,
8759 .type
= ARM_CP_EL3_NO_EL2_C_NZ
,
8760 .fieldoffset
= offsetof(CPUARMState
, cp15
.vmpidr_el2
) },
8763 * The only field of MDCR_EL2 that has a defined architectural reset
8764 * value is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N.
8766 ARMCPRegInfo mdcr_el2
= {
8767 .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
, .type
= ARM_CP_IO
,
8768 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
8769 .writefn
= mdcr_el2_write
,
8770 .access
= PL2_RW
, .resetvalue
= pmu_num_counters(env
),
8771 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el2
),
8773 define_one_arm_cp_reg(cpu
, &mdcr_el2
);
8774 define_arm_cp_regs(cpu
, vpidr_regs
);
8775 define_arm_cp_regs(cpu
, el2_cp_reginfo
);
8776 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8777 define_arm_cp_regs(cpu
, el2_v8_cp_reginfo
);
8779 if (cpu_isar_feature(aa64_sel2
, cpu
)) {
8780 define_arm_cp_regs(cpu
, el2_sec_cp_reginfo
);
8783 * RVBAR_EL2 and RMR_EL2 only implemented if EL2 is the highest EL.
8784 * See commentary near RMR_EL1.
8786 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
8787 static const ARMCPRegInfo el2_reset_regs
[] = {
8788 { .name
= "RVBAR_EL2", .state
= ARM_CP_STATE_AA64
,
8789 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 1,
8791 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
) },
8792 { .name
= "RVBAR", .type
= ARM_CP_ALIAS
,
8793 .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
8795 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
) },
8796 { .name
= "RMR_EL2", .state
= ARM_CP_STATE_AA64
,
8797 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 2,
8798 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 1 },
8800 define_arm_cp_regs(cpu
, el2_reset_regs
);
8804 /* Register the base EL3 cpregs. */
8805 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
8806 define_arm_cp_regs(cpu
, el3_cp_reginfo
);
8807 ARMCPRegInfo el3_regs
[] = {
8808 { .name
= "RVBAR_EL3", .state
= ARM_CP_STATE_AA64
,
8809 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 1,
8811 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
), },
8812 { .name
= "RMR_EL3", .state
= ARM_CP_STATE_AA64
,
8813 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 2,
8814 .access
= PL3_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 1 },
8815 { .name
= "RMR", .state
= ARM_CP_STATE_AA32
,
8816 .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 2,
8817 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
8818 .resetvalue
= arm_feature(env
, ARM_FEATURE_AARCH64
) },
8819 { .name
= "SCTLR_EL3", .state
= ARM_CP_STATE_AA64
,
8820 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 0,
8822 .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
8823 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[3]),
8824 .resetvalue
= cpu
->reset_sctlr
},
8827 define_arm_cp_regs(cpu
, el3_regs
);
8830 * The behaviour of NSACR is sufficiently various that we don't
8831 * try to describe it in a single reginfo:
8832 * if EL3 is 64 bit, then trap to EL3 from S EL1,
8833 * reads as constant 0xc00 from NS EL1 and NS EL2
8834 * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
8835 * if v7 without EL3, register doesn't exist
8836 * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
8838 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
8839 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
8840 static const ARMCPRegInfo nsacr
= {
8841 .name
= "NSACR", .type
= ARM_CP_CONST
,
8842 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
8843 .access
= PL1_RW
, .accessfn
= nsacr_access
,
8846 define_one_arm_cp_reg(cpu
, &nsacr
);
8848 static const ARMCPRegInfo nsacr
= {
8850 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
8851 .access
= PL3_RW
| PL1_R
,
8853 .fieldoffset
= offsetof(CPUARMState
, cp15
.nsacr
)
8855 define_one_arm_cp_reg(cpu
, &nsacr
);
8858 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8859 static const ARMCPRegInfo nsacr
= {
8860 .name
= "NSACR", .type
= ARM_CP_CONST
,
8861 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
8865 define_one_arm_cp_reg(cpu
, &nsacr
);
8869 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
8870 if (arm_feature(env
, ARM_FEATURE_V6
)) {
8871 /* PMSAv6 not implemented */
8872 assert(arm_feature(env
, ARM_FEATURE_V7
));
8873 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
8874 define_arm_cp_regs(cpu
, pmsav7_cp_reginfo
);
8876 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
8879 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
8880 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
8881 /* TTCBR2 is introduced with ARMv8.2-AA32HPD. */
8882 if (cpu_isar_feature(aa32_hpd
, cpu
)) {
8883 define_one_arm_cp_reg(cpu
, &ttbcr2_reginfo
);
8886 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
8887 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
8889 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
8890 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
8892 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
8893 ARMCPRegInfo vapa_cp_reginfo
[] = {
8894 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
8895 .access
= PL1_RW
, .resetvalue
= 0,
8896 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.par_s
),
8897 offsetoflow32(CPUARMState
, cp15
.par_ns
) },
8898 .writefn
= par_write
},
8899 #ifndef CONFIG_USER_ONLY
8900 /* This underdecoding is safe because the reginfo is NO_RAW. */
8901 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
8902 .access
= PL1_W
, .accessfn
= ats_access
,
8903 .writefn
= ats_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
8908 * When LPAE exists this 32-bit PAR register is an alias of the
8909 * 64-bit AArch32 PAR register defined in lpae_cp_reginfo[]
8911 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
8912 vapa_cp_reginfo
[0].type
= ARM_CP_ALIAS
| ARM_CP_NO_GDB
;
8914 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
8916 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
8917 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
8919 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
8920 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
8922 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
8923 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
8925 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
8926 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
8928 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
8929 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
8931 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
8932 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
8934 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
8935 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
8937 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
8938 define_arm_cp_regs(cpu
, lpae_cp_reginfo
);
8940 if (cpu_isar_feature(aa32_jazelle
, cpu
)) {
8941 define_arm_cp_regs(cpu
, jazelle_regs
);
8944 * Slightly awkwardly, the OMAP and StrongARM cores need all of
8945 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
8946 * be read-only (ie write causes UNDEF exception).
8949 ARMCPRegInfo id_pre_v8_midr_cp_reginfo
[] = {
8951 * Pre-v8 MIDR space.
8952 * Note that the MIDR isn't a simple constant register because
8953 * of the TI925 behaviour where writes to another register can
8954 * cause the MIDR value to change.
8956 * Unimplemented registers in the c15 0 0 0 space default to
8957 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
8958 * and friends override accordingly.
8961 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= CP_ANY
,
8962 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
8963 .writefn
= arm_cp_write_ignore
, .raw_writefn
= raw_write
,
8964 .readfn
= midr_read
,
8965 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
8966 .type
= ARM_CP_OVERRIDE
},
8967 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
8969 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
8970 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8972 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
8973 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8975 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
8976 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8978 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
8979 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8981 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
8982 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8984 ARMCPRegInfo id_v8_midr_cp_reginfo
[] = {
8985 { .name
= "MIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
8986 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 0,
8987 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
, .resetvalue
= cpu
->midr
,
8988 .fgt
= FGT_MIDR_EL1
,
8989 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
8990 .readfn
= midr_read
},
8991 /* crn = 0 op1 = 0 crm = 0 op2 = 7 : AArch32 aliases of MIDR */
8992 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
8993 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 7,
8994 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
8995 { .name
= "REVIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
8996 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 6,
8998 .accessfn
= access_aa64_tid1
,
8999 .fgt
= FGT_REVIDR_EL1
,
9000 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->revidr
},
9002 ARMCPRegInfo id_v8_midr_alias_cp_reginfo
= {
9003 .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
| ARM_CP_NO_GDB
,
9004 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
9005 .access
= PL1_R
, .resetvalue
= cpu
->midr
9007 ARMCPRegInfo id_cp_reginfo
[] = {
9008 /* These are common to v8 and pre-v8 */
9010 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
9011 .access
= PL1_R
, .accessfn
= ctr_el0_access
,
9012 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
9013 { .name
= "CTR_EL0", .state
= ARM_CP_STATE_AA64
,
9014 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 0, .crm
= 0,
9015 .access
= PL0_R
, .accessfn
= ctr_el0_access
,
9017 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
9018 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
9020 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
9022 .accessfn
= access_aa32_tid1
,
9023 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
9025 /* TLBTR is specific to VMSA */
9026 ARMCPRegInfo id_tlbtr_reginfo
= {
9028 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
9030 .accessfn
= access_aa32_tid1
,
9031 .type
= ARM_CP_CONST
, .resetvalue
= 0,
9033 /* MPUIR is specific to PMSA V6+ */
9034 ARMCPRegInfo id_mpuir_reginfo
= {
9036 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
9037 .access
= PL1_R
, .type
= ARM_CP_CONST
,
9038 .resetvalue
= cpu
->pmsav7_dregion
<< 8
9040 /* HMPUIR is specific to PMSA V8 */
9041 ARMCPRegInfo id_hmpuir_reginfo
= {
9043 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 4,
9044 .access
= PL2_R
, .type
= ARM_CP_CONST
,
9045 .resetvalue
= cpu
->pmsav8r_hdregion
9047 static const ARMCPRegInfo crn0_wi_reginfo
= {
9048 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
9049 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
9050 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
9052 #ifdef CONFIG_USER_ONLY
9053 static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo
[] = {
9054 { .name
= "MIDR_EL1",
9055 .exported_bits
= R_MIDR_EL1_REVISION_MASK
|
9056 R_MIDR_EL1_PARTNUM_MASK
|
9057 R_MIDR_EL1_ARCHITECTURE_MASK
|
9058 R_MIDR_EL1_VARIANT_MASK
|
9059 R_MIDR_EL1_IMPLEMENTER_MASK
},
9060 { .name
= "REVIDR_EL1" },
9062 modify_arm_cp_regs(id_v8_midr_cp_reginfo
, id_v8_user_midr_cp_reginfo
);
9064 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
9065 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
9068 * Register the blanket "writes ignored" value first to cover the
9069 * whole space. Then update the specific ID registers to allow write
9070 * access, so that they ignore writes rather than causing them to
9073 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
9074 for (i
= 0; i
< ARRAY_SIZE(id_pre_v8_midr_cp_reginfo
); ++i
) {
9075 id_pre_v8_midr_cp_reginfo
[i
].access
= PL1_RW
;
9077 for (i
= 0; i
< ARRAY_SIZE(id_cp_reginfo
); ++i
) {
9078 id_cp_reginfo
[i
].access
= PL1_RW
;
9080 id_mpuir_reginfo
.access
= PL1_RW
;
9081 id_tlbtr_reginfo
.access
= PL1_RW
;
9083 if (arm_feature(env
, ARM_FEATURE_V8
)) {
9084 define_arm_cp_regs(cpu
, id_v8_midr_cp_reginfo
);
9085 if (!arm_feature(env
, ARM_FEATURE_PMSA
)) {
9086 define_one_arm_cp_reg(cpu
, &id_v8_midr_alias_cp_reginfo
);
9089 define_arm_cp_regs(cpu
, id_pre_v8_midr_cp_reginfo
);
9091 define_arm_cp_regs(cpu
, id_cp_reginfo
);
9092 if (!arm_feature(env
, ARM_FEATURE_PMSA
)) {
9093 define_one_arm_cp_reg(cpu
, &id_tlbtr_reginfo
);
9094 } else if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
9095 arm_feature(env
, ARM_FEATURE_V8
)) {
9099 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
9100 define_one_arm_cp_reg(cpu
, &id_hmpuir_reginfo
);
9101 define_arm_cp_regs(cpu
, pmsav8r_cp_reginfo
);
9103 /* Register alias is only valid for first 32 indexes */
9104 for (i
= 0; i
< MIN(cpu
->pmsav7_dregion
, 32); ++i
) {
9105 uint8_t crm
= 0b1000 | extract32(i
, 1, 3);
9106 uint8_t opc1
= extract32(i
, 4, 1);
9107 uint8_t opc2
= extract32(i
, 0, 1) << 2;
9109 tmp_string
= g_strdup_printf("PRBAR%u", i
);
9110 ARMCPRegInfo tmp_prbarn_reginfo
= {
9111 .name
= tmp_string
, .type
= ARM_CP_ALIAS
| ARM_CP_NO_RAW
,
9112 .cp
= 15, .opc1
= opc1
, .crn
= 6, .crm
= crm
, .opc2
= opc2
,
9113 .access
= PL1_RW
, .resetvalue
= 0,
9114 .accessfn
= access_tvm_trvm
,
9115 .writefn
= pmsav8r_regn_write
, .readfn
= pmsav8r_regn_read
9117 define_one_arm_cp_reg(cpu
, &tmp_prbarn_reginfo
);
9120 opc2
= extract32(i
, 0, 1) << 2 | 0x1;
9121 tmp_string
= g_strdup_printf("PRLAR%u", i
);
9122 ARMCPRegInfo tmp_prlarn_reginfo
= {
9123 .name
= tmp_string
, .type
= ARM_CP_ALIAS
| ARM_CP_NO_RAW
,
9124 .cp
= 15, .opc1
= opc1
, .crn
= 6, .crm
= crm
, .opc2
= opc2
,
9125 .access
= PL1_RW
, .resetvalue
= 0,
9126 .accessfn
= access_tvm_trvm
,
9127 .writefn
= pmsav8r_regn_write
, .readfn
= pmsav8r_regn_read
9129 define_one_arm_cp_reg(cpu
, &tmp_prlarn_reginfo
);
9133 /* Register alias is only valid for first 32 indexes */
9134 for (i
= 0; i
< MIN(cpu
->pmsav8r_hdregion
, 32); ++i
) {
9135 uint8_t crm
= 0b1000 | extract32(i
, 1, 3);
9136 uint8_t opc1
= 0b100 | extract32(i
, 4, 1);
9137 uint8_t opc2
= extract32(i
, 0, 1) << 2;
9139 tmp_string
= g_strdup_printf("HPRBAR%u", i
);
9140 ARMCPRegInfo tmp_hprbarn_reginfo
= {
9142 .type
= ARM_CP_NO_RAW
,
9143 .cp
= 15, .opc1
= opc1
, .crn
= 6, .crm
= crm
, .opc2
= opc2
,
9144 .access
= PL2_RW
, .resetvalue
= 0,
9145 .writefn
= pmsav8r_regn_write
, .readfn
= pmsav8r_regn_read
9147 define_one_arm_cp_reg(cpu
, &tmp_hprbarn_reginfo
);
9150 opc2
= extract32(i
, 0, 1) << 2 | 0x1;
9151 tmp_string
= g_strdup_printf("HPRLAR%u", i
);
9152 ARMCPRegInfo tmp_hprlarn_reginfo
= {
9154 .type
= ARM_CP_NO_RAW
,
9155 .cp
= 15, .opc1
= opc1
, .crn
= 6, .crm
= crm
, .opc2
= opc2
,
9156 .access
= PL2_RW
, .resetvalue
= 0,
9157 .writefn
= pmsav8r_regn_write
, .readfn
= pmsav8r_regn_read
9159 define_one_arm_cp_reg(cpu
, &tmp_hprlarn_reginfo
);
9162 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
9163 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
9167 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
9168 ARMCPRegInfo mpidr_cp_reginfo
[] = {
9169 { .name
= "MPIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
9170 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
9171 .fgt
= FGT_MPIDR_EL1
,
9172 .access
= PL1_R
, .readfn
= mpidr_read
, .type
= ARM_CP_NO_RAW
},
9174 #ifdef CONFIG_USER_ONLY
9175 static const ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo
[] = {
9176 { .name
= "MPIDR_EL1",
9177 .fixed_bits
= 0x0000000080000000 },
9179 modify_arm_cp_regs(mpidr_cp_reginfo
, mpidr_user_cp_reginfo
);
9181 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
9184 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
9185 ARMCPRegInfo auxcr_reginfo
[] = {
9186 { .name
= "ACTLR_EL1", .state
= ARM_CP_STATE_BOTH
,
9187 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 1,
9188 .access
= PL1_RW
, .accessfn
= access_tacr
,
9189 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->reset_auxcr
},
9190 { .name
= "ACTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
9191 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 1,
9192 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
9194 { .name
= "ACTLR_EL3", .state
= ARM_CP_STATE_AA64
,
9195 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 1,
9196 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
9199 define_arm_cp_regs(cpu
, auxcr_reginfo
);
9200 if (cpu_isar_feature(aa32_ac2
, cpu
)) {
9201 define_arm_cp_regs(cpu
, actlr2_hactlr2_reginfo
);
9205 if (arm_feature(env
, ARM_FEATURE_CBAR
)) {
9207 * CBAR is IMPDEF, but common on Arm Cortex-A implementations.
9208 * There are two flavours:
9209 * (1) older 32-bit only cores have a simple 32-bit CBAR
9210 * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a
9211 * 32-bit register visible to AArch32 at a different encoding
9212 * to the "flavour 1" register and with the bits rearranged to
9213 * be able to squash a 64-bit address into the 32-bit view.
9214 * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but
9215 * in future if we support AArch32-only configs of some of the
9216 * AArch64 cores we might need to add a specific feature flag
9217 * to indicate cores with "flavour 2" CBAR.
9219 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
9220 /* 32 bit view is [31:18] 0...0 [43:32]. */
9221 uint32_t cbar32
= (extract64(cpu
->reset_cbar
, 18, 14) << 18)
9222 | extract64(cpu
->reset_cbar
, 32, 12);
9223 ARMCPRegInfo cbar_reginfo
[] = {
9225 .type
= ARM_CP_CONST
,
9226 .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 1, .opc2
= 0,
9227 .access
= PL1_R
, .resetvalue
= cbar32
},
9228 { .name
= "CBAR_EL1", .state
= ARM_CP_STATE_AA64
,
9229 .type
= ARM_CP_CONST
,
9230 .opc0
= 3, .opc1
= 1, .crn
= 15, .crm
= 3, .opc2
= 0,
9231 .access
= PL1_R
, .resetvalue
= cpu
->reset_cbar
},
9233 /* We don't implement a r/w 64 bit CBAR currently */
9234 assert(arm_feature(env
, ARM_FEATURE_CBAR_RO
));
9235 define_arm_cp_regs(cpu
, cbar_reginfo
);
9237 ARMCPRegInfo cbar
= {
9239 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
9240 .access
= PL1_R
| PL3_W
, .resetvalue
= cpu
->reset_cbar
,
9241 .fieldoffset
= offsetof(CPUARMState
,
9242 cp15
.c15_config_base_address
)
9244 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
9245 cbar
.access
= PL1_R
;
9246 cbar
.fieldoffset
= 0;
9247 cbar
.type
= ARM_CP_CONST
;
9249 define_one_arm_cp_reg(cpu
, &cbar
);
9253 if (arm_feature(env
, ARM_FEATURE_VBAR
)) {
9254 static const ARMCPRegInfo vbar_cp_reginfo
[] = {
9255 { .name
= "VBAR", .state
= ARM_CP_STATE_BOTH
,
9256 .opc0
= 3, .crn
= 12, .crm
= 0, .opc1
= 0, .opc2
= 0,
9257 .access
= PL1_RW
, .writefn
= vbar_write
,
9258 .fgt
= FGT_VBAR_EL1
,
9259 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.vbar_s
),
9260 offsetof(CPUARMState
, cp15
.vbar_ns
) },
9263 define_arm_cp_regs(cpu
, vbar_cp_reginfo
);
9266 /* Generic registers whose values depend on the implementation */
9268 ARMCPRegInfo sctlr
= {
9269 .name
= "SCTLR", .state
= ARM_CP_STATE_BOTH
,
9270 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
9271 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
9272 .fgt
= FGT_SCTLR_EL1
,
9273 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.sctlr_s
),
9274 offsetof(CPUARMState
, cp15
.sctlr_ns
) },
9275 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
,
9276 .raw_writefn
= raw_write
,
9278 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
9280 * Normally we would always end the TB on an SCTLR write, but Linux
9281 * arch/arm/mach-pxa/sleep.S expects two instructions following
9282 * an MMU enable to execute from cache. Imitate this behaviour.
9284 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
9286 define_one_arm_cp_reg(cpu
, &sctlr
);
9288 if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
9289 arm_feature(env
, ARM_FEATURE_V8
)) {
9290 ARMCPRegInfo vsctlr
= {
9291 .name
= "VSCTLR", .state
= ARM_CP_STATE_AA32
,
9292 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
9293 .access
= PL2_RW
, .resetvalue
= 0x0,
9294 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vsctlr
),
9296 define_one_arm_cp_reg(cpu
, &vsctlr
);
9300 if (cpu_isar_feature(aa64_lor
, cpu
)) {
9301 define_arm_cp_regs(cpu
, lor_reginfo
);
9303 if (cpu_isar_feature(aa64_pan
, cpu
)) {
9304 define_one_arm_cp_reg(cpu
, &pan_reginfo
);
9306 #ifndef CONFIG_USER_ONLY
9307 if (cpu_isar_feature(aa64_ats1e1
, cpu
)) {
9308 define_arm_cp_regs(cpu
, ats1e1_reginfo
);
9310 if (cpu_isar_feature(aa32_ats1e1
, cpu
)) {
9311 define_arm_cp_regs(cpu
, ats1cp_reginfo
);
9314 if (cpu_isar_feature(aa64_uao
, cpu
)) {
9315 define_one_arm_cp_reg(cpu
, &uao_reginfo
);
9318 if (cpu_isar_feature(aa64_dit
, cpu
)) {
9319 define_one_arm_cp_reg(cpu
, &dit_reginfo
);
9321 if (cpu_isar_feature(aa64_ssbs
, cpu
)) {
9322 define_one_arm_cp_reg(cpu
, &ssbs_reginfo
);
9324 if (cpu_isar_feature(any_ras
, cpu
)) {
9325 define_arm_cp_regs(cpu
, minimal_ras_reginfo
);
9328 if (cpu_isar_feature(aa64_vh
, cpu
) ||
9329 cpu_isar_feature(aa64_debugv8p2
, cpu
)) {
9330 define_one_arm_cp_reg(cpu
, &contextidr_el2
);
9332 if (arm_feature(env
, ARM_FEATURE_EL2
) && cpu_isar_feature(aa64_vh
, cpu
)) {
9333 define_arm_cp_regs(cpu
, vhe_reginfo
);
9336 if (cpu_isar_feature(aa64_sve
, cpu
)) {
9337 define_arm_cp_regs(cpu
, zcr_reginfo
);
9340 if (cpu_isar_feature(aa64_hcx
, cpu
)) {
9341 define_one_arm_cp_reg(cpu
, &hcrx_el2_reginfo
);
9344 #ifdef TARGET_AARCH64
9345 if (cpu_isar_feature(aa64_sme
, cpu
)) {
9346 define_arm_cp_regs(cpu
, sme_reginfo
);
9348 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
9349 define_arm_cp_regs(cpu
, pauth_reginfo
);
9351 if (cpu_isar_feature(aa64_rndr
, cpu
)) {
9352 define_arm_cp_regs(cpu
, rndr_reginfo
);
9354 if (cpu_isar_feature(aa64_tlbirange
, cpu
)) {
9355 define_arm_cp_regs(cpu
, tlbirange_reginfo
);
9357 if (cpu_isar_feature(aa64_tlbios
, cpu
)) {
9358 define_arm_cp_regs(cpu
, tlbios_reginfo
);
9360 /* Data Cache clean instructions up to PoP */
9361 if (cpu_isar_feature(aa64_dcpop
, cpu
)) {
9362 define_one_arm_cp_reg(cpu
, dcpop_reg
);
9364 if (cpu_isar_feature(aa64_dcpodp
, cpu
)) {
9365 define_one_arm_cp_reg(cpu
, dcpodp_reg
);
9370 * If full MTE is enabled, add all of the system registers.
9371 * If only "instructions available at EL0" are enabled,
9372 * then define only a RAZ/WI version of PSTATE.TCO.
9374 if (cpu_isar_feature(aa64_mte
, cpu
)) {
9375 ARMCPRegInfo gmid_reginfo
= {
9376 .name
= "GMID_EL1", .state
= ARM_CP_STATE_AA64
,
9377 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 4,
9378 .access
= PL1_R
, .accessfn
= access_aa64_tid5
,
9379 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->gm_blocksize
,
9381 define_one_arm_cp_reg(cpu
, &gmid_reginfo
);
9382 define_arm_cp_regs(cpu
, mte_reginfo
);
9383 define_arm_cp_regs(cpu
, mte_el0_cacheop_reginfo
);
9384 } else if (cpu_isar_feature(aa64_mte_insn_reg
, cpu
)) {
9385 define_arm_cp_regs(cpu
, mte_tco_ro_reginfo
);
9386 define_arm_cp_regs(cpu
, mte_el0_cacheop_reginfo
);
9389 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
9390 define_arm_cp_regs(cpu
, scxtnum_reginfo
);
9393 if (cpu_isar_feature(aa64_fgt
, cpu
)) {
9394 define_arm_cp_regs(cpu
, fgt_reginfo
);
9397 if (cpu_isar_feature(aa64_rme
, cpu
)) {
9398 define_arm_cp_regs(cpu
, rme_reginfo
);
9399 if (cpu_isar_feature(aa64_mte
, cpu
)) {
9400 define_arm_cp_regs(cpu
, rme_mte_reginfo
);
9405 if (cpu_isar_feature(any_predinv
, cpu
)) {
9406 define_arm_cp_regs(cpu
, predinv_reginfo
);
9409 if (cpu_isar_feature(any_ccidx
, cpu
)) {
9410 define_arm_cp_regs(cpu
, ccsidr2_reginfo
);
9413 #ifndef CONFIG_USER_ONLY
9415 * Register redirections and aliases must be done last,
9416 * after the registers from the other extensions have been defined.
9418 if (arm_feature(env
, ARM_FEATURE_EL2
) && cpu_isar_feature(aa64_vh
, cpu
)) {
9419 define_arm_vh_e2h_redirects_aliases(cpu
);
9424 /* Sort alphabetically by type name, except for "any". */
9425 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
9427 ObjectClass
*class_a
= (ObjectClass
*)a
;
9428 ObjectClass
*class_b
= (ObjectClass
*)b
;
9429 const char *name_a
, *name_b
;
9431 name_a
= object_class_get_name(class_a
);
9432 name_b
= object_class_get_name(class_b
);
9433 if (strcmp(name_a
, "any-" TYPE_ARM_CPU
) == 0) {
9435 } else if (strcmp(name_b
, "any-" TYPE_ARM_CPU
) == 0) {
9438 return strcmp(name_a
, name_b
);
9442 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
9444 ObjectClass
*oc
= data
;
9445 CPUClass
*cc
= CPU_CLASS(oc
);
9446 const char *typename
;
9449 typename
= object_class_get_name(oc
);
9450 name
= g_strndup(typename
, strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
9451 if (cc
->deprecation_note
) {
9452 qemu_printf(" %s (deprecated)\n", name
);
9454 qemu_printf(" %s\n", name
);
9459 void arm_cpu_list(void)
9463 list
= object_class_get_list(TYPE_ARM_CPU
, false);
9464 list
= g_slist_sort(list
, arm_cpu_list_compare
);
9465 qemu_printf("Available CPUs:\n");
9466 g_slist_foreach(list
, arm_cpu_list_entry
, NULL
);
9471 * Private utility function for define_one_arm_cp_reg_with_opaque():
9472 * add a single reginfo struct to the hash table.
9474 static void add_cpreg_to_hashtable(ARMCPU
*cpu
, const ARMCPRegInfo
*r
,
9475 void *opaque
, CPState state
,
9476 CPSecureState secstate
,
9477 int crm
, int opc1
, int opc2
,
9480 CPUARMState
*env
= &cpu
->env
;
9483 bool is64
= r
->type
& ARM_CP_64BIT
;
9484 bool ns
= secstate
& ARM_CP_SECSTATE_NS
;
9490 case ARM_CP_STATE_AA32
:
9491 /* We assume it is a cp15 register if the .cp field is left unset. */
9492 if (cp
== 0 && r
->state
== ARM_CP_STATE_BOTH
) {
9495 key
= ENCODE_CP_REG(cp
, is64
, ns
, r
->crn
, crm
, opc1
, opc2
);
9497 case ARM_CP_STATE_AA64
:
9499 * To allow abbreviation of ARMCPRegInfo definitions, we treat
9500 * cp == 0 as equivalent to the value for "standard guest-visible
9501 * sysreg". STATE_BOTH definitions are also always "standard sysreg"
9502 * in their AArch64 view (the .cp value may be non-zero for the
9503 * benefit of the AArch32 view).
9505 if (cp
== 0 || r
->state
== ARM_CP_STATE_BOTH
) {
9506 cp
= CP_REG_ARM64_SYSREG_CP
;
9508 key
= ENCODE_AA64_CP_REG(cp
, r
->crn
, crm
, r
->opc0
, opc1
, opc2
);
9511 g_assert_not_reached();
9514 /* Overriding of an existing definition must be explicitly requested. */
9515 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
9516 const ARMCPRegInfo
*oldreg
= get_arm_cp_reginfo(cpu
->cp_regs
, key
);
9518 assert(oldreg
->type
& ARM_CP_OVERRIDE
);
9523 * Eliminate registers that are not present because the EL is missing.
9524 * Doing this here makes it easier to put all registers for a given
9525 * feature into the same ARMCPRegInfo array and define them all at once.
9528 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
9530 * An EL2 register without EL2 but with EL3 is (usually) RES0.
9531 * See rule RJFFP in section D1.1.3 of DDI0487H.a.
9533 int min_el
= ctz32(r
->access
) / 2;
9534 if (min_el
== 2 && !arm_feature(env
, ARM_FEATURE_EL2
)) {
9535 if (r
->type
& ARM_CP_EL3_NO_EL2_UNDEF
) {
9538 make_const
= !(r
->type
& ARM_CP_EL3_NO_EL2_KEEP
);
9541 CPAccessRights max_el
= (arm_feature(env
, ARM_FEATURE_EL2
)
9543 if ((r
->access
& max_el
) == 0) {
9548 /* Combine cpreg and name into one allocation. */
9549 name_len
= strlen(name
) + 1;
9550 r2
= g_malloc(sizeof(*r2
) + name_len
);
9552 r2
->name
= memcpy(r2
+ 1, name
, name_len
);
9555 * Update fields to match the instantiation, overwiting wildcards
9556 * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH.
9563 r2
->secure
= secstate
;
9565 r2
->opaque
= opaque
;
9569 /* This should not have been a very special register to begin. */
9570 int old_special
= r2
->type
& ARM_CP_SPECIAL_MASK
;
9571 assert(old_special
== 0 || old_special
== ARM_CP_NOP
);
9573 * Set the special function to CONST, retaining the other flags.
9574 * This is important for e.g. ARM_CP_SVE so that we still
9575 * take the SVE trap if CPTR_EL3.EZ == 0.
9577 r2
->type
= (r2
->type
& ~ARM_CP_SPECIAL_MASK
) | ARM_CP_CONST
;
9579 * Usually, these registers become RES0, but there are a few
9580 * special cases like VPIDR_EL2 which have a constant non-zero
9581 * value with writes ignored.
9583 if (!(r
->type
& ARM_CP_EL3_NO_EL2_C_NZ
)) {
9587 * ARM_CP_CONST has precedence, so removing the callbacks and
9588 * offsets are not strictly necessary, but it is potentially
9589 * less confusing to debug later.
9593 r2
->raw_readfn
= NULL
;
9594 r2
->raw_writefn
= NULL
;
9596 r2
->fieldoffset
= 0;
9597 r2
->bank_fieldoffsets
[0] = 0;
9598 r2
->bank_fieldoffsets
[1] = 0;
9600 bool isbanked
= r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1];
9604 * Register is banked (using both entries in array).
9605 * Overwriting fieldoffset as the array is only used to define
9606 * banked registers but later only fieldoffset is used.
9608 r2
->fieldoffset
= r
->bank_fieldoffsets
[ns
];
9610 if (state
== ARM_CP_STATE_AA32
) {
9613 * If the register is banked then we don't need to migrate or
9614 * reset the 32-bit instance in certain cases:
9616 * 1) If the register has both 32-bit and 64-bit instances
9617 * then we can count on the 64-bit instance taking care
9618 * of the non-secure bank.
9619 * 2) If ARMv8 is enabled then we can count on a 64-bit
9620 * version taking care of the secure bank. This requires
9621 * that separate 32 and 64-bit definitions are provided.
9623 if ((r
->state
== ARM_CP_STATE_BOTH
&& ns
) ||
9624 (arm_feature(env
, ARM_FEATURE_V8
) && !ns
)) {
9625 r2
->type
|= ARM_CP_ALIAS
;
9627 } else if ((secstate
!= r
->secure
) && !ns
) {
9629 * The register is not banked so we only want to allow
9630 * migration of the non-secure instance.
9632 r2
->type
|= ARM_CP_ALIAS
;
9635 if (HOST_BIG_ENDIAN
&&
9636 r
->state
== ARM_CP_STATE_BOTH
&& r2
->fieldoffset
) {
9637 r2
->fieldoffset
+= sizeof(uint32_t);
9643 * By convention, for wildcarded registers only the first
9644 * entry is used for migration; the others are marked as
9645 * ALIAS so we don't try to transfer the register
9646 * multiple times. Special registers (ie NOP/WFI) are
9647 * never migratable and not even raw-accessible.
9649 if (r2
->type
& ARM_CP_SPECIAL_MASK
) {
9650 r2
->type
|= ARM_CP_NO_RAW
;
9652 if (((r
->crm
== CP_ANY
) && crm
!= 0) ||
9653 ((r
->opc1
== CP_ANY
) && opc1
!= 0) ||
9654 ((r
->opc2
== CP_ANY
) && opc2
!= 0)) {
9655 r2
->type
|= ARM_CP_ALIAS
| ARM_CP_NO_GDB
;
9659 * Check that raw accesses are either forbidden or handled. Note that
9660 * we can't assert this earlier because the setup of fieldoffset for
9661 * banked registers has to be done first.
9663 if (!(r2
->type
& ARM_CP_NO_RAW
)) {
9664 assert(!raw_accessors_invalid(r2
));
9667 g_hash_table_insert(cpu
->cp_regs
, (gpointer
)(uintptr_t)key
, r2
);
9671 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
9672 const ARMCPRegInfo
*r
, void *opaque
)
9675 * Define implementations of coprocessor registers.
9676 * We store these in a hashtable because typically
9677 * there are less than 150 registers in a space which
9678 * is 16*16*16*8*8 = 262144 in size.
9679 * Wildcarding is supported for the crm, opc1 and opc2 fields.
9680 * If a register is defined twice then the second definition is
9681 * used, so this can be used to define some generic registers and
9682 * then override them with implementation specific variations.
9683 * At least one of the original and the second definition should
9684 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
9685 * against accidental use.
9687 * The state field defines whether the register is to be
9688 * visible in the AArch32 or AArch64 execution state. If the
9689 * state is set to ARM_CP_STATE_BOTH then we synthesise a
9690 * reginfo structure for the AArch32 view, which sees the lower
9691 * 32 bits of the 64 bit register.
9693 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
9694 * be wildcarded. AArch64 registers are always considered to be 64
9695 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
9696 * the register, if any.
9698 int crm
, opc1
, opc2
;
9699 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
9700 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
9701 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
9702 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
9703 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
9704 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
9707 /* 64 bit registers have only CRm and Opc1 fields */
9708 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
9709 /* op0 only exists in the AArch64 encodings */
9710 assert((r
->state
!= ARM_CP_STATE_AA32
) || (r
->opc0
== 0));
9711 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
9712 assert((r
->state
!= ARM_CP_STATE_AA64
) || !(r
->type
& ARM_CP_64BIT
));
9714 * This API is only for Arm's system coprocessors (14 and 15) or
9715 * (M-profile or v7A-and-earlier only) for implementation defined
9716 * coprocessors in the range 0..7. Our decode assumes this, since
9717 * 8..13 can be used for other insns including VFP and Neon. See
9718 * valid_cp() in translate.c. Assert here that we haven't tried
9719 * to use an invalid coprocessor number.
9722 case ARM_CP_STATE_BOTH
:
9723 /* 0 has a special meaning, but otherwise the same rules as AA32. */
9728 case ARM_CP_STATE_AA32
:
9729 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
) &&
9730 !arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
9731 assert(r
->cp
>= 14 && r
->cp
<= 15);
9733 assert(r
->cp
< 8 || (r
->cp
>= 14 && r
->cp
<= 15));
9736 case ARM_CP_STATE_AA64
:
9737 assert(r
->cp
== 0 || r
->cp
== CP_REG_ARM64_SYSREG_CP
);
9740 g_assert_not_reached();
9743 * The AArch64 pseudocode CheckSystemAccess() specifies that op1
9744 * encodes a minimum access level for the register. We roll this
9745 * runtime check into our general permission check code, so check
9746 * here that the reginfo's specified permissions are strict enough
9747 * to encompass the generic architectural permission check.
9749 if (r
->state
!= ARM_CP_STATE_AA32
) {
9750 CPAccessRights mask
;
9753 /* min_EL EL1, but some accessible to EL0 via kernel ABI */
9754 mask
= PL0U_R
| PL1_RW
;
9774 /* min_EL EL1, secure mode only (we don't check the latter) */
9778 /* broken reginfo with out-of-range opc1 */
9779 g_assert_not_reached();
9781 /* assert our permissions are not too lax (stricter is fine) */
9782 assert((r
->access
& ~mask
) == 0);
9786 * Check that the register definition has enough info to handle
9787 * reads and writes if they are permitted.
9789 if (!(r
->type
& (ARM_CP_SPECIAL_MASK
| ARM_CP_CONST
))) {
9790 if (r
->access
& PL3_R
) {
9791 assert((r
->fieldoffset
||
9792 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
9795 if (r
->access
& PL3_W
) {
9796 assert((r
->fieldoffset
||
9797 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
9802 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
9803 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
9804 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
9805 for (state
= ARM_CP_STATE_AA32
;
9806 state
<= ARM_CP_STATE_AA64
; state
++) {
9807 if (r
->state
!= state
&& r
->state
!= ARM_CP_STATE_BOTH
) {
9810 if (state
== ARM_CP_STATE_AA32
) {
9812 * Under AArch32 CP registers can be common
9813 * (same for secure and non-secure world) or banked.
9817 switch (r
->secure
) {
9818 case ARM_CP_SECSTATE_S
:
9819 case ARM_CP_SECSTATE_NS
:
9820 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
9821 r
->secure
, crm
, opc1
, opc2
,
9824 case ARM_CP_SECSTATE_BOTH
:
9825 name
= g_strdup_printf("%s_S", r
->name
);
9826 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
9828 crm
, opc1
, opc2
, name
);
9830 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
9832 crm
, opc1
, opc2
, r
->name
);
9835 g_assert_not_reached();
9839 * AArch64 registers get mapped to non-secure instance
9842 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
9844 crm
, opc1
, opc2
, r
->name
);
9852 /* Define a whole list of registers */
9853 void define_arm_cp_regs_with_opaque_len(ARMCPU
*cpu
, const ARMCPRegInfo
*regs
,
9854 void *opaque
, size_t len
)
9857 for (i
= 0; i
< len
; ++i
) {
9858 define_one_arm_cp_reg_with_opaque(cpu
, regs
+ i
, opaque
);
9863 * Modify ARMCPRegInfo for access from userspace.
9865 * This is a data driven modification directed by
9866 * ARMCPRegUserSpaceInfo. All registers become ARM_CP_CONST as
9867 * user-space cannot alter any values and dynamic values pertaining to
9868 * execution state are hidden from user space view anyway.
9870 void modify_arm_cp_regs_with_len(ARMCPRegInfo
*regs
, size_t regs_len
,
9871 const ARMCPRegUserSpaceInfo
*mods
,
9874 for (size_t mi
= 0; mi
< mods_len
; ++mi
) {
9875 const ARMCPRegUserSpaceInfo
*m
= mods
+ mi
;
9876 GPatternSpec
*pat
= NULL
;
9879 pat
= g_pattern_spec_new(m
->name
);
9881 for (size_t ri
= 0; ri
< regs_len
; ++ri
) {
9882 ARMCPRegInfo
*r
= regs
+ ri
;
9884 if (pat
&& g_pattern_match_string(pat
, r
->name
)) {
9885 r
->type
= ARM_CP_CONST
;
9889 } else if (strcmp(r
->name
, m
->name
) == 0) {
9890 r
->type
= ARM_CP_CONST
;
9892 r
->resetvalue
&= m
->exported_bits
;
9893 r
->resetvalue
|= m
->fixed_bits
;
9898 g_pattern_spec_free(pat
);
9903 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
)
9905 return g_hash_table_lookup(cpregs
, (gpointer
)(uintptr_t)encoded_cp
);
9908 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
9911 /* Helper coprocessor write function for write-ignore registers */
9914 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
9916 /* Helper coprocessor write function for read-as-zero registers */
9920 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
9922 /* Helper coprocessor reset function for do-nothing-on-reset registers */
9925 static int bad_mode_switch(CPUARMState
*env
, int mode
, CPSRWriteType write_type
)
9928 * Return true if it is not valid for us to switch to
9929 * this CPU mode (ie all the UNPREDICTABLE cases in
9930 * the ARM ARM CPSRWriteByInstr pseudocode).
9933 /* Changes to or from Hyp via MSR and CPS are illegal. */
9934 if (write_type
== CPSRWriteByInstr
&&
9935 ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_HYP
||
9936 mode
== ARM_CPU_MODE_HYP
)) {
9941 case ARM_CPU_MODE_USR
:
9943 case ARM_CPU_MODE_SYS
:
9944 case ARM_CPU_MODE_SVC
:
9945 case ARM_CPU_MODE_ABT
:
9946 case ARM_CPU_MODE_UND
:
9947 case ARM_CPU_MODE_IRQ
:
9948 case ARM_CPU_MODE_FIQ
:
9950 * Note that we don't implement the IMPDEF NSACR.RFR which in v7
9951 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
9954 * If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
9955 * and CPS are treated as illegal mode changes.
9957 if (write_type
== CPSRWriteByInstr
&&
9958 (env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
&&
9959 (arm_hcr_el2_eff(env
) & HCR_TGE
)) {
9963 case ARM_CPU_MODE_HYP
:
9964 return !arm_is_el2_enabled(env
) || arm_current_el(env
) < 2;
9965 case ARM_CPU_MODE_MON
:
9966 return arm_current_el(env
) < 3;
9972 uint32_t cpsr_read(CPUARMState
*env
)
9975 ZF
= (env
->ZF
== 0);
9976 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
9977 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
9978 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
9979 | ((env
->condexec_bits
& 0xfc) << 8)
9980 | (env
->GE
<< 16) | (env
->daif
& CPSR_AIF
);
9983 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
,
9984 CPSRWriteType write_type
)
9986 uint32_t changed_daif
;
9987 bool rebuild_hflags
= (write_type
!= CPSRWriteRaw
) &&
9988 (mask
& (CPSR_M
| CPSR_E
| CPSR_IL
));
9990 if (mask
& CPSR_NZCV
) {
9991 env
->ZF
= (~val
) & CPSR_Z
;
9993 env
->CF
= (val
>> 29) & 1;
9994 env
->VF
= (val
<< 3) & 0x80000000;
9996 if (mask
& CPSR_Q
) {
9997 env
->QF
= ((val
& CPSR_Q
) != 0);
9999 if (mask
& CPSR_T
) {
10000 env
->thumb
= ((val
& CPSR_T
) != 0);
10002 if (mask
& CPSR_IT_0_1
) {
10003 env
->condexec_bits
&= ~3;
10004 env
->condexec_bits
|= (val
>> 25) & 3;
10006 if (mask
& CPSR_IT_2_7
) {
10007 env
->condexec_bits
&= 3;
10008 env
->condexec_bits
|= (val
>> 8) & 0xfc;
10010 if (mask
& CPSR_GE
) {
10011 env
->GE
= (val
>> 16) & 0xf;
10015 * In a V7 implementation that includes the security extensions but does
10016 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
10017 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
10018 * bits respectively.
10020 * In a V8 implementation, it is permitted for privileged software to
10021 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
10023 if (write_type
!= CPSRWriteRaw
&& !arm_feature(env
, ARM_FEATURE_V8
) &&
10024 arm_feature(env
, ARM_FEATURE_EL3
) &&
10025 !arm_feature(env
, ARM_FEATURE_EL2
) &&
10026 !arm_is_secure(env
)) {
10028 changed_daif
= (env
->daif
^ val
) & mask
;
10030 if (changed_daif
& CPSR_A
) {
10032 * Check to see if we are allowed to change the masking of async
10033 * abort exceptions from a non-secure state.
10035 if (!(env
->cp15
.scr_el3
& SCR_AW
)) {
10036 qemu_log_mask(LOG_GUEST_ERROR
,
10037 "Ignoring attempt to switch CPSR_A flag from "
10038 "non-secure world with SCR.AW bit clear\n");
10043 if (changed_daif
& CPSR_F
) {
10045 * Check to see if we are allowed to change the masking of FIQ
10046 * exceptions from a non-secure state.
10048 if (!(env
->cp15
.scr_el3
& SCR_FW
)) {
10049 qemu_log_mask(LOG_GUEST_ERROR
,
10050 "Ignoring attempt to switch CPSR_F flag from "
10051 "non-secure world with SCR.FW bit clear\n");
10056 * Check whether non-maskable FIQ (NMFI) support is enabled.
10057 * If this bit is set software is not allowed to mask
10058 * FIQs, but is allowed to set CPSR_F to 0.
10060 if ((A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_NMFI
) &&
10062 qemu_log_mask(LOG_GUEST_ERROR
,
10063 "Ignoring attempt to enable CPSR_F flag "
10064 "(non-maskable FIQ [NMFI] support enabled)\n");
10070 env
->daif
&= ~(CPSR_AIF
& mask
);
10071 env
->daif
|= val
& CPSR_AIF
& mask
;
10073 if (write_type
!= CPSRWriteRaw
&&
10074 ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
)) {
10075 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_USR
) {
10077 * Note that we can only get here in USR mode if this is a
10078 * gdb stub write; for this case we follow the architectural
10079 * behaviour for guest writes in USR mode of ignoring an attempt
10080 * to switch mode. (Those are caught by translate.c for writes
10081 * triggered by guest instructions.)
10084 } else if (bad_mode_switch(env
, val
& CPSR_M
, write_type
)) {
10086 * Attempt to switch to an invalid mode: this is UNPREDICTABLE in
10087 * v7, and has defined behaviour in v8:
10088 * + leave CPSR.M untouched
10089 * + allow changes to the other CPSR fields
10091 * For user changes via the GDB stub, we don't set PSTATE.IL,
10092 * as this would be unnecessarily harsh for a user error.
10095 if (write_type
!= CPSRWriteByGDBStub
&&
10096 arm_feature(env
, ARM_FEATURE_V8
)) {
10100 qemu_log_mask(LOG_GUEST_ERROR
,
10101 "Illegal AArch32 mode switch attempt from %s to %s\n",
10102 aarch32_mode_name(env
->uncached_cpsr
),
10103 aarch32_mode_name(val
));
10105 qemu_log_mask(CPU_LOG_INT
, "%s %s to %s PC 0x%" PRIx32
"\n",
10106 write_type
== CPSRWriteExceptionReturn
?
10107 "Exception return from AArch32" :
10108 "AArch32 mode switch from",
10109 aarch32_mode_name(env
->uncached_cpsr
),
10110 aarch32_mode_name(val
), env
->regs
[15]);
10111 switch_mode(env
, val
& CPSR_M
);
10114 mask
&= ~CACHED_CPSR_BITS
;
10115 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
10116 if (tcg_enabled() && rebuild_hflags
) {
10117 arm_rebuild_hflags(env
);
10121 /* Sign/zero extend */
10122 uint32_t HELPER(sxtb16
)(uint32_t x
)
10125 res
= (uint16_t)(int8_t)x
;
10126 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
10130 static void handle_possible_div0_trap(CPUARMState
*env
, uintptr_t ra
)
10133 * Take a division-by-zero exception if necessary; otherwise return
10134 * to get the usual non-trapping division behaviour (result of 0)
10136 if (arm_feature(env
, ARM_FEATURE_M
)
10137 && (env
->v7m
.ccr
[env
->v7m
.secure
] & R_V7M_CCR_DIV_0_TRP_MASK
)) {
10138 raise_exception_ra(env
, EXCP_DIVBYZERO
, 0, 1, ra
);
10142 uint32_t HELPER(uxtb16
)(uint32_t x
)
10145 res
= (uint16_t)(uint8_t)x
;
10146 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
10150 int32_t HELPER(sdiv
)(CPUARMState
*env
, int32_t num
, int32_t den
)
10153 handle_possible_div0_trap(env
, GETPC());
10156 if (num
== INT_MIN
&& den
== -1) {
10162 uint32_t HELPER(udiv
)(CPUARMState
*env
, uint32_t num
, uint32_t den
)
10165 handle_possible_div0_trap(env
, GETPC());
10171 uint32_t HELPER(rbit
)(uint32_t x
)
10173 return revbit32(x
);
10176 #ifdef CONFIG_USER_ONLY
10178 static void switch_mode(CPUARMState
*env
, int mode
)
10180 ARMCPU
*cpu
= env_archcpu(env
);
10182 if (mode
!= ARM_CPU_MODE_USR
) {
10183 cpu_abort(CPU(cpu
), "Tried to switch out of user mode\n");
10187 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
10188 uint32_t cur_el
, bool secure
)
10193 void aarch64_sync_64_to_32(CPUARMState
*env
)
10195 g_assert_not_reached();
10200 static void switch_mode(CPUARMState
*env
, int mode
)
10205 old_mode
= env
->uncached_cpsr
& CPSR_M
;
10206 if (mode
== old_mode
) {
10210 if (old_mode
== ARM_CPU_MODE_FIQ
) {
10211 memcpy(env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
10212 memcpy(env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
10213 } else if (mode
== ARM_CPU_MODE_FIQ
) {
10214 memcpy(env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
10215 memcpy(env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
10218 i
= bank_number(old_mode
);
10219 env
->banked_r13
[i
] = env
->regs
[13];
10220 env
->banked_spsr
[i
] = env
->spsr
;
10222 i
= bank_number(mode
);
10223 env
->regs
[13] = env
->banked_r13
[i
];
10224 env
->spsr
= env
->banked_spsr
[i
];
10226 env
->banked_r14
[r14_bank_number(old_mode
)] = env
->regs
[14];
10227 env
->regs
[14] = env
->banked_r14
[r14_bank_number(mode
)];
10231 * Physical Interrupt Target EL Lookup Table
10233 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
10235 * The below multi-dimensional table is used for looking up the target
10236 * exception level given numerous condition criteria. Specifically, the
10237 * target EL is based on SCR and HCR routing controls as well as the
10238 * currently executing EL and secure state.
10241 * target_el_table[2][2][2][2][2][4]
10242 * | | | | | +--- Current EL
10243 * | | | | +------ Non-secure(0)/Secure(1)
10244 * | | | +--------- HCR mask override
10245 * | | +------------ SCR exec state control
10246 * | +--------------- SCR mask override
10247 * +------------------ 32-bit(0)/64-bit(1) EL3
10249 * The table values are as such:
10251 * -1 = Cannot occur
10253 * The ARM ARM target EL table includes entries indicating that an "exception
10254 * is not taken". The two cases where this is applicable are:
10255 * 1) An exception is taken from EL3 but the SCR does not have the exception
10257 * 2) An exception is taken from EL2 but the HCR does not have the exception
10259 * In these two cases, the below table contain a target of EL1. This value is
10260 * returned as it is expected that the consumer of the table data will check
10261 * for "target EL >= current EL" to ensure the exception is not taken.
10265 * BIT IRQ IMO Non-secure Secure
10266 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
10268 static const int8_t target_el_table
[2][2][2][2][2][4] = {
10269 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
10270 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
10271 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
10272 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
10273 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
10274 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
10275 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
10276 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
10277 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
10278 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 2, 2, -1, 1 },},},
10279 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, 1, 1 },},
10280 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 2, 2, 2, 1 },},},},
10281 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
10282 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
10283 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},
10284 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},},},},
10288 * Determine the target EL for physical exceptions
10290 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
10291 uint32_t cur_el
, bool secure
)
10293 CPUARMState
*env
= cpu_env(cs
);
10298 /* Is the highest EL AArch64? */
10299 bool is64
= arm_feature(env
, ARM_FEATURE_AARCH64
);
10302 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
10303 rw
= ((env
->cp15
.scr_el3
& SCR_RW
) == SCR_RW
);
10306 * Either EL2 is the highest EL (and so the EL2 register width
10307 * is given by is64); or there is no EL2 or EL3, in which case
10308 * the value of 'rw' does not affect the table lookup anyway.
10313 hcr_el2
= arm_hcr_el2_eff(env
);
10314 switch (excp_idx
) {
10316 scr
= ((env
->cp15
.scr_el3
& SCR_IRQ
) == SCR_IRQ
);
10317 hcr
= hcr_el2
& HCR_IMO
;
10320 scr
= ((env
->cp15
.scr_el3
& SCR_FIQ
) == SCR_FIQ
);
10321 hcr
= hcr_el2
& HCR_FMO
;
10324 scr
= ((env
->cp15
.scr_el3
& SCR_EA
) == SCR_EA
);
10325 hcr
= hcr_el2
& HCR_AMO
;
10330 * For these purposes, TGE and AMO/IMO/FMO both force the
10331 * interrupt to EL2. Fold TGE into the bit extracted above.
10333 hcr
|= (hcr_el2
& HCR_TGE
) != 0;
10335 /* Perform a table-lookup for the target EL given the current state */
10336 target_el
= target_el_table
[is64
][scr
][rw
][hcr
][secure
][cur_el
];
10338 assert(target_el
> 0);
10343 void arm_log_exception(CPUState
*cs
)
10345 int idx
= cs
->exception_index
;
10347 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
10348 const char *exc
= NULL
;
10349 static const char * const excnames
[] = {
10350 [EXCP_UDEF
] = "Undefined Instruction",
10351 [EXCP_SWI
] = "SVC",
10352 [EXCP_PREFETCH_ABORT
] = "Prefetch Abort",
10353 [EXCP_DATA_ABORT
] = "Data Abort",
10354 [EXCP_IRQ
] = "IRQ",
10355 [EXCP_FIQ
] = "FIQ",
10356 [EXCP_BKPT
] = "Breakpoint",
10357 [EXCP_EXCEPTION_EXIT
] = "QEMU v7M exception exit",
10358 [EXCP_KERNEL_TRAP
] = "QEMU intercept of kernel commpage",
10359 [EXCP_HVC
] = "Hypervisor Call",
10360 [EXCP_HYP_TRAP
] = "Hypervisor Trap",
10361 [EXCP_SMC
] = "Secure Monitor Call",
10362 [EXCP_VIRQ
] = "Virtual IRQ",
10363 [EXCP_VFIQ
] = "Virtual FIQ",
10364 [EXCP_SEMIHOST
] = "Semihosting call",
10365 [EXCP_NOCP
] = "v7M NOCP UsageFault",
10366 [EXCP_INVSTATE
] = "v7M INVSTATE UsageFault",
10367 [EXCP_STKOF
] = "v8M STKOF UsageFault",
10368 [EXCP_LAZYFP
] = "v7M exception during lazy FP stacking",
10369 [EXCP_LSERR
] = "v8M LSERR UsageFault",
10370 [EXCP_UNALIGNED
] = "v7M UNALIGNED UsageFault",
10371 [EXCP_DIVBYZERO
] = "v7M DIVBYZERO UsageFault",
10372 [EXCP_VSERR
] = "Virtual SERR",
10373 [EXCP_GPC
] = "Granule Protection Check",
10376 if (idx
>= 0 && idx
< ARRAY_SIZE(excnames
)) {
10377 exc
= excnames
[idx
];
10382 qemu_log_mask(CPU_LOG_INT
, "Taking exception %d [%s] on CPU %d\n",
10383 idx
, exc
, cs
->cpu_index
);
10388 * Function used to synchronize QEMU's AArch64 register set with AArch32
10389 * register set. This is necessary when switching between AArch32 and AArch64
10392 void aarch64_sync_32_to_64(CPUARMState
*env
)
10395 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
10397 /* We can blanket copy R[0:7] to X[0:7] */
10398 for (i
= 0; i
< 8; i
++) {
10399 env
->xregs
[i
] = env
->regs
[i
];
10403 * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
10404 * Otherwise, they come from the banked user regs.
10406 if (mode
== ARM_CPU_MODE_FIQ
) {
10407 for (i
= 8; i
< 13; i
++) {
10408 env
->xregs
[i
] = env
->usr_regs
[i
- 8];
10411 for (i
= 8; i
< 13; i
++) {
10412 env
->xregs
[i
] = env
->regs
[i
];
10417 * Registers x13-x23 are the various mode SP and FP registers. Registers
10418 * r13 and r14 are only copied if we are in that mode, otherwise we copy
10419 * from the mode banked register.
10421 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
10422 env
->xregs
[13] = env
->regs
[13];
10423 env
->xregs
[14] = env
->regs
[14];
10425 env
->xregs
[13] = env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)];
10426 /* HYP is an exception in that it is copied from r14 */
10427 if (mode
== ARM_CPU_MODE_HYP
) {
10428 env
->xregs
[14] = env
->regs
[14];
10430 env
->xregs
[14] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)];
10434 if (mode
== ARM_CPU_MODE_HYP
) {
10435 env
->xregs
[15] = env
->regs
[13];
10437 env
->xregs
[15] = env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)];
10440 if (mode
== ARM_CPU_MODE_IRQ
) {
10441 env
->xregs
[16] = env
->regs
[14];
10442 env
->xregs
[17] = env
->regs
[13];
10444 env
->xregs
[16] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)];
10445 env
->xregs
[17] = env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)];
10448 if (mode
== ARM_CPU_MODE_SVC
) {
10449 env
->xregs
[18] = env
->regs
[14];
10450 env
->xregs
[19] = env
->regs
[13];
10452 env
->xregs
[18] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)];
10453 env
->xregs
[19] = env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)];
10456 if (mode
== ARM_CPU_MODE_ABT
) {
10457 env
->xregs
[20] = env
->regs
[14];
10458 env
->xregs
[21] = env
->regs
[13];
10460 env
->xregs
[20] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)];
10461 env
->xregs
[21] = env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)];
10464 if (mode
== ARM_CPU_MODE_UND
) {
10465 env
->xregs
[22] = env
->regs
[14];
10466 env
->xregs
[23] = env
->regs
[13];
10468 env
->xregs
[22] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)];
10469 env
->xregs
[23] = env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)];
10473 * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
10474 * mode, then we can copy from r8-r14. Otherwise, we copy from the
10475 * FIQ bank for r8-r14.
10477 if (mode
== ARM_CPU_MODE_FIQ
) {
10478 for (i
= 24; i
< 31; i
++) {
10479 env
->xregs
[i
] = env
->regs
[i
- 16]; /* X[24:30] <- R[8:14] */
10482 for (i
= 24; i
< 29; i
++) {
10483 env
->xregs
[i
] = env
->fiq_regs
[i
- 24];
10485 env
->xregs
[29] = env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)];
10486 env
->xregs
[30] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)];
10489 env
->pc
= env
->regs
[15];
10493 * Function used to synchronize QEMU's AArch32 register set with AArch64
10494 * register set. This is necessary when switching between AArch32 and AArch64
10497 void aarch64_sync_64_to_32(CPUARMState
*env
)
10500 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
10502 /* We can blanket copy X[0:7] to R[0:7] */
10503 for (i
= 0; i
< 8; i
++) {
10504 env
->regs
[i
] = env
->xregs
[i
];
10508 * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
10509 * Otherwise, we copy x8-x12 into the banked user regs.
10511 if (mode
== ARM_CPU_MODE_FIQ
) {
10512 for (i
= 8; i
< 13; i
++) {
10513 env
->usr_regs
[i
- 8] = env
->xregs
[i
];
10516 for (i
= 8; i
< 13; i
++) {
10517 env
->regs
[i
] = env
->xregs
[i
];
10522 * Registers r13 & r14 depend on the current mode.
10523 * If we are in a given mode, we copy the corresponding x registers to r13
10524 * and r14. Otherwise, we copy the x register to the banked r13 and r14
10527 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
10528 env
->regs
[13] = env
->xregs
[13];
10529 env
->regs
[14] = env
->xregs
[14];
10531 env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[13];
10534 * HYP is an exception in that it does not have its own banked r14 but
10535 * shares the USR r14
10537 if (mode
== ARM_CPU_MODE_HYP
) {
10538 env
->regs
[14] = env
->xregs
[14];
10540 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[14];
10544 if (mode
== ARM_CPU_MODE_HYP
) {
10545 env
->regs
[13] = env
->xregs
[15];
10547 env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)] = env
->xregs
[15];
10550 if (mode
== ARM_CPU_MODE_IRQ
) {
10551 env
->regs
[14] = env
->xregs
[16];
10552 env
->regs
[13] = env
->xregs
[17];
10554 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[16];
10555 env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[17];
10558 if (mode
== ARM_CPU_MODE_SVC
) {
10559 env
->regs
[14] = env
->xregs
[18];
10560 env
->regs
[13] = env
->xregs
[19];
10562 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[18];
10563 env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[19];
10566 if (mode
== ARM_CPU_MODE_ABT
) {
10567 env
->regs
[14] = env
->xregs
[20];
10568 env
->regs
[13] = env
->xregs
[21];
10570 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[20];
10571 env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[21];
10574 if (mode
== ARM_CPU_MODE_UND
) {
10575 env
->regs
[14] = env
->xregs
[22];
10576 env
->regs
[13] = env
->xregs
[23];
10578 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[22];
10579 env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[23];
10583 * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
10584 * mode, then we can copy to r8-r14. Otherwise, we copy to the
10585 * FIQ bank for r8-r14.
10587 if (mode
== ARM_CPU_MODE_FIQ
) {
10588 for (i
= 24; i
< 31; i
++) {
10589 env
->regs
[i
- 16] = env
->xregs
[i
]; /* X[24:30] -> R[8:14] */
10592 for (i
= 24; i
< 29; i
++) {
10593 env
->fiq_regs
[i
- 24] = env
->xregs
[i
];
10595 env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[29];
10596 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[30];
10599 env
->regs
[15] = env
->pc
;
10602 static void take_aarch32_exception(CPUARMState
*env
, int new_mode
,
10603 uint32_t mask
, uint32_t offset
,
10608 /* Change the CPU state so as to actually take the exception. */
10609 switch_mode(env
, new_mode
);
10612 * For exceptions taken to AArch32 we must clear the SS bit in both
10613 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
10615 env
->pstate
&= ~PSTATE_SS
;
10616 env
->spsr
= cpsr_read(env
);
10617 /* Clear IT bits. */
10618 env
->condexec_bits
= 0;
10619 /* Switch to the new mode, and to the correct instruction set. */
10620 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
10622 /* This must be after mode switching. */
10623 new_el
= arm_current_el(env
);
10625 /* Set new mode endianness */
10626 env
->uncached_cpsr
&= ~CPSR_E
;
10627 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_EE
) {
10628 env
->uncached_cpsr
|= CPSR_E
;
10630 /* J and IL must always be cleared for exception entry */
10631 env
->uncached_cpsr
&= ~(CPSR_IL
| CPSR_J
);
10634 if (cpu_isar_feature(aa32_ssbs
, env_archcpu(env
))) {
10635 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_DSSBS_32
) {
10636 env
->uncached_cpsr
|= CPSR_SSBS
;
10638 env
->uncached_cpsr
&= ~CPSR_SSBS
;
10642 if (new_mode
== ARM_CPU_MODE_HYP
) {
10643 env
->thumb
= (env
->cp15
.sctlr_el
[2] & SCTLR_TE
) != 0;
10644 env
->elr_el
[2] = env
->regs
[15];
10646 /* CPSR.PAN is normally preserved preserved unless... */
10647 if (cpu_isar_feature(aa32_pan
, env_archcpu(env
))) {
10650 if (!arm_is_secure_below_el3(env
)) {
10651 /* ... the target is EL3, from non-secure state. */
10652 env
->uncached_cpsr
&= ~CPSR_PAN
;
10655 /* ... the target is EL3, from secure state ... */
10658 /* ... the target is EL1 and SCTLR.SPAN is 0. */
10659 if (!(env
->cp15
.sctlr_el
[new_el
] & SCTLR_SPAN
)) {
10660 env
->uncached_cpsr
|= CPSR_PAN
;
10666 * this is a lie, as there was no c1_sys on V4T/V5, but who cares
10667 * and we should just guard the thumb mode on V4
10669 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
10671 (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_TE
) != 0;
10673 env
->regs
[14] = env
->regs
[15] + offset
;
10675 env
->regs
[15] = newpc
;
10677 if (tcg_enabled()) {
10678 arm_rebuild_hflags(env
);
10682 static void arm_cpu_do_interrupt_aarch32_hyp(CPUState
*cs
)
10685 * Handle exception entry to Hyp mode; this is sufficiently
10686 * different to entry to other AArch32 modes that we handle it
10689 * The vector table entry used is always the 0x14 Hyp mode entry point,
10690 * unless this is an UNDEF/SVC/HVC/abort taken from Hyp to Hyp.
10691 * The offset applied to the preferred return address is always zero
10692 * (see DDI0487C.a section G1.12.3).
10693 * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values.
10695 uint32_t addr
, mask
;
10696 ARMCPU
*cpu
= ARM_CPU(cs
);
10697 CPUARMState
*env
= &cpu
->env
;
10699 switch (cs
->exception_index
) {
10707 /* Fall through to prefetch abort. */
10708 case EXCP_PREFETCH_ABORT
:
10709 env
->cp15
.ifar_s
= env
->exception
.vaddress
;
10710 qemu_log_mask(CPU_LOG_INT
, "...with HIFAR 0x%x\n",
10711 (uint32_t)env
->exception
.vaddress
);
10714 case EXCP_DATA_ABORT
:
10715 env
->cp15
.dfar_s
= env
->exception
.vaddress
;
10716 qemu_log_mask(CPU_LOG_INT
, "...with HDFAR 0x%x\n",
10717 (uint32_t)env
->exception
.vaddress
);
10729 case EXCP_HYP_TRAP
:
10733 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
10736 if (cs
->exception_index
!= EXCP_IRQ
&& cs
->exception_index
!= EXCP_FIQ
) {
10737 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
10739 * QEMU syndrome values are v8-style. v7 has the IL bit
10740 * UNK/SBZP for "field not valid" cases, where v8 uses RES1.
10741 * If this is a v7 CPU, squash the IL bit in those cases.
10743 if (cs
->exception_index
== EXCP_PREFETCH_ABORT
||
10744 (cs
->exception_index
== EXCP_DATA_ABORT
&&
10745 !(env
->exception
.syndrome
& ARM_EL_ISV
)) ||
10746 syn_get_ec(env
->exception
.syndrome
) == EC_UNCATEGORIZED
) {
10747 env
->exception
.syndrome
&= ~ARM_EL_IL
;
10750 env
->cp15
.esr_el
[2] = env
->exception
.syndrome
;
10753 if (arm_current_el(env
) != 2 && addr
< 0x14) {
10758 if (!(env
->cp15
.scr_el3
& SCR_EA
)) {
10761 if (!(env
->cp15
.scr_el3
& SCR_IRQ
)) {
10764 if (!(env
->cp15
.scr_el3
& SCR_FIQ
)) {
10768 addr
+= env
->cp15
.hvbar
;
10770 take_aarch32_exception(env
, ARM_CPU_MODE_HYP
, mask
, 0, addr
);
10773 static void arm_cpu_do_interrupt_aarch32(CPUState
*cs
)
10775 ARMCPU
*cpu
= ARM_CPU(cs
);
10776 CPUARMState
*env
= &cpu
->env
;
10783 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
10784 switch (syn_get_ec(env
->exception
.syndrome
)) {
10785 case EC_BREAKPOINT
:
10786 case EC_BREAKPOINT_SAME_EL
:
10789 case EC_WATCHPOINT
:
10790 case EC_WATCHPOINT_SAME_EL
:
10796 case EC_VECTORCATCH
:
10805 env
->cp15
.mdscr_el1
= deposit64(env
->cp15
.mdscr_el1
, 2, 4, moe
);
10808 if (env
->exception
.target_el
== 2) {
10809 arm_cpu_do_interrupt_aarch32_hyp(cs
);
10813 switch (cs
->exception_index
) {
10815 new_mode
= ARM_CPU_MODE_UND
;
10825 new_mode
= ARM_CPU_MODE_SVC
;
10828 /* The PC already points to the next instruction. */
10832 /* Fall through to prefetch abort. */
10833 case EXCP_PREFETCH_ABORT
:
10834 A32_BANKED_CURRENT_REG_SET(env
, ifsr
, env
->exception
.fsr
);
10835 A32_BANKED_CURRENT_REG_SET(env
, ifar
, env
->exception
.vaddress
);
10836 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x IFAR 0x%x\n",
10837 env
->exception
.fsr
, (uint32_t)env
->exception
.vaddress
);
10838 new_mode
= ARM_CPU_MODE_ABT
;
10840 mask
= CPSR_A
| CPSR_I
;
10843 case EXCP_DATA_ABORT
:
10844 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
10845 A32_BANKED_CURRENT_REG_SET(env
, dfar
, env
->exception
.vaddress
);
10846 qemu_log_mask(CPU_LOG_INT
, "...with DFSR 0x%x DFAR 0x%x\n",
10847 env
->exception
.fsr
,
10848 (uint32_t)env
->exception
.vaddress
);
10849 new_mode
= ARM_CPU_MODE_ABT
;
10851 mask
= CPSR_A
| CPSR_I
;
10855 new_mode
= ARM_CPU_MODE_IRQ
;
10857 /* Disable IRQ and imprecise data aborts. */
10858 mask
= CPSR_A
| CPSR_I
;
10860 if (env
->cp15
.scr_el3
& SCR_IRQ
) {
10861 /* IRQ routed to monitor mode */
10862 new_mode
= ARM_CPU_MODE_MON
;
10867 new_mode
= ARM_CPU_MODE_FIQ
;
10869 /* Disable FIQ, IRQ and imprecise data aborts. */
10870 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
10871 if (env
->cp15
.scr_el3
& SCR_FIQ
) {
10872 /* FIQ routed to monitor mode */
10873 new_mode
= ARM_CPU_MODE_MON
;
10878 new_mode
= ARM_CPU_MODE_IRQ
;
10880 /* Disable IRQ and imprecise data aborts. */
10881 mask
= CPSR_A
| CPSR_I
;
10885 new_mode
= ARM_CPU_MODE_FIQ
;
10887 /* Disable FIQ, IRQ and imprecise data aborts. */
10888 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
10894 * Note that this is reported as a data abort, but the DFAR
10895 * has an UNKNOWN value. Construct the SError syndrome from
10896 * AET and ExT fields.
10898 ARMMMUFaultInfo fi
= { .type
= ARMFault_AsyncExternal
, };
10900 if (extended_addresses_enabled(env
)) {
10901 env
->exception
.fsr
= arm_fi_to_lfsc(&fi
);
10903 env
->exception
.fsr
= arm_fi_to_sfsc(&fi
);
10905 env
->exception
.fsr
|= env
->cp15
.vsesr_el2
& 0xd000;
10906 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
10907 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x\n",
10908 env
->exception
.fsr
);
10910 new_mode
= ARM_CPU_MODE_ABT
;
10912 mask
= CPSR_A
| CPSR_I
;
10917 new_mode
= ARM_CPU_MODE_MON
;
10919 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
10923 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
10924 return; /* Never happens. Keep compiler happy. */
10927 if (new_mode
== ARM_CPU_MODE_MON
) {
10928 addr
+= env
->cp15
.mvbar
;
10929 } else if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
10930 /* High vectors. When enabled, base address cannot be remapped. */
10931 addr
+= 0xffff0000;
10934 * ARM v7 architectures provide a vector base address register to remap
10935 * the interrupt vector table.
10936 * This register is only followed in non-monitor mode, and is banked.
10937 * Note: only bits 31:5 are valid.
10939 addr
+= A32_BANKED_CURRENT_REG_GET(env
, vbar
);
10942 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
10943 env
->cp15
.scr_el3
&= ~SCR_NS
;
10946 take_aarch32_exception(env
, new_mode
, mask
, offset
, addr
);
10949 static int aarch64_regnum(CPUARMState
*env
, int aarch32_reg
)
10952 * Return the register number of the AArch64 view of the AArch32
10953 * register @aarch32_reg. The CPUARMState CPSR is assumed to still
10954 * be that of the AArch32 mode the exception came from.
10956 int mode
= env
->uncached_cpsr
& CPSR_M
;
10958 switch (aarch32_reg
) {
10960 return aarch32_reg
;
10962 return mode
== ARM_CPU_MODE_FIQ
? aarch32_reg
+ 16 : aarch32_reg
;
10965 case ARM_CPU_MODE_USR
:
10966 case ARM_CPU_MODE_SYS
:
10968 case ARM_CPU_MODE_HYP
:
10970 case ARM_CPU_MODE_IRQ
:
10972 case ARM_CPU_MODE_SVC
:
10974 case ARM_CPU_MODE_ABT
:
10976 case ARM_CPU_MODE_UND
:
10978 case ARM_CPU_MODE_FIQ
:
10981 g_assert_not_reached();
10985 case ARM_CPU_MODE_USR
:
10986 case ARM_CPU_MODE_SYS
:
10987 case ARM_CPU_MODE_HYP
:
10989 case ARM_CPU_MODE_IRQ
:
10991 case ARM_CPU_MODE_SVC
:
10993 case ARM_CPU_MODE_ABT
:
10995 case ARM_CPU_MODE_UND
:
10997 case ARM_CPU_MODE_FIQ
:
11000 g_assert_not_reached();
11005 g_assert_not_reached();
11009 static uint32_t cpsr_read_for_spsr_elx(CPUARMState
*env
)
11011 uint32_t ret
= cpsr_read(env
);
11013 /* Move DIT to the correct location for SPSR_ELx */
11014 if (ret
& CPSR_DIT
) {
11018 /* Merge PSTATE.SS into SPSR_ELx */
11019 ret
|= env
->pstate
& PSTATE_SS
;
11024 static bool syndrome_is_sync_extabt(uint32_t syndrome
)
11026 /* Return true if this syndrome value is a synchronous external abort */
11027 switch (syn_get_ec(syndrome
)) {
11029 case EC_INSNABORT_SAME_EL
:
11031 case EC_DATAABORT_SAME_EL
:
11032 /* Look at fault status code for all the synchronous ext abort cases */
11033 switch (syndrome
& 0x3f) {
11049 /* Handle exception entry to a target EL which is using AArch64 */
11050 static void arm_cpu_do_interrupt_aarch64(CPUState
*cs
)
11052 ARMCPU
*cpu
= ARM_CPU(cs
);
11053 CPUARMState
*env
= &cpu
->env
;
11054 unsigned int new_el
= env
->exception
.target_el
;
11055 target_ulong addr
= env
->cp15
.vbar_el
[new_el
];
11056 unsigned int new_mode
= aarch64_pstate_mode(new_el
, true);
11057 unsigned int old_mode
;
11058 unsigned int cur_el
= arm_current_el(env
);
11061 if (tcg_enabled()) {
11063 * Note that new_el can never be 0. If cur_el is 0, then
11064 * el0_a64 is is_a64(), else el0_a64 is ignored.
11066 aarch64_sve_change_el(env
, cur_el
, new_el
, is_a64(env
));
11069 if (cur_el
< new_el
) {
11071 * Entry vector offset depends on whether the implemented EL
11072 * immediately lower than the target level is using AArch32 or AArch64
11079 is_aa64
= (env
->cp15
.scr_el3
& SCR_RW
) != 0;
11082 hcr
= arm_hcr_el2_eff(env
);
11083 if ((hcr
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
11084 is_aa64
= (hcr
& HCR_RW
) != 0;
11089 is_aa64
= is_a64(env
);
11092 g_assert_not_reached();
11100 } else if (pstate_read(env
) & PSTATE_SP
) {
11104 switch (cs
->exception_index
) {
11106 qemu_log_mask(CPU_LOG_INT
, "...with MFAR 0x%" PRIx64
"\n",
11107 env
->cp15
.mfar_el3
);
11109 case EXCP_PREFETCH_ABORT
:
11110 case EXCP_DATA_ABORT
:
11112 * FEAT_DoubleFault allows synchronous external aborts taken to EL3
11113 * to be taken to the SError vector entrypoint.
11115 if (new_el
== 3 && (env
->cp15
.scr_el3
& SCR_EASE
) &&
11116 syndrome_is_sync_extabt(env
->exception
.syndrome
)) {
11119 env
->cp15
.far_el
[new_el
] = env
->exception
.vaddress
;
11120 qemu_log_mask(CPU_LOG_INT
, "...with FAR 0x%" PRIx64
"\n",
11121 env
->cp15
.far_el
[new_el
]);
11127 case EXCP_HYP_TRAP
:
11129 switch (syn_get_ec(env
->exception
.syndrome
)) {
11130 case EC_ADVSIMDFPACCESSTRAP
:
11132 * QEMU internal FP/SIMD syndromes from AArch32 include the
11133 * TA and coproc fields which are only exposed if the exception
11134 * is taken to AArch32 Hyp mode. Mask them out to get a valid
11135 * AArch64 format syndrome.
11137 env
->exception
.syndrome
&= ~MAKE_64BIT_MASK(0, 20);
11139 case EC_CP14RTTRAP
:
11140 case EC_CP15RTTRAP
:
11141 case EC_CP14DTTRAP
:
11143 * For a trap on AArch32 MRC/MCR/LDC/STC the Rt field is currently
11144 * the raw register field from the insn; when taking this to
11145 * AArch64 we must convert it to the AArch64 view of the register
11146 * number. Notice that we read a 4-bit AArch32 register number and
11147 * write back a 5-bit AArch64 one.
11149 rt
= extract32(env
->exception
.syndrome
, 5, 4);
11150 rt
= aarch64_regnum(env
, rt
);
11151 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
11154 case EC_CP15RRTTRAP
:
11155 case EC_CP14RRTTRAP
:
11156 /* Similarly for MRRC/MCRR traps for Rt and Rt2 fields */
11157 rt
= extract32(env
->exception
.syndrome
, 5, 4);
11158 rt
= aarch64_regnum(env
, rt
);
11159 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
11161 rt
= extract32(env
->exception
.syndrome
, 10, 4);
11162 rt
= aarch64_regnum(env
, rt
);
11163 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
11167 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
11179 /* Construct the SError syndrome from IDS and ISS fields. */
11180 env
->exception
.syndrome
= syn_serror(env
->cp15
.vsesr_el2
& 0x1ffffff);
11181 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
11184 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
11188 old_mode
= pstate_read(env
);
11189 aarch64_save_sp(env
, arm_current_el(env
));
11190 env
->elr_el
[new_el
] = env
->pc
;
11192 old_mode
= cpsr_read_for_spsr_elx(env
);
11193 env
->elr_el
[new_el
] = env
->regs
[15];
11195 aarch64_sync_32_to_64(env
);
11197 env
->condexec_bits
= 0;
11199 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = old_mode
;
11201 qemu_log_mask(CPU_LOG_INT
, "...with ELR 0x%" PRIx64
"\n",
11202 env
->elr_el
[new_el
]);
11204 if (cpu_isar_feature(aa64_pan
, cpu
)) {
11205 /* The value of PSTATE.PAN is normally preserved, except when ... */
11206 new_mode
|= old_mode
& PSTATE_PAN
;
11209 /* ... the target is EL2 with HCR_EL2.{E2H,TGE} == '11' ... */
11210 if ((arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
))
11211 != (HCR_E2H
| HCR_TGE
)) {
11216 /* ... the target is EL1 ... */
11217 /* ... and SCTLR_ELx.SPAN == 0, then set to 1. */
11218 if ((env
->cp15
.sctlr_el
[new_el
] & SCTLR_SPAN
) == 0) {
11219 new_mode
|= PSTATE_PAN
;
11224 if (cpu_isar_feature(aa64_mte
, cpu
)) {
11225 new_mode
|= PSTATE_TCO
;
11228 if (cpu_isar_feature(aa64_ssbs
, cpu
)) {
11229 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_DSSBS_64
) {
11230 new_mode
|= PSTATE_SSBS
;
11232 new_mode
&= ~PSTATE_SSBS
;
11236 pstate_write(env
, PSTATE_DAIF
| new_mode
);
11237 env
->aarch64
= true;
11238 aarch64_restore_sp(env
, new_el
);
11240 if (tcg_enabled()) {
11241 helper_rebuild_hflags_a64(env
, new_el
);
11246 qemu_log_mask(CPU_LOG_INT
, "...to EL%d PC 0x%" PRIx64
" PSTATE 0x%x\n",
11247 new_el
, env
->pc
, pstate_read(env
));
11251 * Do semihosting call and set the appropriate return value. All the
11252 * permission and validity checks have been done at translate time.
11254 * We only see semihosting exceptions in TCG only as they are not
11255 * trapped to the hypervisor in KVM.
11258 static void tcg_handle_semihosting(CPUState
*cs
)
11260 ARMCPU
*cpu
= ARM_CPU(cs
);
11261 CPUARMState
*env
= &cpu
->env
;
11264 qemu_log_mask(CPU_LOG_INT
,
11265 "...handling as semihosting call 0x%" PRIx64
"\n",
11267 do_common_semihosting(cs
);
11270 qemu_log_mask(CPU_LOG_INT
,
11271 "...handling as semihosting call 0x%x\n",
11273 do_common_semihosting(cs
);
11274 env
->regs
[15] += env
->thumb
? 2 : 4;
11280 * Handle a CPU exception for A and R profile CPUs.
11281 * Do any appropriate logging, handle PSCI calls, and then hand off
11282 * to the AArch64-entry or AArch32-entry function depending on the
11283 * target exception level's register width.
11285 * Note: this is used for both TCG (as the do_interrupt tcg op),
11286 * and KVM to re-inject guest debug exceptions, and to
11287 * inject a Synchronous-External-Abort.
11289 void arm_cpu_do_interrupt(CPUState
*cs
)
11291 ARMCPU
*cpu
= ARM_CPU(cs
);
11292 CPUARMState
*env
= &cpu
->env
;
11293 unsigned int new_el
= env
->exception
.target_el
;
11295 assert(!arm_feature(env
, ARM_FEATURE_M
));
11297 arm_log_exception(cs
);
11298 qemu_log_mask(CPU_LOG_INT
, "...from EL%d to EL%d\n", arm_current_el(env
),
11300 if (qemu_loglevel_mask(CPU_LOG_INT
)
11301 && !excp_is_internal(cs
->exception_index
)) {
11302 qemu_log_mask(CPU_LOG_INT
, "...with ESR 0x%x/0x%" PRIx32
"\n",
11303 syn_get_ec(env
->exception
.syndrome
),
11304 env
->exception
.syndrome
);
11307 if (tcg_enabled() && arm_is_psci_call(cpu
, cs
->exception_index
)) {
11308 arm_handle_psci_call(cpu
);
11309 qemu_log_mask(CPU_LOG_INT
, "...handled as PSCI call\n");
11314 * Semihosting semantics depend on the register width of the code
11315 * that caused the exception, not the target exception level, so
11316 * must be handled here.
11319 if (cs
->exception_index
== EXCP_SEMIHOST
) {
11320 tcg_handle_semihosting(cs
);
11326 * Hooks may change global state so BQL should be held, also the
11327 * BQL needs to be held for any modification of
11328 * cs->interrupt_request.
11330 g_assert(qemu_mutex_iothread_locked());
11332 arm_call_pre_el_change_hook(cpu
);
11334 assert(!excp_is_internal(cs
->exception_index
));
11335 if (arm_el_is_aa64(env
, new_el
)) {
11336 arm_cpu_do_interrupt_aarch64(cs
);
11338 arm_cpu_do_interrupt_aarch32(cs
);
11341 arm_call_el_change_hook(cpu
);
11343 if (!kvm_enabled()) {
11344 cs
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
11347 #endif /* !CONFIG_USER_ONLY */
11349 uint64_t arm_sctlr(CPUARMState
*env
, int el
)
11351 /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */
11353 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, 0);
11354 el
= mmu_idx
== ARMMMUIdx_E20_0
? 2 : 1;
11356 return env
->cp15
.sctlr_el
[el
];
11359 int aa64_va_parameter_tbi(uint64_t tcr
, ARMMMUIdx mmu_idx
)
11361 if (regime_has_2_ranges(mmu_idx
)) {
11362 return extract64(tcr
, 37, 2);
11363 } else if (regime_is_stage2(mmu_idx
)) {
11364 return 0; /* VTCR_EL2 */
11366 /* Replicate the single TBI bit so we always have 2 bits. */
11367 return extract32(tcr
, 20, 1) * 3;
11371 int aa64_va_parameter_tbid(uint64_t tcr
, ARMMMUIdx mmu_idx
)
11373 if (regime_has_2_ranges(mmu_idx
)) {
11374 return extract64(tcr
, 51, 2);
11375 } else if (regime_is_stage2(mmu_idx
)) {
11376 return 0; /* VTCR_EL2 */
11378 /* Replicate the single TBID bit so we always have 2 bits. */
11379 return extract32(tcr
, 29, 1) * 3;
11383 int aa64_va_parameter_tcma(uint64_t tcr
, ARMMMUIdx mmu_idx
)
11385 if (regime_has_2_ranges(mmu_idx
)) {
11386 return extract64(tcr
, 57, 2);
11388 /* Replicate the single TCMA bit so we always have 2 bits. */
11389 return extract32(tcr
, 30, 1) * 3;
11393 static ARMGranuleSize
tg0_to_gran_size(int tg
)
11403 return GranInvalid
;
11407 static ARMGranuleSize
tg1_to_gran_size(int tg
)
11417 return GranInvalid
;
11421 static inline bool have4k(ARMCPU
*cpu
, bool stage2
)
11423 return stage2
? cpu_isar_feature(aa64_tgran4_2
, cpu
)
11424 : cpu_isar_feature(aa64_tgran4
, cpu
);
11427 static inline bool have16k(ARMCPU
*cpu
, bool stage2
)
11429 return stage2
? cpu_isar_feature(aa64_tgran16_2
, cpu
)
11430 : cpu_isar_feature(aa64_tgran16
, cpu
);
11433 static inline bool have64k(ARMCPU
*cpu
, bool stage2
)
11435 return stage2
? cpu_isar_feature(aa64_tgran64_2
, cpu
)
11436 : cpu_isar_feature(aa64_tgran64
, cpu
);
11439 static ARMGranuleSize
sanitize_gran_size(ARMCPU
*cpu
, ARMGranuleSize gran
,
11444 if (have4k(cpu
, stage2
)) {
11449 if (have16k(cpu
, stage2
)) {
11454 if (have64k(cpu
, stage2
)) {
11462 * If the guest selects a granule size that isn't implemented,
11463 * the architecture requires that we behave as if it selected one
11464 * that is (with an IMPDEF choice of which one to pick). We choose
11465 * to implement the smallest supported granule size.
11467 if (have4k(cpu
, stage2
)) {
11470 if (have16k(cpu
, stage2
)) {
11473 assert(have64k(cpu
, stage2
));
11477 ARMVAParameters
aa64_va_parameters(CPUARMState
*env
, uint64_t va
,
11478 ARMMMUIdx mmu_idx
, bool data
,
11481 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
11482 bool epd
, hpd
, tsz_oob
, ds
, ha
, hd
;
11483 int select
, tsz
, tbi
, max_tsz
, min_tsz
, ps
, sh
;
11484 ARMGranuleSize gran
;
11485 ARMCPU
*cpu
= env_archcpu(env
);
11486 bool stage2
= regime_is_stage2(mmu_idx
);
11488 if (!regime_has_2_ranges(mmu_idx
)) {
11490 tsz
= extract32(tcr
, 0, 6);
11491 gran
= tg0_to_gran_size(extract32(tcr
, 14, 2));
11496 hpd
= extract32(tcr
, 24, 1);
11499 sh
= extract32(tcr
, 12, 2);
11500 ps
= extract32(tcr
, 16, 3);
11501 ha
= extract32(tcr
, 21, 1) && cpu_isar_feature(aa64_hafs
, cpu
);
11502 hd
= extract32(tcr
, 22, 1) && cpu_isar_feature(aa64_hdbs
, cpu
);
11503 ds
= extract64(tcr
, 32, 1);
11508 * Bit 55 is always between the two regions, and is canonical for
11509 * determining if address tagging is enabled.
11511 select
= extract64(va
, 55, 1);
11513 tsz
= extract32(tcr
, 0, 6);
11514 gran
= tg0_to_gran_size(extract32(tcr
, 14, 2));
11515 epd
= extract32(tcr
, 7, 1);
11516 sh
= extract32(tcr
, 12, 2);
11517 hpd
= extract64(tcr
, 41, 1);
11518 e0pd
= extract64(tcr
, 55, 1);
11520 tsz
= extract32(tcr
, 16, 6);
11521 gran
= tg1_to_gran_size(extract32(tcr
, 30, 2));
11522 epd
= extract32(tcr
, 23, 1);
11523 sh
= extract32(tcr
, 28, 2);
11524 hpd
= extract64(tcr
, 42, 1);
11525 e0pd
= extract64(tcr
, 56, 1);
11527 ps
= extract64(tcr
, 32, 3);
11528 ha
= extract64(tcr
, 39, 1) && cpu_isar_feature(aa64_hafs
, cpu
);
11529 hd
= extract64(tcr
, 40, 1) && cpu_isar_feature(aa64_hdbs
, cpu
);
11530 ds
= extract64(tcr
, 59, 1);
11532 if (e0pd
&& cpu_isar_feature(aa64_e0pd
, cpu
) &&
11533 regime_is_user(env
, mmu_idx
)) {
11538 gran
= sanitize_gran_size(cpu
, gran
, stage2
);
11540 if (cpu_isar_feature(aa64_st
, cpu
)) {
11541 max_tsz
= 48 - (gran
== Gran64K
);
11547 * DS is RES0 unless FEAT_LPA2 is supported for the given page size;
11548 * adjust the effective value of DS, as documented.
11551 if (gran
== Gran64K
) {
11552 if (cpu_isar_feature(aa64_lva
, cpu
)) {
11557 if (regime_is_stage2(mmu_idx
)) {
11558 if (gran
== Gran16K
) {
11559 ds
= cpu_isar_feature(aa64_tgran16_2_lpa2
, cpu
);
11561 ds
= cpu_isar_feature(aa64_tgran4_2_lpa2
, cpu
);
11564 if (gran
== Gran16K
) {
11565 ds
= cpu_isar_feature(aa64_tgran16_lpa2
, cpu
);
11567 ds
= cpu_isar_feature(aa64_tgran4_lpa2
, cpu
);
11575 if (stage2
&& el1_is_aa32
) {
11577 * For AArch32 EL1 the min txsz (and thus max IPA size) requirements
11578 * are loosened: a configured IPA of 40 bits is permitted even if
11579 * the implemented PA is less than that (and so a 40 bit IPA would
11580 * fault for an AArch64 EL1). See R_DTLMN.
11582 min_tsz
= MIN(min_tsz
, 24);
11585 if (tsz
> max_tsz
) {
11588 } else if (tsz
< min_tsz
) {
11595 /* Present TBI as a composite with TBID. */
11596 tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
11598 tbi
&= ~aa64_va_parameter_tbid(tcr
, mmu_idx
);
11600 tbi
= (tbi
>> select
) & 1;
11602 return (ARMVAParameters
) {
11610 .tsz_oob
= tsz_oob
,
11619 * Note that signed overflow is undefined in C. The following routines are
11620 * careful to use unsigned types where modulo arithmetic is required.
11621 * Failure to do so _will_ break on newer gcc.
11624 /* Signed saturating arithmetic. */
11626 /* Perform 16-bit signed saturating addition. */
11627 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
11632 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
11642 /* Perform 8-bit signed saturating addition. */
11643 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
11648 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
11658 /* Perform 16-bit signed saturating subtraction. */
11659 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
11664 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
11674 /* Perform 8-bit signed saturating subtraction. */
11675 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
11680 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
11690 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
11691 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
11692 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
11693 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
11696 #include "op_addsub.h"
11698 /* Unsigned saturating arithmetic. */
11699 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
11709 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
11718 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
11728 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
11737 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
11738 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
11739 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
11740 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
11743 #include "op_addsub.h"
11745 /* Signed modulo arithmetic. */
11746 #define SARITH16(a, b, n, op) do { \
11748 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
11749 RESULT(sum, n, 16); \
11751 ge |= 3 << (n * 2); \
11754 #define SARITH8(a, b, n, op) do { \
11756 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
11757 RESULT(sum, n, 8); \
11763 #define ADD16(a, b, n) SARITH16(a, b, n, +)
11764 #define SUB16(a, b, n) SARITH16(a, b, n, -)
11765 #define ADD8(a, b, n) SARITH8(a, b, n, +)
11766 #define SUB8(a, b, n) SARITH8(a, b, n, -)
11770 #include "op_addsub.h"
11772 /* Unsigned modulo arithmetic. */
11773 #define ADD16(a, b, n) do { \
11775 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
11776 RESULT(sum, n, 16); \
11777 if ((sum >> 16) == 1) \
11778 ge |= 3 << (n * 2); \
11781 #define ADD8(a, b, n) do { \
11783 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
11784 RESULT(sum, n, 8); \
11785 if ((sum >> 8) == 1) \
11789 #define SUB16(a, b, n) do { \
11791 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
11792 RESULT(sum, n, 16); \
11793 if ((sum >> 16) == 0) \
11794 ge |= 3 << (n * 2); \
11797 #define SUB8(a, b, n) do { \
11799 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
11800 RESULT(sum, n, 8); \
11801 if ((sum >> 8) == 0) \
11808 #include "op_addsub.h"
11810 /* Halved signed arithmetic. */
11811 #define ADD16(a, b, n) \
11812 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
11813 #define SUB16(a, b, n) \
11814 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
11815 #define ADD8(a, b, n) \
11816 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
11817 #define SUB8(a, b, n) \
11818 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
11821 #include "op_addsub.h"
11823 /* Halved unsigned arithmetic. */
11824 #define ADD16(a, b, n) \
11825 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
11826 #define SUB16(a, b, n) \
11827 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
11828 #define ADD8(a, b, n) \
11829 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
11830 #define SUB8(a, b, n) \
11831 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
11834 #include "op_addsub.h"
11836 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
11845 /* Unsigned sum of absolute byte differences. */
11846 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
11849 sum
= do_usad(a
, b
);
11850 sum
+= do_usad(a
>> 8, b
>> 8);
11851 sum
+= do_usad(a
>> 16, b
>> 16);
11852 sum
+= do_usad(a
>> 24, b
>> 24);
11856 /* For ARMv6 SEL instruction. */
11857 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
11872 mask
|= 0xff000000;
11874 return (a
& mask
) | (b
& ~mask
);
11879 * The upper bytes of val (above the number specified by 'bytes') must have
11880 * been zeroed out by the caller.
11882 uint32_t HELPER(crc32
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
11886 stl_le_p(buf
, val
);
11888 /* zlib crc32 converts the accumulator and output to one's complement. */
11889 return crc32(acc
^ 0xffffffff, buf
, bytes
) ^ 0xffffffff;
11892 uint32_t HELPER(crc32c
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
11896 stl_le_p(buf
, val
);
11898 /* Linux crc32c converts the output to one's complement. */
11899 return crc32c(acc
, buf
, bytes
) ^ 0xffffffff;
11903 * Return the exception level to which FP-disabled exceptions should
11904 * be taken, or 0 if FP is enabled.
11906 int fp_exception_el(CPUARMState
*env
, int cur_el
)
11908 #ifndef CONFIG_USER_ONLY
11912 * CPACR and the CPTR registers don't exist before v6, so FP is
11913 * always accessible
11915 if (!arm_feature(env
, ARM_FEATURE_V6
)) {
11919 if (arm_feature(env
, ARM_FEATURE_M
)) {
11920 /* CPACR can cause a NOCP UsageFault taken to current security state */
11921 if (!v7m_cpacr_pass(env
, env
->v7m
.secure
, cur_el
!= 0)) {
11925 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) && !env
->v7m
.secure
) {
11926 if (!extract32(env
->v7m
.nsacr
, 10, 1)) {
11927 /* FP insns cause a NOCP UsageFault taken to Secure */
11935 hcr_el2
= arm_hcr_el2_eff(env
);
11938 * The CPACR controls traps to EL1, or PL1 if we're 32 bit:
11939 * 0, 2 : trap EL0 and EL1/PL1 accesses
11940 * 1 : trap only EL0 accesses
11941 * 3 : trap no accesses
11942 * This register is ignored if E2H+TGE are both set.
11944 if ((hcr_el2
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
11945 int fpen
= FIELD_EX64(env
->cp15
.cpacr_el1
, CPACR_EL1
, FPEN
);
11955 /* Trap from Secure PL0 or PL1 to Secure PL1. */
11956 if (!arm_el_is_aa64(env
, 3)
11957 && (cur_el
== 3 || arm_is_secure_below_el3(env
))) {
11968 * The NSACR allows A-profile AArch32 EL3 and M-profile secure mode
11969 * to control non-secure access to the FPU. It doesn't have any
11970 * effect if EL3 is AArch64 or if EL3 doesn't exist at all.
11972 if ((arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
11973 cur_el
<= 2 && !arm_is_secure_below_el3(env
))) {
11974 if (!extract32(env
->cp15
.nsacr
, 10, 1)) {
11975 /* FP insns act as UNDEF */
11976 return cur_el
== 2 ? 2 : 1;
11981 * CPTR_EL2 is present in v7VE or v8, and changes format
11982 * with HCR_EL2.E2H (regardless of TGE).
11985 if (hcr_el2
& HCR_E2H
) {
11986 switch (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, FPEN
)) {
11988 if (cur_el
!= 0 || !(hcr_el2
& HCR_TGE
)) {
11996 } else if (arm_is_el2_enabled(env
)) {
11997 if (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TFP
)) {
12003 /* CPTR_EL3 : present in v8 */
12004 if (FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TFP
)) {
12005 /* Trap all FP ops to EL3 */
12012 /* Return the exception level we're running at if this is our mmu_idx */
12013 int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx
)
12015 if (mmu_idx
& ARM_MMU_IDX_M
) {
12016 return mmu_idx
& ARM_MMU_IDX_M_PRIV
;
12020 case ARMMMUIdx_E10_0
:
12021 case ARMMMUIdx_E20_0
:
12023 case ARMMMUIdx_E10_1
:
12024 case ARMMMUIdx_E10_1_PAN
:
12027 case ARMMMUIdx_E20_2
:
12028 case ARMMMUIdx_E20_2_PAN
:
12033 g_assert_not_reached();
12038 ARMMMUIdx
arm_v7m_mmu_idx_for_secstate(CPUARMState
*env
, bool secstate
)
12040 g_assert_not_reached();
12044 static bool arm_pan_enabled(CPUARMState
*env
)
12047 return env
->pstate
& PSTATE_PAN
;
12049 return env
->uncached_cpsr
& CPSR_PAN
;
12053 ARMMMUIdx
arm_mmu_idx_el(CPUARMState
*env
, int el
)
12058 if (arm_feature(env
, ARM_FEATURE_M
)) {
12059 return arm_v7m_mmu_idx_for_secstate(env
, env
->v7m
.secure
);
12062 /* See ARM pseudo-function ELIsInHost. */
12065 hcr
= arm_hcr_el2_eff(env
);
12066 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
12067 idx
= ARMMMUIdx_E20_0
;
12069 idx
= ARMMMUIdx_E10_0
;
12073 if (arm_pan_enabled(env
)) {
12074 idx
= ARMMMUIdx_E10_1_PAN
;
12076 idx
= ARMMMUIdx_E10_1
;
12080 /* Note that TGE does not apply at EL2. */
12081 if (arm_hcr_el2_eff(env
) & HCR_E2H
) {
12082 if (arm_pan_enabled(env
)) {
12083 idx
= ARMMMUIdx_E20_2_PAN
;
12085 idx
= ARMMMUIdx_E20_2
;
12088 idx
= ARMMMUIdx_E2
;
12092 return ARMMMUIdx_E3
;
12094 g_assert_not_reached();
12100 ARMMMUIdx
arm_mmu_idx(CPUARMState
*env
)
12102 return arm_mmu_idx_el(env
, arm_current_el(env
));
12105 static bool mve_no_pred(CPUARMState
*env
)
12108 * Return true if there is definitely no predication of MVE
12109 * instructions by VPR or LTPSIZE. (Returning false even if there
12110 * isn't any predication is OK; generated code will just be
12112 * If the CPU does not implement MVE then this TB flag is always 0.
12114 * NOTE: if you change this logic, the "recalculate s->mve_no_pred"
12115 * logic in gen_update_fp_context() needs to be updated to match.
12117 * We do not include the effect of the ECI bits here -- they are
12118 * tracked in other TB flags. This simplifies the logic for
12119 * "when did we emit code that changes the MVE_NO_PRED TB flag
12120 * and thus need to end the TB?".
12122 if (cpu_isar_feature(aa32_mve
, env_archcpu(env
))) {
12125 if (env
->v7m
.vpr
) {
12128 if (env
->v7m
.ltpsize
< 4) {
12134 void cpu_get_tb_cpu_state(CPUARMState
*env
, vaddr
*pc
,
12135 uint64_t *cs_base
, uint32_t *pflags
)
12137 CPUARMTBFlags flags
;
12139 assert_hflags_rebuild_correctly(env
);
12140 flags
= env
->hflags
;
12142 if (EX_TBFLAG_ANY(flags
, AARCH64_STATE
)) {
12144 if (cpu_isar_feature(aa64_bti
, env_archcpu(env
))) {
12145 DP_TBFLAG_A64(flags
, BTYPE
, env
->btype
);
12148 *pc
= env
->regs
[15];
12150 if (arm_feature(env
, ARM_FEATURE_M
)) {
12151 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) &&
12152 FIELD_EX32(env
->v7m
.fpccr
[M_REG_S
], V7M_FPCCR
, S
)
12153 != env
->v7m
.secure
) {
12154 DP_TBFLAG_M32(flags
, FPCCR_S_WRONG
, 1);
12157 if ((env
->v7m
.fpccr
[env
->v7m
.secure
] & R_V7M_FPCCR_ASPEN_MASK
) &&
12158 (!(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_FPCA_MASK
) ||
12159 (env
->v7m
.secure
&&
12160 !(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SFPA_MASK
)))) {
12162 * ASPEN is set, but FPCA/SFPA indicate that there is no
12163 * active FP context; we must create a new FP context before
12164 * executing any FP insn.
12166 DP_TBFLAG_M32(flags
, NEW_FP_CTXT_NEEDED
, 1);
12169 bool is_secure
= env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_S_MASK
;
12170 if (env
->v7m
.fpccr
[is_secure
] & R_V7M_FPCCR_LSPACT_MASK
) {
12171 DP_TBFLAG_M32(flags
, LSPACT
, 1);
12174 if (mve_no_pred(env
)) {
12175 DP_TBFLAG_M32(flags
, MVE_NO_PRED
, 1);
12179 * Note that XSCALE_CPAR shares bits with VECSTRIDE.
12180 * Note that VECLEN+VECSTRIDE are RES0 for M-profile.
12182 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
12183 DP_TBFLAG_A32(flags
, XSCALE_CPAR
, env
->cp15
.c15_cpar
);
12185 DP_TBFLAG_A32(flags
, VECLEN
, env
->vfp
.vec_len
);
12186 DP_TBFLAG_A32(flags
, VECSTRIDE
, env
->vfp
.vec_stride
);
12188 if (env
->vfp
.xregs
[ARM_VFP_FPEXC
] & (1 << 30)) {
12189 DP_TBFLAG_A32(flags
, VFPEN
, 1);
12193 DP_TBFLAG_AM32(flags
, THUMB
, env
->thumb
);
12194 DP_TBFLAG_AM32(flags
, CONDEXEC
, env
->condexec_bits
);
12198 * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
12199 * states defined in the ARM ARM for software singlestep:
12200 * SS_ACTIVE PSTATE.SS State
12201 * 0 x Inactive (the TB flag for SS is always 0)
12202 * 1 0 Active-pending
12203 * 1 1 Active-not-pending
12204 * SS_ACTIVE is set in hflags; PSTATE__SS is computed every TB.
12206 if (EX_TBFLAG_ANY(flags
, SS_ACTIVE
) && (env
->pstate
& PSTATE_SS
)) {
12207 DP_TBFLAG_ANY(flags
, PSTATE__SS
, 1);
12210 *pflags
= flags
.flags
;
12211 *cs_base
= flags
.flags2
;
12214 #ifdef TARGET_AARCH64
12216 * The manual says that when SVE is enabled and VQ is widened the
12217 * implementation is allowed to zero the previously inaccessible
12218 * portion of the registers. The corollary to that is that when
12219 * SVE is enabled and VQ is narrowed we are also allowed to zero
12220 * the now inaccessible portion of the registers.
12222 * The intent of this is that no predicate bit beyond VQ is ever set.
12223 * Which means that some operations on predicate registers themselves
12224 * may operate on full uint64_t or even unrolled across the maximum
12225 * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally
12226 * may well be cheaper than conditionals to restrict the operation
12227 * to the relevant portion of a uint16_t[16].
12229 void aarch64_sve_narrow_vq(CPUARMState
*env
, unsigned vq
)
12234 assert(vq
>= 1 && vq
<= ARM_MAX_VQ
);
12235 assert(vq
<= env_archcpu(env
)->sve_max_vq
);
12237 /* Zap the high bits of the zregs. */
12238 for (i
= 0; i
< 32; i
++) {
12239 memset(&env
->vfp
.zregs
[i
].d
[2 * vq
], 0, 16 * (ARM_MAX_VQ
- vq
));
12242 /* Zap the high bits of the pregs and ffr. */
12245 pmask
= ~(-1ULL << (16 * (vq
& 3)));
12247 for (j
= vq
/ 4; j
< ARM_MAX_VQ
/ 4; j
++) {
12248 for (i
= 0; i
< 17; ++i
) {
12249 env
->vfp
.pregs
[i
].p
[j
] &= pmask
;
12255 static uint32_t sve_vqm1_for_el_sm_ena(CPUARMState
*env
, int el
, bool sm
)
12260 exc_el
= sme_exception_el(env
, el
);
12262 exc_el
= sve_exception_el(env
, el
);
12265 return 0; /* disabled */
12267 return sve_vqm1_for_el_sm(env
, el
, sm
);
12271 * Notice a change in SVE vector size when changing EL.
12273 void aarch64_sve_change_el(CPUARMState
*env
, int old_el
,
12274 int new_el
, bool el0_a64
)
12276 ARMCPU
*cpu
= env_archcpu(env
);
12277 int old_len
, new_len
;
12278 bool old_a64
, new_a64
, sm
;
12280 /* Nothing to do if no SVE. */
12281 if (!cpu_isar_feature(aa64_sve
, cpu
)) {
12285 /* Nothing to do if FP is disabled in either EL. */
12286 if (fp_exception_el(env
, old_el
) || fp_exception_el(env
, new_el
)) {
12290 old_a64
= old_el
? arm_el_is_aa64(env
, old_el
) : el0_a64
;
12291 new_a64
= new_el
? arm_el_is_aa64(env
, new_el
) : el0_a64
;
12294 * Both AArch64.TakeException and AArch64.ExceptionReturn
12295 * invoke ResetSVEState when taking an exception from, or
12296 * returning to, AArch32 state when PSTATE.SM is enabled.
12298 sm
= FIELD_EX64(env
->svcr
, SVCR
, SM
);
12299 if (old_a64
!= new_a64
&& sm
) {
12300 arm_reset_sve_state(env
);
12305 * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped
12306 * at ELx, or not available because the EL is in AArch32 state, then
12307 * for all purposes other than a direct read, the ZCR_ELx.LEN field
12308 * has an effective value of 0".
12310 * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0).
12311 * If we ignore aa32 state, we would fail to see the vq4->vq0 transition
12312 * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that
12313 * we already have the correct register contents when encountering the
12314 * vq0->vq0 transition between EL0->EL1.
12316 old_len
= new_len
= 0;
12318 old_len
= sve_vqm1_for_el_sm_ena(env
, old_el
, sm
);
12321 new_len
= sve_vqm1_for_el_sm_ena(env
, new_el
, sm
);
12324 /* When changing vector length, clear inaccessible state. */
12325 if (new_len
< old_len
) {
12326 aarch64_sve_narrow_vq(env
, new_len
+ 1);
12331 #ifndef CONFIG_USER_ONLY
12332 ARMSecuritySpace
arm_security_space(CPUARMState
*env
)
12334 if (arm_feature(env
, ARM_FEATURE_M
)) {
12335 return arm_secure_to_space(env
->v7m
.secure
);
12339 * If EL3 is not supported then the secure state is implementation
12340 * defined, in which case QEMU defaults to non-secure.
12342 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
12343 return ARMSS_NonSecure
;
12346 /* Check for AArch64 EL3 or AArch32 Mon. */
12348 if (extract32(env
->pstate
, 2, 2) == 3) {
12349 if (cpu_isar_feature(aa64_rme
, env_archcpu(env
))) {
12352 return ARMSS_Secure
;
12356 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
12357 return ARMSS_Secure
;
12361 return arm_security_space_below_el3(env
);
12364 ARMSecuritySpace
arm_security_space_below_el3(CPUARMState
*env
)
12366 assert(!arm_feature(env
, ARM_FEATURE_M
));
12369 * If EL3 is not supported then the secure state is implementation
12370 * defined, in which case QEMU defaults to non-secure.
12372 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
12373 return ARMSS_NonSecure
;
12377 * Note NSE cannot be set without RME, and NSE & !NS is Reserved.
12378 * Ignoring NSE when !NS retains consistency without having to
12379 * modify other predicates.
12381 if (!(env
->cp15
.scr_el3
& SCR_NS
)) {
12382 return ARMSS_Secure
;
12383 } else if (env
->cp15
.scr_el3
& SCR_NSE
) {
12384 return ARMSS_Realm
;
12386 return ARMSS_NonSecure
;
12389 #endif /* !CONFIG_USER_ONLY */