migration: Create load_setup()/cleanup() methods
[qemu/ar7.git] / hw / ppc / spapr_rtas_ddw.c
blob177dcffc9b05a9e616f1fb1096da66ccd3db03b4
1 /*
2 * QEMU sPAPR Dynamic DMA windows support
4 * Copyright (c) 2015 Alexey Kardashevskiy, IBM Corporation.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License,
9 * or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "cpu.h"
22 #include "qemu/error-report.h"
23 #include "hw/ppc/spapr.h"
24 #include "hw/pci-host/spapr.h"
25 #include "trace.h"
27 static int spapr_phb_get_active_win_num_cb(Object *child, void *opaque)
29 sPAPRTCETable *tcet;
31 tcet = (sPAPRTCETable *) object_dynamic_cast(child, TYPE_SPAPR_TCE_TABLE);
32 if (tcet && tcet->nb_table) {
33 ++*(unsigned *)opaque;
35 return 0;
38 static unsigned spapr_phb_get_active_win_num(sPAPRPHBState *sphb)
40 unsigned ret = 0;
42 object_child_foreach(OBJECT(sphb), spapr_phb_get_active_win_num_cb, &ret);
44 return ret;
47 static int spapr_phb_get_free_liobn_cb(Object *child, void *opaque)
49 sPAPRTCETable *tcet;
51 tcet = (sPAPRTCETable *) object_dynamic_cast(child, TYPE_SPAPR_TCE_TABLE);
52 if (tcet && !tcet->nb_table) {
53 *(uint32_t *)opaque = tcet->liobn;
54 return 1;
56 return 0;
59 static unsigned spapr_phb_get_free_liobn(sPAPRPHBState *sphb)
61 uint32_t liobn = 0;
63 object_child_foreach(OBJECT(sphb), spapr_phb_get_free_liobn_cb, &liobn);
65 return liobn;
68 static uint32_t spapr_page_mask_to_query_mask(uint64_t page_mask)
70 int i;
71 uint32_t mask = 0;
72 const struct { int shift; uint32_t mask; } masks[] = {
73 { 12, RTAS_DDW_PGSIZE_4K },
74 { 16, RTAS_DDW_PGSIZE_64K },
75 { 24, RTAS_DDW_PGSIZE_16M },
76 { 25, RTAS_DDW_PGSIZE_32M },
77 { 26, RTAS_DDW_PGSIZE_64M },
78 { 27, RTAS_DDW_PGSIZE_128M },
79 { 28, RTAS_DDW_PGSIZE_256M },
80 { 34, RTAS_DDW_PGSIZE_16G },
83 for (i = 0; i < ARRAY_SIZE(masks); ++i) {
84 if (page_mask & (1ULL << masks[i].shift)) {
85 mask |= masks[i].mask;
89 return mask;
92 static void rtas_ibm_query_pe_dma_window(PowerPCCPU *cpu,
93 sPAPRMachineState *spapr,
94 uint32_t token, uint32_t nargs,
95 target_ulong args,
96 uint32_t nret, target_ulong rets)
98 sPAPRPHBState *sphb;
99 uint64_t buid, max_window_size;
100 uint32_t avail, addr, pgmask = 0;
101 MachineState *machine = MACHINE(spapr);
103 if ((nargs != 3) || (nret != 5)) {
104 goto param_error_exit;
107 buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
108 addr = rtas_ld(args, 0);
109 sphb = spapr_pci_find_phb(spapr, buid);
110 if (!sphb || !sphb->ddw_enabled) {
111 goto param_error_exit;
114 /* Translate page mask to LoPAPR format */
115 pgmask = spapr_page_mask_to_query_mask(sphb->page_size_mask);
118 * This is "Largest contiguous block of TCEs allocated specifically
119 * for (that is, are reserved for) this PE".
120 * Return the maximum number as maximum supported RAM size was in 4K pages.
122 if (machine->ram_size == machine->maxram_size) {
123 max_window_size = machine->ram_size;
124 } else {
125 MemoryHotplugState *hpms = &spapr->hotplug_memory;
127 max_window_size = hpms->base + memory_region_size(&hpms->mr);
130 avail = SPAPR_PCI_DMA_MAX_WINDOWS - spapr_phb_get_active_win_num(sphb);
132 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
133 rtas_st(rets, 1, avail);
134 rtas_st(rets, 2, max_window_size >> SPAPR_TCE_PAGE_SHIFT);
135 rtas_st(rets, 3, pgmask);
136 rtas_st(rets, 4, 0); /* DMA migration mask, not supported */
138 trace_spapr_iommu_ddw_query(buid, addr, avail, max_window_size, pgmask);
139 return;
141 param_error_exit:
142 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
145 static void rtas_ibm_create_pe_dma_window(PowerPCCPU *cpu,
146 sPAPRMachineState *spapr,
147 uint32_t token, uint32_t nargs,
148 target_ulong args,
149 uint32_t nret, target_ulong rets)
151 sPAPRPHBState *sphb;
152 sPAPRTCETable *tcet = NULL;
153 uint32_t addr, page_shift, window_shift, liobn;
154 uint64_t buid, win_addr;
155 int windows;
157 if ((nargs != 5) || (nret != 4)) {
158 goto param_error_exit;
161 buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
162 addr = rtas_ld(args, 0);
163 sphb = spapr_pci_find_phb(spapr, buid);
164 if (!sphb || !sphb->ddw_enabled) {
165 goto param_error_exit;
168 page_shift = rtas_ld(args, 3);
169 window_shift = rtas_ld(args, 4);
170 liobn = spapr_phb_get_free_liobn(sphb);
171 windows = spapr_phb_get_active_win_num(sphb);
173 if (!(sphb->page_size_mask & (1ULL << page_shift)) ||
174 (window_shift < page_shift)) {
175 goto param_error_exit;
178 if (!liobn || !sphb->ddw_enabled || windows == SPAPR_PCI_DMA_MAX_WINDOWS) {
179 goto hw_error_exit;
182 tcet = spapr_tce_find_by_liobn(liobn);
183 if (!tcet) {
184 goto hw_error_exit;
187 win_addr = (windows == 0) ? sphb->dma_win_addr : sphb->dma64_win_addr;
188 spapr_tce_table_enable(tcet, page_shift, win_addr,
189 1ULL << (window_shift - page_shift));
190 if (!tcet->nb_table) {
191 goto hw_error_exit;
194 trace_spapr_iommu_ddw_create(buid, addr, 1ULL << page_shift,
195 1ULL << window_shift, tcet->bus_offset, liobn);
197 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
198 rtas_st(rets, 1, liobn);
199 rtas_st(rets, 2, tcet->bus_offset >> 32);
200 rtas_st(rets, 3, tcet->bus_offset & ((uint32_t) -1));
202 return;
204 hw_error_exit:
205 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
206 return;
208 param_error_exit:
209 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
212 static void rtas_ibm_remove_pe_dma_window(PowerPCCPU *cpu,
213 sPAPRMachineState *spapr,
214 uint32_t token, uint32_t nargs,
215 target_ulong args,
216 uint32_t nret, target_ulong rets)
218 sPAPRPHBState *sphb;
219 sPAPRTCETable *tcet;
220 uint32_t liobn;
222 if ((nargs != 1) || (nret != 1)) {
223 goto param_error_exit;
226 liobn = rtas_ld(args, 0);
227 tcet = spapr_tce_find_by_liobn(liobn);
228 if (!tcet) {
229 goto param_error_exit;
232 sphb = SPAPR_PCI_HOST_BRIDGE(OBJECT(tcet)->parent);
233 if (!sphb || !sphb->ddw_enabled || !tcet->nb_table) {
234 goto param_error_exit;
237 spapr_tce_table_disable(tcet);
238 trace_spapr_iommu_ddw_remove(liobn);
240 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
241 return;
243 param_error_exit:
244 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
247 static void rtas_ibm_reset_pe_dma_window(PowerPCCPU *cpu,
248 sPAPRMachineState *spapr,
249 uint32_t token, uint32_t nargs,
250 target_ulong args,
251 uint32_t nret, target_ulong rets)
253 sPAPRPHBState *sphb;
254 uint64_t buid;
255 uint32_t addr;
257 if ((nargs != 3) || (nret != 1)) {
258 goto param_error_exit;
261 buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
262 addr = rtas_ld(args, 0);
263 sphb = spapr_pci_find_phb(spapr, buid);
264 if (!sphb || !sphb->ddw_enabled) {
265 goto param_error_exit;
268 spapr_phb_dma_reset(sphb);
269 trace_spapr_iommu_ddw_reset(buid, addr);
271 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
273 return;
275 param_error_exit:
276 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
279 static void spapr_rtas_ddw_init(void)
281 spapr_rtas_register(RTAS_IBM_QUERY_PE_DMA_WINDOW,
282 "ibm,query-pe-dma-window",
283 rtas_ibm_query_pe_dma_window);
284 spapr_rtas_register(RTAS_IBM_CREATE_PE_DMA_WINDOW,
285 "ibm,create-pe-dma-window",
286 rtas_ibm_create_pe_dma_window);
287 spapr_rtas_register(RTAS_IBM_REMOVE_PE_DMA_WINDOW,
288 "ibm,remove-pe-dma-window",
289 rtas_ibm_remove_pe_dma_window);
290 spapr_rtas_register(RTAS_IBM_RESET_PE_DMA_WINDOW,
291 "ibm,reset-pe-dma-window",
292 rtas_ibm_reset_pe_dma_window);
295 type_init(spapr_rtas_ddw_init)