hw/mips/mips_jazz.c

   1 /*
   2  * QEMU MIPS Jazz support
   3  *
   4  * Copyright (c) 2007-2008 Hervé Poussineau
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "hw/hw.h"
  27 #include "hw/mips/mips.h"
  28 #include "hw/mips/cpudevs.h"
  29 #include "hw/i386/pc.h"
  30 #include "hw/char/serial.h"
  31 #include "hw/isa/isa.h"
  32 #include "hw/block/fdc.h"
  33 #include "sysemu/sysemu.h"
  34 #include "sysemu/arch_init.h"
  35 #include "hw/boards.h"
  36 #include "net/net.h"
  37 #include "hw/scsi/esp.h"
  38 #include "hw/mips/bios.h"
  39 #include "hw/loader.h"
  40 #include "hw/timer/mc146818rtc.h"
  41 #include "hw/timer/i8254.h"
  42 #include "hw/audio/pcspk.h"
  43 #include "sysemu/block-backend.h"
  44 #include "hw/sysbus.h"
  45 #include "exec/address-spaces.h"
  46 #include "sysemu/qtest.h"
  47 #include "qemu/error-report.h"
  48 #include "qemu/help_option.h"
  49
  50 enum jazz_model_e
  51 {
  52     JAZZ_MAGNUM,
  53     JAZZ_PICA61,
  54 };
  55
  56 static void main_cpu_reset(void *opaque)
  57 {
  58     MIPSCPU *cpu = opaque;
  59
  60     cpu_reset(CPU(cpu));
  61 }
  62
  63 static uint64_t rtc_read(void *opaque, hwaddr addr, unsigned size)
  64 {
  65     uint8_t val;
  66     address_space_read(&address_space_memory, 0x90000071,
  67                        MEMTXATTRS_UNSPECIFIED, &val, 1);
  68     return val;
  69 }
  70
  71 static void rtc_write(void *opaque, hwaddr addr,
  72                       uint64_t val, unsigned size)
  73 {
  74     uint8_t buf = val & 0xff;
  75     address_space_write(&address_space_memory, 0x90000071,
  76                         MEMTXATTRS_UNSPECIFIED, &buf, 1);
  77 }
  78
  79 static const MemoryRegionOps rtc_ops = {
  80     .read = rtc_read,
  81     .write = rtc_write,
  82     .endianness = DEVICE_NATIVE_ENDIAN,
  83 };
  84
  85 static uint64_t dma_dummy_read(void *opaque, hwaddr addr,
  86                                unsigned size)
  87 {
  88     /* Nothing to do. That is only to ensure that
  89      * the current DMA acknowledge cycle is completed. */
  90     return 0xff;
  91 }
  92
  93 static void dma_dummy_write(void *opaque, hwaddr addr,
  94                             uint64_t val, unsigned size)
  95 {
  96     /* Nothing to do. That is only to ensure that
  97      * the current DMA acknowledge cycle is completed. */
  98 }
  99
 100 static const MemoryRegionOps dma_dummy_ops = {
 101     .read = dma_dummy_read,
 102     .write = dma_dummy_write,
 103     .endianness = DEVICE_NATIVE_ENDIAN,
 104 };
 105
 106 #define MAGNUM_BIOS_SIZE_MAX 0x7e000
 107 #define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
 108
 109 static CPUUnassignedAccess real_do_unassigned_access;
 110 static void mips_jazz_do_unassigned_access(CPUState *cpu, hwaddr addr,
 111                                            bool is_write, bool is_exec,
 112                                            int opaque, unsigned size)
 113 {
 114     if (!is_exec) {
 115         /* ignore invalid access (ie do not raise exception) */
 116         return;
 117     }
 118     (*real_do_unassigned_access)(cpu, addr, is_write, is_exec, opaque, size);
 119 }
 120
 121 static void mips_jazz_init(MachineState *machine,
 122                            enum jazz_model_e jazz_model)
 123 {
 124     MemoryRegion *address_space = get_system_memory();
 125     const char *cpu_model = machine->cpu_model;
 126     char *filename;
 127     int bios_size, n;
 128     MIPSCPU *cpu;
 129     CPUClass *cc;
 130     CPUMIPSState *env;
 131     qemu_irq *i8259;
 132     rc4030_dma *dmas;
 133     MemoryRegion *rc4030_dma_mr;
 134     MemoryRegion *isa_mem = g_new(MemoryRegion, 1);
 135     MemoryRegion *isa_io = g_new(MemoryRegion, 1);
 136     MemoryRegion *rtc = g_new(MemoryRegion, 1);
 137     MemoryRegion *i8042 = g_new(MemoryRegion, 1);
 138     MemoryRegion *dma_dummy = g_new(MemoryRegion, 1);
 139     NICInfo *nd;
 140     DeviceState *dev, *rc4030;
 141     SysBusDevice *sysbus;
 142     ISABus *isa_bus;
 143     ISADevice *pit;
 144     DriveInfo *fds[MAX_FD];
 145     qemu_irq esp_reset, dma_enable;
 146     MemoryRegion *ram = g_new(MemoryRegion, 1);
 147     MemoryRegion *bios = g_new(MemoryRegion, 1);
 148     MemoryRegion *bios2 = g_new(MemoryRegion, 1);
 149
 150     /* init CPUs */
 151     if (cpu_model == NULL) {
 152         cpu_model = "R4000";
 153     }
 154     cpu = cpu_mips_init(cpu_model);
 155     if (cpu == NULL) {
 156         fprintf(stderr, "Unable to find CPU definition\n");
 157         exit(1);
 158     }
 159     env = &cpu->env;
 160     qemu_register_reset(main_cpu_reset, cpu);
 161
 162     /* Chipset returns 0 in invalid reads and do not raise data exceptions.
 163      * However, we can't simply add a global memory region to catch
 164      * everything, as memory core directly call unassigned_mem_read/write
 165      * on some invalid accesses, which call do_unassigned_access on the
 166      * CPU, which raise an exception.
 167      * Handle that case by hijacking the do_unassigned_access method on
 168      * the CPU, and do not raise exceptions for data access. */
 169     cc = CPU_GET_CLASS(cpu);
 170     real_do_unassigned_access = cc->do_unassigned_access;
 171     cc->do_unassigned_access = mips_jazz_do_unassigned_access;
 172
 173     /* allocate RAM */
 174     memory_region_allocate_system_memory(ram, NULL, "mips_jazz.ram",
 175                                          machine->ram_size);
 176     memory_region_add_subregion(address_space, 0, ram);
 177
 178     memory_region_init_ram(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE,
 179                            &error_fatal);
 180     vmstate_register_ram_global(bios);
 181     memory_region_set_readonly(bios, true);
 182     memory_region_init_alias(bios2, NULL, "mips_jazz.bios", bios,
 183                              0, MAGNUM_BIOS_SIZE);
 184     memory_region_add_subregion(address_space, 0x1fc00000LL, bios);
 185     memory_region_add_subregion(address_space, 0xfff00000LL, bios2);
 186
 187     /* load the BIOS image. */
 188     if (bios_name == NULL)
 189         bios_name = BIOS_FILENAME;
 190     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 191     if (filename) {
 192         bios_size = load_image_targphys(filename, 0xfff00000LL,
 193                                         MAGNUM_BIOS_SIZE);
 194         g_free(filename);
 195     } else {
 196         bios_size = -1;
 197     }
 198     if ((bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) && !qtest_enabled()) {
 199         error_report("Could not load MIPS bios '%s'", bios_name);
 200         exit(1);
 201     }
 202
 203     /* Init CPU internal devices */
 204     cpu_mips_irq_init_cpu(cpu);
 205     cpu_mips_clock_init(cpu);
 206
 207     /* Chipset */
 208     rc4030 = rc4030_init(&dmas, &rc4030_dma_mr);
 209     sysbus = SYS_BUS_DEVICE(rc4030);
 210     sysbus_connect_irq(sysbus, 0, env->irq[6]);
 211     sysbus_connect_irq(sysbus, 1, env->irq[3]);
 212     memory_region_add_subregion(address_space, 0x80000000,
 213                                 sysbus_mmio_get_region(sysbus, 0));
 214     memory_region_add_subregion(address_space, 0xf0000000,
 215                                 sysbus_mmio_get_region(sysbus, 1));
 216     memory_region_init_io(dma_dummy, NULL, &dma_dummy_ops, NULL, "dummy_dma", 0x1000);
 217     memory_region_add_subregion(address_space, 0x8000d000, dma_dummy);
 218
 219     /* ISA bus: IO space at 0x90000000, mem space at 0x91000000 */
 220     memory_region_init(isa_io, NULL, "isa-io", 0x00010000);
 221     memory_region_init(isa_mem, NULL, "isa-mem", 0x01000000);
 222     memory_region_add_subregion(address_space, 0x90000000, isa_io);
 223     memory_region_add_subregion(address_space, 0x91000000, isa_mem);
 224     isa_bus = isa_bus_new(NULL, isa_mem, isa_io, &error_abort);
 225
 226     /* ISA devices */
 227     i8259 = i8259_init(isa_bus, env->irq[4]);
 228     isa_bus_irqs(isa_bus, i8259);
 229     DMA_init(isa_bus, 0);
 230     pit = pit_init(isa_bus, 0x40, 0, NULL);
 231     pcspk_init(isa_bus, pit);
 232
 233     /* Video card */
 234     switch (jazz_model) {
 235     case JAZZ_MAGNUM:
 236         dev = qdev_create(NULL, "sysbus-g364");
 237         qdev_init_nofail(dev);
 238         sysbus = SYS_BUS_DEVICE(dev);
 239         sysbus_mmio_map(sysbus, 0, 0x60080000);
 240         sysbus_mmio_map(sysbus, 1, 0x40000000);
 241         sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 3));
 242         {
 243             /* Simple ROM, so user doesn't have to provide one */
 244             MemoryRegion *rom_mr = g_new(MemoryRegion, 1);
 245             memory_region_init_ram(rom_mr, NULL, "g364fb.rom", 0x80000,
 246                                    &error_fatal);
 247             vmstate_register_ram_global(rom_mr);
 248             memory_region_set_readonly(rom_mr, true);
 249             uint8_t *rom = memory_region_get_ram_ptr(rom_mr);
 250             memory_region_add_subregion(address_space, 0x60000000, rom_mr);
 251             rom[0] = 0x10; /* Mips G364 */
 252         }
 253         break;
 254     case JAZZ_PICA61:
 255         isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory());
 256         break;
 257     default:
 258         break;
 259     }
 260
 261     /* Network controller */
 262     for (n = 0; n < nb_nics; n++) {
 263         nd = &nd_table[n];
 264         if (!nd->model)
 265             nd->model = g_strdup("dp83932");
 266         if (strcmp(nd->model, "dp83932") == 0) {
 267             qemu_check_nic_model(nd, "dp83932");
 268
 269             dev = qdev_create(NULL, "dp8393x");
 270             qdev_set_nic_properties(dev, nd);
 271             qdev_prop_set_uint8(dev, "it_shift", 2);
 272             qdev_prop_set_ptr(dev, "dma_mr", rc4030_dma_mr);
 273             qdev_init_nofail(dev);
 274             sysbus = SYS_BUS_DEVICE(dev);
 275             sysbus_mmio_map(sysbus, 0, 0x80001000);
 276             sysbus_mmio_map(sysbus, 1, 0x8000b000);
 277             sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 4));
 278             break;
 279         } else if (is_help_option(nd->model)) {
 280             fprintf(stderr, "qemu: Supported NICs: dp83932\n");
 281             exit(1);
 282         } else {
 283             fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
 284             exit(1);
 285         }
 286     }
 287
 288     /* SCSI adapter */
 289     esp_init(0x80002000, 0,
 290              rc4030_dma_read, rc4030_dma_write, dmas[0],
 291              qdev_get_gpio_in(rc4030, 5), &esp_reset, &dma_enable);
 292
 293     /* Floppy */
 294     for (n = 0; n < MAX_FD; n++) {
 295         fds[n] = drive_get(IF_FLOPPY, 0, n);
 296     }
 297     /* FIXME: we should enable DMA with a custom IsaDma device */
 298     fdctrl_init_sysbus(qdev_get_gpio_in(rc4030, 1), -1, 0x80003000, fds);
 299
 300     /* Real time clock */
 301     rtc_init(isa_bus, 1980, NULL);
 302     memory_region_init_io(rtc, NULL, &rtc_ops, NULL, "rtc", 0x1000);
 303     memory_region_add_subregion(address_space, 0x80004000, rtc);
 304
 305     /* Keyboard (i8042) */
 306     i8042_mm_init(qdev_get_gpio_in(rc4030, 6), qdev_get_gpio_in(rc4030, 7),
 307                   i8042, 0x1000, 0x1);
 308     memory_region_add_subregion(address_space, 0x80005000, i8042);
 309
 310     /* Serial ports */
 311     if (serial_hds[0]) {
 312         serial_mm_init(address_space, 0x80006000, 0,
 313                        qdev_get_gpio_in(rc4030, 8), 8000000/16,
 314                        serial_hds[0], DEVICE_NATIVE_ENDIAN);
 315     }
 316     if (serial_hds[1]) {
 317         serial_mm_init(address_space, 0x80007000, 0,
 318                        qdev_get_gpio_in(rc4030, 9), 8000000/16,
 319                        serial_hds[1], DEVICE_NATIVE_ENDIAN);
 320     }
 321
 322     /* Parallel port */
 323     if (parallel_hds[0])
 324         parallel_mm_init(address_space, 0x80008000, 0,
 325                          qdev_get_gpio_in(rc4030, 0), parallel_hds[0]);
 326
 327     /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
 328
 329     /* NVRAM */
 330     dev = qdev_create(NULL, "ds1225y");
 331     qdev_init_nofail(dev);
 332     sysbus = SYS_BUS_DEVICE(dev);
 333     sysbus_mmio_map(sysbus, 0, 0x80009000);
 334
 335     /* LED indicator */
 336     sysbus_create_simple("jazz-led", 0x8000f000, NULL);
 337 }
 338
 339 static
 340 void mips_magnum_init(MachineState *machine)
 341 {
 342     mips_jazz_init(machine, JAZZ_MAGNUM);
 343 }
 344
 345 static
 346 void mips_pica61_init(MachineState *machine)
 347 {
 348     mips_jazz_init(machine, JAZZ_PICA61);
 349 }
 350
 351 static void mips_magnum_class_init(ObjectClass *oc, void *data)
 352 {
 353     MachineClass *mc = MACHINE_CLASS(oc);
 354
 355     mc->desc = "MIPS Magnum";
 356     mc->init = mips_magnum_init;
 357     mc->block_default_type = IF_SCSI;
 358 }
 359
 360 static const TypeInfo mips_magnum_type = {
 361     .name = MACHINE_TYPE_NAME("magnum"),
 362     .parent = TYPE_MACHINE,
 363     .class_init = mips_magnum_class_init,
 364 };
 365
 366 static void mips_pica61_class_init(ObjectClass *oc, void *data)
 367 {
 368     MachineClass *mc = MACHINE_CLASS(oc);
 369
 370     mc->desc = "Acer Pica 61";
 371     mc->init = mips_pica61_init;
 372     mc->block_default_type = IF_SCSI;
 373 }
 374
 375 static const TypeInfo mips_pica61_type = {
 376     .name = MACHINE_TYPE_NAME("pica61"),
 377     .parent = TYPE_MACHINE,
 378     .class_init = mips_pica61_class_init,
 379 };
 380
 381 static void mips_jazz_machine_init(void)
 382 {
 383     type_register_static(&mips_magnum_type);
 384     type_register_static(&mips_pica61_type);
 385 }
 386
 387 type_init(mips_jazz_machine_init)