2 * Motorola ColdFire MCF5206 SoC embedded peripheral emulation.
4 * Copyright (c) 2007 CodeSourcery.
6 * This code is licensed under the GPL
8 #include "qemu/osdep.h"
10 #include "hw/m68k/mcf.h"
11 #include "qemu/timer.h"
12 #include "hw/ptimer.h"
13 #include "sysemu/sysemu.h"
14 #include "exec/address-spaces.h"
16 /* General purpose timer module. */
37 static void m5206_timer_update(m5206_timer_state
*s
)
39 if ((s
->tmr
& TMR_ORI
) != 0 && (s
->ter
& TER_REF
))
40 qemu_irq_raise(s
->irq
);
42 qemu_irq_lower(s
->irq
);
45 static void m5206_timer_reset(m5206_timer_state
*s
)
51 static void m5206_timer_recalibrate(m5206_timer_state
*s
)
56 ptimer_stop(s
->timer
);
58 if ((s
->tmr
& TMR_RST
) == 0)
61 prescale
= (s
->tmr
>> 8) + 1;
62 mode
= (s
->tmr
>> 1) & 3;
66 if (mode
== 3 || mode
== 0)
67 hw_error("m5206_timer: mode %d not implemented\n", mode
);
68 if ((s
->tmr
& TMR_FRR
) == 0)
69 hw_error("m5206_timer: free running mode not implemented\n");
71 /* Assume 66MHz system clock. */
72 ptimer_set_freq(s
->timer
, 66000000 / prescale
);
74 ptimer_set_limit(s
->timer
, s
->trr
, 0);
76 ptimer_run(s
->timer
, 0);
79 static void m5206_timer_trigger(void *opaque
)
81 m5206_timer_state
*s
= (m5206_timer_state
*)opaque
;
83 m5206_timer_update(s
);
86 static uint32_t m5206_timer_read(m5206_timer_state
*s
, uint32_t addr
)
96 return s
->trr
- ptimer_get_count(s
->timer
);
104 static void m5206_timer_write(m5206_timer_state
*s
, uint32_t addr
, uint32_t val
)
108 if ((s
->tmr
& TMR_RST
) != 0 && (val
& TMR_RST
) == 0) {
109 m5206_timer_reset(s
);
112 m5206_timer_recalibrate(s
);
116 m5206_timer_recalibrate(s
);
122 ptimer_set_count(s
->timer
, val
);
130 m5206_timer_update(s
);
133 static m5206_timer_state
*m5206_timer_init(qemu_irq irq
)
135 m5206_timer_state
*s
;
138 s
= (m5206_timer_state
*)g_malloc0(sizeof(m5206_timer_state
));
139 bh
= qemu_bh_new(m5206_timer_trigger
, s
);
140 s
->timer
= ptimer_init(bh
);
142 m5206_timer_reset(s
);
146 /* System Integration Module. */
151 m5206_timer_state
*timer
[2];
155 uint16_t imr
; /* 1 == interrupt is masked. */
160 /* Include the UART vector registers here. */
164 /* Interrupt controller. */
166 static int m5206_find_pending_irq(m5206_mbar_state
*s
)
175 active
= s
->ipr
& ~s
->imr
;
179 for (i
= 1; i
< 14; i
++) {
180 if (active
& (1 << i
)) {
181 if ((s
->icr
[i
] & 0x1f) > level
) {
182 level
= s
->icr
[i
] & 0x1f;
194 static void m5206_mbar_update(m5206_mbar_state
*s
)
200 irq
= m5206_find_pending_irq(s
);
204 level
= (tmp
>> 2) & 7;
220 /* Unknown vector. */
221 fprintf(stderr
, "Unhandled vector for IRQ %d\n", irq
);
230 m68k_set_irq_level(s
->cpu
, level
, vector
);
233 static void m5206_mbar_set_irq(void *opaque
, int irq
, int level
)
235 m5206_mbar_state
*s
= (m5206_mbar_state
*)opaque
;
239 s
->ipr
&= ~(1 << irq
);
241 m5206_mbar_update(s
);
244 /* System Integration Module. */
246 static void m5206_mbar_reset(m5206_mbar_state
*s
)
268 static uint64_t m5206_mbar_read(m5206_mbar_state
*s
,
269 uint64_t offset
, unsigned size
)
271 if (offset
>= 0x100 && offset
< 0x120) {
272 return m5206_timer_read(s
->timer
[0], offset
- 0x100);
273 } else if (offset
>= 0x120 && offset
< 0x140) {
274 return m5206_timer_read(s
->timer
[1], offset
- 0x120);
275 } else if (offset
>= 0x140 && offset
< 0x160) {
276 return mcf_uart_read(s
->uart
[0], offset
- 0x140, size
);
277 } else if (offset
>= 0x180 && offset
< 0x1a0) {
278 return mcf_uart_read(s
->uart
[1], offset
- 0x180, size
);
281 case 0x03: return s
->scr
;
282 case 0x14 ... 0x20: return s
->icr
[offset
- 0x13];
283 case 0x36: return s
->imr
;
284 case 0x3a: return s
->ipr
;
285 case 0x40: return s
->rsr
;
287 case 0x42: return s
->swivr
;
289 /* DRAM mask register. */
290 /* FIXME: currently hardcoded to 128Mb. */
293 while (mask
> ram_size
)
295 return mask
& 0x0ffe0000;
297 case 0x5c: return 1; /* DRAM bank 1 empty. */
298 case 0xcb: return s
->par
;
299 case 0x170: return s
->uivr
[0];
300 case 0x1b0: return s
->uivr
[1];
302 hw_error("Bad MBAR read offset 0x%x", (int)offset
);
306 static void m5206_mbar_write(m5206_mbar_state
*s
, uint32_t offset
,
307 uint64_t value
, unsigned size
)
309 if (offset
>= 0x100 && offset
< 0x120) {
310 m5206_timer_write(s
->timer
[0], offset
- 0x100, value
);
312 } else if (offset
>= 0x120 && offset
< 0x140) {
313 m5206_timer_write(s
->timer
[1], offset
- 0x120, value
);
315 } else if (offset
>= 0x140 && offset
< 0x160) {
316 mcf_uart_write(s
->uart
[0], offset
- 0x140, value
, size
);
318 } else if (offset
>= 0x180 && offset
< 0x1a0) {
319 mcf_uart_write(s
->uart
[1], offset
- 0x180, value
, size
);
327 s
->icr
[offset
- 0x13] = value
;
328 m5206_mbar_update(s
);
332 m5206_mbar_update(s
);
338 /* TODO: implement watchdog. */
349 case 0x178: case 0x17c: case 0x1c8: case 0x1bc:
350 /* Not implemented: UART Output port bits. */
356 hw_error("Bad MBAR write offset 0x%x", (int)offset
);
361 /* Internal peripherals use a variety of register widths.
362 This lookup table allows a single routine to handle all of them. */
363 static const uint8_t m5206_mbar_width
[] =
365 /* 000-040 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2,
366 /* 040-080 */ 1, 2, 2, 2, 4, 1, 2, 4, 1, 2, 4, 2, 2, 4, 2, 2,
367 /* 080-0c0 */ 4, 2, 2, 4, 2, 2, 4, 2, 2, 4, 2, 2, 4, 2, 2, 4,
368 /* 0c0-100 */ 2, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
369 /* 100-140 */ 2, 2, 2, 2, 1, 0, 0, 0, 2, 2, 2, 2, 1, 0, 0, 0,
370 /* 140-180 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
371 /* 180-1c0 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
372 /* 1c0-200 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
375 static uint32_t m5206_mbar_readw(void *opaque
, hwaddr offset
);
376 static uint32_t m5206_mbar_readl(void *opaque
, hwaddr offset
);
378 static uint32_t m5206_mbar_readb(void *opaque
, hwaddr offset
)
380 m5206_mbar_state
*s
= (m5206_mbar_state
*)opaque
;
382 if (offset
>= 0x200) {
383 hw_error("Bad MBAR read offset 0x%x", (int)offset
);
385 if (m5206_mbar_width
[offset
>> 2] > 1) {
387 val
= m5206_mbar_readw(opaque
, offset
& ~1);
388 if ((offset
& 1) == 0) {
393 return m5206_mbar_read(s
, offset
, 1);
396 static uint32_t m5206_mbar_readw(void *opaque
, hwaddr offset
)
398 m5206_mbar_state
*s
= (m5206_mbar_state
*)opaque
;
401 if (offset
>= 0x200) {
402 hw_error("Bad MBAR read offset 0x%x", (int)offset
);
404 width
= m5206_mbar_width
[offset
>> 2];
407 val
= m5206_mbar_readl(opaque
, offset
& ~3);
408 if ((offset
& 3) == 0)
411 } else if (width
< 2) {
413 val
= m5206_mbar_readb(opaque
, offset
) << 8;
414 val
|= m5206_mbar_readb(opaque
, offset
+ 1);
417 return m5206_mbar_read(s
, offset
, 2);
420 static uint32_t m5206_mbar_readl(void *opaque
, hwaddr offset
)
422 m5206_mbar_state
*s
= (m5206_mbar_state
*)opaque
;
425 if (offset
>= 0x200) {
426 hw_error("Bad MBAR read offset 0x%x", (int)offset
);
428 width
= m5206_mbar_width
[offset
>> 2];
431 val
= m5206_mbar_readw(opaque
, offset
) << 16;
432 val
|= m5206_mbar_readw(opaque
, offset
+ 2);
435 return m5206_mbar_read(s
, offset
, 4);
438 static void m5206_mbar_writew(void *opaque
, hwaddr offset
,
440 static void m5206_mbar_writel(void *opaque
, hwaddr offset
,
443 static void m5206_mbar_writeb(void *opaque
, hwaddr offset
,
446 m5206_mbar_state
*s
= (m5206_mbar_state
*)opaque
;
449 if (offset
>= 0x200) {
450 hw_error("Bad MBAR write offset 0x%x", (int)offset
);
452 width
= m5206_mbar_width
[offset
>> 2];
455 tmp
= m5206_mbar_readw(opaque
, offset
& ~1);
457 tmp
= (tmp
& 0xff00) | value
;
459 tmp
= (tmp
& 0x00ff) | (value
<< 8);
461 m5206_mbar_writew(opaque
, offset
& ~1, tmp
);
464 m5206_mbar_write(s
, offset
, value
, 1);
467 static void m5206_mbar_writew(void *opaque
, hwaddr offset
,
470 m5206_mbar_state
*s
= (m5206_mbar_state
*)opaque
;
473 if (offset
>= 0x200) {
474 hw_error("Bad MBAR write offset 0x%x", (int)offset
);
476 width
= m5206_mbar_width
[offset
>> 2];
479 tmp
= m5206_mbar_readl(opaque
, offset
& ~3);
481 tmp
= (tmp
& 0xffff0000) | value
;
483 tmp
= (tmp
& 0x0000ffff) | (value
<< 16);
485 m5206_mbar_writel(opaque
, offset
& ~3, tmp
);
487 } else if (width
< 2) {
488 m5206_mbar_writeb(opaque
, offset
, value
>> 8);
489 m5206_mbar_writeb(opaque
, offset
+ 1, value
& 0xff);
492 m5206_mbar_write(s
, offset
, value
, 2);
495 static void m5206_mbar_writel(void *opaque
, hwaddr offset
,
498 m5206_mbar_state
*s
= (m5206_mbar_state
*)opaque
;
501 if (offset
>= 0x200) {
502 hw_error("Bad MBAR write offset 0x%x", (int)offset
);
504 width
= m5206_mbar_width
[offset
>> 2];
506 m5206_mbar_writew(opaque
, offset
, value
>> 16);
507 m5206_mbar_writew(opaque
, offset
+ 2, value
& 0xffff);
510 m5206_mbar_write(s
, offset
, value
, 4);
513 static const MemoryRegionOps m5206_mbar_ops
= {
526 .endianness
= DEVICE_NATIVE_ENDIAN
,
529 qemu_irq
*mcf5206_init(MemoryRegion
*sysmem
, uint32_t base
, M68kCPU
*cpu
)
534 s
= (m5206_mbar_state
*)g_malloc0(sizeof(m5206_mbar_state
));
536 memory_region_init_io(&s
->iomem
, NULL
, &m5206_mbar_ops
, s
,
538 memory_region_add_subregion(sysmem
, base
, &s
->iomem
);
540 pic
= qemu_allocate_irqs(m5206_mbar_set_irq
, s
, 14);
541 s
->timer
[0] = m5206_timer_init(pic
[9]);
542 s
->timer
[1] = m5206_timer_init(pic
[10]);
543 s
->uart
[0] = mcf_uart_init(pic
[12], serial_hds
[0]);
544 s
->uart
[1] = mcf_uart_init(pic
[13], serial_hds
[1]);