hw/dma/bcm2835_dma.c

   1 /*
   2  * Raspberry Pi emulation (c) 2012 Gregory Estrade
   3  * This code is licensed under the GNU GPLv2 and later.
   4  */
   5
   6 #include "qemu/osdep.h"
   7 #include "hw/dma/bcm2835_dma.h"
   8
   9 /* DMA CS Control and Status bits */
  10 #define BCM2708_DMA_ACTIVE      (1 << 0)
  11 #define BCM2708_DMA_END         (1 << 1) /* GE */
  12 #define BCM2708_DMA_INT         (1 << 2)
  13 #define BCM2708_DMA_ISPAUSED    (1 << 4)  /* Pause requested or not active */
  14 #define BCM2708_DMA_ISHELD      (1 << 5)  /* Is held by DREQ flow control */
  15 #define BCM2708_DMA_ERR         (1 << 8)
  16 #define BCM2708_DMA_ABORT       (1 << 30) /* stop current CB, go to next, WO */
  17 #define BCM2708_DMA_RESET       (1 << 31) /* WO, self clearing */
  18
  19 /* DMA control block "info" field bits */
  20 #define BCM2708_DMA_INT_EN      (1 << 0)
  21 #define BCM2708_DMA_TDMODE      (1 << 1)
  22 #define BCM2708_DMA_WAIT_RESP   (1 << 3)
  23 #define BCM2708_DMA_D_INC       (1 << 4)
  24 #define BCM2708_DMA_D_WIDTH     (1 << 5)
  25 #define BCM2708_DMA_D_DREQ      (1 << 6)
  26 #define BCM2708_DMA_D_IGNORE    (1 << 7)
  27 #define BCM2708_DMA_S_INC       (1 << 8)
  28 #define BCM2708_DMA_S_WIDTH     (1 << 9)
  29 #define BCM2708_DMA_S_DREQ      (1 << 10)
  30 #define BCM2708_DMA_S_IGNORE    (1 << 11)
  31
  32 /* Register offsets */
  33 #define BCM2708_DMA_CS          0x00 /* Control and Status */
  34 #define BCM2708_DMA_ADDR        0x04 /* Control block address */
  35 /* the current control block appears in the following registers - read only */
  36 #define BCM2708_DMA_INFO        0x08
  37 #define BCM2708_DMA_SOURCE_AD   0x0c
  38 #define BCM2708_DMA_DEST_AD     0x10
  39 #define BCM2708_DMA_TXFR_LEN    0x14
  40 #define BCM2708_DMA_STRIDE      0x18
  41 #define BCM2708_DMA_NEXTCB      0x1C
  42 #define BCM2708_DMA_DEBUG       0x20
  43
  44 #define BCM2708_DMA_INT_STATUS  0xfe0 /* Interrupt status of each channel */
  45 #define BCM2708_DMA_ENABLE      0xff0 /* Global enable bits for each channel */
  46
  47 #define BCM2708_DMA_CS_RW_MASK  0x30ff0001 /* All RW bits in DMA_CS */
  48
  49 static void bcm2835_dma_update(BCM2835DMAState *s, unsigned c)
  50 {
  51     BCM2835DMAChan *ch = &s->chan[c];
  52     uint32_t data, xlen, ylen;
  53     int16_t dst_stride, src_stride;
  54
  55     if (!(s->enable & (1 << c))) {
  56         return;
  57     }
  58
  59     while ((s->enable & (1 << c)) && (ch->conblk_ad != 0)) {
  60         /* CB fetch */
  61         ch->ti = ldl_phys(&s->dma_as, ch->conblk_ad);
  62         ch->source_ad = ldl_phys(&s->dma_as, ch->conblk_ad + 4);
  63         ch->dest_ad = ldl_phys(&s->dma_as, ch->conblk_ad + 8);
  64         ch->txfr_len = ldl_phys(&s->dma_as, ch->conblk_ad + 12);
  65         ch->stride = ldl_phys(&s->dma_as, ch->conblk_ad + 16);
  66         ch->nextconbk = ldl_phys(&s->dma_as, ch->conblk_ad + 20);
  67
  68         if (ch->ti & BCM2708_DMA_TDMODE) {
  69             /* 2D transfer mode */
  70             ylen = (ch->txfr_len >> 16) & 0x3fff;
  71             xlen = ch->txfr_len & 0xffff;
  72             dst_stride = ch->stride >> 16;
  73             src_stride = ch->stride & 0xffff;
  74         } else {
  75             ylen = 1;
  76             xlen = ch->txfr_len;
  77             dst_stride = 0;
  78             src_stride = 0;
  79         }
  80
  81         while (ylen != 0) {
  82             /* Normal transfer mode */
  83             while (xlen != 0) {
  84                 if (ch->ti & BCM2708_DMA_S_IGNORE) {
  85                     /* Ignore reads */
  86                     data = 0;
  87                 } else {
  88                     data = ldl_phys(&s->dma_as, ch->source_ad);
  89                 }
  90                 if (ch->ti & BCM2708_DMA_S_INC) {
  91                     ch->source_ad += 4;
  92                 }
  93
  94                 if (ch->ti & BCM2708_DMA_D_IGNORE) {
  95                     /* Ignore writes */
  96                 } else {
  97                     stl_phys(&s->dma_as, ch->dest_ad, data);
  98                 }
  99                 if (ch->ti & BCM2708_DMA_D_INC) {
 100                     ch->dest_ad += 4;
 101                 }
 102
 103                 /* update remaining transfer length */
 104                 xlen -= 4;
 105                 if (ch->ti & BCM2708_DMA_TDMODE) {
 106                     ch->txfr_len = (ylen << 16) | xlen;
 107                 } else {
 108                     ch->txfr_len = xlen;
 109                 }
 110             }
 111
 112             if (--ylen != 0) {
 113                 ch->source_ad += src_stride;
 114                 ch->dest_ad += dst_stride;
 115             }
 116         }
 117         ch->cs |= BCM2708_DMA_END;
 118         if (ch->ti & BCM2708_DMA_INT_EN) {
 119             ch->cs |= BCM2708_DMA_INT;
 120             s->int_status |= (1 << c);
 121             qemu_set_irq(ch->irq, 1);
 122         }
 123
 124         /* Process next CB */
 125         ch->conblk_ad = ch->nextconbk;
 126     }
 127     ch->cs &= ~BCM2708_DMA_ACTIVE;
 128 }
 129
 130 static uint64_t bcm2835_dma_read(BCM2835DMAState *s, hwaddr offset,
 131                                  unsigned size, unsigned c)
 132 {
 133     BCM2835DMAChan *ch = &s->chan[c];
 134     uint32_t res = 0;
 135
 136     assert(size == 4);
 137     assert(c < BCM2835_DMA_NCHANS);
 138
 139     switch (offset) {
 140     case BCM2708_DMA_CS:
 141         res = ch->cs;
 142         break;
 143     case BCM2708_DMA_ADDR:
 144         res = ch->conblk_ad;
 145         break;
 146     case BCM2708_DMA_INFO:
 147         res = ch->ti;
 148         break;
 149     case BCM2708_DMA_SOURCE_AD:
 150         res = ch->source_ad;
 151         break;
 152     case BCM2708_DMA_DEST_AD:
 153         res = ch->dest_ad;
 154         break;
 155     case BCM2708_DMA_TXFR_LEN:
 156         res = ch->txfr_len;
 157         break;
 158     case BCM2708_DMA_STRIDE:
 159         res = ch->stride;
 160         break;
 161     case BCM2708_DMA_NEXTCB:
 162         res = ch->nextconbk;
 163         break;
 164     case BCM2708_DMA_DEBUG:
 165         res = ch->debug;
 166         break;
 167     default:
 168         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
 169                       __func__, offset);
 170         break;
 171     }
 172     return res;
 173 }
 174
 175 static void bcm2835_dma_write(BCM2835DMAState *s, hwaddr offset,
 176                               uint64_t value, unsigned size, unsigned c)
 177 {
 178     BCM2835DMAChan *ch = &s->chan[c];
 179     uint32_t oldcs;
 180
 181     assert(size == 4);
 182     assert(c < BCM2835_DMA_NCHANS);
 183
 184     switch (offset) {
 185     case BCM2708_DMA_CS:
 186         oldcs = ch->cs;
 187         if (value & BCM2708_DMA_RESET) {
 188             ch->cs |= BCM2708_DMA_RESET;
 189         }
 190         if (value & BCM2708_DMA_ABORT) {
 191             ch->cs |= BCM2708_DMA_ABORT;
 192         }
 193         if (value & BCM2708_DMA_END) {
 194             ch->cs &= ~BCM2708_DMA_END;
 195         }
 196         if (value & BCM2708_DMA_INT) {
 197             ch->cs &= ~BCM2708_DMA_INT;
 198             s->int_status &= ~(1 << c);
 199             qemu_set_irq(ch->irq, 0);
 200         }
 201         ch->cs &= ~BCM2708_DMA_CS_RW_MASK;
 202         ch->cs |= (value & BCM2708_DMA_CS_RW_MASK);
 203         if (!(oldcs & BCM2708_DMA_ACTIVE) && (ch->cs & BCM2708_DMA_ACTIVE)) {
 204             bcm2835_dma_update(s, c);
 205         }
 206         break;
 207     case BCM2708_DMA_ADDR:
 208         ch->conblk_ad = value;
 209         break;
 210     case BCM2708_DMA_DEBUG:
 211         ch->debug = value;
 212         break;
 213     default:
 214         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
 215                       __func__, offset);
 216         break;
 217     }
 218 }
 219
 220 static uint64_t bcm2835_dma0_read(void *opaque, hwaddr offset, unsigned size)
 221 {
 222     BCM2835DMAState *s = opaque;
 223
 224     if (offset < 0xf00) {
 225         return bcm2835_dma_read(s, (offset & 0xff), size, (offset >> 8) & 0xf);
 226     } else {
 227         switch (offset) {
 228         case BCM2708_DMA_INT_STATUS:
 229             return s->int_status;
 230         case BCM2708_DMA_ENABLE:
 231             return s->enable;
 232         default:
 233             qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
 234                           __func__, offset);
 235             return 0;
 236         }
 237     }
 238 }
 239
 240 static uint64_t bcm2835_dma15_read(void *opaque, hwaddr offset, unsigned size)
 241 {
 242     return bcm2835_dma_read(opaque, (offset & 0xff), size, 15);
 243 }
 244
 245 static void bcm2835_dma0_write(void *opaque, hwaddr offset, uint64_t value,
 246                                unsigned size)
 247 {
 248     BCM2835DMAState *s = opaque;
 249
 250     if (offset < 0xf00) {
 251         bcm2835_dma_write(s, (offset & 0xff), value, size, (offset >> 8) & 0xf);
 252     } else {
 253         switch (offset) {
 254         case BCM2708_DMA_INT_STATUS:
 255             break;
 256         case BCM2708_DMA_ENABLE:
 257             s->enable = (value & 0xffff);
 258             break;
 259         default:
 260             qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
 261                           __func__, offset);
 262         }
 263     }
 264
 265 }
 266
 267 static void bcm2835_dma15_write(void *opaque, hwaddr offset, uint64_t value,
 268                                 unsigned size)
 269 {
 270     bcm2835_dma_write(opaque, (offset & 0xff), value, size, 15);
 271 }
 272
 273 static const MemoryRegionOps bcm2835_dma0_ops = {
 274     .read = bcm2835_dma0_read,
 275     .write = bcm2835_dma0_write,
 276     .endianness = DEVICE_NATIVE_ENDIAN,
 277     .valid.min_access_size = 4,
 278     .valid.max_access_size = 4,
 279 };
 280
 281 static const MemoryRegionOps bcm2835_dma15_ops = {
 282     .read = bcm2835_dma15_read,
 283     .write = bcm2835_dma15_write,
 284     .endianness = DEVICE_NATIVE_ENDIAN,
 285     .valid.min_access_size = 4,
 286     .valid.max_access_size = 4,
 287 };
 288
 289 static const VMStateDescription vmstate_bcm2835_dma_chan = {
 290     .name = TYPE_BCM2835_DMA "-chan",
 291     .version_id = 1,
 292     .minimum_version_id = 1,
 293     .fields = (VMStateField[]) {
 294         VMSTATE_UINT32(cs, BCM2835DMAChan),
 295         VMSTATE_UINT32(conblk_ad, BCM2835DMAChan),
 296         VMSTATE_UINT32(ti, BCM2835DMAChan),
 297         VMSTATE_UINT32(source_ad, BCM2835DMAChan),
 298         VMSTATE_UINT32(dest_ad, BCM2835DMAChan),
 299         VMSTATE_UINT32(txfr_len, BCM2835DMAChan),
 300         VMSTATE_UINT32(stride, BCM2835DMAChan),
 301         VMSTATE_UINT32(nextconbk, BCM2835DMAChan),
 302         VMSTATE_UINT32(debug, BCM2835DMAChan),
 303         VMSTATE_END_OF_LIST()
 304     }
 305 };
 306
 307 static const VMStateDescription vmstate_bcm2835_dma = {
 308     .name = TYPE_BCM2835_DMA,
 309     .version_id = 1,
 310     .minimum_version_id = 1,
 311     .fields = (VMStateField[]) {
 312         VMSTATE_STRUCT_ARRAY(chan, BCM2835DMAState, BCM2835_DMA_NCHANS, 1,
 313                              vmstate_bcm2835_dma_chan, BCM2835DMAChan),
 314         VMSTATE_UINT32(int_status, BCM2835DMAState),
 315         VMSTATE_UINT32(enable, BCM2835DMAState),
 316         VMSTATE_END_OF_LIST()
 317     }
 318 };
 319
 320 static void bcm2835_dma_init(Object *obj)
 321 {
 322     BCM2835DMAState *s = BCM2835_DMA(obj);
 323     int n;
 324
 325     /* DMA channels 0-14 occupy a contiguous block of IO memory, along
 326      * with the global enable and interrupt status bits. Channel 15
 327      * has the same register map, but is mapped at a discontiguous
 328      * address in a separate IO block.
 329      */
 330     memory_region_init_io(&s->iomem0, OBJECT(s), &bcm2835_dma0_ops, s,
 331                           TYPE_BCM2835_DMA, 0x1000);
 332     sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem0);
 333
 334     memory_region_init_io(&s->iomem15, OBJECT(s), &bcm2835_dma15_ops, s,
 335                           TYPE_BCM2835_DMA "-chan15", 0x100);
 336     sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem15);
 337
 338     for (n = 0; n < 16; n++) {
 339         sysbus_init_irq(SYS_BUS_DEVICE(s), &s->chan[n].irq);
 340     }
 341 }
 342
 343 static void bcm2835_dma_reset(DeviceState *dev)
 344 {
 345     BCM2835DMAState *s = BCM2835_DMA(dev);
 346     int n;
 347
 348     s->enable = 0xffff;
 349     s->int_status = 0;
 350     for (n = 0; n < BCM2835_DMA_NCHANS; n++) {
 351         s->chan[n].cs = 0;
 352         s->chan[n].conblk_ad = 0;
 353     }
 354 }
 355
 356 static void bcm2835_dma_realize(DeviceState *dev, Error **errp)
 357 {
 358     BCM2835DMAState *s = BCM2835_DMA(dev);
 359     Error *err = NULL;
 360     Object *obj;
 361
 362     obj = object_property_get_link(OBJECT(dev), "dma-mr", &err);
 363     if (obj == NULL) {
 364         error_setg(errp, "%s: required dma-mr link not found: %s",
 365                    __func__, error_get_pretty(err));
 366         return;
 367     }
 368
 369     s->dma_mr = MEMORY_REGION(obj);
 370     address_space_init(&s->dma_as, s->dma_mr, NULL);
 371
 372     bcm2835_dma_reset(dev);
 373 }
 374
 375 static void bcm2835_dma_class_init(ObjectClass *klass, void *data)
 376 {
 377     DeviceClass *dc = DEVICE_CLASS(klass);
 378
 379     dc->realize = bcm2835_dma_realize;
 380     dc->reset = bcm2835_dma_reset;
 381     dc->vmsd = &vmstate_bcm2835_dma;
 382 }
 383
 384 static TypeInfo bcm2835_dma_info = {
 385     .name          = TYPE_BCM2835_DMA,
 386     .parent        = TYPE_SYS_BUS_DEVICE,
 387     .instance_size = sizeof(BCM2835DMAState),
 388     .class_init    = bcm2835_dma_class_init,
 389     .instance_init = bcm2835_dma_init,
 390 };
 391
 392 static void bcm2835_dma_register_types(void)
 393 {
 394     type_register_static(&bcm2835_dma_info);
 395 }
 396
 397 type_init(bcm2835_dma_register_types)