block/nvme.c

   1 /*
   2  * NVMe block driver based on vfio
   3  *
   4  * Copyright 2016 - 2018 Red Hat, Inc.
   5  *
   6  * Authors:
   7  *   Fam Zheng <famz@redhat.com>
   8  *   Paolo Bonzini <pbonzini@redhat.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  */
  13
  14 #include "qemu/osdep.h"
  15 #include <linux/vfio.h>
  16 #include "qapi/error.h"
  17 #include "qapi/qmp/qdict.h"
  18 #include "qapi/qmp/qstring.h"
  19 #include "qemu/error-report.h"
  20 #include "qemu/cutils.h"
  21 #include "qemu/option.h"
  22 #include "qemu/vfio-helpers.h"
  23 #include "block/block_int.h"
  24 #include "trace.h"
  25
  26 #include "block/nvme.h"
  27
  28 #define NVME_SQ_ENTRY_BYTES 64
  29 #define NVME_CQ_ENTRY_BYTES 16
  30 #define NVME_QUEUE_SIZE 128
  31 #define NVME_BAR_SIZE 8192
  32
  33 typedef struct {
  34     int32_t  head, tail;
  35     uint8_t  *queue;
  36     uint64_t iova;
  37     /* Hardware MMIO register */
  38     volatile uint32_t *doorbell;
  39 } NVMeQueue;
  40
  41 typedef struct {
  42     BlockCompletionFunc *cb;
  43     void *opaque;
  44     int cid;
  45     void *prp_list_page;
  46     uint64_t prp_list_iova;
  47     bool busy;
  48 } NVMeRequest;
  49
  50 typedef struct {
  51     CoQueue     free_req_queue;
  52     QemuMutex   lock;
  53
  54     /* Fields protected by BQL */
  55     int         index;
  56     uint8_t     *prp_list_pages;
  57
  58     /* Fields protected by @lock */
  59     NVMeQueue   sq, cq;
  60     int         cq_phase;
  61     NVMeRequest reqs[NVME_QUEUE_SIZE];
  62     bool        busy;
  63     int         need_kick;
  64     int         inflight;
  65 } NVMeQueuePair;
  66
  67 /* Memory mapped registers */
  68 typedef volatile struct {
  69     uint64_t cap;
  70     uint32_t vs;
  71     uint32_t intms;
  72     uint32_t intmc;
  73     uint32_t cc;
  74     uint32_t reserved0;
  75     uint32_t csts;
  76     uint32_t nssr;
  77     uint32_t aqa;
  78     uint64_t asq;
  79     uint64_t acq;
  80     uint32_t cmbloc;
  81     uint32_t cmbsz;
  82     uint8_t  reserved1[0xec0];
  83     uint8_t  cmd_set_specfic[0x100];
  84     uint32_t doorbells[];
  85 } QEMU_PACKED NVMeRegs;
  86
  87 QEMU_BUILD_BUG_ON(offsetof(NVMeRegs, doorbells) != 0x1000);
  88
  89 typedef struct {
  90     AioContext *aio_context;
  91     QEMUVFIOState *vfio;
  92     NVMeRegs *regs;
  93     /* The submission/completion queue pairs.
  94      * [0]: admin queue.
  95      * [1..]: io queues.
  96      */
  97     NVMeQueuePair **queues;
  98     int nr_queues;
  99     size_t page_size;
 100     /* How many uint32_t elements does each doorbell entry take. */
 101     size_t doorbell_scale;
 102     bool write_cache_supported;
 103     EventNotifier irq_notifier;
 104     uint64_t nsze; /* Namespace size reported by identify command */
 105     int nsid;      /* The namespace id to read/write data. */
 106     uint64_t max_transfer;
 107     bool plugged;
 108
 109     CoMutex dma_map_lock;
 110     CoQueue dma_flush_queue;
 111
 112     /* Total size of mapped qiov, accessed under dma_map_lock */
 113     int dma_map_count;
 114 } BDRVNVMeState;
 115
 116 #define NVME_BLOCK_OPT_DEVICE "device"
 117 #define NVME_BLOCK_OPT_NAMESPACE "namespace"
 118
 119 static QemuOptsList runtime_opts = {
 120     .name = "nvme",
 121     .head = QTAILQ_HEAD_INITIALIZER(runtime_opts.head),
 122     .desc = {
 123         {
 124             .name = NVME_BLOCK_OPT_DEVICE,
 125             .type = QEMU_OPT_STRING,
 126             .help = "NVMe PCI device address",
 127         },
 128         {
 129             .name = NVME_BLOCK_OPT_NAMESPACE,
 130             .type = QEMU_OPT_NUMBER,
 131             .help = "NVMe namespace",
 132         },
 133         { /* end of list */ }
 134     },
 135 };
 136
 137 static void nvme_init_queue(BlockDriverState *bs, NVMeQueue *q,
 138                             int nentries, int entry_bytes, Error **errp)
 139 {
 140     BDRVNVMeState *s = bs->opaque;
 141     size_t bytes;
 142     int r;
 143
 144     bytes = ROUND_UP(nentries * entry_bytes, s->page_size);
 145     q->head = q->tail = 0;
 146     q->queue = qemu_try_blockalign0(bs, bytes);
 147
 148     if (!q->queue) {
 149         error_setg(errp, "Cannot allocate queue");
 150         return;
 151     }
 152     r = qemu_vfio_dma_map(s->vfio, q->queue, bytes, false, &q->iova);
 153     if (r) {
 154         error_setg(errp, "Cannot map queue");
 155     }
 156 }
 157
 158 static void nvme_free_queue_pair(BlockDriverState *bs, NVMeQueuePair *q)
 159 {
 160     qemu_vfree(q->prp_list_pages);
 161     qemu_vfree(q->sq.queue);
 162     qemu_vfree(q->cq.queue);
 163     qemu_mutex_destroy(&q->lock);
 164     g_free(q);
 165 }
 166
 167 static void nvme_free_req_queue_cb(void *opaque)
 168 {
 169     NVMeQueuePair *q = opaque;
 170
 171     qemu_mutex_lock(&q->lock);
 172     while (qemu_co_enter_next(&q->free_req_queue, &q->lock)) {
 173         /* Retry all pending requests */
 174     }
 175     qemu_mutex_unlock(&q->lock);
 176 }
 177
 178 static NVMeQueuePair *nvme_create_queue_pair(BlockDriverState *bs,
 179                                              int idx, int size,
 180                                              Error **errp)
 181 {
 182     int i, r;
 183     BDRVNVMeState *s = bs->opaque;
 184     Error *local_err = NULL;
 185     NVMeQueuePair *q = g_new0(NVMeQueuePair, 1);
 186     uint64_t prp_list_iova;
 187
 188     qemu_mutex_init(&q->lock);
 189     q->index = idx;
 190     qemu_co_queue_init(&q->free_req_queue);
 191     q->prp_list_pages = qemu_blockalign0(bs, s->page_size * NVME_QUEUE_SIZE);
 192     r = qemu_vfio_dma_map(s->vfio, q->prp_list_pages,
 193                           s->page_size * NVME_QUEUE_SIZE,
 194                           false, &prp_list_iova);
 195     if (r) {
 196         goto fail;
 197     }
 198     for (i = 0; i < NVME_QUEUE_SIZE; i++) {
 199         NVMeRequest *req = &q->reqs[i];
 200         req->cid = i + 1;
 201         req->prp_list_page = q->prp_list_pages + i * s->page_size;
 202         req->prp_list_iova = prp_list_iova + i * s->page_size;
 203     }
 204     nvme_init_queue(bs, &q->sq, size, NVME_SQ_ENTRY_BYTES, &local_err);
 205     if (local_err) {
 206         error_propagate(errp, local_err);
 207         goto fail;
 208     }
 209     q->sq.doorbell = &s->regs->doorbells[idx * 2 * s->doorbell_scale];
 210
 211     nvme_init_queue(bs, &q->cq, size, NVME_CQ_ENTRY_BYTES, &local_err);
 212     if (local_err) {
 213         error_propagate(errp, local_err);
 214         goto fail;
 215     }
 216     q->cq.doorbell = &s->regs->doorbells[idx * 2 * s->doorbell_scale + 1];
 217
 218     return q;
 219 fail:
 220     nvme_free_queue_pair(bs, q);
 221     return NULL;
 222 }
 223
 224 /* With q->lock */
 225 static void nvme_kick(BDRVNVMeState *s, NVMeQueuePair *q)
 226 {
 227     if (s->plugged || !q->need_kick) {
 228         return;
 229     }
 230     trace_nvme_kick(s, q->index);
 231     assert(!(q->sq.tail & 0xFF00));
 232     /* Fence the write to submission queue entry before notifying the device. */
 233     smp_wmb();
 234     *q->sq.doorbell = cpu_to_le32(q->sq.tail);
 235     q->inflight += q->need_kick;
 236     q->need_kick = 0;
 237 }
 238
 239 /* Find a free request element if any, otherwise:
 240  * a) if in coroutine context, try to wait for one to become available;
 241  * b) if not in coroutine, return NULL;
 242  */
 243 static NVMeRequest *nvme_get_free_req(NVMeQueuePair *q)
 244 {
 245     int i;
 246     NVMeRequest *req = NULL;
 247
 248     qemu_mutex_lock(&q->lock);
 249     while (q->inflight + q->need_kick > NVME_QUEUE_SIZE - 2) {
 250         /* We have to leave one slot empty as that is the full queue case (head
 251          * == tail + 1). */
 252         if (qemu_in_coroutine()) {
 253             trace_nvme_free_req_queue_wait(q);
 254             qemu_co_queue_wait(&q->free_req_queue, &q->lock);
 255         } else {
 256             qemu_mutex_unlock(&q->lock);
 257             return NULL;
 258         }
 259     }
 260     for (i = 0; i < NVME_QUEUE_SIZE; i++) {
 261         if (!q->reqs[i].busy) {
 262             q->reqs[i].busy = true;
 263             req = &q->reqs[i];
 264             break;
 265         }
 266     }
 267     /* We have checked inflight and need_kick while holding q->lock, so one
 268      * free req must be available. */
 269     assert(req);
 270     qemu_mutex_unlock(&q->lock);
 271     return req;
 272 }
 273
 274 static inline int nvme_translate_error(const NvmeCqe *c)
 275 {
 276     uint16_t status = (le16_to_cpu(c->status) >> 1) & 0xFF;
 277     if (status) {
 278         trace_nvme_error(le32_to_cpu(c->result),
 279                          le16_to_cpu(c->sq_head),
 280                          le16_to_cpu(c->sq_id),
 281                          le16_to_cpu(c->cid),
 282                          le16_to_cpu(status));
 283     }
 284     switch (status) {
 285     case 0:
 286         return 0;
 287     case 1:
 288         return -ENOSYS;
 289     case 2:
 290         return -EINVAL;
 291     default:
 292         return -EIO;
 293     }
 294 }
 295
 296 /* With q->lock */
 297 static bool nvme_process_completion(BDRVNVMeState *s, NVMeQueuePair *q)
 298 {
 299     bool progress = false;
 300     NVMeRequest *preq;
 301     NVMeRequest req;
 302     NvmeCqe *c;
 303
 304     trace_nvme_process_completion(s, q->index, q->inflight);
 305     if (q->busy || s->plugged) {
 306         trace_nvme_process_completion_queue_busy(s, q->index);
 307         return false;
 308     }
 309     q->busy = true;
 310     assert(q->inflight >= 0);
 311     while (q->inflight) {
 312         int16_t cid;
 313         c = (NvmeCqe *)&q->cq.queue[q->cq.head * NVME_CQ_ENTRY_BYTES];
 314         if (!c->cid || (le16_to_cpu(c->status) & 0x1) == q->cq_phase) {
 315             break;
 316         }
 317         q->cq.head = (q->cq.head + 1) % NVME_QUEUE_SIZE;
 318         if (!q->cq.head) {
 319             q->cq_phase = !q->cq_phase;
 320         }
 321         cid = le16_to_cpu(c->cid);
 322         if (cid == 0 || cid > NVME_QUEUE_SIZE) {
 323             fprintf(stderr, "Unexpected CID in completion queue: %" PRIu32 "\n",
 324                     cid);
 325             continue;
 326         }
 327         assert(cid <= NVME_QUEUE_SIZE);
 328         trace_nvme_complete_command(s, q->index, cid);
 329         preq = &q->reqs[cid - 1];
 330         req = *preq;
 331         assert(req.cid == cid);
 332         assert(req.cb);
 333         preq->busy = false;
 334         preq->cb = preq->opaque = NULL;
 335         qemu_mutex_unlock(&q->lock);
 336         req.cb(req.opaque, nvme_translate_error(c));
 337         qemu_mutex_lock(&q->lock);
 338         c->cid = cpu_to_le16(0);
 339         q->inflight--;
 340         /* Flip Phase Tag bit. */
 341         c->status = cpu_to_le16(le16_to_cpu(c->status) ^ 0x1);
 342         progress = true;
 343     }
 344     if (progress) {
 345         /* Notify the device so it can post more completions. */
 346         smp_mb_release();
 347         *q->cq.doorbell = cpu_to_le32(q->cq.head);
 348         if (!qemu_co_queue_empty(&q->free_req_queue)) {
 349             aio_bh_schedule_oneshot(s->aio_context, nvme_free_req_queue_cb, q);
 350         }
 351     }
 352     q->busy = false;
 353     return progress;
 354 }
 355
 356 static void nvme_trace_command(const NvmeCmd *cmd)
 357 {
 358     int i;
 359
 360     for (i = 0; i < 8; ++i) {
 361         uint8_t *cmdp = (uint8_t *)cmd + i * 8;
 362         trace_nvme_submit_command_raw(cmdp[0], cmdp[1], cmdp[2], cmdp[3],
 363                                       cmdp[4], cmdp[5], cmdp[6], cmdp[7]);
 364     }
 365 }
 366
 367 static void nvme_submit_command(BDRVNVMeState *s, NVMeQueuePair *q,
 368                                 NVMeRequest *req,
 369                                 NvmeCmd *cmd, BlockCompletionFunc cb,
 370                                 void *opaque)
 371 {
 372     assert(!req->cb);
 373     req->cb = cb;
 374     req->opaque = opaque;
 375     cmd->cid = cpu_to_le32(req->cid);
 376
 377     trace_nvme_submit_command(s, q->index, req->cid);
 378     nvme_trace_command(cmd);
 379     qemu_mutex_lock(&q->lock);
 380     memcpy((uint8_t *)q->sq.queue +
 381            q->sq.tail * NVME_SQ_ENTRY_BYTES, cmd, sizeof(*cmd));
 382     q->sq.tail = (q->sq.tail + 1) % NVME_QUEUE_SIZE;
 383     q->need_kick++;
 384     nvme_kick(s, q);
 385     nvme_process_completion(s, q);
 386     qemu_mutex_unlock(&q->lock);
 387 }
 388
 389 static void nvme_cmd_sync_cb(void *opaque, int ret)
 390 {
 391     int *pret = opaque;
 392     *pret = ret;
 393 }
 394
 395 static int nvme_cmd_sync(BlockDriverState *bs, NVMeQueuePair *q,
 396                          NvmeCmd *cmd)
 397 {
 398     NVMeRequest *req;
 399     BDRVNVMeState *s = bs->opaque;
 400     int ret = -EINPROGRESS;
 401     req = nvme_get_free_req(q);
 402     if (!req) {
 403         return -EBUSY;
 404     }
 405     nvme_submit_command(s, q, req, cmd, nvme_cmd_sync_cb, &ret);
 406
 407     BDRV_POLL_WHILE(bs, ret == -EINPROGRESS);
 408     return ret;
 409 }
 410
 411 static void nvme_identify(BlockDriverState *bs, int namespace, Error **errp)
 412 {
 413     BDRVNVMeState *s = bs->opaque;
 414     NvmeIdCtrl *idctrl;
 415     NvmeIdNs *idns;
 416     uint8_t *resp;
 417     int r;
 418     uint64_t iova;
 419     NvmeCmd cmd = {
 420         .opcode = NVME_ADM_CMD_IDENTIFY,
 421         .cdw10 = cpu_to_le32(0x1),
 422     };
 423
 424     resp = qemu_try_blockalign0(bs, sizeof(NvmeIdCtrl));
 425     if (!resp) {
 426         error_setg(errp, "Cannot allocate buffer for identify response");
 427         goto out;
 428     }
 429     idctrl = (NvmeIdCtrl *)resp;
 430     idns = (NvmeIdNs *)resp;
 431     r = qemu_vfio_dma_map(s->vfio, resp, sizeof(NvmeIdCtrl), true, &iova);
 432     if (r) {
 433         error_setg(errp, "Cannot map buffer for DMA");
 434         goto out;
 435     }
 436     cmd.prp1 = cpu_to_le64(iova);
 437
 438     if (nvme_cmd_sync(bs, s->queues[0], &cmd)) {
 439         error_setg(errp, "Failed to identify controller");
 440         goto out;
 441     }
 442
 443     if (le32_to_cpu(idctrl->nn) < namespace) {
 444         error_setg(errp, "Invalid namespace");
 445         goto out;
 446     }
 447     s->write_cache_supported = le32_to_cpu(idctrl->vwc) & 0x1;
 448     s->max_transfer = (idctrl->mdts ? 1 << idctrl->mdts : 0) * s->page_size;
 449     /* For now the page list buffer per command is one page, to hold at most
 450      * s->page_size / sizeof(uint64_t) entries. */
 451     s->max_transfer = MIN_NON_ZERO(s->max_transfer,
 452                           s->page_size / sizeof(uint64_t) * s->page_size);
 453
 454     memset(resp, 0, 4096);
 455
 456     cmd.cdw10 = 0;
 457     cmd.nsid = cpu_to_le32(namespace);
 458     if (nvme_cmd_sync(bs, s->queues[0], &cmd)) {
 459         error_setg(errp, "Failed to identify namespace");
 460         goto out;
 461     }
 462
 463     s->nsze = le64_to_cpu(idns->nsze);
 464
 465 out:
 466     qemu_vfio_dma_unmap(s->vfio, resp);
 467     qemu_vfree(resp);
 468 }
 469
 470 static bool nvme_poll_queues(BDRVNVMeState *s)
 471 {
 472     bool progress = false;
 473     int i;
 474
 475     for (i = 0; i < s->nr_queues; i++) {
 476         NVMeQueuePair *q = s->queues[i];
 477         qemu_mutex_lock(&q->lock);
 478         while (nvme_process_completion(s, q)) {
 479             /* Keep polling */
 480             progress = true;
 481         }
 482         qemu_mutex_unlock(&q->lock);
 483     }
 484     return progress;
 485 }
 486
 487 static void nvme_handle_event(EventNotifier *n)
 488 {
 489     BDRVNVMeState *s = container_of(n, BDRVNVMeState, irq_notifier);
 490
 491     trace_nvme_handle_event(s);
 492     event_notifier_test_and_clear(n);
 493     nvme_poll_queues(s);
 494 }
 495
 496 static bool nvme_add_io_queue(BlockDriverState *bs, Error **errp)
 497 {
 498     BDRVNVMeState *s = bs->opaque;
 499     int n = s->nr_queues;
 500     NVMeQueuePair *q;
 501     NvmeCmd cmd;
 502     int queue_size = NVME_QUEUE_SIZE;
 503
 504     q = nvme_create_queue_pair(bs, n, queue_size, errp);
 505     if (!q) {
 506         return false;
 507     }
 508     cmd = (NvmeCmd) {
 509         .opcode = NVME_ADM_CMD_CREATE_CQ,
 510         .prp1 = cpu_to_le64(q->cq.iova),
 511         .cdw10 = cpu_to_le32(((queue_size - 1) << 16) | (n & 0xFFFF)),
 512         .cdw11 = cpu_to_le32(0x3),
 513     };
 514     if (nvme_cmd_sync(bs, s->queues[0], &cmd)) {
 515         error_setg(errp, "Failed to create io queue [%d]", n);
 516         nvme_free_queue_pair(bs, q);
 517         return false;
 518     }
 519     cmd = (NvmeCmd) {
 520         .opcode = NVME_ADM_CMD_CREATE_SQ,
 521         .prp1 = cpu_to_le64(q->sq.iova),
 522         .cdw10 = cpu_to_le32(((queue_size - 1) << 16) | (n & 0xFFFF)),
 523         .cdw11 = cpu_to_le32(0x1 | (n << 16)),
 524     };
 525     if (nvme_cmd_sync(bs, s->queues[0], &cmd)) {
 526         error_setg(errp, "Failed to create io queue [%d]", n);
 527         nvme_free_queue_pair(bs, q);
 528         return false;
 529     }
 530     s->queues = g_renew(NVMeQueuePair *, s->queues, n + 1);
 531     s->queues[n] = q;
 532     s->nr_queues++;
 533     return true;
 534 }
 535
 536 static bool nvme_poll_cb(void *opaque)
 537 {
 538     EventNotifier *e = opaque;
 539     BDRVNVMeState *s = container_of(e, BDRVNVMeState, irq_notifier);
 540     bool progress = false;
 541
 542     trace_nvme_poll_cb(s);
 543     progress = nvme_poll_queues(s);
 544     return progress;
 545 }
 546
 547 static int nvme_init(BlockDriverState *bs, const char *device, int namespace,
 548                      Error **errp)
 549 {
 550     BDRVNVMeState *s = bs->opaque;
 551     int ret;
 552     uint64_t cap;
 553     uint64_t timeout_ms;
 554     uint64_t deadline, now;
 555     Error *local_err = NULL;
 556
 557     qemu_co_mutex_init(&s->dma_map_lock);
 558     qemu_co_queue_init(&s->dma_flush_queue);
 559     s->nsid = namespace;
 560     s->aio_context = bdrv_get_aio_context(bs);
 561     ret = event_notifier_init(&s->irq_notifier, 0);
 562     if (ret) {
 563         error_setg(errp, "Failed to init event notifier");
 564         return ret;
 565     }
 566
 567     s->vfio = qemu_vfio_open_pci(device, errp);
 568     if (!s->vfio) {
 569         ret = -EINVAL;
 570         goto out;
 571     }
 572
 573     s->regs = qemu_vfio_pci_map_bar(s->vfio, 0, 0, NVME_BAR_SIZE, errp);
 574     if (!s->regs) {
 575         ret = -EINVAL;
 576         goto out;
 577     }
 578
 579     /* Perform initialize sequence as described in NVMe spec "7.6.1
 580      * Initialization". */
 581
 582     cap = le64_to_cpu(s->regs->cap);
 583     if (!(cap & (1ULL << 37))) {
 584         error_setg(errp, "Device doesn't support NVMe command set");
 585         ret = -EINVAL;
 586         goto out;
 587     }
 588
 589     s->page_size = MAX(4096, 1 << (12 + ((cap >> 48) & 0xF)));
 590     s->doorbell_scale = (4 << (((cap >> 32) & 0xF))) / sizeof(uint32_t);
 591     bs->bl.opt_mem_alignment = s->page_size;
 592     timeout_ms = MIN(500 * ((cap >> 24) & 0xFF), 30000);
 593
 594     /* Reset device to get a clean state. */
 595     s->regs->cc = cpu_to_le32(le32_to_cpu(s->regs->cc) & 0xFE);
 596     /* Wait for CSTS.RDY = 0. */
 597     deadline = qemu_clock_get_ns(QEMU_CLOCK_REALTIME) + timeout_ms * 1000000ULL;
 598     while (le32_to_cpu(s->regs->csts) & 0x1) {
 599         if (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) > deadline) {
 600             error_setg(errp, "Timeout while waiting for device to reset (%"
 601                              PRId64 " ms)",
 602                        timeout_ms);
 603             ret = -ETIMEDOUT;
 604             goto out;
 605         }
 606     }
 607
 608     /* Set up admin queue. */
 609     s->queues = g_new(NVMeQueuePair *, 1);
 610     s->nr_queues = 1;
 611     s->queues[0] = nvme_create_queue_pair(bs, 0, NVME_QUEUE_SIZE, errp);
 612     if (!s->queues[0]) {
 613         ret = -EINVAL;
 614         goto out;
 615     }
 616     QEMU_BUILD_BUG_ON(NVME_QUEUE_SIZE & 0xF000);
 617     s->regs->aqa = cpu_to_le32((NVME_QUEUE_SIZE << 16) | NVME_QUEUE_SIZE);
 618     s->regs->asq = cpu_to_le64(s->queues[0]->sq.iova);
 619     s->regs->acq = cpu_to_le64(s->queues[0]->cq.iova);
 620
 621     /* After setting up all control registers we can enable device now. */
 622     s->regs->cc = cpu_to_le32((ctz32(NVME_CQ_ENTRY_BYTES) << 20) |
 623                               (ctz32(NVME_SQ_ENTRY_BYTES) << 16) |
 624                               0x1);
 625     /* Wait for CSTS.RDY = 1. */
 626     now = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
 627     deadline = now + timeout_ms * 1000000;
 628     while (!(le32_to_cpu(s->regs->csts) & 0x1)) {
 629         if (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) > deadline) {
 630             error_setg(errp, "Timeout while waiting for device to start (%"
 631                              PRId64 " ms)",
 632                        timeout_ms);
 633             ret = -ETIMEDOUT;
 634             goto out;
 635         }
 636     }
 637
 638     ret = qemu_vfio_pci_init_irq(s->vfio, &s->irq_notifier,
 639                                  VFIO_PCI_MSIX_IRQ_INDEX, errp);
 640     if (ret) {
 641         goto out;
 642     }
 643     aio_set_event_notifier(bdrv_get_aio_context(bs), &s->irq_notifier,
 644                            false, nvme_handle_event, nvme_poll_cb);
 645
 646     nvme_identify(bs, namespace, &local_err);
 647     if (local_err) {
 648         error_propagate(errp, local_err);
 649         ret = -EIO;
 650         goto out;
 651     }
 652
 653     /* Set up command queues. */
 654     if (!nvme_add_io_queue(bs, errp)) {
 655         ret = -EIO;
 656     }
 657 out:
 658     /* Cleaning up is done in nvme_file_open() upon error. */
 659     return ret;
 660 }
 661
 662 /* Parse a filename in the format of nvme://XXXX:XX:XX.X/X. Example:
 663  *
 664  *     nvme://0000:44:00.0/1
 665  *
 666  * where the "nvme://" is a fixed form of the protocol prefix, the middle part
 667  * is the PCI address, and the last part is the namespace number starting from
 668  * 1 according to the NVMe spec. */
 669 static void nvme_parse_filename(const char *filename, QDict *options,
 670                                 Error **errp)
 671 {
 672     int pref = strlen("nvme://");
 673
 674     if (strlen(filename) > pref && !strncmp(filename, "nvme://", pref)) {
 675         const char *tmp = filename + pref;
 676         char *device;
 677         const char *namespace;
 678         unsigned long ns;
 679         const char *slash = strchr(tmp, '/');
 680         if (!slash) {
 681             qdict_put_str(options, NVME_BLOCK_OPT_DEVICE, tmp);
 682             return;
 683         }
 684         device = g_strndup(tmp, slash - tmp);
 685         qdict_put_str(options, NVME_BLOCK_OPT_DEVICE, device);
 686         g_free(device);
 687         namespace = slash + 1;
 688         if (*namespace && qemu_strtoul(namespace, NULL, 10, &ns)) {
 689             error_setg(errp, "Invalid namespace '%s', positive number expected",
 690                        namespace);
 691             return;
 692         }
 693         qdict_put_str(options, NVME_BLOCK_OPT_NAMESPACE,
 694                       *namespace ? namespace : "1");
 695     }
 696 }
 697
 698 static int nvme_enable_disable_write_cache(BlockDriverState *bs, bool enable,
 699                                            Error **errp)
 700 {
 701     int ret;
 702     BDRVNVMeState *s = bs->opaque;
 703     NvmeCmd cmd = {
 704         .opcode = NVME_ADM_CMD_SET_FEATURES,
 705         .nsid = cpu_to_le32(s->nsid),
 706         .cdw10 = cpu_to_le32(0x06),
 707         .cdw11 = cpu_to_le32(enable ? 0x01 : 0x00),
 708     };
 709
 710     ret = nvme_cmd_sync(bs, s->queues[0], &cmd);
 711     if (ret) {
 712         error_setg(errp, "Failed to configure NVMe write cache");
 713     }
 714     return ret;
 715 }
 716
 717 static void nvme_close(BlockDriverState *bs)
 718 {
 719     int i;
 720     BDRVNVMeState *s = bs->opaque;
 721
 722     for (i = 0; i < s->nr_queues; ++i) {
 723         nvme_free_queue_pair(bs, s->queues[i]);
 724     }
 725     g_free(s->queues);
 726     aio_set_event_notifier(bdrv_get_aio_context(bs), &s->irq_notifier,
 727                            false, NULL, NULL);
 728     event_notifier_cleanup(&s->irq_notifier);
 729     qemu_vfio_pci_unmap_bar(s->vfio, 0, (void *)s->regs, 0, NVME_BAR_SIZE);
 730     qemu_vfio_close(s->vfio);
 731 }
 732
 733 static int nvme_file_open(BlockDriverState *bs, QDict *options, int flags,
 734                           Error **errp)
 735 {
 736     const char *device;
 737     QemuOpts *opts;
 738     int namespace;
 739     int ret;
 740     BDRVNVMeState *s = bs->opaque;
 741
 742     opts = qemu_opts_create(&runtime_opts, NULL, 0, &error_abort);
 743     qemu_opts_absorb_qdict(opts, options, &error_abort);
 744     device = qemu_opt_get(opts, NVME_BLOCK_OPT_DEVICE);
 745     if (!device) {
 746         error_setg(errp, "'" NVME_BLOCK_OPT_DEVICE "' option is required");
 747         qemu_opts_del(opts);
 748         return -EINVAL;
 749     }
 750
 751     namespace = qemu_opt_get_number(opts, NVME_BLOCK_OPT_NAMESPACE, 1);
 752     ret = nvme_init(bs, device, namespace, errp);
 753     qemu_opts_del(opts);
 754     if (ret) {
 755         goto fail;
 756     }
 757     if (flags & BDRV_O_NOCACHE) {
 758         if (!s->write_cache_supported) {
 759             error_setg(errp,
 760                        "NVMe controller doesn't support write cache configuration");
 761             ret = -EINVAL;
 762         } else {
 763             ret = nvme_enable_disable_write_cache(bs, !(flags & BDRV_O_NOCACHE),
 764                                                   errp);
 765         }
 766         if (ret) {
 767             goto fail;
 768         }
 769     }
 770     bs->supported_write_flags = BDRV_REQ_FUA;
 771     return 0;
 772 fail:
 773     nvme_close(bs);
 774     return ret;
 775 }
 776
 777 static int64_t nvme_getlength(BlockDriverState *bs)
 778 {
 779     BDRVNVMeState *s = bs->opaque;
 780
 781     return s->nsze << BDRV_SECTOR_BITS;
 782 }
 783
 784 /* Called with s->dma_map_lock */
 785 static coroutine_fn int nvme_cmd_unmap_qiov(BlockDriverState *bs,
 786                                             QEMUIOVector *qiov)
 787 {
 788     int r = 0;
 789     BDRVNVMeState *s = bs->opaque;
 790
 791     s->dma_map_count -= qiov->size;
 792     if (!s->dma_map_count && !qemu_co_queue_empty(&s->dma_flush_queue)) {
 793         r = qemu_vfio_dma_reset_temporary(s->vfio);
 794         if (!r) {
 795             qemu_co_queue_restart_all(&s->dma_flush_queue);
 796         }
 797     }
 798     return r;
 799 }
 800
 801 /* Called with s->dma_map_lock */
 802 static coroutine_fn int nvme_cmd_map_qiov(BlockDriverState *bs, NvmeCmd *cmd,
 803                                           NVMeRequest *req, QEMUIOVector *qiov)
 804 {
 805     BDRVNVMeState *s = bs->opaque;
 806     uint64_t *pagelist = req->prp_list_page;
 807     int i, j, r;
 808     int entries = 0;
 809
 810     assert(qiov->size);
 811     assert(QEMU_IS_ALIGNED(qiov->size, s->page_size));
 812     assert(qiov->size / s->page_size <= s->page_size / sizeof(uint64_t));
 813     for (i = 0; i < qiov->niov; ++i) {
 814         bool retry = true;
 815         uint64_t iova;
 816 try_map:
 817         r = qemu_vfio_dma_map(s->vfio,
 818                               qiov->iov[i].iov_base,
 819                               qiov->iov[i].iov_len,
 820                               true, &iova);
 821         if (r == -ENOMEM && retry) {
 822             retry = false;
 823             trace_nvme_dma_flush_queue_wait(s);
 824             if (s->dma_map_count) {
 825                 trace_nvme_dma_map_flush(s);
 826                 qemu_co_queue_wait(&s->dma_flush_queue, &s->dma_map_lock);
 827             } else {
 828                 r = qemu_vfio_dma_reset_temporary(s->vfio);
 829                 if (r) {
 830                     goto fail;
 831                 }
 832             }
 833             goto try_map;
 834         }
 835         if (r) {
 836             goto fail;
 837         }
 838
 839         for (j = 0; j < qiov->iov[i].iov_len / s->page_size; j++) {
 840             pagelist[entries++] = iova + j * s->page_size;
 841         }
 842         trace_nvme_cmd_map_qiov_iov(s, i, qiov->iov[i].iov_base,
 843                                     qiov->iov[i].iov_len / s->page_size);
 844     }
 845
 846     s->dma_map_count += qiov->size;
 847
 848     assert(entries <= s->page_size / sizeof(uint64_t));
 849     switch (entries) {
 850     case 0:
 851         abort();
 852     case 1:
 853         cmd->prp1 = cpu_to_le64(pagelist[0]);
 854         cmd->prp2 = 0;
 855         break;
 856     case 2:
 857         cmd->prp1 = cpu_to_le64(pagelist[0]);
 858         cmd->prp2 = cpu_to_le64(pagelist[1]);;
 859         break;
 860     default:
 861         cmd->prp1 = cpu_to_le64(pagelist[0]);
 862         cmd->prp2 = cpu_to_le64(req->prp_list_iova);
 863         for (i = 0; i < entries - 1; ++i) {
 864             pagelist[i] = cpu_to_le64(pagelist[i + 1]);
 865         }
 866         pagelist[entries - 1] = 0;
 867         break;
 868     }
 869     trace_nvme_cmd_map_qiov(s, cmd, req, qiov, entries);
 870     for (i = 0; i < entries; ++i) {
 871         trace_nvme_cmd_map_qiov_pages(s, i, pagelist[i]);
 872     }
 873     return 0;
 874 fail:
 875     /* No need to unmap [0 - i) iovs even if we've failed, since we don't
 876      * increment s->dma_map_count. This is okay for fixed mapping memory areas
 877      * because they are already mapped before calling this function; for
 878      * temporary mappings, a later nvme_cmd_(un)map_qiov will reclaim by
 879      * calling qemu_vfio_dma_reset_temporary when necessary. */
 880     return r;
 881 }
 882
 883 typedef struct {
 884     Coroutine *co;
 885     int ret;
 886     AioContext *ctx;
 887 } NVMeCoData;
 888
 889 static void nvme_rw_cb_bh(void *opaque)
 890 {
 891     NVMeCoData *data = opaque;
 892     qemu_coroutine_enter(data->co);
 893 }
 894
 895 static void nvme_rw_cb(void *opaque, int ret)
 896 {
 897     NVMeCoData *data = opaque;
 898     data->ret = ret;
 899     if (!data->co) {
 900         /* The rw coroutine hasn't yielded, don't try to enter. */
 901         return;
 902     }
 903     aio_bh_schedule_oneshot(data->ctx, nvme_rw_cb_bh, data);
 904 }
 905
 906 static coroutine_fn int nvme_co_prw_aligned(BlockDriverState *bs,
 907                                             uint64_t offset, uint64_t bytes,
 908                                             QEMUIOVector *qiov,
 909                                             bool is_write,
 910                                             int flags)
 911 {
 912     int r;
 913     BDRVNVMeState *s = bs->opaque;
 914     NVMeQueuePair *ioq = s->queues[1];
 915     NVMeRequest *req;
 916     uint32_t cdw12 = (((bytes >> BDRV_SECTOR_BITS) - 1) & 0xFFFF) |
 917                        (flags & BDRV_REQ_FUA ? 1 << 30 : 0);
 918     NvmeCmd cmd = {
 919         .opcode = is_write ? NVME_CMD_WRITE : NVME_CMD_READ,
 920         .nsid = cpu_to_le32(s->nsid),
 921         .cdw10 = cpu_to_le32((offset >> BDRV_SECTOR_BITS) & 0xFFFFFFFF),
 922         .cdw11 = cpu_to_le32(((offset >> BDRV_SECTOR_BITS) >> 32) & 0xFFFFFFFF),
 923         .cdw12 = cpu_to_le32(cdw12),
 924     };
 925     NVMeCoData data = {
 926         .ctx = bdrv_get_aio_context(bs),
 927         .ret = -EINPROGRESS,
 928     };
 929
 930     trace_nvme_prw_aligned(s, is_write, offset, bytes, flags, qiov->niov);
 931     assert(s->nr_queues > 1);
 932     req = nvme_get_free_req(ioq);
 933     assert(req);
 934
 935     qemu_co_mutex_lock(&s->dma_map_lock);
 936     r = nvme_cmd_map_qiov(bs, &cmd, req, qiov);
 937     qemu_co_mutex_unlock(&s->dma_map_lock);
 938     if (r) {
 939         req->busy = false;
 940         return r;
 941     }
 942     nvme_submit_command(s, ioq, req, &cmd, nvme_rw_cb, &data);
 943
 944     data.co = qemu_coroutine_self();
 945     while (data.ret == -EINPROGRESS) {
 946         qemu_coroutine_yield();
 947     }
 948
 949     qemu_co_mutex_lock(&s->dma_map_lock);
 950     r = nvme_cmd_unmap_qiov(bs, qiov);
 951     qemu_co_mutex_unlock(&s->dma_map_lock);
 952     if (r) {
 953         return r;
 954     }
 955
 956     trace_nvme_rw_done(s, is_write, offset, bytes, data.ret);
 957     return data.ret;
 958 }
 959
 960 static inline bool nvme_qiov_aligned(BlockDriverState *bs,
 961                                      const QEMUIOVector *qiov)
 962 {
 963     int i;
 964     BDRVNVMeState *s = bs->opaque;
 965
 966     for (i = 0; i < qiov->niov; ++i) {
 967         if (!QEMU_PTR_IS_ALIGNED(qiov->iov[i].iov_base, s->page_size) ||
 968             !QEMU_IS_ALIGNED(qiov->iov[i].iov_len, s->page_size)) {
 969             trace_nvme_qiov_unaligned(qiov, i, qiov->iov[i].iov_base,
 970                                       qiov->iov[i].iov_len, s->page_size);
 971             return false;
 972         }
 973     }
 974     return true;
 975 }
 976
 977 static int nvme_co_prw(BlockDriverState *bs, uint64_t offset, uint64_t bytes,
 978                        QEMUIOVector *qiov, bool is_write, int flags)
 979 {
 980     BDRVNVMeState *s = bs->opaque;
 981     int r;
 982     uint8_t *buf = NULL;
 983     QEMUIOVector local_qiov;
 984
 985     assert(QEMU_IS_ALIGNED(offset, s->page_size));
 986     assert(QEMU_IS_ALIGNED(bytes, s->page_size));
 987     assert(bytes <= s->max_transfer);
 988     if (nvme_qiov_aligned(bs, qiov)) {
 989         return nvme_co_prw_aligned(bs, offset, bytes, qiov, is_write, flags);
 990     }
 991     trace_nvme_prw_buffered(s, offset, bytes, qiov->niov, is_write);
 992     buf = qemu_try_blockalign(bs, bytes);
 993
 994     if (!buf) {
 995         return -ENOMEM;
 996     }
 997     qemu_iovec_init(&local_qiov, 1);
 998     if (is_write) {
 999         qemu_iovec_to_buf(qiov, 0, buf, bytes);
1000     }
1001     qemu_iovec_add(&local_qiov, buf, bytes);
1002     r = nvme_co_prw_aligned(bs, offset, bytes, &local_qiov, is_write, flags);
1003     qemu_iovec_destroy(&local_qiov);
1004     if (!r && !is_write) {
1005         qemu_iovec_from_buf(qiov, 0, buf, bytes);
1006     }
1007     qemu_vfree(buf);
1008     return r;
1009 }
1010
1011 static coroutine_fn int nvme_co_preadv(BlockDriverState *bs,
1012                                        uint64_t offset, uint64_t bytes,
1013                                        QEMUIOVector *qiov, int flags)
1014 {
1015     return nvme_co_prw(bs, offset, bytes, qiov, false, flags);
1016 }
1017
1018 static coroutine_fn int nvme_co_pwritev(BlockDriverState *bs,
1019                                         uint64_t offset, uint64_t bytes,
1020                                         QEMUIOVector *qiov, int flags)
1021 {
1022     return nvme_co_prw(bs, offset, bytes, qiov, true, flags);
1023 }
1024
1025 static coroutine_fn int nvme_co_flush(BlockDriverState *bs)
1026 {
1027     BDRVNVMeState *s = bs->opaque;
1028     NVMeQueuePair *ioq = s->queues[1];
1029     NVMeRequest *req;
1030     NvmeCmd cmd = {
1031         .opcode = NVME_CMD_FLUSH,
1032         .nsid = cpu_to_le32(s->nsid),
1033     };
1034     NVMeCoData data = {
1035         .ctx = bdrv_get_aio_context(bs),
1036         .ret = -EINPROGRESS,
1037     };
1038
1039     assert(s->nr_queues > 1);
1040     req = nvme_get_free_req(ioq);
1041     assert(req);
1042     nvme_submit_command(s, ioq, req, &cmd, nvme_rw_cb, &data);
1043
1044     data.co = qemu_coroutine_self();
1045     if (data.ret == -EINPROGRESS) {
1046         qemu_coroutine_yield();
1047     }
1048
1049     return data.ret;
1050 }
1051
1052
1053 static int nvme_reopen_prepare(BDRVReopenState *reopen_state,
1054                                BlockReopenQueue *queue, Error **errp)
1055 {
1056     return 0;
1057 }
1058
1059 static void nvme_refresh_filename(BlockDriverState *bs, QDict *opts)
1060 {
1061     qdict_del(opts, "filename");
1062
1063     if (!qdict_size(opts)) {
1064         snprintf(bs->exact_filename, sizeof(bs->exact_filename), "%s://",
1065                  bs->drv->format_name);
1066     }
1067
1068     qdict_put_str(opts, "driver", bs->drv->format_name);
1069     bs->full_open_options = qobject_ref(opts);
1070 }
1071
1072 static void nvme_refresh_limits(BlockDriverState *bs, Error **errp)
1073 {
1074     BDRVNVMeState *s = bs->opaque;
1075
1076     bs->bl.opt_mem_alignment = s->page_size;
1077     bs->bl.request_alignment = s->page_size;
1078     bs->bl.max_transfer = s->max_transfer;
1079 }
1080
1081 static void nvme_detach_aio_context(BlockDriverState *bs)
1082 {
1083     BDRVNVMeState *s = bs->opaque;
1084
1085     aio_set_event_notifier(bdrv_get_aio_context(bs), &s->irq_notifier,
1086                            false, NULL, NULL);
1087 }
1088
1089 static void nvme_attach_aio_context(BlockDriverState *bs,
1090                                     AioContext *new_context)
1091 {
1092     BDRVNVMeState *s = bs->opaque;
1093
1094     s->aio_context = new_context;
1095     aio_set_event_notifier(new_context, &s->irq_notifier,
1096                            false, nvme_handle_event, nvme_poll_cb);
1097 }
1098
1099 static void nvme_aio_plug(BlockDriverState *bs)
1100 {
1101     BDRVNVMeState *s = bs->opaque;
1102     assert(!s->plugged);
1103     s->plugged = true;
1104 }
1105
1106 static void nvme_aio_unplug(BlockDriverState *bs)
1107 {
1108     int i;
1109     BDRVNVMeState *s = bs->opaque;
1110     assert(s->plugged);
1111     s->plugged = false;
1112     for (i = 1; i < s->nr_queues; i++) {
1113         NVMeQueuePair *q = s->queues[i];
1114         qemu_mutex_lock(&q->lock);
1115         nvme_kick(s, q);
1116         nvme_process_completion(s, q);
1117         qemu_mutex_unlock(&q->lock);
1118     }
1119 }
1120
1121 static void nvme_register_buf(BlockDriverState *bs, void *host, size_t size)
1122 {
1123     int ret;
1124     BDRVNVMeState *s = bs->opaque;
1125
1126     ret = qemu_vfio_dma_map(s->vfio, host, size, false, NULL);
1127     if (ret) {
1128         /* FIXME: we may run out of IOVA addresses after repeated
1129          * bdrv_register_buf/bdrv_unregister_buf, because nvme_vfio_dma_unmap
1130          * doesn't reclaim addresses for fixed mappings. */
1131         error_report("nvme_register_buf failed: %s", strerror(-ret));
1132     }
1133 }
1134
1135 static void nvme_unregister_buf(BlockDriverState *bs, void *host)
1136 {
1137     BDRVNVMeState *s = bs->opaque;
1138
1139     qemu_vfio_dma_unmap(s->vfio, host);
1140 }
1141
1142 static BlockDriver bdrv_nvme = {
1143     .format_name              = "nvme",
1144     .protocol_name            = "nvme",
1145     .instance_size            = sizeof(BDRVNVMeState),
1146
1147     .bdrv_parse_filename      = nvme_parse_filename,
1148     .bdrv_file_open           = nvme_file_open,
1149     .bdrv_close               = nvme_close,
1150     .bdrv_getlength           = nvme_getlength,
1151
1152     .bdrv_co_preadv           = nvme_co_preadv,
1153     .bdrv_co_pwritev          = nvme_co_pwritev,
1154     .bdrv_co_flush_to_disk    = nvme_co_flush,
1155     .bdrv_reopen_prepare      = nvme_reopen_prepare,
1156
1157     .bdrv_refresh_filename    = nvme_refresh_filename,
1158     .bdrv_refresh_limits      = nvme_refresh_limits,
1159
1160     .bdrv_detach_aio_context  = nvme_detach_aio_context,
1161     .bdrv_attach_aio_context  = nvme_attach_aio_context,
1162
1163     .bdrv_io_plug             = nvme_aio_plug,
1164     .bdrv_io_unplug           = nvme_aio_unplug,
1165
1166     .bdrv_register_buf        = nvme_register_buf,
1167     .bdrv_unregister_buf      = nvme_unregister_buf,
1168 };
1169
1170 static void bdrv_nvme_init(void)
1171 {
1172     bdrv_register(&bdrv_nvme);
1173 }
1174
1175 block_init(bdrv_nvme_init);