2 * QEMU PC keyboard emulation
4 * Copyright (c) 2003 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "qemu/error-report.h"
28 #include "qemu/timer.h"
29 #include "qapi/error.h"
30 #include "hw/isa/isa.h"
31 #include "migration/vmstate.h"
32 #include "hw/acpi/acpi_aml_interface.h"
33 #include "hw/input/ps2.h"
35 #include "hw/input/i8042.h"
36 #include "hw/qdev-properties.h"
37 #include "sysemu/reset.h"
38 #include "sysemu/runstate.h"
42 /* Keyboard Controller Commands */
45 #define KBD_CCMD_READ_MODE 0x20
47 #define KBD_CCMD_WRITE_MODE 0x60
48 /* Get controller version */
49 #define KBD_CCMD_GET_VERSION 0xA1
50 /* Disable mouse interface */
51 #define KBD_CCMD_MOUSE_DISABLE 0xA7
52 /* Enable mouse interface */
53 #define KBD_CCMD_MOUSE_ENABLE 0xA8
54 /* Mouse interface test */
55 #define KBD_CCMD_TEST_MOUSE 0xA9
56 /* Controller self test */
57 #define KBD_CCMD_SELF_TEST 0xAA
58 /* Keyboard interface test */
59 #define KBD_CCMD_KBD_TEST 0xAB
60 /* Keyboard interface disable */
61 #define KBD_CCMD_KBD_DISABLE 0xAD
62 /* Keyboard interface enable */
63 #define KBD_CCMD_KBD_ENABLE 0xAE
65 #define KBD_CCMD_READ_INPORT 0xC0
66 /* read output port */
67 #define KBD_CCMD_READ_OUTPORT 0xD0
68 /* write output port */
69 #define KBD_CCMD_WRITE_OUTPORT 0xD1
70 #define KBD_CCMD_WRITE_OBUF 0xD2
71 /* Write to output buffer as if initiated by the auxiliary device */
72 #define KBD_CCMD_WRITE_AUX_OBUF 0xD3
73 /* Write the following byte to the mouse */
74 #define KBD_CCMD_WRITE_MOUSE 0xD4
75 /* HP vectra only ? */
76 #define KBD_CCMD_DISABLE_A20 0xDD
77 /* HP vectra only ? */
78 #define KBD_CCMD_ENABLE_A20 0xDF
79 /* Pulse bits 3-0 of the output port P2. */
80 #define KBD_CCMD_PULSE_BITS_3_0 0xF0
81 /* Pulse bit 0 of the output port P2 = CPU reset. */
82 #define KBD_CCMD_RESET 0xFE
83 /* Pulse no bits of the output port P2. */
84 #define KBD_CCMD_NO_OP 0xFF
86 /* Status Register Bits */
88 /* Keyboard output buffer full */
89 #define KBD_STAT_OBF 0x01
90 /* Keyboard input buffer full */
91 #define KBD_STAT_IBF 0x02
92 /* Self test successful */
93 #define KBD_STAT_SELFTEST 0x04
94 /* Last write was a command write (0=data) */
95 #define KBD_STAT_CMD 0x08
96 /* Zero if keyboard locked */
97 #define KBD_STAT_UNLOCKED 0x10
98 /* Mouse output buffer full */
99 #define KBD_STAT_MOUSE_OBF 0x20
100 /* General receive/xmit timeout */
101 #define KBD_STAT_GTO 0x40
103 #define KBD_STAT_PERR 0x80
105 /* Controller Mode Register Bits */
107 /* Keyboard data generate IRQ1 */
108 #define KBD_MODE_KBD_INT 0x01
109 /* Mouse data generate IRQ12 */
110 #define KBD_MODE_MOUSE_INT 0x02
111 /* The system flag (?) */
112 #define KBD_MODE_SYS 0x04
113 /* The keylock doesn't affect the keyboard if set */
114 #define KBD_MODE_NO_KEYLOCK 0x08
115 /* Disable keyboard interface */
116 #define KBD_MODE_DISABLE_KBD 0x10
117 /* Disable mouse interface */
118 #define KBD_MODE_DISABLE_MOUSE 0x20
119 /* Scan code conversion to PC format */
120 #define KBD_MODE_KCC 0x40
121 #define KBD_MODE_RFU 0x80
123 /* Output Port Bits */
124 #define KBD_OUT_RESET 0x01 /* 1=normal mode, 0=reset */
125 #define KBD_OUT_A20 0x02 /* x86 only */
126 #define KBD_OUT_OBF 0x10 /* Keyboard output buffer full */
127 #define KBD_OUT_MOUSE_OBF 0x20 /* Mouse output buffer full */
130 * OSes typically write 0xdd/0xdf to turn the A20 line off and on.
131 * We make the default value of the outport include these four bits,
132 * so that the subsection is rarely necessary.
134 #define KBD_OUT_ONES 0xcc
136 #define KBD_PENDING_KBD_COMPAT 0x01
137 #define KBD_PENDING_AUX_COMPAT 0x02
138 #define KBD_PENDING_CTRL_KBD 0x04
139 #define KBD_PENDING_CTRL_AUX 0x08
140 #define KBD_PENDING_KBD KBD_MODE_DISABLE_KBD /* 0x10 */
141 #define KBD_PENDING_AUX KBD_MODE_DISABLE_MOUSE /* 0x20 */
143 #define KBD_MIGR_TIMER_PENDING 0x1
145 #define KBD_OBSRC_KBD 0x01
146 #define KBD_OBSRC_MOUSE 0x02
147 #define KBD_OBSRC_CTRL 0x04
151 * XXX: not generating the irqs if KBD_MODE_DISABLE_KBD is set may be
152 * incorrect, but it avoids having to simulate exact delays
154 static void kbd_update_irq_lines(KBDState
*s
)
156 int irq_kbd_level
, irq_mouse_level
;
161 if (s
->status
& KBD_STAT_OBF
) {
162 if (s
->status
& KBD_STAT_MOUSE_OBF
) {
163 if (s
->mode
& KBD_MODE_MOUSE_INT
) {
167 if ((s
->mode
& KBD_MODE_KBD_INT
) &&
168 !(s
->mode
& KBD_MODE_DISABLE_KBD
)) {
173 qemu_set_irq(s
->irqs
[I8042_KBD_IRQ
], irq_kbd_level
);
174 qemu_set_irq(s
->irqs
[I8042_MOUSE_IRQ
], irq_mouse_level
);
177 static void kbd_deassert_irq(KBDState
*s
)
179 s
->status
&= ~(KBD_STAT_OBF
| KBD_STAT_MOUSE_OBF
);
180 s
->outport
&= ~(KBD_OUT_OBF
| KBD_OUT_MOUSE_OBF
);
181 kbd_update_irq_lines(s
);
184 static uint8_t kbd_pending(KBDState
*s
)
186 if (s
->extended_state
) {
187 return s
->pending
& (~s
->mode
| ~(KBD_PENDING_KBD
| KBD_PENDING_AUX
));
193 /* update irq and KBD_STAT_[MOUSE_]OBF */
194 static void kbd_update_irq(KBDState
*s
)
196 uint8_t pending
= kbd_pending(s
);
198 s
->status
&= ~(KBD_STAT_OBF
| KBD_STAT_MOUSE_OBF
);
199 s
->outport
&= ~(KBD_OUT_OBF
| KBD_OUT_MOUSE_OBF
);
201 s
->status
|= KBD_STAT_OBF
;
202 s
->outport
|= KBD_OUT_OBF
;
203 if (pending
& KBD_PENDING_CTRL_KBD
) {
204 s
->obsrc
= KBD_OBSRC_CTRL
;
205 } else if (pending
& KBD_PENDING_CTRL_AUX
) {
206 s
->status
|= KBD_STAT_MOUSE_OBF
;
207 s
->outport
|= KBD_OUT_MOUSE_OBF
;
208 s
->obsrc
= KBD_OBSRC_CTRL
;
209 } else if (pending
& KBD_PENDING_KBD
) {
210 s
->obsrc
= KBD_OBSRC_KBD
;
212 s
->status
|= KBD_STAT_MOUSE_OBF
;
213 s
->outport
|= KBD_OUT_MOUSE_OBF
;
214 s
->obsrc
= KBD_OBSRC_MOUSE
;
217 kbd_update_irq_lines(s
);
220 static void kbd_safe_update_irq(KBDState
*s
)
223 * with KBD_STAT_OBF set, a call to kbd_read_data() will eventually call
226 if (s
->status
& KBD_STAT_OBF
) {
229 /* the throttle timer is pending and will call kbd_update_irq() */
230 if (s
->throttle_timer
&& timer_pending(s
->throttle_timer
)) {
233 if (kbd_pending(s
)) {
238 static void kbd_update_kbd_irq(void *opaque
, int level
)
240 KBDState
*s
= opaque
;
243 s
->pending
|= KBD_PENDING_KBD
;
245 s
->pending
&= ~KBD_PENDING_KBD
;
247 kbd_safe_update_irq(s
);
250 static void kbd_update_aux_irq(void *opaque
, int level
)
252 KBDState
*s
= opaque
;
255 s
->pending
|= KBD_PENDING_AUX
;
257 s
->pending
&= ~KBD_PENDING_AUX
;
259 kbd_safe_update_irq(s
);
262 static void kbd_throttle_timeout(void *opaque
)
264 KBDState
*s
= opaque
;
266 if (kbd_pending(s
)) {
271 static uint64_t kbd_read_status(void *opaque
, hwaddr addr
,
274 KBDState
*s
= opaque
;
277 trace_pckbd_kbd_read_status(val
);
281 static void kbd_queue(KBDState
*s
, int b
, int aux
)
283 if (s
->extended_state
) {
285 s
->pending
&= ~KBD_PENDING_CTRL_KBD
& ~KBD_PENDING_CTRL_AUX
;
286 s
->pending
|= aux
? KBD_PENDING_CTRL_AUX
: KBD_PENDING_CTRL_KBD
;
287 kbd_safe_update_irq(s
);
289 ps2_queue(aux
? s
->mouse
: s
->kbd
, b
);
293 static uint8_t kbd_dequeue(KBDState
*s
)
295 uint8_t b
= s
->cbdata
;
297 s
->pending
&= ~KBD_PENDING_CTRL_KBD
& ~KBD_PENDING_CTRL_AUX
;
298 if (kbd_pending(s
)) {
304 static void outport_write(KBDState
*s
, uint32_t val
)
306 trace_pckbd_outport_write(val
);
308 qemu_set_irq(s
->a20_out
, (val
>> 1) & 1);
310 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
314 static void kbd_write_command(void *opaque
, hwaddr addr
,
315 uint64_t val
, unsigned size
)
317 KBDState
*s
= opaque
;
319 trace_pckbd_kbd_write_command(val
);
322 * Bits 3-0 of the output port P2 of the keyboard controller may be pulsed
323 * low for approximately 6 micro seconds. Bits 3-0 of the KBD_CCMD_PULSE
324 * command specify the output port bits to be pulsed.
325 * 0: Bit should be pulsed. 1: Bit should not be modified.
326 * The only useful version of this command is pulsing bit 0,
327 * which does a CPU reset.
329 if ((val
& KBD_CCMD_PULSE_BITS_3_0
) == KBD_CCMD_PULSE_BITS_3_0
) {
331 val
= KBD_CCMD_RESET
;
333 val
= KBD_CCMD_NO_OP
;
338 case KBD_CCMD_READ_MODE
:
339 kbd_queue(s
, s
->mode
, 0);
341 case KBD_CCMD_WRITE_MODE
:
342 case KBD_CCMD_WRITE_OBUF
:
343 case KBD_CCMD_WRITE_AUX_OBUF
:
344 case KBD_CCMD_WRITE_MOUSE
:
345 case KBD_CCMD_WRITE_OUTPORT
:
348 case KBD_CCMD_MOUSE_DISABLE
:
349 s
->mode
|= KBD_MODE_DISABLE_MOUSE
;
351 case KBD_CCMD_MOUSE_ENABLE
:
352 s
->mode
&= ~KBD_MODE_DISABLE_MOUSE
;
353 kbd_safe_update_irq(s
);
355 case KBD_CCMD_TEST_MOUSE
:
356 kbd_queue(s
, 0x00, 0);
358 case KBD_CCMD_SELF_TEST
:
359 s
->status
|= KBD_STAT_SELFTEST
;
360 kbd_queue(s
, 0x55, 0);
362 case KBD_CCMD_KBD_TEST
:
363 kbd_queue(s
, 0x00, 0);
365 case KBD_CCMD_KBD_DISABLE
:
366 s
->mode
|= KBD_MODE_DISABLE_KBD
;
368 case KBD_CCMD_KBD_ENABLE
:
369 s
->mode
&= ~KBD_MODE_DISABLE_KBD
;
370 kbd_safe_update_irq(s
);
372 case KBD_CCMD_READ_INPORT
:
373 kbd_queue(s
, 0x80, 0);
375 case KBD_CCMD_READ_OUTPORT
:
376 kbd_queue(s
, s
->outport
, 0);
378 case KBD_CCMD_ENABLE_A20
:
379 qemu_irq_raise(s
->a20_out
);
380 s
->outport
|= KBD_OUT_A20
;
382 case KBD_CCMD_DISABLE_A20
:
383 qemu_irq_lower(s
->a20_out
);
384 s
->outport
&= ~KBD_OUT_A20
;
387 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
393 qemu_log_mask(LOG_GUEST_ERROR
,
394 "unsupported keyboard cmd=0x%02" PRIx64
"\n", val
);
399 static uint64_t kbd_read_data(void *opaque
, hwaddr addr
,
402 KBDState
*s
= opaque
;
404 if (s
->status
& KBD_STAT_OBF
) {
406 if (s
->obsrc
& KBD_OBSRC_KBD
) {
407 if (s
->throttle_timer
) {
408 timer_mod(s
->throttle_timer
,
409 qemu_clock_get_us(QEMU_CLOCK_VIRTUAL
) + 1000);
411 s
->obdata
= ps2_read_data(s
->kbd
);
412 } else if (s
->obsrc
& KBD_OBSRC_MOUSE
) {
413 s
->obdata
= ps2_read_data(s
->mouse
);
414 } else if (s
->obsrc
& KBD_OBSRC_CTRL
) {
415 s
->obdata
= kbd_dequeue(s
);
419 trace_pckbd_kbd_read_data(s
->obdata
);
423 static void kbd_write_data(void *opaque
, hwaddr addr
,
424 uint64_t val
, unsigned size
)
426 KBDState
*s
= opaque
;
428 trace_pckbd_kbd_write_data(val
);
430 switch (s
->write_cmd
) {
432 ps2_write_keyboard(s
->kbd
, val
);
433 /* sending data to the keyboard reenables PS/2 communication */
434 s
->mode
&= ~KBD_MODE_DISABLE_KBD
;
435 kbd_safe_update_irq(s
);
437 case KBD_CCMD_WRITE_MODE
:
439 ps2_keyboard_set_translation(s
->kbd
, (s
->mode
& KBD_MODE_KCC
) != 0);
441 * a write to the mode byte interrupt enable flags directly updates
444 kbd_update_irq_lines(s
);
446 * a write to the mode byte disable interface flags may raise
447 * an irq if there is pending data in the PS/2 queues.
449 kbd_safe_update_irq(s
);
451 case KBD_CCMD_WRITE_OBUF
:
452 kbd_queue(s
, val
, 0);
454 case KBD_CCMD_WRITE_AUX_OBUF
:
455 kbd_queue(s
, val
, 1);
457 case KBD_CCMD_WRITE_OUTPORT
:
458 outport_write(s
, val
);
460 case KBD_CCMD_WRITE_MOUSE
:
461 ps2_write_mouse(s
->mouse
, val
);
462 /* sending data to the mouse reenables PS/2 communication */
463 s
->mode
&= ~KBD_MODE_DISABLE_MOUSE
;
464 kbd_safe_update_irq(s
);
472 static void kbd_reset(void *opaque
)
474 KBDState
*s
= opaque
;
476 s
->mode
= KBD_MODE_KBD_INT
| KBD_MODE_MOUSE_INT
;
477 s
->status
= KBD_STAT_CMD
| KBD_STAT_UNLOCKED
;
478 s
->outport
= KBD_OUT_RESET
| KBD_OUT_A20
| KBD_OUT_ONES
;
481 if (s
->throttle_timer
) {
482 timer_del(s
->throttle_timer
);
486 static uint8_t kbd_outport_default(KBDState
*s
)
488 return KBD_OUT_RESET
| KBD_OUT_A20
| KBD_OUT_ONES
489 | (s
->status
& KBD_STAT_OBF
? KBD_OUT_OBF
: 0)
490 | (s
->status
& KBD_STAT_MOUSE_OBF
? KBD_OUT_MOUSE_OBF
: 0);
493 static int kbd_outport_post_load(void *opaque
, int version_id
)
495 KBDState
*s
= opaque
;
496 s
->outport_present
= true;
500 static bool kbd_outport_needed(void *opaque
)
502 KBDState
*s
= opaque
;
503 return s
->outport
!= kbd_outport_default(s
);
506 static const VMStateDescription vmstate_kbd_outport
= {
507 .name
= "pckbd_outport",
509 .minimum_version_id
= 1,
510 .post_load
= kbd_outport_post_load
,
511 .needed
= kbd_outport_needed
,
512 .fields
= (VMStateField
[]) {
513 VMSTATE_UINT8(outport
, KBDState
),
514 VMSTATE_END_OF_LIST()
518 static int kbd_extended_state_pre_save(void *opaque
)
520 KBDState
*s
= opaque
;
522 s
->migration_flags
= 0;
523 if (s
->throttle_timer
&& timer_pending(s
->throttle_timer
)) {
524 s
->migration_flags
|= KBD_MIGR_TIMER_PENDING
;
530 static int kbd_extended_state_post_load(void *opaque
, int version_id
)
532 KBDState
*s
= opaque
;
534 if (s
->migration_flags
& KBD_MIGR_TIMER_PENDING
) {
535 kbd_throttle_timeout(s
);
537 s
->extended_state_loaded
= true;
542 static bool kbd_extended_state_needed(void *opaque
)
544 KBDState
*s
= opaque
;
546 return s
->extended_state
;
549 static const VMStateDescription vmstate_kbd_extended_state
= {
550 .name
= "pckbd/extended_state",
551 .post_load
= kbd_extended_state_post_load
,
552 .pre_save
= kbd_extended_state_pre_save
,
553 .needed
= kbd_extended_state_needed
,
554 .fields
= (VMStateField
[]) {
555 VMSTATE_UINT32(migration_flags
, KBDState
),
556 VMSTATE_UINT32(obsrc
, KBDState
),
557 VMSTATE_UINT8(obdata
, KBDState
),
558 VMSTATE_UINT8(cbdata
, KBDState
),
559 VMSTATE_END_OF_LIST()
563 static int kbd_pre_save(void *opaque
)
565 KBDState
*s
= opaque
;
567 if (s
->extended_state
) {
568 s
->pending_tmp
= s
->pending
;
571 if (s
->pending
& KBD_PENDING_KBD
) {
572 s
->pending_tmp
|= KBD_PENDING_KBD_COMPAT
;
574 if (s
->pending
& KBD_PENDING_AUX
) {
575 s
->pending_tmp
|= KBD_PENDING_AUX_COMPAT
;
581 static int kbd_pre_load(void *opaque
)
583 KBDState
*s
= opaque
;
585 s
->outport_present
= false;
586 s
->extended_state_loaded
= false;
590 static int kbd_post_load(void *opaque
, int version_id
)
592 KBDState
*s
= opaque
;
593 if (!s
->outport_present
) {
594 s
->outport
= kbd_outport_default(s
);
596 s
->pending
= s
->pending_tmp
;
597 if (!s
->extended_state_loaded
) {
598 s
->obsrc
= s
->status
& KBD_STAT_OBF
?
599 (s
->status
& KBD_STAT_MOUSE_OBF
? KBD_OBSRC_MOUSE
: KBD_OBSRC_KBD
) :
601 if (s
->pending
& KBD_PENDING_KBD_COMPAT
) {
602 s
->pending
|= KBD_PENDING_KBD
;
604 if (s
->pending
& KBD_PENDING_AUX_COMPAT
) {
605 s
->pending
|= KBD_PENDING_AUX
;
608 /* clear all unused flags */
609 s
->pending
&= KBD_PENDING_CTRL_KBD
| KBD_PENDING_CTRL_AUX
|
610 KBD_PENDING_KBD
| KBD_PENDING_AUX
;
614 static const VMStateDescription vmstate_kbd
= {
617 .minimum_version_id
= 3,
618 .pre_load
= kbd_pre_load
,
619 .post_load
= kbd_post_load
,
620 .pre_save
= kbd_pre_save
,
621 .fields
= (VMStateField
[]) {
622 VMSTATE_UINT8(write_cmd
, KBDState
),
623 VMSTATE_UINT8(status
, KBDState
),
624 VMSTATE_UINT8(mode
, KBDState
),
625 VMSTATE_UINT8(pending_tmp
, KBDState
),
626 VMSTATE_END_OF_LIST()
628 .subsections
= (const VMStateDescription
* []) {
629 &vmstate_kbd_outport
,
630 &vmstate_kbd_extended_state
,
635 /* Memory mapped interface */
636 static uint64_t kbd_mm_readfn(void *opaque
, hwaddr addr
, unsigned size
)
638 KBDState
*s
= opaque
;
640 if (addr
& s
->mask
) {
641 return kbd_read_status(s
, 0, 1) & 0xff;
643 return kbd_read_data(s
, 0, 1) & 0xff;
647 static void kbd_mm_writefn(void *opaque
, hwaddr addr
,
648 uint64_t value
, unsigned size
)
650 KBDState
*s
= opaque
;
652 if (addr
& s
->mask
) {
653 kbd_write_command(s
, 0, value
& 0xff, 1);
655 kbd_write_data(s
, 0, value
& 0xff, 1);
660 static const MemoryRegionOps i8042_mmio_ops
= {
661 .read
= kbd_mm_readfn
,
662 .write
= kbd_mm_writefn
,
663 .valid
.min_access_size
= 1,
664 .valid
.max_access_size
= 4,
665 .endianness
= DEVICE_NATIVE_ENDIAN
,
668 static void i8042_mmio_set_kbd_irq(void *opaque
, int n
, int level
)
670 MMIOKBDState
*s
= I8042_MMIO(opaque
);
671 KBDState
*ks
= &s
->kbd
;
673 kbd_update_kbd_irq(ks
, level
);
676 static void i8042_mmio_set_mouse_irq(void *opaque
, int n
, int level
)
678 MMIOKBDState
*s
= I8042_MMIO(opaque
);
679 KBDState
*ks
= &s
->kbd
;
681 kbd_update_aux_irq(ks
, level
);
684 static void i8042_mmio_reset(DeviceState
*dev
)
686 MMIOKBDState
*s
= I8042_MMIO(dev
);
687 KBDState
*ks
= &s
->kbd
;
692 static void i8042_mmio_realize(DeviceState
*dev
, Error
**errp
)
694 MMIOKBDState
*s
= I8042_MMIO(dev
);
695 KBDState
*ks
= &s
->kbd
;
697 memory_region_init_io(&s
->region
, OBJECT(dev
), &i8042_mmio_ops
, ks
,
700 sysbus_init_mmio(SYS_BUS_DEVICE(dev
), &s
->region
);
702 ks
->kbd
= ps2_kbd_init();
703 qdev_connect_gpio_out(DEVICE(ks
->kbd
), PS2_DEVICE_IRQ
,
704 qdev_get_gpio_in_named(dev
, "ps2-kbd-input-irq",
706 ks
->mouse
= ps2_mouse_init();
707 qdev_connect_gpio_out(DEVICE(ks
->mouse
), PS2_DEVICE_IRQ
,
708 qdev_get_gpio_in_named(dev
, "ps2-mouse-input-irq",
712 static void i8042_mmio_init(Object
*obj
)
714 MMIOKBDState
*s
= I8042_MMIO(obj
);
715 KBDState
*ks
= &s
->kbd
;
717 ks
->extended_state
= true;
719 qdev_init_gpio_out(DEVICE(obj
), ks
->irqs
, 2);
720 qdev_init_gpio_in_named(DEVICE(obj
), i8042_mmio_set_kbd_irq
,
721 "ps2-kbd-input-irq", 1);
722 qdev_init_gpio_in_named(DEVICE(obj
), i8042_mmio_set_mouse_irq
,
723 "ps2-mouse-input-irq", 1);
726 static Property i8042_mmio_properties
[] = {
727 DEFINE_PROP_UINT64("mask", MMIOKBDState
, kbd
.mask
, UINT64_MAX
),
728 DEFINE_PROP_UINT32("size", MMIOKBDState
, size
, -1),
729 DEFINE_PROP_END_OF_LIST(),
732 static const VMStateDescription vmstate_kbd_mmio
= {
733 .name
= "pckbd-mmio",
735 .minimum_version_id
= 1,
736 .fields
= (VMStateField
[]) {
737 VMSTATE_STRUCT(kbd
, MMIOKBDState
, 0, vmstate_kbd
, KBDState
),
738 VMSTATE_END_OF_LIST()
742 static void i8042_mmio_class_init(ObjectClass
*klass
, void *data
)
744 DeviceClass
*dc
= DEVICE_CLASS(klass
);
746 dc
->realize
= i8042_mmio_realize
;
747 dc
->reset
= i8042_mmio_reset
;
748 dc
->vmsd
= &vmstate_kbd_mmio
;
749 device_class_set_props(dc
, i8042_mmio_properties
);
750 set_bit(DEVICE_CATEGORY_INPUT
, dc
->categories
);
753 MMIOKBDState
*i8042_mm_init(qemu_irq kbd_irq
, qemu_irq mouse_irq
,
754 ram_addr_t size
, hwaddr mask
)
758 dev
= qdev_new(TYPE_I8042_MMIO
);
759 qdev_prop_set_uint64(dev
, "mask", mask
);
760 qdev_prop_set_uint32(dev
, "size", size
);
761 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
763 qdev_connect_gpio_out(dev
, I8042_KBD_IRQ
, kbd_irq
);
764 qdev_connect_gpio_out(dev
, I8042_MOUSE_IRQ
, mouse_irq
);
766 return I8042_MMIO(dev
);
769 static const TypeInfo i8042_mmio_info
= {
770 .name
= TYPE_I8042_MMIO
,
771 .parent
= TYPE_SYS_BUS_DEVICE
,
772 .instance_init
= i8042_mmio_init
,
773 .instance_size
= sizeof(MMIOKBDState
),
774 .class_init
= i8042_mmio_class_init
777 void i8042_isa_mouse_fake_event(ISAKBDState
*isa
)
779 KBDState
*s
= &isa
->kbd
;
781 ps2_mouse_fake_event(s
->mouse
);
784 void i8042_setup_a20_line(ISADevice
*dev
, qemu_irq a20_out
)
786 qdev_connect_gpio_out_named(DEVICE(dev
), I8042_A20_LINE
, 0, a20_out
);
789 static const VMStateDescription vmstate_kbd_isa
= {
792 .minimum_version_id
= 3,
793 .fields
= (VMStateField
[]) {
794 VMSTATE_STRUCT(kbd
, ISAKBDState
, 0, vmstate_kbd
, KBDState
),
795 VMSTATE_END_OF_LIST()
799 static const MemoryRegionOps i8042_data_ops
= {
800 .read
= kbd_read_data
,
801 .write
= kbd_write_data
,
803 .min_access_size
= 1,
804 .max_access_size
= 1,
806 .endianness
= DEVICE_LITTLE_ENDIAN
,
809 static const MemoryRegionOps i8042_cmd_ops
= {
810 .read
= kbd_read_status
,
811 .write
= kbd_write_command
,
813 .min_access_size
= 1,
814 .max_access_size
= 1,
816 .endianness
= DEVICE_LITTLE_ENDIAN
,
819 static void i8042_set_kbd_irq(void *opaque
, int n
, int level
)
821 ISAKBDState
*s
= I8042(opaque
);
822 KBDState
*ks
= &s
->kbd
;
824 kbd_update_kbd_irq(ks
, level
);
827 static void i8042_set_mouse_irq(void *opaque
, int n
, int level
)
829 ISAKBDState
*s
= I8042(opaque
);
830 KBDState
*ks
= &s
->kbd
;
832 kbd_update_aux_irq(ks
, level
);
836 static void i8042_reset(DeviceState
*dev
)
838 ISAKBDState
*s
= I8042(dev
);
839 KBDState
*ks
= &s
->kbd
;
844 static void i8042_initfn(Object
*obj
)
846 ISAKBDState
*isa_s
= I8042(obj
);
847 KBDState
*s
= &isa_s
->kbd
;
849 memory_region_init_io(isa_s
->io
+ 0, obj
, &i8042_data_ops
, s
,
851 memory_region_init_io(isa_s
->io
+ 1, obj
, &i8042_cmd_ops
, s
,
854 qdev_init_gpio_out_named(DEVICE(obj
), &s
->a20_out
, I8042_A20_LINE
, 1);
856 qdev_init_gpio_out(DEVICE(obj
), s
->irqs
, 2);
857 qdev_init_gpio_in_named(DEVICE(obj
), i8042_set_kbd_irq
,
858 "ps2-kbd-input-irq", 1);
859 qdev_init_gpio_in_named(DEVICE(obj
), i8042_set_mouse_irq
,
860 "ps2-mouse-input-irq", 1);
863 static void i8042_realizefn(DeviceState
*dev
, Error
**errp
)
865 ISADevice
*isadev
= ISA_DEVICE(dev
);
866 ISAKBDState
*isa_s
= I8042(dev
);
867 KBDState
*s
= &isa_s
->kbd
;
869 if (isa_s
->kbd_irq
>= ISA_NUM_IRQS
) {
870 error_setg(errp
, "Maximum value for \"kbd-irq\" is: %u",
875 if (isa_s
->mouse_irq
>= ISA_NUM_IRQS
) {
876 error_setg(errp
, "Maximum value for \"mouse-irq\" is: %u",
881 isa_connect_gpio_out(isadev
, I8042_KBD_IRQ
, isa_s
->kbd_irq
);
882 isa_connect_gpio_out(isadev
, I8042_MOUSE_IRQ
, isa_s
->mouse_irq
);
884 isa_register_ioport(isadev
, isa_s
->io
+ 0, 0x60);
885 isa_register_ioport(isadev
, isa_s
->io
+ 1, 0x64);
887 s
->kbd
= ps2_kbd_init();
888 qdev_connect_gpio_out(DEVICE(s
->kbd
), PS2_DEVICE_IRQ
,
889 qdev_get_gpio_in_named(dev
, "ps2-kbd-input-irq",
891 s
->mouse
= ps2_mouse_init();
892 qdev_connect_gpio_out(DEVICE(s
->mouse
), PS2_DEVICE_IRQ
,
893 qdev_get_gpio_in_named(dev
, "ps2-mouse-input-irq",
895 if (isa_s
->kbd_throttle
&& !isa_s
->kbd
.extended_state
) {
896 warn_report(TYPE_I8042
": can't enable kbd-throttle without"
897 " extended-state, disabling kbd-throttle");
898 } else if (isa_s
->kbd_throttle
) {
899 s
->throttle_timer
= timer_new_us(QEMU_CLOCK_VIRTUAL
,
900 kbd_throttle_timeout
, s
);
904 static void i8042_build_aml(AcpiDevAmlIf
*adev
, Aml
*scope
)
906 ISAKBDState
*isa_s
= I8042(adev
);
911 crs
= aml_resource_template();
912 aml_append(crs
, aml_io(AML_DECODE16
, 0x0060, 0x0060, 0x01, 0x01));
913 aml_append(crs
, aml_io(AML_DECODE16
, 0x0064, 0x0064, 0x01, 0x01));
914 aml_append(crs
, aml_irq_no_flags(isa_s
->kbd_irq
));
916 kbd
= aml_device("KBD");
917 aml_append(kbd
, aml_name_decl("_HID", aml_eisaid("PNP0303")));
918 aml_append(kbd
, aml_name_decl("_STA", aml_int(0xf)));
919 aml_append(kbd
, aml_name_decl("_CRS", crs
));
921 crs
= aml_resource_template();
922 aml_append(crs
, aml_irq_no_flags(isa_s
->mouse_irq
));
924 mou
= aml_device("MOU");
925 aml_append(mou
, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
926 aml_append(mou
, aml_name_decl("_STA", aml_int(0xf)));
927 aml_append(mou
, aml_name_decl("_CRS", crs
));
929 aml_append(scope
, kbd
);
930 aml_append(scope
, mou
);
933 static Property i8042_properties
[] = {
934 DEFINE_PROP_BOOL("extended-state", ISAKBDState
, kbd
.extended_state
, true),
935 DEFINE_PROP_BOOL("kbd-throttle", ISAKBDState
, kbd_throttle
, false),
936 DEFINE_PROP_UINT8("kbd-irq", ISAKBDState
, kbd_irq
, 1),
937 DEFINE_PROP_UINT8("mouse-irq", ISAKBDState
, mouse_irq
, 12),
938 DEFINE_PROP_END_OF_LIST(),
941 static void i8042_class_initfn(ObjectClass
*klass
, void *data
)
943 DeviceClass
*dc
= DEVICE_CLASS(klass
);
944 AcpiDevAmlIfClass
*adevc
= ACPI_DEV_AML_IF_CLASS(klass
);
946 device_class_set_props(dc
, i8042_properties
);
947 dc
->reset
= i8042_reset
;
948 dc
->realize
= i8042_realizefn
;
949 dc
->vmsd
= &vmstate_kbd_isa
;
950 adevc
->build_dev_aml
= i8042_build_aml
;
951 set_bit(DEVICE_CATEGORY_INPUT
, dc
->categories
);
954 static const TypeInfo i8042_info
= {
956 .parent
= TYPE_ISA_DEVICE
,
957 .instance_size
= sizeof(ISAKBDState
),
958 .instance_init
= i8042_initfn
,
959 .class_init
= i8042_class_initfn
,
960 .interfaces
= (InterfaceInfo
[]) {
961 { TYPE_ACPI_DEV_AML_IF
},
966 static void i8042_register_types(void)
968 type_register_static(&i8042_info
);
969 type_register_static(&i8042_mmio_info
);
972 type_init(i8042_register_types
)