docs: Update documentation for stderr (now log) tracing backend.
[qemu/ar7.git] / target-openrisc / gdbstub.c
blobedc301a7c5dcf71b15ae3d1339c29808117d4521
1 /*
2 * OpenRISC gdb server stub
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 * Copyright (c) 2013 SUSE LINUX Products GmbH
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
22 #include "exec/gdbstub.h"
24 int openrisc_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
26 OpenRISCCPU *cpu = OPENRISC_CPU(cs);
27 CPUOpenRISCState *env = &cpu->env;
29 if (n < 32) {
30 return gdb_get_reg32(mem_buf, env->gpr[n]);
31 } else {
32 switch (n) {
33 case 32: /* PPC */
34 return gdb_get_reg32(mem_buf, env->ppc);
36 case 33: /* NPC */
37 return gdb_get_reg32(mem_buf, env->npc);
39 case 34: /* SR */
40 return gdb_get_reg32(mem_buf, env->sr);
42 default:
43 break;
46 return 0;
49 int openrisc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
51 OpenRISCCPU *cpu = OPENRISC_CPU(cs);
52 CPUClass *cc = CPU_GET_CLASS(cs);
53 CPUOpenRISCState *env = &cpu->env;
54 uint32_t tmp;
56 if (n > cc->gdb_num_core_regs) {
57 return 0;
60 tmp = ldl_p(mem_buf);
62 if (n < 32) {
63 env->gpr[n] = tmp;
64 } else {
65 switch (n) {
66 case 32: /* PPC */
67 env->ppc = tmp;
68 break;
70 case 33: /* NPC */
71 env->npc = tmp;
72 break;
74 case 34: /* SR */
75 env->sr = tmp;
76 break;
78 default:
79 break;
82 return 4;