hw/misc/macio/gpio.c

   1 /*
   2  * PowerMac NewWorld MacIO GPIO emulation
   3  *
   4  * Copyright (c) 2016 Benjamin Herrenschmidt
   5  * Copyright (c) 2018 Mark Cave-Ayland
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "hw/hw.h"
  28 #include "hw/ppc/mac.h"
  29 #include "hw/misc/macio/macio.h"
  30 #include "hw/misc/macio/gpio.h"
  31 #include "hw/nmi.h"
  32 #include "qemu/log.h"
  33 #include "trace.h"
  34
  35
  36 void macio_set_gpio(MacIOGPIOState *s, uint32_t gpio, bool state)
  37 {
  38     uint8_t new_reg;
  39
  40     trace_macio_set_gpio(gpio, state);
  41
  42     if (s->gpio_regs[gpio] & 4) {
  43         qemu_log_mask(LOG_GUEST_ERROR,
  44                       "GPIO: Setting GPIO %d while it's an output\n", gpio);
  45     }
  46
  47     new_reg = s->gpio_regs[gpio] & ~2;
  48     if (state) {
  49         new_reg |= 2;
  50     }
  51
  52     if (new_reg == s->gpio_regs[gpio]) {
  53         return;
  54     }
  55
  56     s->gpio_regs[gpio] = new_reg;
  57
  58     /* This is will work until we fix the binding between MacIO and
  59      * the MPIC properly so we can route all GPIOs and avoid going
  60      * via the top level platform code.
  61      *
  62      * Note that we probably need to get access to the MPIC config to
  63      * decode polarity since qemu always use "raise" regardless.
  64      *
  65      * For now, we hard wire known GPIOs
  66      */
  67
  68     switch (gpio) {
  69     case 1:
  70         /* Level low */
  71         if (!state) {
  72             trace_macio_gpio_irq_assert(gpio);
  73             qemu_irq_raise(s->gpio_extirqs[gpio]);
  74         } else {
  75             trace_macio_gpio_irq_deassert(gpio);
  76             qemu_irq_lower(s->gpio_extirqs[gpio]);
  77         }
  78         break;
  79
  80     case 9:
  81         /* Edge, triggered by NMI below */
  82         if (state) {
  83             trace_macio_gpio_irq_assert(gpio);
  84             qemu_irq_raise(s->gpio_extirqs[gpio]);
  85         } else {
  86             trace_macio_gpio_irq_deassert(gpio);
  87             qemu_irq_lower(s->gpio_extirqs[gpio]);
  88         }
  89         break;
  90
  91     default:
  92         qemu_log_mask(LOG_UNIMP, "GPIO: setting unimplemented GPIO %d", gpio);
  93     }
  94 }
  95
  96 static void macio_gpio_write(void *opaque, hwaddr addr, uint64_t value,
  97                              unsigned size)
  98 {
  99     MacIOGPIOState *s = opaque;
 100     uint8_t ibit;
 101
 102     trace_macio_gpio_write(addr, value);
 103
 104     /* Levels regs are read-only */
 105     if (addr < 8) {
 106         return;
 107     }
 108
 109     addr -= 8;
 110     if (addr < 36) {
 111         value &= ~2;
 112
 113         if (value & 4) {
 114             ibit = (value & 1) << 1;
 115         } else {
 116             ibit = s->gpio_regs[addr] & 2;
 117         }
 118
 119         s->gpio_regs[addr] = value | ibit;
 120     }
 121 }
 122
 123 static uint64_t macio_gpio_read(void *opaque, hwaddr addr, unsigned size)
 124 {
 125     MacIOGPIOState *s = opaque;
 126     uint64_t val = 0;
 127
 128     /* Levels regs */
 129     if (addr < 8) {
 130         val = s->gpio_levels[addr];
 131     } else {
 132         addr -= 8;
 133
 134         if (addr < 36) {
 135             val = s->gpio_regs[addr];
 136         }
 137     }
 138
 139     trace_macio_gpio_write(addr, val);
 140     return val;
 141 }
 142
 143 static const MemoryRegionOps macio_gpio_ops = {
 144     .read = macio_gpio_read,
 145     .write = macio_gpio_write,
 146     .endianness = DEVICE_LITTLE_ENDIAN,
 147     .impl = {
 148         .min_access_size = 1,
 149         .max_access_size = 1,
 150     },
 151 };
 152
 153 static void macio_gpio_realize(DeviceState *dev, Error **errp)
 154 {
 155     MacIOGPIOState *s = MACIO_GPIO(dev);
 156
 157     s->gpio_extirqs[1] = qdev_get_gpio_in(DEVICE(s->pic),
 158                                           NEWWORLD_EXTING_GPIO1);
 159     s->gpio_extirqs[9] = qdev_get_gpio_in(DEVICE(s->pic),
 160                                           NEWWORLD_EXTING_GPIO9);
 161 }
 162
 163 static void macio_gpio_init(Object *obj)
 164 {
 165     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 166     MacIOGPIOState *s = MACIO_GPIO(obj);
 167
 168     object_property_add_link(obj, "pic", TYPE_OPENPIC,
 169                              (Object **) &s->pic,
 170                              qdev_prop_allow_set_link_before_realize,
 171                              0, NULL);
 172
 173     memory_region_init_io(&s->gpiomem, OBJECT(s), &macio_gpio_ops, obj,
 174                           "gpio", 0x30);
 175     sysbus_init_mmio(sbd, &s->gpiomem);
 176 }
 177
 178 static const VMStateDescription vmstate_macio_gpio = {
 179     .name = "macio_gpio",
 180     .version_id = 0,
 181     .minimum_version_id = 0,
 182     .fields = (VMStateField[]) {
 183         VMSTATE_UINT8_ARRAY(gpio_levels, MacIOGPIOState, 8),
 184         VMSTATE_UINT8_ARRAY(gpio_regs, MacIOGPIOState, 36),
 185         VMSTATE_END_OF_LIST()
 186     }
 187 };
 188
 189 static void macio_gpio_reset(DeviceState *dev)
 190 {
 191     MacIOGPIOState *s = MACIO_GPIO(dev);
 192
 193     /* GPIO 1 is up by default */
 194     macio_set_gpio(s, 1, true);
 195 }
 196
 197 static void macio_gpio_nmi(NMIState *n, int cpu_index, Error **errp)
 198 {
 199     macio_set_gpio(MACIO_GPIO(n), 9, true);
 200     macio_set_gpio(MACIO_GPIO(n), 9, false);
 201 }
 202
 203 static void macio_gpio_class_init(ObjectClass *oc, void *data)
 204 {
 205     DeviceClass *dc = DEVICE_CLASS(oc);
 206     NMIClass *nc = NMI_CLASS(oc);
 207
 208     dc->realize = macio_gpio_realize;
 209     dc->reset = macio_gpio_reset;
 210     dc->vmsd = &vmstate_macio_gpio;
 211     nc->nmi_monitor_handler = macio_gpio_nmi;
 212 }
 213
 214 static const TypeInfo macio_gpio_init_info = {
 215     .name          = TYPE_MACIO_GPIO,
 216     .parent        = TYPE_SYS_BUS_DEVICE,
 217     .instance_size = sizeof(MacIOGPIOState),
 218     .instance_init = macio_gpio_init,
 219     .class_init    = macio_gpio_class_init,
 220     .interfaces = (InterfaceInfo[]) {
 221         { TYPE_NMI },
 222         { }
 223     },
 224 };
 225
 226 static void macio_gpio_register_types(void)
 227 {
 228     type_register_static(&macio_gpio_init_info);
 229 }
 230
 231 type_init(macio_gpio_register_types)